1 /* 2 * Driver for Broadcom BCM2835 SPI Controllers 3 * 4 * Copyright (C) 2012 Chris Boot 5 * Copyright (C) 2013 Stephen Warren 6 * Copyright (C) 2015 Martin Sperl 7 * 8 * This driver is inspired by: 9 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 10 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 23 #include <asm/page.h> 24 #include <linux/clk.h> 25 #include <linux/completion.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/err.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/kernel.h> 33 #include <linux/module.h> 34 #include <linux/of.h> 35 #include <linux/of_address.h> 36 #include <linux/of_device.h> 37 #include <linux/of_gpio.h> 38 #include <linux/of_irq.h> 39 #include <linux/spi/spi.h> 40 41 /* SPI register offsets */ 42 #define BCM2835_SPI_CS 0x00 43 #define BCM2835_SPI_FIFO 0x04 44 #define BCM2835_SPI_CLK 0x08 45 #define BCM2835_SPI_DLEN 0x0c 46 #define BCM2835_SPI_LTOH 0x10 47 #define BCM2835_SPI_DC 0x14 48 49 /* Bitfields in CS */ 50 #define BCM2835_SPI_CS_LEN_LONG 0x02000000 51 #define BCM2835_SPI_CS_DMA_LEN 0x01000000 52 #define BCM2835_SPI_CS_CSPOL2 0x00800000 53 #define BCM2835_SPI_CS_CSPOL1 0x00400000 54 #define BCM2835_SPI_CS_CSPOL0 0x00200000 55 #define BCM2835_SPI_CS_RXF 0x00100000 56 #define BCM2835_SPI_CS_RXR 0x00080000 57 #define BCM2835_SPI_CS_TXD 0x00040000 58 #define BCM2835_SPI_CS_RXD 0x00020000 59 #define BCM2835_SPI_CS_DONE 0x00010000 60 #define BCM2835_SPI_CS_LEN 0x00002000 61 #define BCM2835_SPI_CS_REN 0x00001000 62 #define BCM2835_SPI_CS_ADCS 0x00000800 63 #define BCM2835_SPI_CS_INTR 0x00000400 64 #define BCM2835_SPI_CS_INTD 0x00000200 65 #define BCM2835_SPI_CS_DMAEN 0x00000100 66 #define BCM2835_SPI_CS_TA 0x00000080 67 #define BCM2835_SPI_CS_CSPOL 0x00000040 68 #define BCM2835_SPI_CS_CLEAR_RX 0x00000020 69 #define BCM2835_SPI_CS_CLEAR_TX 0x00000010 70 #define BCM2835_SPI_CS_CPOL 0x00000008 71 #define BCM2835_SPI_CS_CPHA 0x00000004 72 #define BCM2835_SPI_CS_CS_10 0x00000002 73 #define BCM2835_SPI_CS_CS_01 0x00000001 74 75 #define BCM2835_SPI_POLLING_LIMIT_US 30 76 #define BCM2835_SPI_POLLING_JIFFIES 2 77 #define BCM2835_SPI_DMA_MIN_LENGTH 96 78 #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ 79 | SPI_NO_CS | SPI_3WIRE) 80 81 #define DRV_NAME "spi-bcm2835" 82 83 struct bcm2835_spi { 84 void __iomem *regs; 85 struct clk *clk; 86 int irq; 87 const u8 *tx_buf; 88 u8 *rx_buf; 89 int tx_len; 90 int rx_len; 91 bool dma_pending; 92 }; 93 94 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) 95 { 96 return readl(bs->regs + reg); 97 } 98 99 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val) 100 { 101 writel(val, bs->regs + reg); 102 } 103 104 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs) 105 { 106 u8 byte; 107 108 while ((bs->rx_len) && 109 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) { 110 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO); 111 if (bs->rx_buf) 112 *bs->rx_buf++ = byte; 113 bs->rx_len--; 114 } 115 } 116 117 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs) 118 { 119 u8 byte; 120 121 while ((bs->tx_len) && 122 (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) { 123 byte = bs->tx_buf ? *bs->tx_buf++ : 0; 124 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte); 125 bs->tx_len--; 126 } 127 } 128 129 static void bcm2835_spi_reset_hw(struct spi_master *master) 130 { 131 struct bcm2835_spi *bs = spi_master_get_devdata(master); 132 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 133 134 /* Disable SPI interrupts and transfer */ 135 cs &= ~(BCM2835_SPI_CS_INTR | 136 BCM2835_SPI_CS_INTD | 137 BCM2835_SPI_CS_DMAEN | 138 BCM2835_SPI_CS_TA); 139 /* and reset RX/TX FIFOS */ 140 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; 141 142 /* and reset the SPI_HW */ 143 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 144 /* as well as DLEN */ 145 bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); 146 } 147 148 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) 149 { 150 struct spi_master *master = dev_id; 151 struct bcm2835_spi *bs = spi_master_get_devdata(master); 152 153 /* Read as many bytes as possible from FIFO */ 154 bcm2835_rd_fifo(bs); 155 /* Write as many bytes as possible to FIFO */ 156 bcm2835_wr_fifo(bs); 157 158 /* based on flags decide if we can finish the transfer */ 159 if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) { 160 /* Transfer complete - reset SPI HW */ 161 bcm2835_spi_reset_hw(master); 162 /* wake up the framework */ 163 complete(&master->xfer_completion); 164 } 165 166 return IRQ_HANDLED; 167 } 168 169 static int bcm2835_spi_transfer_one_irq(struct spi_master *master, 170 struct spi_device *spi, 171 struct spi_transfer *tfr, 172 u32 cs) 173 { 174 struct bcm2835_spi *bs = spi_master_get_devdata(master); 175 176 /* fill in fifo if we have gpio-cs 177 * note that there have been rare events where the native-CS 178 * flapped for <1us which may change the behaviour 179 * with gpio-cs this does not happen, so it is implemented 180 * only for this case 181 */ 182 if (gpio_is_valid(spi->cs_gpio)) { 183 /* enable HW block, but without interrupts enabled 184 * this would triggern an immediate interrupt 185 */ 186 bcm2835_wr(bs, BCM2835_SPI_CS, 187 cs | BCM2835_SPI_CS_TA); 188 /* fill in tx fifo as much as possible */ 189 bcm2835_wr_fifo(bs); 190 } 191 192 /* 193 * Enable the HW block. This will immediately trigger a DONE (TX 194 * empty) interrupt, upon which we will fill the TX FIFO with the 195 * first TX bytes. Pre-filling the TX FIFO here to avoid the 196 * interrupt doesn't work:-( 197 */ 198 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; 199 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 200 201 /* signal that we need to wait for completion */ 202 return 1; 203 } 204 205 /* 206 * DMA support 207 * 208 * this implementation has currently a few issues in so far as it does 209 * not work arrount limitations of the HW. 210 * 211 * the main one being that DMA transfers are limited to 16 bit 212 * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN 213 * 214 * also we currently assume that the scatter-gather fragments are 215 * all multiple of 4 (except the last) - otherwise we would need 216 * to reset the FIFO before subsequent transfers... 217 * this also means that tx/rx transfers sg's need to be of equal size! 218 * 219 * there may be a few more border-cases we may need to address as well 220 * but unfortunately this would mean splitting up the scatter-gather 221 * list making it slightly unpractical... 222 */ 223 static void bcm2835_spi_dma_done(void *data) 224 { 225 struct spi_master *master = data; 226 struct bcm2835_spi *bs = spi_master_get_devdata(master); 227 228 /* reset fifo and HW */ 229 bcm2835_spi_reset_hw(master); 230 231 /* and terminate tx-dma as we do not have an irq for it 232 * because when the rx dma will terminate and this callback 233 * is called the tx-dma must have finished - can't get to this 234 * situation otherwise... 235 */ 236 dmaengine_terminate_all(master->dma_tx); 237 238 /* mark as no longer pending */ 239 bs->dma_pending = 0; 240 241 /* and mark as completed */; 242 complete(&master->xfer_completion); 243 } 244 245 static int bcm2835_spi_prepare_sg(struct spi_master *master, 246 struct spi_transfer *tfr, 247 bool is_tx) 248 { 249 struct dma_chan *chan; 250 struct scatterlist *sgl; 251 unsigned int nents; 252 enum dma_transfer_direction dir; 253 unsigned long flags; 254 255 struct dma_async_tx_descriptor *desc; 256 dma_cookie_t cookie; 257 258 if (is_tx) { 259 dir = DMA_MEM_TO_DEV; 260 chan = master->dma_tx; 261 nents = tfr->tx_sg.nents; 262 sgl = tfr->tx_sg.sgl; 263 flags = 0 /* no tx interrupt */; 264 265 } else { 266 dir = DMA_DEV_TO_MEM; 267 chan = master->dma_rx; 268 nents = tfr->rx_sg.nents; 269 sgl = tfr->rx_sg.sgl; 270 flags = DMA_PREP_INTERRUPT; 271 } 272 /* prepare the channel */ 273 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); 274 if (!desc) 275 return -EINVAL; 276 277 /* set callback for rx */ 278 if (!is_tx) { 279 desc->callback = bcm2835_spi_dma_done; 280 desc->callback_param = master; 281 } 282 283 /* submit it to DMA-engine */ 284 cookie = dmaengine_submit(desc); 285 286 return dma_submit_error(cookie); 287 } 288 289 static inline int bcm2835_check_sg_length(struct sg_table *sgt) 290 { 291 int i; 292 struct scatterlist *sgl; 293 294 /* check that the sg entries are word-sized (except for last) */ 295 for_each_sg(sgt->sgl, sgl, (int)sgt->nents - 1, i) { 296 if (sg_dma_len(sgl) % 4) 297 return -EFAULT; 298 } 299 300 return 0; 301 } 302 303 static int bcm2835_spi_transfer_one_dma(struct spi_master *master, 304 struct spi_device *spi, 305 struct spi_transfer *tfr, 306 u32 cs) 307 { 308 struct bcm2835_spi *bs = spi_master_get_devdata(master); 309 int ret; 310 311 /* check that the scatter gather segments are all a multiple of 4 */ 312 if (bcm2835_check_sg_length(&tfr->tx_sg) || 313 bcm2835_check_sg_length(&tfr->rx_sg)) { 314 dev_warn_once(&spi->dev, 315 "scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n"); 316 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); 317 } 318 319 /* setup tx-DMA */ 320 ret = bcm2835_spi_prepare_sg(master, tfr, true); 321 if (ret) 322 return ret; 323 324 /* start TX early */ 325 dma_async_issue_pending(master->dma_tx); 326 327 /* mark as dma pending */ 328 bs->dma_pending = 1; 329 330 /* set the DMA length */ 331 bcm2835_wr(bs, BCM2835_SPI_DLEN, tfr->len); 332 333 /* start the HW */ 334 bcm2835_wr(bs, BCM2835_SPI_CS, 335 cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); 336 337 /* setup rx-DMA late - to run transfers while 338 * mapping of the rx buffers still takes place 339 * this saves 10us or more. 340 */ 341 ret = bcm2835_spi_prepare_sg(master, tfr, false); 342 if (ret) { 343 /* need to reset on errors */ 344 dmaengine_terminate_all(master->dma_tx); 345 bcm2835_spi_reset_hw(master); 346 return ret; 347 } 348 349 /* start rx dma late */ 350 dma_async_issue_pending(master->dma_rx); 351 352 /* wait for wakeup in framework */ 353 return 1; 354 } 355 356 static bool bcm2835_spi_can_dma(struct spi_master *master, 357 struct spi_device *spi, 358 struct spi_transfer *tfr) 359 { 360 /* only run for gpio_cs */ 361 if (!gpio_is_valid(spi->cs_gpio)) 362 return false; 363 364 /* we start DMA efforts only on bigger transfers */ 365 if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) 366 return false; 367 368 /* BCM2835_SPI_DLEN has defined a max transfer size as 369 * 16 bit, so max is 65535 370 * we can revisit this by using an alternative transfer 371 * method - ideally this would get done without any more 372 * interaction... 373 */ 374 if (tfr->len > 65535) { 375 dev_warn_once(&spi->dev, 376 "transfer size of %d too big for dma-transfer\n", 377 tfr->len); 378 return false; 379 } 380 381 /* if we run rx/tx_buf with word aligned addresses then we are OK */ 382 if ((((size_t)tfr->rx_buf & 3) == 0) && 383 (((size_t)tfr->tx_buf & 3) == 0)) 384 return true; 385 386 /* otherwise we only allow transfers within the same page 387 * to avoid wasting time on dma_mapping when it is not practical 388 */ 389 if (((size_t)tfr->tx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { 390 dev_warn_once(&spi->dev, 391 "Unaligned spi tx-transfer bridging page\n"); 392 return false; 393 } 394 if (((size_t)tfr->rx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { 395 dev_warn_once(&spi->dev, 396 "Unaligned spi rx-transfer bridging page\n"); 397 return false; 398 } 399 400 /* return OK */ 401 return true; 402 } 403 404 static void bcm2835_dma_release(struct spi_master *master) 405 { 406 if (master->dma_tx) { 407 dmaengine_terminate_all(master->dma_tx); 408 dma_release_channel(master->dma_tx); 409 master->dma_tx = NULL; 410 } 411 if (master->dma_rx) { 412 dmaengine_terminate_all(master->dma_rx); 413 dma_release_channel(master->dma_rx); 414 master->dma_rx = NULL; 415 } 416 } 417 418 static void bcm2835_dma_init(struct spi_master *master, struct device *dev) 419 { 420 struct dma_slave_config slave_config; 421 const __be32 *addr; 422 dma_addr_t dma_reg_base; 423 int ret; 424 425 /* base address in dma-space */ 426 addr = of_get_address(master->dev.of_node, 0, NULL, NULL); 427 if (!addr) { 428 dev_err(dev, "could not get DMA-register address - not using dma mode\n"); 429 goto err; 430 } 431 dma_reg_base = be32_to_cpup(addr); 432 433 /* get tx/rx dma */ 434 master->dma_tx = dma_request_slave_channel(dev, "tx"); 435 if (!master->dma_tx) { 436 dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); 437 goto err; 438 } 439 master->dma_rx = dma_request_slave_channel(dev, "rx"); 440 if (!master->dma_rx) { 441 dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); 442 goto err_release; 443 } 444 445 /* configure DMAs */ 446 slave_config.direction = DMA_MEM_TO_DEV; 447 slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); 448 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 449 450 ret = dmaengine_slave_config(master->dma_tx, &slave_config); 451 if (ret) 452 goto err_config; 453 454 slave_config.direction = DMA_DEV_TO_MEM; 455 slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); 456 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 457 458 ret = dmaengine_slave_config(master->dma_rx, &slave_config); 459 if (ret) 460 goto err_config; 461 462 /* all went well, so set can_dma */ 463 master->can_dma = bcm2835_spi_can_dma; 464 master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */ 465 /* need to do TX AND RX DMA, so we need dummy buffers */ 466 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; 467 468 return; 469 470 err_config: 471 dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", 472 ret); 473 err_release: 474 bcm2835_dma_release(master); 475 err: 476 return; 477 } 478 479 static int bcm2835_spi_transfer_one_poll(struct spi_master *master, 480 struct spi_device *spi, 481 struct spi_transfer *tfr, 482 u32 cs, 483 unsigned long long xfer_time_us) 484 { 485 struct bcm2835_spi *bs = spi_master_get_devdata(master); 486 unsigned long timeout; 487 488 /* enable HW block without interrupts */ 489 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); 490 491 /* fill in the fifo before timeout calculations 492 * if we are interrupted here, then the data is 493 * getting transferred by the HW while we are interrupted 494 */ 495 bcm2835_wr_fifo(bs); 496 497 /* set the timeout */ 498 timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES; 499 500 /* loop until finished the transfer */ 501 while (bs->rx_len) { 502 /* fill in tx fifo with remaining data */ 503 bcm2835_wr_fifo(bs); 504 505 /* read from fifo as much as possible */ 506 bcm2835_rd_fifo(bs); 507 508 /* if there is still data pending to read 509 * then check the timeout 510 */ 511 if (bs->rx_len && time_after(jiffies, timeout)) { 512 dev_dbg_ratelimited(&spi->dev, 513 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", 514 jiffies - timeout, 515 bs->tx_len, bs->rx_len); 516 /* fall back to interrupt mode */ 517 return bcm2835_spi_transfer_one_irq(master, spi, 518 tfr, cs); 519 } 520 } 521 522 /* Transfer complete - reset SPI HW */ 523 bcm2835_spi_reset_hw(master); 524 /* and return without waiting for completion */ 525 return 0; 526 } 527 528 static int bcm2835_spi_transfer_one(struct spi_master *master, 529 struct spi_device *spi, 530 struct spi_transfer *tfr) 531 { 532 struct bcm2835_spi *bs = spi_master_get_devdata(master); 533 unsigned long spi_hz, clk_hz, cdiv; 534 unsigned long spi_used_hz; 535 unsigned long long xfer_time_us; 536 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 537 538 /* set clock */ 539 spi_hz = tfr->speed_hz; 540 clk_hz = clk_get_rate(bs->clk); 541 542 if (spi_hz >= clk_hz / 2) { 543 cdiv = 2; /* clk_hz/2 is the fastest we can go */ 544 } else if (spi_hz) { 545 /* CDIV must be a multiple of two */ 546 cdiv = DIV_ROUND_UP(clk_hz, spi_hz); 547 cdiv += (cdiv % 2); 548 549 if (cdiv >= 65536) 550 cdiv = 0; /* 0 is the slowest we can go */ 551 } else { 552 cdiv = 0; /* 0 is the slowest we can go */ 553 } 554 spi_used_hz = cdiv ? (clk_hz / cdiv) : (clk_hz / 65536); 555 bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv); 556 557 /* handle all the 3-wire mode */ 558 if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf)) 559 cs |= BCM2835_SPI_CS_REN; 560 else 561 cs &= ~BCM2835_SPI_CS_REN; 562 563 /* for gpio_cs set dummy CS so that no HW-CS get changed 564 * we can not run this in bcm2835_spi_set_cs, as it does 565 * not get called for cs_gpio cases, so we need to do it here 566 */ 567 if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS)) 568 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; 569 570 /* set transmit buffers and length */ 571 bs->tx_buf = tfr->tx_buf; 572 bs->rx_buf = tfr->rx_buf; 573 bs->tx_len = tfr->len; 574 bs->rx_len = tfr->len; 575 576 /* calculate the estimated time in us the transfer runs */ 577 xfer_time_us = (unsigned long long)tfr->len 578 * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ 579 * 1000000; 580 do_div(xfer_time_us, spi_used_hz); 581 582 /* for short requests run polling*/ 583 if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) 584 return bcm2835_spi_transfer_one_poll(master, spi, tfr, 585 cs, xfer_time_us); 586 587 /* run in dma mode if conditions are right */ 588 if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr)) 589 return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs); 590 591 /* run in interrupt-mode */ 592 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); 593 } 594 595 static int bcm2835_spi_prepare_message(struct spi_master *master, 596 struct spi_message *msg) 597 { 598 struct spi_device *spi = msg->spi; 599 struct bcm2835_spi *bs = spi_master_get_devdata(master); 600 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 601 602 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA); 603 604 if (spi->mode & SPI_CPOL) 605 cs |= BCM2835_SPI_CS_CPOL; 606 if (spi->mode & SPI_CPHA) 607 cs |= BCM2835_SPI_CS_CPHA; 608 609 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 610 611 return 0; 612 } 613 614 static void bcm2835_spi_handle_err(struct spi_master *master, 615 struct spi_message *msg) 616 { 617 struct bcm2835_spi *bs = spi_master_get_devdata(master); 618 619 /* if an error occurred and we have an active dma, then terminate */ 620 if (bs->dma_pending) { 621 dmaengine_terminate_all(master->dma_tx); 622 dmaengine_terminate_all(master->dma_rx); 623 bs->dma_pending = 0; 624 } 625 /* and reset */ 626 bcm2835_spi_reset_hw(master); 627 } 628 629 static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level) 630 { 631 /* 632 * we can assume that we are "native" as per spi_set_cs 633 * calling us ONLY when cs_gpio is not set 634 * we can also assume that we are CS < 3 as per bcm2835_spi_setup 635 * we would not get called because of error handling there. 636 * the level passed is the electrical level not enabled/disabled 637 * so it has to get translated back to enable/disable 638 * see spi_set_cs in spi.c for the implementation 639 */ 640 641 struct spi_master *master = spi->master; 642 struct bcm2835_spi *bs = spi_master_get_devdata(master); 643 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); 644 bool enable; 645 646 /* calculate the enable flag from the passed gpio_level */ 647 enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level; 648 649 /* set flags for "reverse" polarity in the registers */ 650 if (spi->mode & SPI_CS_HIGH) { 651 /* set the correct CS-bits */ 652 cs |= BCM2835_SPI_CS_CSPOL; 653 cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select; 654 } else { 655 /* clean the CS-bits */ 656 cs &= ~BCM2835_SPI_CS_CSPOL; 657 cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select); 658 } 659 660 /* select the correct chip_select depending on disabled/enabled */ 661 if (enable) { 662 /* set cs correctly */ 663 if (spi->mode & SPI_NO_CS) { 664 /* use the "undefined" chip-select */ 665 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; 666 } else { 667 /* set the chip select */ 668 cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01); 669 cs |= spi->chip_select; 670 } 671 } else { 672 /* disable CSPOL which puts HW-CS into deselected state */ 673 cs &= ~BCM2835_SPI_CS_CSPOL; 674 /* use the "undefined" chip-select as precaution */ 675 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; 676 } 677 678 /* finally set the calculated flags in SPI_CS */ 679 bcm2835_wr(bs, BCM2835_SPI_CS, cs); 680 } 681 682 static int chip_match_name(struct gpio_chip *chip, void *data) 683 { 684 return !strcmp(chip->label, data); 685 } 686 687 static int bcm2835_spi_setup(struct spi_device *spi) 688 { 689 int err; 690 struct gpio_chip *chip; 691 /* 692 * sanity checking the native-chipselects 693 */ 694 if (spi->mode & SPI_NO_CS) 695 return 0; 696 if (gpio_is_valid(spi->cs_gpio)) 697 return 0; 698 if (spi->chip_select > 1) { 699 /* error in the case of native CS requested with CS > 1 700 * officially there is a CS2, but it is not documented 701 * which GPIO is connected with that... 702 */ 703 dev_err(&spi->dev, 704 "setup: only two native chip-selects are supported\n"); 705 return -EINVAL; 706 } 707 /* now translate native cs to GPIO */ 708 709 /* get the gpio chip for the base */ 710 chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); 711 if (!chip) 712 return 0; 713 714 /* and calculate the real CS */ 715 spi->cs_gpio = chip->base + 8 - spi->chip_select; 716 717 /* and set up the "mode" and level */ 718 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", 719 spi->chip_select, spi->cs_gpio); 720 721 /* set up GPIO as output and pull to the correct level */ 722 err = gpio_direction_output(spi->cs_gpio, 723 (spi->mode & SPI_CS_HIGH) ? 0 : 1); 724 if (err) { 725 dev_err(&spi->dev, 726 "could not set CS%i gpio %i as output: %i", 727 spi->chip_select, spi->cs_gpio, err); 728 return err; 729 } 730 731 return 0; 732 } 733 734 static int bcm2835_spi_probe(struct platform_device *pdev) 735 { 736 struct spi_master *master; 737 struct bcm2835_spi *bs; 738 struct resource *res; 739 int err; 740 741 master = spi_alloc_master(&pdev->dev, sizeof(*bs)); 742 if (!master) { 743 dev_err(&pdev->dev, "spi_alloc_master() failed\n"); 744 return -ENOMEM; 745 } 746 747 platform_set_drvdata(pdev, master); 748 749 master->mode_bits = BCM2835_SPI_MODE_BITS; 750 master->bits_per_word_mask = SPI_BPW_MASK(8); 751 master->num_chipselect = 3; 752 master->setup = bcm2835_spi_setup; 753 master->set_cs = bcm2835_spi_set_cs; 754 master->transfer_one = bcm2835_spi_transfer_one; 755 master->handle_err = bcm2835_spi_handle_err; 756 master->prepare_message = bcm2835_spi_prepare_message; 757 master->dev.of_node = pdev->dev.of_node; 758 759 bs = spi_master_get_devdata(master); 760 761 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 762 bs->regs = devm_ioremap_resource(&pdev->dev, res); 763 if (IS_ERR(bs->regs)) { 764 err = PTR_ERR(bs->regs); 765 goto out_master_put; 766 } 767 768 bs->clk = devm_clk_get(&pdev->dev, NULL); 769 if (IS_ERR(bs->clk)) { 770 err = PTR_ERR(bs->clk); 771 dev_err(&pdev->dev, "could not get clk: %d\n", err); 772 goto out_master_put; 773 } 774 775 bs->irq = platform_get_irq(pdev, 0); 776 if (bs->irq <= 0) { 777 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); 778 err = bs->irq ? bs->irq : -ENODEV; 779 goto out_master_put; 780 } 781 782 clk_prepare_enable(bs->clk); 783 784 bcm2835_dma_init(master, &pdev->dev); 785 786 /* initialise the hardware with the default polarities */ 787 bcm2835_wr(bs, BCM2835_SPI_CS, 788 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 789 790 err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, 791 dev_name(&pdev->dev), master); 792 if (err) { 793 dev_err(&pdev->dev, "could not request IRQ: %d\n", err); 794 goto out_clk_disable; 795 } 796 797 err = devm_spi_register_master(&pdev->dev, master); 798 if (err) { 799 dev_err(&pdev->dev, "could not register SPI master: %d\n", err); 800 goto out_clk_disable; 801 } 802 803 return 0; 804 805 out_clk_disable: 806 clk_disable_unprepare(bs->clk); 807 out_master_put: 808 spi_master_put(master); 809 return err; 810 } 811 812 static int bcm2835_spi_remove(struct platform_device *pdev) 813 { 814 struct spi_master *master = platform_get_drvdata(pdev); 815 struct bcm2835_spi *bs = spi_master_get_devdata(master); 816 817 /* Clear FIFOs, and disable the HW block */ 818 bcm2835_wr(bs, BCM2835_SPI_CS, 819 BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); 820 821 clk_disable_unprepare(bs->clk); 822 823 bcm2835_dma_release(master); 824 825 return 0; 826 } 827 828 static const struct of_device_id bcm2835_spi_match[] = { 829 { .compatible = "brcm,bcm2835-spi", }, 830 {} 831 }; 832 MODULE_DEVICE_TABLE(of, bcm2835_spi_match); 833 834 static struct platform_driver bcm2835_spi_driver = { 835 .driver = { 836 .name = DRV_NAME, 837 .of_match_table = bcm2835_spi_match, 838 }, 839 .probe = bcm2835_spi_probe, 840 .remove = bcm2835_spi_remove, 841 }; 842 module_platform_driver(bcm2835_spi_driver); 843 844 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835"); 845 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>"); 846 MODULE_LICENSE("GPL v2"); 847