1 /* 2 * Copyright 2016 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License, version 2, as 6 * published by the Free Software Foundation (the "GPL"). 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License version 2 (GPLv2) for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * version 2 (GPLv2) along with this source code. 15 */ 16 17 #ifndef __SPI_BCM_QSPI_H__ 18 #define __SPI_BCM_QSPI_H__ 19 20 #include <linux/types.h> 21 #include <linux/io.h> 22 23 /* BSPI interrupt masks */ 24 #define INTR_BSPI_LR_OVERREAD_MASK BIT(4) 25 #define INTR_BSPI_LR_SESSION_DONE_MASK BIT(3) 26 #define INTR_BSPI_LR_IMPATIENT_MASK BIT(2) 27 #define INTR_BSPI_LR_SESSION_ABORTED_MASK BIT(1) 28 #define INTR_BSPI_LR_FULLNESS_REACHED_MASK BIT(0) 29 30 #define BSPI_LR_INTERRUPTS_DATA \ 31 (INTR_BSPI_LR_SESSION_DONE_MASK | \ 32 INTR_BSPI_LR_FULLNESS_REACHED_MASK) 33 34 #define BSPI_LR_INTERRUPTS_ERROR \ 35 (INTR_BSPI_LR_OVERREAD_MASK | \ 36 INTR_BSPI_LR_IMPATIENT_MASK | \ 37 INTR_BSPI_LR_SESSION_ABORTED_MASK) 38 39 #define BSPI_LR_INTERRUPTS_ALL \ 40 (BSPI_LR_INTERRUPTS_ERROR | \ 41 BSPI_LR_INTERRUPTS_DATA) 42 43 /* MSPI Interrupt masks */ 44 #define INTR_MSPI_HALTED_MASK BIT(6) 45 #define INTR_MSPI_DONE_MASK BIT(5) 46 47 #define MSPI_INTERRUPTS_ALL \ 48 (INTR_MSPI_DONE_MASK | \ 49 INTR_MSPI_HALTED_MASK) 50 51 #define QSPI_INTERRUPTS_ALL \ 52 (MSPI_INTERRUPTS_ALL | \ 53 BSPI_LR_INTERRUPTS_ALL) 54 55 struct platform_device; 56 struct dev_pm_ops; 57 58 enum { 59 MSPI_DONE = 0x1, 60 BSPI_DONE = 0x2, 61 BSPI_ERR = 0x4, 62 MSPI_BSPI_DONE = 0x7 63 }; 64 65 struct bcm_qspi_soc_intc { 66 void (*bcm_qspi_int_ack)(struct bcm_qspi_soc_intc *soc_intc, int type); 67 void (*bcm_qspi_int_set)(struct bcm_qspi_soc_intc *soc_intc, int type, 68 bool en); 69 u32 (*bcm_qspi_get_int_status)(struct bcm_qspi_soc_intc *soc_intc); 70 }; 71 72 /* Read controller register*/ 73 static inline u32 bcm_qspi_readl(bool be, void __iomem *addr) 74 { 75 if (be) 76 return ioread32be(addr); 77 else 78 return readl_relaxed(addr); 79 } 80 81 /* Write controller register*/ 82 static inline void bcm_qspi_writel(bool be, 83 unsigned int data, void __iomem *addr) 84 { 85 if (be) 86 iowrite32be(data, addr); 87 else 88 writel_relaxed(data, addr); 89 } 90 91 static inline u32 get_qspi_mask(int type) 92 { 93 switch (type) { 94 case MSPI_DONE: 95 return INTR_MSPI_DONE_MASK; 96 case BSPI_DONE: 97 return BSPI_LR_INTERRUPTS_ALL; 98 case MSPI_BSPI_DONE: 99 return QSPI_INTERRUPTS_ALL; 100 case BSPI_ERR: 101 return BSPI_LR_INTERRUPTS_ERROR; 102 } 103 104 return 0; 105 } 106 107 /* The common driver functions to be called by the SoC platform driver */ 108 int bcm_qspi_probe(struct platform_device *pdev, 109 struct bcm_qspi_soc_intc *soc_intc); 110 int bcm_qspi_remove(struct platform_device *pdev); 111 112 /* pm_ops used by the SoC platform driver called on PM suspend/resume */ 113 extern const struct dev_pm_ops bcm_qspi_pm_ops; 114 115 #endif /* __SPI_BCM_QSPI_H__ */ 116