1 /* 2 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers 3 * 4 * Copyright 2016 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License, version 2, as 8 * published by the Free Software Foundation (the "GPL"). 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License version 2 (GPLv2) for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * version 2 (GPLv2) along with this source code. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/device.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/ioport.h> 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/of.h> 29 #include <linux/of_irq.h> 30 #include <linux/platform_device.h> 31 #include <linux/slab.h> 32 #include <linux/spi/spi.h> 33 #include <linux/sysfs.h> 34 #include <linux/types.h> 35 #include "spi-bcm-qspi.h" 36 37 #define DRIVER_NAME "bcm_qspi" 38 39 40 /* BSPI register offsets */ 41 #define BSPI_REVISION_ID 0x000 42 #define BSPI_SCRATCH 0x004 43 #define BSPI_MAST_N_BOOT_CTRL 0x008 44 #define BSPI_BUSY_STATUS 0x00c 45 #define BSPI_INTR_STATUS 0x010 46 #define BSPI_B0_STATUS 0x014 47 #define BSPI_B0_CTRL 0x018 48 #define BSPI_B1_STATUS 0x01c 49 #define BSPI_B1_CTRL 0x020 50 #define BSPI_STRAP_OVERRIDE_CTRL 0x024 51 #define BSPI_FLEX_MODE_ENABLE 0x028 52 #define BSPI_BITS_PER_CYCLE 0x02c 53 #define BSPI_BITS_PER_PHASE 0x030 54 #define BSPI_CMD_AND_MODE_BYTE 0x034 55 #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038 56 #define BSPI_BSPI_XOR_VALUE 0x03c 57 #define BSPI_BSPI_XOR_ENABLE 0x040 58 #define BSPI_BSPI_PIO_MODE_ENABLE 0x044 59 #define BSPI_BSPI_PIO_IODIR 0x048 60 #define BSPI_BSPI_PIO_DATA 0x04c 61 62 /* RAF register offsets */ 63 #define BSPI_RAF_START_ADDR 0x100 64 #define BSPI_RAF_NUM_WORDS 0x104 65 #define BSPI_RAF_CTRL 0x108 66 #define BSPI_RAF_FULLNESS 0x10c 67 #define BSPI_RAF_WATERMARK 0x110 68 #define BSPI_RAF_STATUS 0x114 69 #define BSPI_RAF_READ_DATA 0x118 70 #define BSPI_RAF_WORD_CNT 0x11c 71 #define BSPI_RAF_CURR_ADDR 0x120 72 73 /* Override mode masks */ 74 #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0) 75 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1) 76 #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2) 77 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3) 78 #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4) 79 80 #define BSPI_ADDRLEN_3BYTES 3 81 #define BSPI_ADDRLEN_4BYTES 4 82 83 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1) 84 85 #define BSPI_RAF_CTRL_START_MASK BIT(0) 86 #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1) 87 88 #define BSPI_BPP_MODE_SELECT_MASK BIT(8) 89 #define BSPI_BPP_ADDR_SELECT_MASK BIT(16) 90 91 #define BSPI_READ_LENGTH 512 92 93 /* MSPI register offsets */ 94 #define MSPI_SPCR0_LSB 0x000 95 #define MSPI_SPCR0_MSB 0x004 96 #define MSPI_SPCR1_LSB 0x008 97 #define MSPI_SPCR1_MSB 0x00c 98 #define MSPI_NEWQP 0x010 99 #define MSPI_ENDQP 0x014 100 #define MSPI_SPCR2 0x018 101 #define MSPI_MSPI_STATUS 0x020 102 #define MSPI_CPTQP 0x024 103 #define MSPI_SPCR3 0x028 104 #define MSPI_TXRAM 0x040 105 #define MSPI_RXRAM 0x0c0 106 #define MSPI_CDRAM 0x140 107 #define MSPI_WRITE_LOCK 0x180 108 109 #define MSPI_MASTER_BIT BIT(7) 110 111 #define MSPI_NUM_CDRAM 16 112 #define MSPI_CDRAM_CONT_BIT BIT(7) 113 #define MSPI_CDRAM_BITSE_BIT BIT(6) 114 #define MSPI_CDRAM_PCS 0xf 115 116 #define MSPI_SPCR2_SPE BIT(6) 117 #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7) 118 119 #define MSPI_MSPI_STATUS_SPIF BIT(0) 120 121 #define INTR_BASE_BIT_SHIFT 0x02 122 #define INTR_COUNT 0x07 123 124 #define NUM_CHIPSELECT 4 125 #define QSPI_SPBR_MIN 8U 126 #define QSPI_SPBR_MAX 255U 127 128 #define OPCODE_DIOR 0xBB 129 #define OPCODE_QIOR 0xEB 130 #define OPCODE_DIOR_4B 0xBC 131 #define OPCODE_QIOR_4B 0xEC 132 133 #define MAX_CMD_SIZE 6 134 135 #define ADDR_4MB_MASK GENMASK(22, 0) 136 137 /* stop at end of transfer, no other reason */ 138 #define TRANS_STATUS_BREAK_NONE 0 139 /* stop at end of spi_message */ 140 #define TRANS_STATUS_BREAK_EOM 1 141 /* stop at end of spi_transfer if delay */ 142 #define TRANS_STATUS_BREAK_DELAY 2 143 /* stop at end of spi_transfer if cs_change */ 144 #define TRANS_STATUS_BREAK_CS_CHANGE 4 145 /* stop if we run out of bytes */ 146 #define TRANS_STATUS_BREAK_NO_BYTES 8 147 148 /* events that make us stop filling TX slots */ 149 #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \ 150 TRANS_STATUS_BREAK_DELAY | \ 151 TRANS_STATUS_BREAK_CS_CHANGE) 152 153 /* events that make us deassert CS */ 154 #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \ 155 TRANS_STATUS_BREAK_CS_CHANGE) 156 157 struct bcm_qspi_parms { 158 u32 speed_hz; 159 u8 mode; 160 u8 bits_per_word; 161 }; 162 163 struct bcm_xfer_mode { 164 bool flex_mode; 165 unsigned int width; 166 unsigned int addrlen; 167 unsigned int hp; 168 }; 169 170 enum base_type { 171 MSPI, 172 BSPI, 173 CHIP_SELECT, 174 BASEMAX, 175 }; 176 177 enum irq_source { 178 SINGLE_L2, 179 MUXED_L1, 180 }; 181 182 struct bcm_qspi_irq { 183 const char *irq_name; 184 const irq_handler_t irq_handler; 185 int irq_source; 186 u32 mask; 187 }; 188 189 struct bcm_qspi_dev_id { 190 const struct bcm_qspi_irq *irqp; 191 void *dev; 192 }; 193 194 195 struct qspi_trans { 196 struct spi_transfer *trans; 197 int byte; 198 bool mspi_last_trans; 199 }; 200 201 struct bcm_qspi { 202 struct platform_device *pdev; 203 struct spi_master *master; 204 struct clk *clk; 205 u32 base_clk; 206 u32 max_speed_hz; 207 void __iomem *base[BASEMAX]; 208 209 /* Some SoCs provide custom interrupt status register(s) */ 210 struct bcm_qspi_soc_intc *soc_intc; 211 212 struct bcm_qspi_parms last_parms; 213 struct qspi_trans trans_pos; 214 int curr_cs; 215 int bspi_maj_rev; 216 int bspi_min_rev; 217 int bspi_enabled; 218 struct spi_flash_read_message *bspi_rf_msg; 219 u32 bspi_rf_msg_idx; 220 u32 bspi_rf_msg_len; 221 u32 bspi_rf_msg_status; 222 struct bcm_xfer_mode xfer_mode; 223 u32 s3_strap_override_ctrl; 224 bool bspi_mode; 225 bool big_endian; 226 int num_irqs; 227 struct bcm_qspi_dev_id *dev_ids; 228 struct completion mspi_done; 229 struct completion bspi_done; 230 }; 231 232 static inline bool has_bspi(struct bcm_qspi *qspi) 233 { 234 return qspi->bspi_mode; 235 } 236 237 /* Read qspi controller register*/ 238 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type, 239 unsigned int offset) 240 { 241 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset); 242 } 243 244 /* Write qspi controller register*/ 245 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type, 246 unsigned int offset, unsigned int data) 247 { 248 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset); 249 } 250 251 /* BSPI helpers */ 252 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi) 253 { 254 int i; 255 256 /* this should normally finish within 10us */ 257 for (i = 0; i < 1000; i++) { 258 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1)) 259 return 0; 260 udelay(1); 261 } 262 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n"); 263 return -EIO; 264 } 265 266 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi) 267 { 268 if (qspi->bspi_maj_rev < 4) 269 return true; 270 return false; 271 } 272 273 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi) 274 { 275 bcm_qspi_bspi_busy_poll(qspi); 276 /* Force rising edge for the b0/b1 'flush' field */ 277 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1); 278 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1); 279 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0); 280 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0); 281 } 282 283 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi) 284 { 285 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) & 286 BSPI_RAF_STATUS_FIFO_EMPTY_MASK); 287 } 288 289 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi) 290 { 291 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA); 292 293 /* BSPI v3 LR is LE only, convert data to host endianness */ 294 if (bcm_qspi_bspi_ver_three(qspi)) 295 data = le32_to_cpu(data); 296 297 return data; 298 } 299 300 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi) 301 { 302 bcm_qspi_bspi_busy_poll(qspi); 303 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL, 304 BSPI_RAF_CTRL_START_MASK); 305 } 306 307 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi) 308 { 309 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL, 310 BSPI_RAF_CTRL_CLEAR_MASK); 311 bcm_qspi_bspi_flush_prefetch_buffers(qspi); 312 } 313 314 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi) 315 { 316 u32 *buf = (u32 *)qspi->bspi_rf_msg->buf; 317 u32 data = 0; 318 319 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_msg, 320 qspi->bspi_rf_msg->buf, qspi->bspi_rf_msg_len); 321 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) { 322 data = bcm_qspi_bspi_lr_read_fifo(qspi); 323 if (likely(qspi->bspi_rf_msg_len >= 4) && 324 IS_ALIGNED((uintptr_t)buf, 4)) { 325 buf[qspi->bspi_rf_msg_idx++] = data; 326 qspi->bspi_rf_msg_len -= 4; 327 } else { 328 /* Read out remaining bytes, make sure*/ 329 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_msg_idx]; 330 331 data = cpu_to_le32(data); 332 while (qspi->bspi_rf_msg_len) { 333 *cbuf++ = (u8)data; 334 data >>= 8; 335 qspi->bspi_rf_msg_len--; 336 } 337 } 338 } 339 } 340 341 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte, 342 int bpp, int bpc, int flex_mode) 343 { 344 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0); 345 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc); 346 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp); 347 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte); 348 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode); 349 } 350 351 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, 352 struct spi_flash_read_message *msg, 353 int hp) 354 { 355 int bpc = 0, bpp = 0; 356 u8 command = msg->read_opcode; 357 int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE; 358 int addrlen = msg->addr_width; 359 int addr_nbits = msg->addr_nbits ? msg->addr_nbits : SPI_NBITS_SINGLE; 360 int flex_mode = 1; 361 362 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n", 363 width, addrlen, hp); 364 365 if (addrlen == BSPI_ADDRLEN_4BYTES) 366 bpp = BSPI_BPP_ADDR_SELECT_MASK; 367 368 bpp |= msg->dummy_bytes * (8/addr_nbits); 369 370 switch (width) { 371 case SPI_NBITS_SINGLE: 372 if (addrlen == BSPI_ADDRLEN_3BYTES) 373 /* default mode, does not need flex_cmd */ 374 flex_mode = 0; 375 break; 376 case SPI_NBITS_DUAL: 377 bpc = 0x00000001; 378 if (hp) { 379 bpc |= 0x00010100; /* address and mode are 2-bit */ 380 bpp = BSPI_BPP_MODE_SELECT_MASK; 381 } 382 break; 383 case SPI_NBITS_QUAD: 384 bpc = 0x00000002; 385 if (hp) { 386 bpc |= 0x00020200; /* address and mode are 4-bit */ 387 bpp |= BSPI_BPP_MODE_SELECT_MASK; 388 } 389 break; 390 default: 391 return -EINVAL; 392 } 393 394 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode); 395 396 return 0; 397 } 398 399 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, 400 struct spi_flash_read_message *msg, 401 int hp) 402 { 403 int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE; 404 int addrlen = msg->addr_width; 405 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); 406 407 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n", 408 width, addrlen, hp); 409 410 switch (width) { 411 case SPI_NBITS_SINGLE: 412 /* clear quad/dual mode */ 413 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD | 414 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL); 415 break; 416 case SPI_NBITS_QUAD: 417 /* clear dual mode and set quad mode */ 418 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; 419 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD; 420 break; 421 case SPI_NBITS_DUAL: 422 /* clear quad mode set dual mode */ 423 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD; 424 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; 425 break; 426 default: 427 return -EINVAL; 428 } 429 430 if (addrlen == BSPI_ADDRLEN_4BYTES) 431 /* set 4byte mode*/ 432 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE; 433 else 434 /* clear 4 byte mode */ 435 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE; 436 437 /* set the override mode */ 438 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; 439 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data); 440 bcm_qspi_bspi_set_xfer_params(qspi, msg->read_opcode, 0, 0, 0); 441 442 return 0; 443 } 444 445 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi, 446 struct spi_flash_read_message *msg, int hp) 447 { 448 int error = 0; 449 int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE; 450 int addrlen = msg->addr_width; 451 452 /* default mode */ 453 qspi->xfer_mode.flex_mode = true; 454 455 if (!bcm_qspi_bspi_ver_three(qspi)) { 456 u32 val, mask; 457 458 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); 459 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; 460 if (val & mask || qspi->s3_strap_override_ctrl & mask) { 461 qspi->xfer_mode.flex_mode = false; 462 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0); 463 error = bcm_qspi_bspi_set_override(qspi, msg, hp); 464 } 465 } 466 467 if (qspi->xfer_mode.flex_mode) 468 error = bcm_qspi_bspi_set_flex_mode(qspi, msg, hp); 469 470 if (error) { 471 dev_warn(&qspi->pdev->dev, 472 "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n", 473 width, addrlen, hp); 474 } else if (qspi->xfer_mode.width != width || 475 qspi->xfer_mode.addrlen != addrlen || 476 qspi->xfer_mode.hp != hp) { 477 qspi->xfer_mode.width = width; 478 qspi->xfer_mode.addrlen = addrlen; 479 qspi->xfer_mode.hp = hp; 480 dev_dbg(&qspi->pdev->dev, 481 "cs:%d %d-lane output, %d-byte address%s\n", 482 qspi->curr_cs, 483 qspi->xfer_mode.width, 484 qspi->xfer_mode.addrlen, 485 qspi->xfer_mode.hp != -1 ? ", hp mode" : ""); 486 } 487 488 return error; 489 } 490 491 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) 492 { 493 if (!has_bspi(qspi) || (qspi->bspi_enabled)) 494 return; 495 496 qspi->bspi_enabled = 1; 497 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0) 498 return; 499 500 bcm_qspi_bspi_flush_prefetch_buffers(qspi); 501 udelay(1); 502 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0); 503 udelay(1); 504 } 505 506 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) 507 { 508 if (!has_bspi(qspi) || (!qspi->bspi_enabled)) 509 return; 510 511 qspi->bspi_enabled = 0; 512 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1)) 513 return; 514 515 bcm_qspi_bspi_busy_poll(qspi); 516 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1); 517 udelay(1); 518 } 519 520 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs) 521 { 522 u32 data = 0; 523 524 if (qspi->curr_cs == cs) 525 return; 526 if (qspi->base[CHIP_SELECT]) { 527 data = bcm_qspi_read(qspi, CHIP_SELECT, 0); 528 data = (data & ~0xff) | (1 << cs); 529 bcm_qspi_write(qspi, CHIP_SELECT, 0, data); 530 usleep_range(10, 20); 531 } 532 qspi->curr_cs = cs; 533 } 534 535 /* MSPI helpers */ 536 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, 537 const struct bcm_qspi_parms *xp) 538 { 539 u32 spcr, spbr = 0; 540 541 if (xp->speed_hz) 542 spbr = qspi->base_clk / (2 * xp->speed_hz); 543 544 spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX); 545 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr); 546 547 spcr = MSPI_MASTER_BIT; 548 /* for 16 bit the data should be zero */ 549 if (xp->bits_per_word != 16) 550 spcr |= xp->bits_per_word << 2; 551 spcr |= xp->mode & 3; 552 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); 553 554 qspi->last_parms = *xp; 555 } 556 557 static void bcm_qspi_update_parms(struct bcm_qspi *qspi, 558 struct spi_device *spi, 559 struct spi_transfer *trans) 560 { 561 struct bcm_qspi_parms xp; 562 563 xp.speed_hz = trans->speed_hz; 564 xp.bits_per_word = trans->bits_per_word; 565 xp.mode = spi->mode; 566 567 bcm_qspi_hw_set_parms(qspi, &xp); 568 } 569 570 static int bcm_qspi_setup(struct spi_device *spi) 571 { 572 struct bcm_qspi_parms *xp; 573 574 if (spi->bits_per_word > 16) 575 return -EINVAL; 576 577 xp = spi_get_ctldata(spi); 578 if (!xp) { 579 xp = kzalloc(sizeof(*xp), GFP_KERNEL); 580 if (!xp) 581 return -ENOMEM; 582 spi_set_ctldata(spi, xp); 583 } 584 xp->speed_hz = spi->max_speed_hz; 585 xp->mode = spi->mode; 586 587 if (spi->bits_per_word) 588 xp->bits_per_word = spi->bits_per_word; 589 else 590 xp->bits_per_word = 8; 591 592 return 0; 593 } 594 595 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi, 596 struct qspi_trans *qt) 597 { 598 if (qt->mspi_last_trans && 599 spi_transfer_is_last(qspi->master, qt->trans)) 600 return true; 601 else 602 return false; 603 } 604 605 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi, 606 struct qspi_trans *qt, int flags) 607 { 608 int ret = TRANS_STATUS_BREAK_NONE; 609 610 /* count the last transferred bytes */ 611 if (qt->trans->bits_per_word <= 8) 612 qt->byte++; 613 else 614 qt->byte += 2; 615 616 if (qt->byte >= qt->trans->len) { 617 /* we're at the end of the spi_transfer */ 618 /* in TX mode, need to pause for a delay or CS change */ 619 if (qt->trans->delay_usecs && 620 (flags & TRANS_STATUS_BREAK_DELAY)) 621 ret |= TRANS_STATUS_BREAK_DELAY; 622 if (qt->trans->cs_change && 623 (flags & TRANS_STATUS_BREAK_CS_CHANGE)) 624 ret |= TRANS_STATUS_BREAK_CS_CHANGE; 625 if (ret) 626 goto done; 627 628 dev_dbg(&qspi->pdev->dev, "advance msg exit\n"); 629 if (bcm_qspi_mspi_transfer_is_last(qspi, qt)) 630 ret = TRANS_STATUS_BREAK_EOM; 631 else 632 ret = TRANS_STATUS_BREAK_NO_BYTES; 633 634 qt->trans = NULL; 635 } 636 637 done: 638 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n", 639 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret); 640 return ret; 641 } 642 643 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot) 644 { 645 u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4; 646 647 /* mask out reserved bits */ 648 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff; 649 } 650 651 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot) 652 { 653 u32 reg_offset = MSPI_RXRAM; 654 u32 lsb_offset = reg_offset + (slot << 3) + 0x4; 655 u32 msb_offset = reg_offset + (slot << 3); 656 657 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) | 658 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8); 659 } 660 661 static void read_from_hw(struct bcm_qspi *qspi, int slots) 662 { 663 struct qspi_trans tp; 664 int slot; 665 666 bcm_qspi_disable_bspi(qspi); 667 668 if (slots > MSPI_NUM_CDRAM) { 669 /* should never happen */ 670 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__); 671 return; 672 } 673 674 tp = qspi->trans_pos; 675 676 for (slot = 0; slot < slots; slot++) { 677 if (tp.trans->bits_per_word <= 8) { 678 u8 *buf = tp.trans->rx_buf; 679 680 if (buf) 681 buf[tp.byte] = read_rxram_slot_u8(qspi, slot); 682 dev_dbg(&qspi->pdev->dev, "RD %02x\n", 683 buf ? buf[tp.byte] : 0xff); 684 } else { 685 u16 *buf = tp.trans->rx_buf; 686 687 if (buf) 688 buf[tp.byte / 2] = read_rxram_slot_u16(qspi, 689 slot); 690 dev_dbg(&qspi->pdev->dev, "RD %04x\n", 691 buf ? buf[tp.byte] : 0xffff); 692 } 693 694 update_qspi_trans_byte_count(qspi, &tp, 695 TRANS_STATUS_BREAK_NONE); 696 } 697 698 qspi->trans_pos = tp; 699 } 700 701 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot, 702 u8 val) 703 { 704 u32 reg_offset = MSPI_TXRAM + (slot << 3); 705 706 /* mask out reserved bits */ 707 bcm_qspi_write(qspi, MSPI, reg_offset, val); 708 } 709 710 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot, 711 u16 val) 712 { 713 u32 reg_offset = MSPI_TXRAM; 714 u32 msb_offset = reg_offset + (slot << 3); 715 u32 lsb_offset = reg_offset + (slot << 3) + 0x4; 716 717 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8)); 718 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff)); 719 } 720 721 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot) 722 { 723 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2)); 724 } 725 726 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val) 727 { 728 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val); 729 } 730 731 /* Return number of slots written */ 732 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) 733 { 734 struct qspi_trans tp; 735 int slot = 0, tstatus = 0; 736 u32 mspi_cdram = 0; 737 738 bcm_qspi_disable_bspi(qspi); 739 tp = qspi->trans_pos; 740 bcm_qspi_update_parms(qspi, spi, tp.trans); 741 742 /* Run until end of transfer or reached the max data */ 743 while (!tstatus && slot < MSPI_NUM_CDRAM) { 744 if (tp.trans->bits_per_word <= 8) { 745 const u8 *buf = tp.trans->tx_buf; 746 u8 val = buf ? buf[tp.byte] : 0xff; 747 748 write_txram_slot_u8(qspi, slot, val); 749 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val); 750 } else { 751 const u16 *buf = tp.trans->tx_buf; 752 u16 val = buf ? buf[tp.byte / 2] : 0xffff; 753 754 write_txram_slot_u16(qspi, slot, val); 755 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); 756 } 757 mspi_cdram = MSPI_CDRAM_CONT_BIT; 758 mspi_cdram |= (~(1 << spi->chip_select) & 759 MSPI_CDRAM_PCS); 760 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 : 761 MSPI_CDRAM_BITSE_BIT); 762 763 write_cdram_slot(qspi, slot, mspi_cdram); 764 765 tstatus = update_qspi_trans_byte_count(qspi, &tp, 766 TRANS_STATUS_BREAK_TX); 767 slot++; 768 } 769 770 if (!slot) { 771 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__); 772 goto done; 773 } 774 775 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot); 776 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); 777 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1); 778 779 if (tstatus & TRANS_STATUS_BREAK_DESELECT) { 780 mspi_cdram = read_cdram_slot(qspi, slot - 1) & 781 ~MSPI_CDRAM_CONT_BIT; 782 write_cdram_slot(qspi, slot - 1, mspi_cdram); 783 } 784 785 if (has_bspi(qspi)) 786 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1); 787 788 /* Must flush previous writes before starting MSPI operation */ 789 mb(); 790 /* Set cont | spe | spifie */ 791 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0); 792 793 done: 794 return slot; 795 } 796 797 static int bcm_qspi_bspi_flash_read(struct spi_device *spi, 798 struct spi_flash_read_message *msg) 799 { 800 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); 801 u32 addr = 0, len, rdlen, len_words; 802 int ret = 0; 803 unsigned long timeo = msecs_to_jiffies(100); 804 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 805 806 if (bcm_qspi_bspi_ver_three(qspi)) 807 if (msg->addr_width == BSPI_ADDRLEN_4BYTES) 808 return -EIO; 809 810 bcm_qspi_chip_select(qspi, spi->chip_select); 811 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); 812 813 /* 814 * when using flex mode we need to send 815 * the upper address byte to bspi 816 */ 817 if (bcm_qspi_bspi_ver_three(qspi) == false) { 818 addr = msg->from & 0xff000000; 819 bcm_qspi_write(qspi, BSPI, 820 BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr); 821 } 822 823 if (!qspi->xfer_mode.flex_mode) 824 addr = msg->from; 825 else 826 addr = msg->from & 0x00ffffff; 827 828 if (bcm_qspi_bspi_ver_three(qspi) == true) 829 addr = (addr + 0xc00000) & 0xffffff; 830 831 /* 832 * read into the entire buffer by breaking the reads 833 * into RAF buffer read lengths 834 */ 835 len = msg->len; 836 qspi->bspi_rf_msg_idx = 0; 837 838 do { 839 if (len > BSPI_READ_LENGTH) 840 rdlen = BSPI_READ_LENGTH; 841 else 842 rdlen = len; 843 844 reinit_completion(&qspi->bspi_done); 845 bcm_qspi_enable_bspi(qspi); 846 len_words = (rdlen + 3) >> 2; 847 qspi->bspi_rf_msg = msg; 848 qspi->bspi_rf_msg_status = 0; 849 qspi->bspi_rf_msg_len = rdlen; 850 dev_dbg(&qspi->pdev->dev, 851 "bspi xfr addr 0x%x len 0x%x", addr, rdlen); 852 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr); 853 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words); 854 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0); 855 if (qspi->soc_intc) { 856 /* 857 * clear soc MSPI and BSPI interrupts and enable 858 * BSPI interrupts. 859 */ 860 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE); 861 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true); 862 } 863 864 /* Must flush previous writes before starting BSPI operation */ 865 mb(); 866 bcm_qspi_bspi_lr_start(qspi); 867 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) { 868 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n"); 869 ret = -ETIMEDOUT; 870 break; 871 } 872 873 /* set msg return length */ 874 msg->retlen += rdlen; 875 addr += rdlen; 876 len -= rdlen; 877 } while (len); 878 879 return ret; 880 } 881 882 static int bcm_qspi_transfer_one(struct spi_master *master, 883 struct spi_device *spi, 884 struct spi_transfer *trans) 885 { 886 struct bcm_qspi *qspi = spi_master_get_devdata(master); 887 int slots; 888 unsigned long timeo = msecs_to_jiffies(100); 889 890 bcm_qspi_chip_select(qspi, spi->chip_select); 891 qspi->trans_pos.trans = trans; 892 qspi->trans_pos.byte = 0; 893 894 while (qspi->trans_pos.byte < trans->len) { 895 reinit_completion(&qspi->mspi_done); 896 897 slots = write_to_hw(qspi, spi); 898 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) { 899 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n"); 900 return -ETIMEDOUT; 901 } 902 903 read_from_hw(qspi, slots); 904 } 905 906 return 0; 907 } 908 909 static int bcm_qspi_mspi_flash_read(struct spi_device *spi, 910 struct spi_flash_read_message *msg) 911 { 912 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); 913 struct spi_transfer t[2]; 914 u8 cmd[6]; 915 int ret; 916 917 memset(cmd, 0, sizeof(cmd)); 918 memset(t, 0, sizeof(t)); 919 920 /* tx */ 921 /* opcode is in cmd[0] */ 922 cmd[0] = msg->read_opcode; 923 cmd[1] = msg->from >> (msg->addr_width * 8 - 8); 924 cmd[2] = msg->from >> (msg->addr_width * 8 - 16); 925 cmd[3] = msg->from >> (msg->addr_width * 8 - 24); 926 cmd[4] = msg->from >> (msg->addr_width * 8 - 32); 927 t[0].tx_buf = cmd; 928 t[0].len = msg->addr_width + msg->dummy_bytes + 1; 929 t[0].bits_per_word = spi->bits_per_word; 930 t[0].tx_nbits = msg->opcode_nbits; 931 /* lets mspi know that this is not last transfer */ 932 qspi->trans_pos.mspi_last_trans = false; 933 ret = bcm_qspi_transfer_one(spi->master, spi, &t[0]); 934 935 /* rx */ 936 qspi->trans_pos.mspi_last_trans = true; 937 if (!ret) { 938 /* rx */ 939 t[1].rx_buf = msg->buf; 940 t[1].len = msg->len; 941 t[1].rx_nbits = msg->data_nbits; 942 t[1].bits_per_word = spi->bits_per_word; 943 ret = bcm_qspi_transfer_one(spi->master, spi, &t[1]); 944 } 945 946 if (!ret) 947 msg->retlen = msg->len; 948 949 return ret; 950 } 951 952 static int bcm_qspi_flash_read(struct spi_device *spi, 953 struct spi_flash_read_message *msg) 954 { 955 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); 956 int ret = 0; 957 bool mspi_read = false; 958 u32 addr, len; 959 u_char *buf; 960 961 buf = msg->buf; 962 addr = msg->from; 963 len = msg->len; 964 965 if (bcm_qspi_bspi_ver_three(qspi) == true) { 966 /* 967 * The address coming into this function is a raw flash offset. 968 * But for BSPI <= V3, we need to convert it to a remapped BSPI 969 * address. If it crosses a 4MB boundary, just revert back to 970 * using MSPI. 971 */ 972 addr = (addr + 0xc00000) & 0xffffff; 973 974 if ((~ADDR_4MB_MASK & addr) ^ 975 (~ADDR_4MB_MASK & (addr + len - 1))) 976 mspi_read = true; 977 } 978 979 /* non-aligned and very short transfers are handled by MSPI */ 980 if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) || 981 len < 4) 982 mspi_read = true; 983 984 if (mspi_read) 985 return bcm_qspi_mspi_flash_read(spi, msg); 986 987 ret = bcm_qspi_bspi_set_mode(qspi, msg, -1); 988 989 if (!ret) 990 ret = bcm_qspi_bspi_flash_read(spi, msg); 991 992 return ret; 993 } 994 995 static void bcm_qspi_cleanup(struct spi_device *spi) 996 { 997 struct bcm_qspi_parms *xp = spi_get_ctldata(spi); 998 999 kfree(xp); 1000 } 1001 1002 static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id) 1003 { 1004 struct bcm_qspi_dev_id *qspi_dev_id = dev_id; 1005 struct bcm_qspi *qspi = qspi_dev_id->dev; 1006 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS); 1007 1008 if (status & MSPI_MSPI_STATUS_SPIF) { 1009 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1010 /* clear interrupt */ 1011 status &= ~MSPI_MSPI_STATUS_SPIF; 1012 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status); 1013 if (qspi->soc_intc) 1014 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE); 1015 complete(&qspi->mspi_done); 1016 return IRQ_HANDLED; 1017 } 1018 1019 return IRQ_NONE; 1020 } 1021 1022 static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id) 1023 { 1024 struct bcm_qspi_dev_id *qspi_dev_id = dev_id; 1025 struct bcm_qspi *qspi = qspi_dev_id->dev; 1026 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1027 u32 status = qspi_dev_id->irqp->mask; 1028 1029 if (qspi->bspi_enabled && qspi->bspi_rf_msg) { 1030 bcm_qspi_bspi_lr_data_read(qspi); 1031 if (qspi->bspi_rf_msg_len == 0) { 1032 qspi->bspi_rf_msg = NULL; 1033 if (qspi->soc_intc) { 1034 /* disable soc BSPI interrupt */ 1035 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, 1036 false); 1037 /* indicate done */ 1038 status = INTR_BSPI_LR_SESSION_DONE_MASK; 1039 } 1040 1041 if (qspi->bspi_rf_msg_status) 1042 bcm_qspi_bspi_lr_clear(qspi); 1043 else 1044 bcm_qspi_bspi_flush_prefetch_buffers(qspi); 1045 } 1046 1047 if (qspi->soc_intc) 1048 /* clear soc BSPI interrupt */ 1049 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE); 1050 } 1051 1052 status &= INTR_BSPI_LR_SESSION_DONE_MASK; 1053 if (qspi->bspi_enabled && status && qspi->bspi_rf_msg_len == 0) 1054 complete(&qspi->bspi_done); 1055 1056 return IRQ_HANDLED; 1057 } 1058 1059 static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id) 1060 { 1061 struct bcm_qspi_dev_id *qspi_dev_id = dev_id; 1062 struct bcm_qspi *qspi = qspi_dev_id->dev; 1063 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1064 1065 dev_err(&qspi->pdev->dev, "BSPI INT error\n"); 1066 qspi->bspi_rf_msg_status = -EIO; 1067 if (qspi->soc_intc) 1068 /* clear soc interrupt */ 1069 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR); 1070 1071 complete(&qspi->bspi_done); 1072 return IRQ_HANDLED; 1073 } 1074 1075 static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id) 1076 { 1077 struct bcm_qspi_dev_id *qspi_dev_id = dev_id; 1078 struct bcm_qspi *qspi = qspi_dev_id->dev; 1079 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1080 irqreturn_t ret = IRQ_NONE; 1081 1082 if (soc_intc) { 1083 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc); 1084 1085 if (status & MSPI_DONE) 1086 ret = bcm_qspi_mspi_l2_isr(irq, dev_id); 1087 else if (status & BSPI_DONE) 1088 ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id); 1089 else if (status & BSPI_ERR) 1090 ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id); 1091 } 1092 1093 return ret; 1094 } 1095 1096 static const struct bcm_qspi_irq qspi_irq_tab[] = { 1097 { 1098 .irq_name = "spi_lr_fullness_reached", 1099 .irq_handler = bcm_qspi_bspi_lr_l2_isr, 1100 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK, 1101 }, 1102 { 1103 .irq_name = "spi_lr_session_aborted", 1104 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, 1105 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK, 1106 }, 1107 { 1108 .irq_name = "spi_lr_impatient", 1109 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, 1110 .mask = INTR_BSPI_LR_IMPATIENT_MASK, 1111 }, 1112 { 1113 .irq_name = "spi_lr_session_done", 1114 .irq_handler = bcm_qspi_bspi_lr_l2_isr, 1115 .mask = INTR_BSPI_LR_SESSION_DONE_MASK, 1116 }, 1117 #ifdef QSPI_INT_DEBUG 1118 /* this interrupt is for debug purposes only, dont request irq */ 1119 { 1120 .irq_name = "spi_lr_overread", 1121 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, 1122 .mask = INTR_BSPI_LR_OVERREAD_MASK, 1123 }, 1124 #endif 1125 { 1126 .irq_name = "mspi_done", 1127 .irq_handler = bcm_qspi_mspi_l2_isr, 1128 .mask = INTR_MSPI_DONE_MASK, 1129 }, 1130 { 1131 .irq_name = "mspi_halted", 1132 .irq_handler = bcm_qspi_mspi_l2_isr, 1133 .mask = INTR_MSPI_HALTED_MASK, 1134 }, 1135 { 1136 /* single muxed L1 interrupt source */ 1137 .irq_name = "spi_l1_intr", 1138 .irq_handler = bcm_qspi_l1_isr, 1139 .irq_source = MUXED_L1, 1140 .mask = QSPI_INTERRUPTS_ALL, 1141 }, 1142 }; 1143 1144 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi) 1145 { 1146 u32 val = 0; 1147 1148 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID); 1149 qspi->bspi_maj_rev = (val >> 8) & 0xff; 1150 qspi->bspi_min_rev = val & 0xff; 1151 if (!(bcm_qspi_bspi_ver_three(qspi))) { 1152 /* Force mapping of BSPI address -> flash offset */ 1153 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0); 1154 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1); 1155 } 1156 qspi->bspi_enabled = 1; 1157 bcm_qspi_disable_bspi(qspi); 1158 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0); 1159 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0); 1160 } 1161 1162 static void bcm_qspi_hw_init(struct bcm_qspi *qspi) 1163 { 1164 struct bcm_qspi_parms parms; 1165 1166 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0); 1167 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0); 1168 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); 1169 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0); 1170 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20); 1171 1172 parms.mode = SPI_MODE_3; 1173 parms.bits_per_word = 8; 1174 parms.speed_hz = qspi->max_speed_hz; 1175 bcm_qspi_hw_set_parms(qspi, &parms); 1176 1177 if (has_bspi(qspi)) 1178 bcm_qspi_bspi_init(qspi); 1179 } 1180 1181 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi) 1182 { 1183 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0); 1184 if (has_bspi(qspi)) 1185 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); 1186 1187 } 1188 1189 static const struct of_device_id bcm_qspi_of_match[] = { 1190 { .compatible = "brcm,spi-bcm-qspi" }, 1191 {}, 1192 }; 1193 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); 1194 1195 int bcm_qspi_probe(struct platform_device *pdev, 1196 struct bcm_qspi_soc_intc *soc_intc) 1197 { 1198 struct device *dev = &pdev->dev; 1199 struct bcm_qspi *qspi; 1200 struct spi_master *master; 1201 struct resource *res; 1202 int irq, ret = 0, num_ints = 0; 1203 u32 val; 1204 const char *name = NULL; 1205 int num_irqs = ARRAY_SIZE(qspi_irq_tab); 1206 1207 /* We only support device-tree instantiation */ 1208 if (!dev->of_node) 1209 return -ENODEV; 1210 1211 if (!of_match_node(bcm_qspi_of_match, dev->of_node)) 1212 return -ENODEV; 1213 1214 master = spi_alloc_master(dev, sizeof(struct bcm_qspi)); 1215 if (!master) { 1216 dev_err(dev, "error allocating spi_master\n"); 1217 return -ENOMEM; 1218 } 1219 1220 qspi = spi_master_get_devdata(master); 1221 qspi->pdev = pdev; 1222 qspi->trans_pos.trans = NULL; 1223 qspi->trans_pos.byte = 0; 1224 qspi->trans_pos.mspi_last_trans = true; 1225 qspi->master = master; 1226 1227 master->bus_num = -1; 1228 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD; 1229 master->setup = bcm_qspi_setup; 1230 master->transfer_one = bcm_qspi_transfer_one; 1231 master->spi_flash_read = bcm_qspi_flash_read; 1232 master->cleanup = bcm_qspi_cleanup; 1233 master->dev.of_node = dev->of_node; 1234 master->num_chipselect = NUM_CHIPSELECT; 1235 1236 qspi->big_endian = of_device_is_big_endian(dev->of_node); 1237 1238 if (!of_property_read_u32(dev->of_node, "num-cs", &val)) 1239 master->num_chipselect = val; 1240 1241 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi"); 1242 if (!res) 1243 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1244 "mspi"); 1245 1246 if (res) { 1247 qspi->base[MSPI] = devm_ioremap_resource(dev, res); 1248 if (IS_ERR(qspi->base[MSPI])) { 1249 ret = PTR_ERR(qspi->base[MSPI]); 1250 goto qspi_probe_err; 1251 } 1252 } else { 1253 goto qspi_resource_err; 1254 } 1255 1256 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi"); 1257 if (res) { 1258 qspi->base[BSPI] = devm_ioremap_resource(dev, res); 1259 if (IS_ERR(qspi->base[BSPI])) { 1260 ret = PTR_ERR(qspi->base[BSPI]); 1261 goto qspi_probe_err; 1262 } 1263 qspi->bspi_mode = true; 1264 } else { 1265 qspi->bspi_mode = false; 1266 } 1267 1268 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : ""); 1269 1270 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg"); 1271 if (res) { 1272 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res); 1273 if (IS_ERR(qspi->base[CHIP_SELECT])) { 1274 ret = PTR_ERR(qspi->base[CHIP_SELECT]); 1275 goto qspi_resource_err; 1276 } 1277 } 1278 1279 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id), 1280 GFP_KERNEL); 1281 if (!qspi->dev_ids) { 1282 ret = -ENOMEM; 1283 goto qspi_resource_err; 1284 } 1285 1286 for (val = 0; val < num_irqs; val++) { 1287 irq = -1; 1288 name = qspi_irq_tab[val].irq_name; 1289 if (qspi_irq_tab[val].irq_source == SINGLE_L2) { 1290 /* get the l2 interrupts */ 1291 irq = platform_get_irq_byname(pdev, name); 1292 } else if (!num_ints && soc_intc) { 1293 /* all mspi, bspi intrs muxed to one L1 intr */ 1294 irq = platform_get_irq(pdev, 0); 1295 } 1296 1297 if (irq >= 0) { 1298 ret = devm_request_irq(&pdev->dev, irq, 1299 qspi_irq_tab[val].irq_handler, 0, 1300 name, 1301 &qspi->dev_ids[val]); 1302 if (ret < 0) { 1303 dev_err(&pdev->dev, "IRQ %s not found\n", name); 1304 goto qspi_probe_err; 1305 } 1306 1307 qspi->dev_ids[val].dev = qspi; 1308 qspi->dev_ids[val].irqp = &qspi_irq_tab[val]; 1309 num_ints++; 1310 dev_dbg(&pdev->dev, "registered IRQ %s %d\n", 1311 qspi_irq_tab[val].irq_name, 1312 irq); 1313 } 1314 } 1315 1316 if (!num_ints) { 1317 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n"); 1318 ret = -EINVAL; 1319 goto qspi_probe_err; 1320 } 1321 1322 /* 1323 * Some SoCs integrate spi controller (e.g., its interrupt bits) 1324 * in specific ways 1325 */ 1326 if (soc_intc) { 1327 qspi->soc_intc = soc_intc; 1328 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true); 1329 } else { 1330 qspi->soc_intc = NULL; 1331 } 1332 1333 qspi->clk = devm_clk_get(&pdev->dev, NULL); 1334 if (IS_ERR(qspi->clk)) { 1335 dev_warn(dev, "unable to get clock\n"); 1336 ret = PTR_ERR(qspi->clk); 1337 goto qspi_probe_err; 1338 } 1339 1340 ret = clk_prepare_enable(qspi->clk); 1341 if (ret) { 1342 dev_err(dev, "failed to prepare clock\n"); 1343 goto qspi_probe_err; 1344 } 1345 1346 qspi->base_clk = clk_get_rate(qspi->clk); 1347 qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); 1348 1349 bcm_qspi_hw_init(qspi); 1350 init_completion(&qspi->mspi_done); 1351 init_completion(&qspi->bspi_done); 1352 qspi->curr_cs = -1; 1353 1354 platform_set_drvdata(pdev, qspi); 1355 1356 qspi->xfer_mode.width = -1; 1357 qspi->xfer_mode.addrlen = -1; 1358 qspi->xfer_mode.hp = -1; 1359 1360 ret = devm_spi_register_master(&pdev->dev, master); 1361 if (ret < 0) { 1362 dev_err(dev, "can't register master\n"); 1363 goto qspi_reg_err; 1364 } 1365 1366 return 0; 1367 1368 qspi_reg_err: 1369 bcm_qspi_hw_uninit(qspi); 1370 clk_disable_unprepare(qspi->clk); 1371 qspi_probe_err: 1372 kfree(qspi->dev_ids); 1373 qspi_resource_err: 1374 spi_master_put(master); 1375 return ret; 1376 } 1377 /* probe function to be called by SoC specific platform driver probe */ 1378 EXPORT_SYMBOL_GPL(bcm_qspi_probe); 1379 1380 int bcm_qspi_remove(struct platform_device *pdev) 1381 { 1382 struct bcm_qspi *qspi = platform_get_drvdata(pdev); 1383 1384 bcm_qspi_hw_uninit(qspi); 1385 clk_disable_unprepare(qspi->clk); 1386 kfree(qspi->dev_ids); 1387 spi_unregister_master(qspi->master); 1388 1389 return 0; 1390 } 1391 /* function to be called by SoC specific platform driver remove() */ 1392 EXPORT_SYMBOL_GPL(bcm_qspi_remove); 1393 1394 static int __maybe_unused bcm_qspi_suspend(struct device *dev) 1395 { 1396 struct bcm_qspi *qspi = dev_get_drvdata(dev); 1397 1398 /* store the override strap value */ 1399 if (!bcm_qspi_bspi_ver_three(qspi)) 1400 qspi->s3_strap_override_ctrl = 1401 bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); 1402 1403 spi_master_suspend(qspi->master); 1404 clk_disable(qspi->clk); 1405 bcm_qspi_hw_uninit(qspi); 1406 1407 return 0; 1408 }; 1409 1410 static int __maybe_unused bcm_qspi_resume(struct device *dev) 1411 { 1412 struct bcm_qspi *qspi = dev_get_drvdata(dev); 1413 int ret = 0; 1414 1415 bcm_qspi_hw_init(qspi); 1416 bcm_qspi_chip_select(qspi, qspi->curr_cs); 1417 if (qspi->soc_intc) 1418 /* enable MSPI interrupt */ 1419 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE, 1420 true); 1421 1422 ret = clk_enable(qspi->clk); 1423 if (!ret) 1424 spi_master_resume(qspi->master); 1425 1426 return ret; 1427 } 1428 1429 SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume); 1430 1431 /* pm_ops to be called by SoC specific platform driver */ 1432 EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops); 1433 1434 MODULE_AUTHOR("Kamal Dasu"); 1435 MODULE_DESCRIPTION("Broadcom QSPI driver"); 1436 MODULE_LICENSE("GPL v2"); 1437 MODULE_ALIAS("platform:" DRIVER_NAME); 1438