1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers 4 * 5 * Copyright 2016 Broadcom 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi-mem.h> 23 #include <linux/sysfs.h> 24 #include <linux/types.h> 25 #include "spi-bcm-qspi.h" 26 27 #define DRIVER_NAME "bcm_qspi" 28 29 30 /* BSPI register offsets */ 31 #define BSPI_REVISION_ID 0x000 32 #define BSPI_SCRATCH 0x004 33 #define BSPI_MAST_N_BOOT_CTRL 0x008 34 #define BSPI_BUSY_STATUS 0x00c 35 #define BSPI_INTR_STATUS 0x010 36 #define BSPI_B0_STATUS 0x014 37 #define BSPI_B0_CTRL 0x018 38 #define BSPI_B1_STATUS 0x01c 39 #define BSPI_B1_CTRL 0x020 40 #define BSPI_STRAP_OVERRIDE_CTRL 0x024 41 #define BSPI_FLEX_MODE_ENABLE 0x028 42 #define BSPI_BITS_PER_CYCLE 0x02c 43 #define BSPI_BITS_PER_PHASE 0x030 44 #define BSPI_CMD_AND_MODE_BYTE 0x034 45 #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038 46 #define BSPI_BSPI_XOR_VALUE 0x03c 47 #define BSPI_BSPI_XOR_ENABLE 0x040 48 #define BSPI_BSPI_PIO_MODE_ENABLE 0x044 49 #define BSPI_BSPI_PIO_IODIR 0x048 50 #define BSPI_BSPI_PIO_DATA 0x04c 51 52 /* RAF register offsets */ 53 #define BSPI_RAF_START_ADDR 0x100 54 #define BSPI_RAF_NUM_WORDS 0x104 55 #define BSPI_RAF_CTRL 0x108 56 #define BSPI_RAF_FULLNESS 0x10c 57 #define BSPI_RAF_WATERMARK 0x110 58 #define BSPI_RAF_STATUS 0x114 59 #define BSPI_RAF_READ_DATA 0x118 60 #define BSPI_RAF_WORD_CNT 0x11c 61 #define BSPI_RAF_CURR_ADDR 0x120 62 63 /* Override mode masks */ 64 #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE BIT(0) 65 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL BIT(1) 66 #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2) 67 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD BIT(3) 68 #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE BIT(4) 69 70 #define BSPI_ADDRLEN_3BYTES 3 71 #define BSPI_ADDRLEN_4BYTES 4 72 73 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1) 74 75 #define BSPI_RAF_CTRL_START_MASK BIT(0) 76 #define BSPI_RAF_CTRL_CLEAR_MASK BIT(1) 77 78 #define BSPI_BPP_MODE_SELECT_MASK BIT(8) 79 #define BSPI_BPP_ADDR_SELECT_MASK BIT(16) 80 81 #define BSPI_READ_LENGTH 256 82 83 /* MSPI register offsets */ 84 #define MSPI_SPCR0_LSB 0x000 85 #define MSPI_SPCR0_MSB 0x004 86 #define MSPI_SPCR0_MSB_CPHA BIT(0) 87 #define MSPI_SPCR0_MSB_CPOL BIT(1) 88 #define MSPI_SPCR0_MSB_BITS_SHIFT 0x2 89 #define MSPI_SPCR1_LSB 0x008 90 #define MSPI_SPCR1_MSB 0x00c 91 #define MSPI_NEWQP 0x010 92 #define MSPI_ENDQP 0x014 93 #define MSPI_SPCR2 0x018 94 #define MSPI_MSPI_STATUS 0x020 95 #define MSPI_CPTQP 0x024 96 #define MSPI_SPCR3 0x028 97 #define MSPI_REV 0x02c 98 #define MSPI_TXRAM 0x040 99 #define MSPI_RXRAM 0x0c0 100 #define MSPI_CDRAM 0x140 101 #define MSPI_WRITE_LOCK 0x180 102 103 #define MSPI_MASTER_BIT BIT(7) 104 105 #define MSPI_NUM_CDRAM 16 106 #define MSPI_CDRAM_OUTP BIT(8) 107 #define MSPI_CDRAM_CONT_BIT BIT(7) 108 #define MSPI_CDRAM_BITSE_BIT BIT(6) 109 #define MSPI_CDRAM_DT_BIT BIT(5) 110 #define MSPI_CDRAM_PCS 0xf 111 112 #define MSPI_SPCR2_SPE BIT(6) 113 #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7) 114 115 #define MSPI_SPCR3_FASTBR BIT(0) 116 #define MSPI_SPCR3_FASTDT BIT(1) 117 #define MSPI_SPCR3_SYSCLKSEL_MASK GENMASK(11, 10) 118 #define MSPI_SPCR3_SYSCLKSEL_27 (MSPI_SPCR3_SYSCLKSEL_MASK & \ 119 ~(BIT(10) | BIT(11))) 120 #define MSPI_SPCR3_SYSCLKSEL_108 (MSPI_SPCR3_SYSCLKSEL_MASK & \ 121 BIT(11)) 122 #define MSPI_SPCR3_TXRXDAM_MASK GENMASK(4, 2) 123 #define MSPI_SPCR3_DAM_8BYTE 0 124 #define MSPI_SPCR3_DAM_16BYTE (BIT(2) | BIT(4)) 125 #define MSPI_SPCR3_DAM_32BYTE (BIT(3) | BIT(5)) 126 #define MSPI_SPCR3_HALFDUPLEX BIT(6) 127 #define MSPI_SPCR3_HDOUTTYPE BIT(7) 128 #define MSPI_SPCR3_DATA_REG_SZ BIT(8) 129 #define MSPI_SPCR3_CPHARX BIT(9) 130 131 #define MSPI_MSPI_STATUS_SPIF BIT(0) 132 133 #define INTR_BASE_BIT_SHIFT 0x02 134 #define INTR_COUNT 0x07 135 136 #define NUM_CHIPSELECT 4 137 #define QSPI_SPBR_MAX 255U 138 #define MSPI_BASE_FREQ 27000000UL 139 140 #define OPCODE_DIOR 0xBB 141 #define OPCODE_QIOR 0xEB 142 #define OPCODE_DIOR_4B 0xBC 143 #define OPCODE_QIOR_4B 0xEC 144 145 #define MAX_CMD_SIZE 6 146 147 #define ADDR_4MB_MASK GENMASK(22, 0) 148 149 /* stop at end of transfer, no other reason */ 150 #define TRANS_STATUS_BREAK_NONE 0 151 /* stop at end of spi_message */ 152 #define TRANS_STATUS_BREAK_EOM 1 153 /* stop at end of spi_transfer if delay */ 154 #define TRANS_STATUS_BREAK_DELAY 2 155 /* stop at end of spi_transfer if cs_change */ 156 #define TRANS_STATUS_BREAK_CS_CHANGE 4 157 /* stop if we run out of bytes */ 158 #define TRANS_STATUS_BREAK_NO_BYTES 8 159 160 /* events that make us stop filling TX slots */ 161 #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \ 162 TRANS_STATUS_BREAK_DELAY | \ 163 TRANS_STATUS_BREAK_CS_CHANGE) 164 165 /* events that make us deassert CS */ 166 #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \ 167 TRANS_STATUS_BREAK_CS_CHANGE) 168 169 /* 170 * Used for writing and reading data in the right order 171 * to TXRAM and RXRAM when used as 32-bit registers respectively 172 */ 173 #define swap4bytes(__val) \ 174 ((((__val) >> 24) & 0x000000FF) | (((__val) >> 8) & 0x0000FF00) | \ 175 (((__val) << 8) & 0x00FF0000) | (((__val) << 24) & 0xFF000000)) 176 177 struct bcm_qspi_parms { 178 u32 speed_hz; 179 u8 mode; 180 u8 bits_per_word; 181 }; 182 183 struct bcm_xfer_mode { 184 bool flex_mode; 185 unsigned int width; 186 unsigned int addrlen; 187 unsigned int hp; 188 }; 189 190 enum base_type { 191 MSPI, 192 BSPI, 193 CHIP_SELECT, 194 BASEMAX, 195 }; 196 197 enum irq_source { 198 SINGLE_L2, 199 MUXED_L1, 200 }; 201 202 struct bcm_qspi_irq { 203 const char *irq_name; 204 const irq_handler_t irq_handler; 205 int irq_source; 206 u32 mask; 207 }; 208 209 struct bcm_qspi_dev_id { 210 const struct bcm_qspi_irq *irqp; 211 void *dev; 212 }; 213 214 215 struct qspi_trans { 216 struct spi_transfer *trans; 217 int byte; 218 bool mspi_last_trans; 219 }; 220 221 struct bcm_qspi { 222 struct platform_device *pdev; 223 struct spi_master *master; 224 struct clk *clk; 225 u32 base_clk; 226 u32 max_speed_hz; 227 void __iomem *base[BASEMAX]; 228 229 /* Some SoCs provide custom interrupt status register(s) */ 230 struct bcm_qspi_soc_intc *soc_intc; 231 232 struct bcm_qspi_parms last_parms; 233 struct qspi_trans trans_pos; 234 int curr_cs; 235 int bspi_maj_rev; 236 int bspi_min_rev; 237 int bspi_enabled; 238 const struct spi_mem_op *bspi_rf_op; 239 u32 bspi_rf_op_idx; 240 u32 bspi_rf_op_len; 241 u32 bspi_rf_op_status; 242 struct bcm_xfer_mode xfer_mode; 243 u32 s3_strap_override_ctrl; 244 bool bspi_mode; 245 bool big_endian; 246 int num_irqs; 247 struct bcm_qspi_dev_id *dev_ids; 248 struct completion mspi_done; 249 struct completion bspi_done; 250 u8 mspi_maj_rev; 251 u8 mspi_min_rev; 252 bool mspi_spcr3_sysclk; 253 }; 254 255 static inline bool has_bspi(struct bcm_qspi *qspi) 256 { 257 return qspi->bspi_mode; 258 } 259 260 /* hardware supports spcr3 and fast baud-rate */ 261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) 262 { 263 if (!has_bspi(qspi) && 264 ((qspi->mspi_maj_rev >= 1) && 265 (qspi->mspi_min_rev >= 5))) 266 return true; 267 268 return false; 269 } 270 271 /* hardware supports sys clk 108Mhz */ 272 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) 273 { 274 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || 275 ((qspi->mspi_maj_rev >= 1) && 276 (qspi->mspi_min_rev >= 6)))) 277 return true; 278 279 return false; 280 } 281 282 static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi) 283 { 284 if (bcm_qspi_has_fastbr(qspi)) 285 return (bcm_qspi_has_sysclk_108(qspi) ? 4 : 1); 286 else 287 return 8; 288 } 289 290 static u32 bcm_qspi_calc_spbr(u32 clk_speed_hz, 291 const struct bcm_qspi_parms *xp) 292 { 293 u32 spbr = 0; 294 295 /* SPBR = System Clock/(2 * SCK Baud Rate) */ 296 if (xp->speed_hz) 297 spbr = clk_speed_hz / (xp->speed_hz * 2); 298 299 return spbr; 300 } 301 302 /* Read qspi controller register*/ 303 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type, 304 unsigned int offset) 305 { 306 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset); 307 } 308 309 /* Write qspi controller register*/ 310 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type, 311 unsigned int offset, unsigned int data) 312 { 313 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset); 314 } 315 316 /* BSPI helpers */ 317 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi) 318 { 319 int i; 320 321 /* this should normally finish within 10us */ 322 for (i = 0; i < 1000; i++) { 323 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1)) 324 return 0; 325 udelay(1); 326 } 327 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n"); 328 return -EIO; 329 } 330 331 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi) 332 { 333 if (qspi->bspi_maj_rev < 4) 334 return true; 335 return false; 336 } 337 338 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi) 339 { 340 bcm_qspi_bspi_busy_poll(qspi); 341 /* Force rising edge for the b0/b1 'flush' field */ 342 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1); 343 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1); 344 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0); 345 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0); 346 } 347 348 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi) 349 { 350 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) & 351 BSPI_RAF_STATUS_FIFO_EMPTY_MASK); 352 } 353 354 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi) 355 { 356 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA); 357 358 /* BSPI v3 LR is LE only, convert data to host endianness */ 359 if (bcm_qspi_bspi_ver_three(qspi)) 360 data = le32_to_cpu(data); 361 362 return data; 363 } 364 365 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi) 366 { 367 bcm_qspi_bspi_busy_poll(qspi); 368 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL, 369 BSPI_RAF_CTRL_START_MASK); 370 } 371 372 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi) 373 { 374 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL, 375 BSPI_RAF_CTRL_CLEAR_MASK); 376 bcm_qspi_bspi_flush_prefetch_buffers(qspi); 377 } 378 379 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi) 380 { 381 u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in; 382 u32 data = 0; 383 384 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op, 385 qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len); 386 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) { 387 data = bcm_qspi_bspi_lr_read_fifo(qspi); 388 if (likely(qspi->bspi_rf_op_len >= 4) && 389 IS_ALIGNED((uintptr_t)buf, 4)) { 390 buf[qspi->bspi_rf_op_idx++] = data; 391 qspi->bspi_rf_op_len -= 4; 392 } else { 393 /* Read out remaining bytes, make sure*/ 394 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx]; 395 396 data = cpu_to_le32(data); 397 while (qspi->bspi_rf_op_len) { 398 *cbuf++ = (u8)data; 399 data >>= 8; 400 qspi->bspi_rf_op_len--; 401 } 402 } 403 } 404 } 405 406 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte, 407 int bpp, int bpc, int flex_mode) 408 { 409 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0); 410 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc); 411 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp); 412 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte); 413 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode); 414 } 415 416 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, 417 const struct spi_mem_op *op, int hp) 418 { 419 int bpc = 0, bpp = 0; 420 u8 command = op->cmd.opcode; 421 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE; 422 int addrlen = op->addr.nbytes; 423 int flex_mode = 1; 424 425 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n", 426 width, addrlen, hp); 427 428 if (addrlen == BSPI_ADDRLEN_4BYTES) 429 bpp = BSPI_BPP_ADDR_SELECT_MASK; 430 431 if (op->dummy.nbytes) 432 bpp |= (op->dummy.nbytes * 8) / op->dummy.buswidth; 433 434 switch (width) { 435 case SPI_NBITS_SINGLE: 436 if (addrlen == BSPI_ADDRLEN_3BYTES) 437 /* default mode, does not need flex_cmd */ 438 flex_mode = 0; 439 break; 440 case SPI_NBITS_DUAL: 441 bpc = 0x00000001; 442 if (hp) { 443 bpc |= 0x00010100; /* address and mode are 2-bit */ 444 bpp = BSPI_BPP_MODE_SELECT_MASK; 445 } 446 break; 447 case SPI_NBITS_QUAD: 448 bpc = 0x00000002; 449 if (hp) { 450 bpc |= 0x00020200; /* address and mode are 4-bit */ 451 bpp |= BSPI_BPP_MODE_SELECT_MASK; 452 } 453 break; 454 default: 455 return -EINVAL; 456 } 457 458 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode); 459 460 return 0; 461 } 462 463 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, 464 const struct spi_mem_op *op, int hp) 465 { 466 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE; 467 int addrlen = op->addr.nbytes; 468 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); 469 470 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n", 471 width, addrlen, hp); 472 473 switch (width) { 474 case SPI_NBITS_SINGLE: 475 /* clear quad/dual mode */ 476 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD | 477 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL); 478 break; 479 case SPI_NBITS_QUAD: 480 /* clear dual mode and set quad mode */ 481 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; 482 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD; 483 break; 484 case SPI_NBITS_DUAL: 485 /* clear quad mode set dual mode */ 486 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD; 487 data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; 488 break; 489 default: 490 return -EINVAL; 491 } 492 493 if (addrlen == BSPI_ADDRLEN_4BYTES) 494 /* set 4byte mode*/ 495 data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE; 496 else 497 /* clear 4 byte mode */ 498 data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE; 499 500 /* set the override mode */ 501 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; 502 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data); 503 bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0); 504 505 return 0; 506 } 507 508 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi, 509 const struct spi_mem_op *op, int hp) 510 { 511 int error = 0; 512 int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE; 513 int addrlen = op->addr.nbytes; 514 515 /* default mode */ 516 qspi->xfer_mode.flex_mode = true; 517 518 if (!bcm_qspi_bspi_ver_three(qspi)) { 519 u32 val, mask; 520 521 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); 522 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; 523 if (val & mask || qspi->s3_strap_override_ctrl & mask) { 524 qspi->xfer_mode.flex_mode = false; 525 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0); 526 error = bcm_qspi_bspi_set_override(qspi, op, hp); 527 } 528 } 529 530 if (qspi->xfer_mode.flex_mode) 531 error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp); 532 533 if (error) { 534 dev_warn(&qspi->pdev->dev, 535 "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n", 536 width, addrlen, hp); 537 } else if (qspi->xfer_mode.width != width || 538 qspi->xfer_mode.addrlen != addrlen || 539 qspi->xfer_mode.hp != hp) { 540 qspi->xfer_mode.width = width; 541 qspi->xfer_mode.addrlen = addrlen; 542 qspi->xfer_mode.hp = hp; 543 dev_dbg(&qspi->pdev->dev, 544 "cs:%d %d-lane output, %d-byte address%s\n", 545 qspi->curr_cs, 546 qspi->xfer_mode.width, 547 qspi->xfer_mode.addrlen, 548 qspi->xfer_mode.hp != -1 ? ", hp mode" : ""); 549 } 550 551 return error; 552 } 553 554 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi) 555 { 556 if (!has_bspi(qspi)) 557 return; 558 559 qspi->bspi_enabled = 1; 560 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0) 561 return; 562 563 bcm_qspi_bspi_flush_prefetch_buffers(qspi); 564 udelay(1); 565 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0); 566 udelay(1); 567 } 568 569 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi) 570 { 571 if (!has_bspi(qspi)) 572 return; 573 574 qspi->bspi_enabled = 0; 575 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1)) 576 return; 577 578 bcm_qspi_bspi_busy_poll(qspi); 579 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1); 580 udelay(1); 581 } 582 583 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs) 584 { 585 u32 rd = 0; 586 u32 wr = 0; 587 588 if (qspi->base[CHIP_SELECT]) { 589 rd = bcm_qspi_read(qspi, CHIP_SELECT, 0); 590 wr = (rd & ~0xff) | (1 << cs); 591 if (rd == wr) 592 return; 593 bcm_qspi_write(qspi, CHIP_SELECT, 0, wr); 594 usleep_range(10, 20); 595 } 596 597 dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs); 598 qspi->curr_cs = cs; 599 } 600 601 /* MSPI helpers */ 602 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, 603 const struct bcm_qspi_parms *xp) 604 { 605 u32 spcr, spbr = 0; 606 607 if (!qspi->mspi_maj_rev) 608 /* legacy controller */ 609 spcr = MSPI_MASTER_BIT; 610 else 611 spcr = 0; 612 613 /* 614 * Bits per transfer. BITS determines the number of data bits 615 * transferred if the command control bit (BITSE of a 616 * CDRAM Register) is equal to 1. 617 * If CDRAM BITSE is equal to 0, 8 data bits are transferred 618 * regardless 619 */ 620 if (xp->bits_per_word != 16 && xp->bits_per_word != 64) 621 spcr |= xp->bits_per_word << MSPI_SPCR0_MSB_BITS_SHIFT; 622 623 spcr |= xp->mode & (MSPI_SPCR0_MSB_CPHA | MSPI_SPCR0_MSB_CPOL); 624 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); 625 626 if (bcm_qspi_has_fastbr(qspi)) { 627 spcr = 0; 628 629 /* enable fastbr */ 630 spcr |= MSPI_SPCR3_FASTBR; 631 632 if (xp->mode & SPI_3WIRE) 633 spcr |= MSPI_SPCR3_HALFDUPLEX | MSPI_SPCR3_HDOUTTYPE; 634 635 if (bcm_qspi_has_sysclk_108(qspi)) { 636 /* check requested baud rate before moving to 108Mhz */ 637 spbr = bcm_qspi_calc_spbr(MSPI_BASE_FREQ * 4, xp); 638 if (spbr > QSPI_SPBR_MAX) { 639 /* use SYSCLK_27Mhz for slower baud rates */ 640 spcr &= ~MSPI_SPCR3_SYSCLKSEL_MASK; 641 qspi->base_clk = MSPI_BASE_FREQ; 642 } else { 643 /* SYSCLK_108Mhz */ 644 spcr |= MSPI_SPCR3_SYSCLKSEL_108; 645 qspi->base_clk = MSPI_BASE_FREQ * 4; 646 } 647 } 648 649 if (xp->bits_per_word > 16) { 650 /* data_reg_size 1 (64bit) */ 651 spcr |= MSPI_SPCR3_DATA_REG_SZ; 652 /* TxRx RAM data access mode 2 for 32B and set fastdt */ 653 spcr |= MSPI_SPCR3_DAM_32BYTE | MSPI_SPCR3_FASTDT; 654 /* 655 * Set length of delay after transfer 656 * DTL from 0(256) to 1 657 */ 658 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 1); 659 } else { 660 /* data_reg_size[8] = 0 */ 661 spcr &= ~(MSPI_SPCR3_DATA_REG_SZ); 662 663 /* 664 * TxRx RAM access mode 8B 665 * and disable fastdt 666 */ 667 spcr &= ~(MSPI_SPCR3_DAM_32BYTE); 668 } 669 bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr); 670 } 671 672 /* SCK Baud Rate = System Clock/(2 * SPBR) */ 673 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); 674 spbr = bcm_qspi_calc_spbr(qspi->base_clk, xp); 675 spbr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX); 676 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr); 677 678 qspi->last_parms = *xp; 679 } 680 681 static void bcm_qspi_update_parms(struct bcm_qspi *qspi, 682 struct spi_device *spi, 683 struct spi_transfer *trans) 684 { 685 struct bcm_qspi_parms xp; 686 687 xp.speed_hz = trans->speed_hz; 688 xp.bits_per_word = trans->bits_per_word; 689 xp.mode = spi->mode; 690 691 bcm_qspi_hw_set_parms(qspi, &xp); 692 } 693 694 static int bcm_qspi_setup(struct spi_device *spi) 695 { 696 struct bcm_qspi_parms *xp; 697 698 if (spi->bits_per_word > 64) 699 return -EINVAL; 700 701 xp = spi_get_ctldata(spi); 702 if (!xp) { 703 xp = kzalloc(sizeof(*xp), GFP_KERNEL); 704 if (!xp) 705 return -ENOMEM; 706 spi_set_ctldata(spi, xp); 707 } 708 xp->speed_hz = spi->max_speed_hz; 709 xp->mode = spi->mode; 710 711 if (spi->bits_per_word) 712 xp->bits_per_word = spi->bits_per_word; 713 else 714 xp->bits_per_word = 8; 715 716 return 0; 717 } 718 719 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi, 720 struct qspi_trans *qt) 721 { 722 if (qt->mspi_last_trans && 723 spi_transfer_is_last(qspi->master, qt->trans)) 724 return true; 725 else 726 return false; 727 } 728 729 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi, 730 struct qspi_trans *qt, int flags) 731 { 732 int ret = TRANS_STATUS_BREAK_NONE; 733 734 /* count the last transferred bytes */ 735 if (qt->trans->bits_per_word <= 8) 736 qt->byte++; 737 else if (qt->trans->bits_per_word <= 16) 738 qt->byte += 2; 739 else if (qt->trans->bits_per_word <= 32) 740 qt->byte += 4; 741 else if (qt->trans->bits_per_word <= 64) 742 qt->byte += 8; 743 744 if (qt->byte >= qt->trans->len) { 745 /* we're at the end of the spi_transfer */ 746 /* in TX mode, need to pause for a delay or CS change */ 747 if (qt->trans->delay.value && 748 (flags & TRANS_STATUS_BREAK_DELAY)) 749 ret |= TRANS_STATUS_BREAK_DELAY; 750 if (qt->trans->cs_change && 751 (flags & TRANS_STATUS_BREAK_CS_CHANGE)) 752 ret |= TRANS_STATUS_BREAK_CS_CHANGE; 753 754 if (bcm_qspi_mspi_transfer_is_last(qspi, qt)) 755 ret |= TRANS_STATUS_BREAK_EOM; 756 else 757 ret |= TRANS_STATUS_BREAK_NO_BYTES; 758 759 qt->trans = NULL; 760 } 761 762 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n", 763 qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret); 764 return ret; 765 } 766 767 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot) 768 { 769 u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4; 770 771 /* mask out reserved bits */ 772 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff; 773 } 774 775 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot) 776 { 777 u32 reg_offset = MSPI_RXRAM; 778 u32 lsb_offset = reg_offset + (slot << 3) + 0x4; 779 u32 msb_offset = reg_offset + (slot << 3); 780 781 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) | 782 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8); 783 } 784 785 static inline u32 read_rxram_slot_u32(struct bcm_qspi *qspi, int slot) 786 { 787 u32 reg_offset = MSPI_RXRAM; 788 u32 offset = reg_offset + (slot << 3); 789 u32 val; 790 791 val = bcm_qspi_read(qspi, MSPI, offset); 792 val = swap4bytes(val); 793 794 return val; 795 } 796 797 static inline u64 read_rxram_slot_u64(struct bcm_qspi *qspi, int slot) 798 { 799 u32 reg_offset = MSPI_RXRAM; 800 u32 lsb_offset = reg_offset + (slot << 3) + 0x4; 801 u32 msb_offset = reg_offset + (slot << 3); 802 u32 msb, lsb; 803 804 msb = bcm_qspi_read(qspi, MSPI, msb_offset); 805 msb = swap4bytes(msb); 806 lsb = bcm_qspi_read(qspi, MSPI, lsb_offset); 807 lsb = swap4bytes(lsb); 808 809 return ((u64)msb << 32 | lsb); 810 } 811 812 static void read_from_hw(struct bcm_qspi *qspi, int slots) 813 { 814 struct qspi_trans tp; 815 int slot; 816 817 bcm_qspi_disable_bspi(qspi); 818 819 if (slots > MSPI_NUM_CDRAM) { 820 /* should never happen */ 821 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__); 822 return; 823 } 824 825 tp = qspi->trans_pos; 826 827 for (slot = 0; slot < slots; slot++) { 828 if (tp.trans->bits_per_word <= 8) { 829 u8 *buf = tp.trans->rx_buf; 830 831 if (buf) 832 buf[tp.byte] = read_rxram_slot_u8(qspi, slot); 833 dev_dbg(&qspi->pdev->dev, "RD %02x\n", 834 buf ? buf[tp.byte] : 0x0); 835 } else if (tp.trans->bits_per_word <= 16) { 836 u16 *buf = tp.trans->rx_buf; 837 838 if (buf) 839 buf[tp.byte / 2] = read_rxram_slot_u16(qspi, 840 slot); 841 dev_dbg(&qspi->pdev->dev, "RD %04x\n", 842 buf ? buf[tp.byte / 2] : 0x0); 843 } else if (tp.trans->bits_per_word <= 32) { 844 u32 *buf = tp.trans->rx_buf; 845 846 if (buf) 847 buf[tp.byte / 4] = read_rxram_slot_u32(qspi, 848 slot); 849 dev_dbg(&qspi->pdev->dev, "RD %08x\n", 850 buf ? buf[tp.byte / 4] : 0x0); 851 852 } else if (tp.trans->bits_per_word <= 64) { 853 u64 *buf = tp.trans->rx_buf; 854 855 if (buf) 856 buf[tp.byte / 8] = read_rxram_slot_u64(qspi, 857 slot); 858 dev_dbg(&qspi->pdev->dev, "RD %llx\n", 859 buf ? buf[tp.byte / 8] : 0x0); 860 861 862 } 863 864 update_qspi_trans_byte_count(qspi, &tp, 865 TRANS_STATUS_BREAK_NONE); 866 } 867 868 qspi->trans_pos = tp; 869 } 870 871 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot, 872 u8 val) 873 { 874 u32 reg_offset = MSPI_TXRAM + (slot << 3); 875 876 /* mask out reserved bits */ 877 bcm_qspi_write(qspi, MSPI, reg_offset, val); 878 } 879 880 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot, 881 u16 val) 882 { 883 u32 reg_offset = MSPI_TXRAM; 884 u32 msb_offset = reg_offset + (slot << 3); 885 u32 lsb_offset = reg_offset + (slot << 3) + 0x4; 886 887 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8)); 888 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff)); 889 } 890 891 static inline void write_txram_slot_u32(struct bcm_qspi *qspi, int slot, 892 u32 val) 893 { 894 u32 reg_offset = MSPI_TXRAM; 895 u32 msb_offset = reg_offset + (slot << 3); 896 897 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(val)); 898 } 899 900 static inline void write_txram_slot_u64(struct bcm_qspi *qspi, int slot, 901 u64 val) 902 { 903 u32 reg_offset = MSPI_TXRAM; 904 u32 msb_offset = reg_offset + (slot << 3); 905 u32 lsb_offset = reg_offset + (slot << 3) + 0x4; 906 u32 msb = upper_32_bits(val); 907 u32 lsb = lower_32_bits(val); 908 909 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(msb)); 910 bcm_qspi_write(qspi, MSPI, lsb_offset, swap4bytes(lsb)); 911 } 912 913 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot) 914 { 915 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2)); 916 } 917 918 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val) 919 { 920 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val); 921 } 922 923 /* Return number of slots written */ 924 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) 925 { 926 struct qspi_trans tp; 927 int slot = 0, tstatus = 0; 928 u32 mspi_cdram = 0; 929 930 bcm_qspi_disable_bspi(qspi); 931 tp = qspi->trans_pos; 932 bcm_qspi_update_parms(qspi, spi, tp.trans); 933 934 /* Run until end of transfer or reached the max data */ 935 while (!tstatus && slot < MSPI_NUM_CDRAM) { 936 mspi_cdram = MSPI_CDRAM_CONT_BIT; 937 if (tp.trans->bits_per_word <= 8) { 938 const u8 *buf = tp.trans->tx_buf; 939 u8 val = buf ? buf[tp.byte] : 0x00; 940 941 write_txram_slot_u8(qspi, slot, val); 942 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val); 943 } else if (tp.trans->bits_per_word <= 16) { 944 const u16 *buf = tp.trans->tx_buf; 945 u16 val = buf ? buf[tp.byte / 2] : 0x0000; 946 947 write_txram_slot_u16(qspi, slot, val); 948 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); 949 } else if (tp.trans->bits_per_word <= 32) { 950 const u32 *buf = tp.trans->tx_buf; 951 u32 val = buf ? buf[tp.byte/4] : 0x0; 952 953 write_txram_slot_u32(qspi, slot, val); 954 dev_dbg(&qspi->pdev->dev, "WR %08x\n", val); 955 } else if (tp.trans->bits_per_word <= 64) { 956 const u64 *buf = tp.trans->tx_buf; 957 u64 val = (buf ? buf[tp.byte/8] : 0x0); 958 959 /* use the length of delay from SPCR1_LSB */ 960 if (bcm_qspi_has_fastbr(qspi)) 961 mspi_cdram |= MSPI_CDRAM_DT_BIT; 962 963 write_txram_slot_u64(qspi, slot, val); 964 dev_dbg(&qspi->pdev->dev, "WR %llx\n", val); 965 } 966 967 mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 : 968 MSPI_CDRAM_BITSE_BIT); 969 970 /* set 3wrire halfduplex mode data from master to slave */ 971 if ((spi->mode & SPI_3WIRE) && tp.trans->tx_buf) 972 mspi_cdram |= MSPI_CDRAM_OUTP; 973 974 if (has_bspi(qspi)) 975 mspi_cdram &= ~1; 976 else 977 mspi_cdram |= (~(1 << spi->chip_select) & 978 MSPI_CDRAM_PCS); 979 980 write_cdram_slot(qspi, slot, mspi_cdram); 981 982 tstatus = update_qspi_trans_byte_count(qspi, &tp, 983 TRANS_STATUS_BREAK_TX); 984 slot++; 985 } 986 987 if (!slot) { 988 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__); 989 goto done; 990 } 991 992 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot); 993 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); 994 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1); 995 996 /* 997 * case 1) EOM =1, cs_change =0: SSb inactive 998 * case 2) EOM =1, cs_change =1: SSb stay active 999 * case 3) EOM =0, cs_change =0: SSb stay active 1000 * case 4) EOM =0, cs_change =1: SSb inactive 1001 */ 1002 if (((tstatus & TRANS_STATUS_BREAK_DESELECT) 1003 == TRANS_STATUS_BREAK_CS_CHANGE) || 1004 ((tstatus & TRANS_STATUS_BREAK_DESELECT) 1005 == TRANS_STATUS_BREAK_EOM)) { 1006 mspi_cdram = read_cdram_slot(qspi, slot - 1) & 1007 ~MSPI_CDRAM_CONT_BIT; 1008 write_cdram_slot(qspi, slot - 1, mspi_cdram); 1009 } 1010 1011 if (has_bspi(qspi)) 1012 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1); 1013 1014 /* Must flush previous writes before starting MSPI operation */ 1015 mb(); 1016 /* Set cont | spe | spifie */ 1017 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0); 1018 1019 done: 1020 return slot; 1021 } 1022 1023 static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi, 1024 const struct spi_mem_op *op) 1025 { 1026 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); 1027 u32 addr = 0, len, rdlen, len_words, from = 0; 1028 int ret = 0; 1029 unsigned long timeo = msecs_to_jiffies(100); 1030 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1031 1032 if (bcm_qspi_bspi_ver_three(qspi)) 1033 if (op->addr.nbytes == BSPI_ADDRLEN_4BYTES) 1034 return -EIO; 1035 1036 from = op->addr.val; 1037 if (!spi->cs_gpiod) 1038 bcm_qspi_chip_select(qspi, spi->chip_select); 1039 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); 1040 1041 /* 1042 * when using flex mode we need to send 1043 * the upper address byte to bspi 1044 */ 1045 if (!bcm_qspi_bspi_ver_three(qspi)) { 1046 addr = from & 0xff000000; 1047 bcm_qspi_write(qspi, BSPI, 1048 BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr); 1049 } 1050 1051 if (!qspi->xfer_mode.flex_mode) 1052 addr = from; 1053 else 1054 addr = from & 0x00ffffff; 1055 1056 if (bcm_qspi_bspi_ver_three(qspi) == true) 1057 addr = (addr + 0xc00000) & 0xffffff; 1058 1059 /* 1060 * read into the entire buffer by breaking the reads 1061 * into RAF buffer read lengths 1062 */ 1063 len = op->data.nbytes; 1064 qspi->bspi_rf_op_idx = 0; 1065 1066 do { 1067 if (len > BSPI_READ_LENGTH) 1068 rdlen = BSPI_READ_LENGTH; 1069 else 1070 rdlen = len; 1071 1072 reinit_completion(&qspi->bspi_done); 1073 bcm_qspi_enable_bspi(qspi); 1074 len_words = (rdlen + 3) >> 2; 1075 qspi->bspi_rf_op = op; 1076 qspi->bspi_rf_op_status = 0; 1077 qspi->bspi_rf_op_len = rdlen; 1078 dev_dbg(&qspi->pdev->dev, 1079 "bspi xfr addr 0x%x len 0x%x", addr, rdlen); 1080 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr); 1081 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words); 1082 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0); 1083 if (qspi->soc_intc) { 1084 /* 1085 * clear soc MSPI and BSPI interrupts and enable 1086 * BSPI interrupts. 1087 */ 1088 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE); 1089 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true); 1090 } 1091 1092 /* Must flush previous writes before starting BSPI operation */ 1093 mb(); 1094 bcm_qspi_bspi_lr_start(qspi); 1095 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) { 1096 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n"); 1097 ret = -ETIMEDOUT; 1098 break; 1099 } 1100 1101 /* set msg return length */ 1102 addr += rdlen; 1103 len -= rdlen; 1104 } while (len); 1105 1106 return ret; 1107 } 1108 1109 static int bcm_qspi_transfer_one(struct spi_master *master, 1110 struct spi_device *spi, 1111 struct spi_transfer *trans) 1112 { 1113 struct bcm_qspi *qspi = spi_master_get_devdata(master); 1114 int slots; 1115 unsigned long timeo = msecs_to_jiffies(100); 1116 1117 if (!spi->cs_gpiod) 1118 bcm_qspi_chip_select(qspi, spi->chip_select); 1119 qspi->trans_pos.trans = trans; 1120 qspi->trans_pos.byte = 0; 1121 1122 while (qspi->trans_pos.byte < trans->len) { 1123 reinit_completion(&qspi->mspi_done); 1124 1125 slots = write_to_hw(qspi, spi); 1126 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) { 1127 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n"); 1128 return -ETIMEDOUT; 1129 } 1130 1131 read_from_hw(qspi, slots); 1132 } 1133 bcm_qspi_enable_bspi(qspi); 1134 1135 return 0; 1136 } 1137 1138 static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi, 1139 const struct spi_mem_op *op) 1140 { 1141 struct spi_master *master = spi->master; 1142 struct bcm_qspi *qspi = spi_master_get_devdata(master); 1143 struct spi_transfer t[2]; 1144 u8 cmd[6] = { }; 1145 int ret, i; 1146 1147 memset(cmd, 0, sizeof(cmd)); 1148 memset(t, 0, sizeof(t)); 1149 1150 /* tx */ 1151 /* opcode is in cmd[0] */ 1152 cmd[0] = op->cmd.opcode; 1153 for (i = 0; i < op->addr.nbytes; i++) 1154 cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); 1155 1156 t[0].tx_buf = cmd; 1157 t[0].len = op->addr.nbytes + op->dummy.nbytes + 1; 1158 t[0].bits_per_word = spi->bits_per_word; 1159 t[0].tx_nbits = op->cmd.buswidth; 1160 /* lets mspi know that this is not last transfer */ 1161 qspi->trans_pos.mspi_last_trans = false; 1162 ret = bcm_qspi_transfer_one(master, spi, &t[0]); 1163 1164 /* rx */ 1165 qspi->trans_pos.mspi_last_trans = true; 1166 if (!ret) { 1167 /* rx */ 1168 t[1].rx_buf = op->data.buf.in; 1169 t[1].len = op->data.nbytes; 1170 t[1].rx_nbits = op->data.buswidth; 1171 t[1].bits_per_word = spi->bits_per_word; 1172 ret = bcm_qspi_transfer_one(master, spi, &t[1]); 1173 } 1174 1175 return ret; 1176 } 1177 1178 static int bcm_qspi_exec_mem_op(struct spi_mem *mem, 1179 const struct spi_mem_op *op) 1180 { 1181 struct spi_device *spi = mem->spi; 1182 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); 1183 int ret = 0; 1184 bool mspi_read = false; 1185 u32 addr = 0, len; 1186 u_char *buf; 1187 1188 if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 || 1189 op->data.dir != SPI_MEM_DATA_IN) 1190 return -ENOTSUPP; 1191 1192 buf = op->data.buf.in; 1193 addr = op->addr.val; 1194 len = op->data.nbytes; 1195 1196 if (bcm_qspi_bspi_ver_three(qspi) == true) { 1197 /* 1198 * The address coming into this function is a raw flash offset. 1199 * But for BSPI <= V3, we need to convert it to a remapped BSPI 1200 * address. If it crosses a 4MB boundary, just revert back to 1201 * using MSPI. 1202 */ 1203 addr = (addr + 0xc00000) & 0xffffff; 1204 1205 if ((~ADDR_4MB_MASK & addr) ^ 1206 (~ADDR_4MB_MASK & (addr + len - 1))) 1207 mspi_read = true; 1208 } 1209 1210 /* non-aligned and very short transfers are handled by MSPI */ 1211 if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) || 1212 len < 4) 1213 mspi_read = true; 1214 1215 if (mspi_read) 1216 return bcm_qspi_mspi_exec_mem_op(spi, op); 1217 1218 ret = bcm_qspi_bspi_set_mode(qspi, op, 0); 1219 1220 if (!ret) 1221 ret = bcm_qspi_bspi_exec_mem_op(spi, op); 1222 1223 return ret; 1224 } 1225 1226 static void bcm_qspi_cleanup(struct spi_device *spi) 1227 { 1228 struct bcm_qspi_parms *xp = spi_get_ctldata(spi); 1229 1230 kfree(xp); 1231 } 1232 1233 static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id) 1234 { 1235 struct bcm_qspi_dev_id *qspi_dev_id = dev_id; 1236 struct bcm_qspi *qspi = qspi_dev_id->dev; 1237 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS); 1238 1239 if (status & MSPI_MSPI_STATUS_SPIF) { 1240 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1241 /* clear interrupt */ 1242 status &= ~MSPI_MSPI_STATUS_SPIF; 1243 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status); 1244 if (qspi->soc_intc) 1245 soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE); 1246 complete(&qspi->mspi_done); 1247 return IRQ_HANDLED; 1248 } 1249 1250 return IRQ_NONE; 1251 } 1252 1253 static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id) 1254 { 1255 struct bcm_qspi_dev_id *qspi_dev_id = dev_id; 1256 struct bcm_qspi *qspi = qspi_dev_id->dev; 1257 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1258 u32 status = qspi_dev_id->irqp->mask; 1259 1260 if (qspi->bspi_enabled && qspi->bspi_rf_op) { 1261 bcm_qspi_bspi_lr_data_read(qspi); 1262 if (qspi->bspi_rf_op_len == 0) { 1263 qspi->bspi_rf_op = NULL; 1264 if (qspi->soc_intc) { 1265 /* disable soc BSPI interrupt */ 1266 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, 1267 false); 1268 /* indicate done */ 1269 status = INTR_BSPI_LR_SESSION_DONE_MASK; 1270 } 1271 1272 if (qspi->bspi_rf_op_status) 1273 bcm_qspi_bspi_lr_clear(qspi); 1274 else 1275 bcm_qspi_bspi_flush_prefetch_buffers(qspi); 1276 } 1277 1278 if (qspi->soc_intc) 1279 /* clear soc BSPI interrupt */ 1280 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE); 1281 } 1282 1283 status &= INTR_BSPI_LR_SESSION_DONE_MASK; 1284 if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0) 1285 complete(&qspi->bspi_done); 1286 1287 return IRQ_HANDLED; 1288 } 1289 1290 static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id) 1291 { 1292 struct bcm_qspi_dev_id *qspi_dev_id = dev_id; 1293 struct bcm_qspi *qspi = qspi_dev_id->dev; 1294 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1295 1296 dev_err(&qspi->pdev->dev, "BSPI INT error\n"); 1297 qspi->bspi_rf_op_status = -EIO; 1298 if (qspi->soc_intc) 1299 /* clear soc interrupt */ 1300 soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR); 1301 1302 complete(&qspi->bspi_done); 1303 return IRQ_HANDLED; 1304 } 1305 1306 static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id) 1307 { 1308 struct bcm_qspi_dev_id *qspi_dev_id = dev_id; 1309 struct bcm_qspi *qspi = qspi_dev_id->dev; 1310 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc; 1311 irqreturn_t ret = IRQ_NONE; 1312 1313 if (soc_intc) { 1314 u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc); 1315 1316 if (status & MSPI_DONE) 1317 ret = bcm_qspi_mspi_l2_isr(irq, dev_id); 1318 else if (status & BSPI_DONE) 1319 ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id); 1320 else if (status & BSPI_ERR) 1321 ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id); 1322 } 1323 1324 return ret; 1325 } 1326 1327 static const struct bcm_qspi_irq qspi_irq_tab[] = { 1328 { 1329 .irq_name = "spi_lr_fullness_reached", 1330 .irq_handler = bcm_qspi_bspi_lr_l2_isr, 1331 .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK, 1332 }, 1333 { 1334 .irq_name = "spi_lr_session_aborted", 1335 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, 1336 .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK, 1337 }, 1338 { 1339 .irq_name = "spi_lr_impatient", 1340 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, 1341 .mask = INTR_BSPI_LR_IMPATIENT_MASK, 1342 }, 1343 { 1344 .irq_name = "spi_lr_session_done", 1345 .irq_handler = bcm_qspi_bspi_lr_l2_isr, 1346 .mask = INTR_BSPI_LR_SESSION_DONE_MASK, 1347 }, 1348 #ifdef QSPI_INT_DEBUG 1349 /* this interrupt is for debug purposes only, dont request irq */ 1350 { 1351 .irq_name = "spi_lr_overread", 1352 .irq_handler = bcm_qspi_bspi_lr_err_l2_isr, 1353 .mask = INTR_BSPI_LR_OVERREAD_MASK, 1354 }, 1355 #endif 1356 { 1357 .irq_name = "mspi_done", 1358 .irq_handler = bcm_qspi_mspi_l2_isr, 1359 .mask = INTR_MSPI_DONE_MASK, 1360 }, 1361 { 1362 .irq_name = "mspi_halted", 1363 .irq_handler = bcm_qspi_mspi_l2_isr, 1364 .mask = INTR_MSPI_HALTED_MASK, 1365 }, 1366 { 1367 /* single muxed L1 interrupt source */ 1368 .irq_name = "spi_l1_intr", 1369 .irq_handler = bcm_qspi_l1_isr, 1370 .irq_source = MUXED_L1, 1371 .mask = QSPI_INTERRUPTS_ALL, 1372 }, 1373 }; 1374 1375 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi) 1376 { 1377 u32 val = 0; 1378 1379 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID); 1380 qspi->bspi_maj_rev = (val >> 8) & 0xff; 1381 qspi->bspi_min_rev = val & 0xff; 1382 if (!(bcm_qspi_bspi_ver_three(qspi))) { 1383 /* Force mapping of BSPI address -> flash offset */ 1384 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0); 1385 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1); 1386 } 1387 qspi->bspi_enabled = 1; 1388 bcm_qspi_disable_bspi(qspi); 1389 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0); 1390 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0); 1391 } 1392 1393 static void bcm_qspi_hw_init(struct bcm_qspi *qspi) 1394 { 1395 struct bcm_qspi_parms parms; 1396 1397 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0); 1398 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0); 1399 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); 1400 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0); 1401 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20); 1402 1403 parms.mode = SPI_MODE_3; 1404 parms.bits_per_word = 8; 1405 parms.speed_hz = qspi->max_speed_hz; 1406 bcm_qspi_hw_set_parms(qspi, &parms); 1407 1408 if (has_bspi(qspi)) 1409 bcm_qspi_bspi_init(qspi); 1410 } 1411 1412 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi) 1413 { 1414 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS); 1415 1416 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0); 1417 if (has_bspi(qspi)) 1418 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); 1419 1420 /* clear interrupt */ 1421 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1); 1422 } 1423 1424 static const struct spi_controller_mem_ops bcm_qspi_mem_ops = { 1425 .exec_op = bcm_qspi_exec_mem_op, 1426 }; 1427 1428 struct bcm_qspi_data { 1429 bool has_mspi_rev; 1430 bool has_spcr3_sysclk; 1431 }; 1432 1433 static const struct bcm_qspi_data bcm_qspi_no_rev_data = { 1434 .has_mspi_rev = false, 1435 .has_spcr3_sysclk = false, 1436 }; 1437 1438 static const struct bcm_qspi_data bcm_qspi_rev_data = { 1439 .has_mspi_rev = true, 1440 .has_spcr3_sysclk = false, 1441 }; 1442 1443 static const struct bcm_qspi_data bcm_qspi_spcr3_data = { 1444 .has_mspi_rev = true, 1445 .has_spcr3_sysclk = true, 1446 }; 1447 1448 static const struct of_device_id bcm_qspi_of_match[] = { 1449 { 1450 .compatible = "brcm,spi-bcm7445-qspi", 1451 .data = &bcm_qspi_rev_data, 1452 1453 }, 1454 { 1455 .compatible = "brcm,spi-bcm-qspi", 1456 .data = &bcm_qspi_no_rev_data, 1457 }, 1458 { 1459 .compatible = "brcm,spi-bcm7216-qspi", 1460 .data = &bcm_qspi_spcr3_data, 1461 }, 1462 { 1463 .compatible = "brcm,spi-bcm7278-qspi", 1464 .data = &bcm_qspi_spcr3_data, 1465 }, 1466 {}, 1467 }; 1468 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); 1469 1470 int bcm_qspi_probe(struct platform_device *pdev, 1471 struct bcm_qspi_soc_intc *soc_intc) 1472 { 1473 const struct of_device_id *of_id = NULL; 1474 const struct bcm_qspi_data *data; 1475 struct device *dev = &pdev->dev; 1476 struct bcm_qspi *qspi; 1477 struct spi_master *master; 1478 struct resource *res; 1479 int irq, ret = 0, num_ints = 0; 1480 u32 val; 1481 u32 rev = 0; 1482 const char *name = NULL; 1483 int num_irqs = ARRAY_SIZE(qspi_irq_tab); 1484 1485 /* We only support device-tree instantiation */ 1486 if (!dev->of_node) 1487 return -ENODEV; 1488 1489 of_id = of_match_node(bcm_qspi_of_match, dev->of_node); 1490 if (!of_id) 1491 return -ENODEV; 1492 1493 data = of_id->data; 1494 1495 master = devm_spi_alloc_master(dev, sizeof(struct bcm_qspi)); 1496 if (!master) { 1497 dev_err(dev, "error allocating spi_master\n"); 1498 return -ENOMEM; 1499 } 1500 1501 qspi = spi_master_get_devdata(master); 1502 1503 qspi->clk = devm_clk_get_optional(&pdev->dev, NULL); 1504 if (IS_ERR(qspi->clk)) 1505 return PTR_ERR(qspi->clk); 1506 1507 qspi->pdev = pdev; 1508 qspi->trans_pos.trans = NULL; 1509 qspi->trans_pos.byte = 0; 1510 qspi->trans_pos.mspi_last_trans = true; 1511 qspi->master = master; 1512 1513 master->bus_num = -1; 1514 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD | 1515 SPI_3WIRE; 1516 master->setup = bcm_qspi_setup; 1517 master->transfer_one = bcm_qspi_transfer_one; 1518 master->mem_ops = &bcm_qspi_mem_ops; 1519 master->cleanup = bcm_qspi_cleanup; 1520 master->dev.of_node = dev->of_node; 1521 master->num_chipselect = NUM_CHIPSELECT; 1522 master->use_gpio_descriptors = true; 1523 1524 qspi->big_endian = of_device_is_big_endian(dev->of_node); 1525 1526 if (!of_property_read_u32(dev->of_node, "num-cs", &val)) 1527 master->num_chipselect = val; 1528 1529 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi"); 1530 if (!res) 1531 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1532 "mspi"); 1533 1534 if (res) { 1535 qspi->base[MSPI] = devm_ioremap_resource(dev, res); 1536 if (IS_ERR(qspi->base[MSPI])) 1537 return PTR_ERR(qspi->base[MSPI]); 1538 } else { 1539 return 0; 1540 } 1541 1542 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi"); 1543 if (res) { 1544 qspi->base[BSPI] = devm_ioremap_resource(dev, res); 1545 if (IS_ERR(qspi->base[BSPI])) 1546 return PTR_ERR(qspi->base[BSPI]); 1547 qspi->bspi_mode = true; 1548 } else { 1549 qspi->bspi_mode = false; 1550 } 1551 1552 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : ""); 1553 1554 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg"); 1555 if (res) { 1556 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res); 1557 if (IS_ERR(qspi->base[CHIP_SELECT])) 1558 return PTR_ERR(qspi->base[CHIP_SELECT]); 1559 } 1560 1561 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id), 1562 GFP_KERNEL); 1563 if (!qspi->dev_ids) 1564 return -ENOMEM; 1565 1566 /* 1567 * Some SoCs integrate spi controller (e.g., its interrupt bits) 1568 * in specific ways 1569 */ 1570 if (soc_intc) { 1571 qspi->soc_intc = soc_intc; 1572 soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true); 1573 } else { 1574 qspi->soc_intc = NULL; 1575 } 1576 1577 if (qspi->clk) { 1578 ret = clk_prepare_enable(qspi->clk); 1579 if (ret) { 1580 dev_err(dev, "failed to prepare clock\n"); 1581 goto qspi_probe_err; 1582 } 1583 qspi->base_clk = clk_get_rate(qspi->clk); 1584 } else { 1585 qspi->base_clk = MSPI_BASE_FREQ; 1586 } 1587 1588 if (data->has_mspi_rev) { 1589 rev = bcm_qspi_read(qspi, MSPI, MSPI_REV); 1590 /* some older revs do not have a MSPI_REV register */ 1591 if ((rev & 0xff) == 0xff) 1592 rev = 0; 1593 } 1594 1595 qspi->mspi_maj_rev = (rev >> 4) & 0xf; 1596 qspi->mspi_min_rev = rev & 0xf; 1597 qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk; 1598 1599 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); 1600 1601 /* 1602 * On SW resets it is possible to have the mask still enabled 1603 * Need to disable the mask and clear the status while we init 1604 */ 1605 bcm_qspi_hw_uninit(qspi); 1606 1607 for (val = 0; val < num_irqs; val++) { 1608 irq = -1; 1609 name = qspi_irq_tab[val].irq_name; 1610 if (qspi_irq_tab[val].irq_source == SINGLE_L2) { 1611 /* get the l2 interrupts */ 1612 irq = platform_get_irq_byname_optional(pdev, name); 1613 } else if (!num_ints && soc_intc) { 1614 /* all mspi, bspi intrs muxed to one L1 intr */ 1615 irq = platform_get_irq(pdev, 0); 1616 } 1617 1618 if (irq >= 0) { 1619 ret = devm_request_irq(&pdev->dev, irq, 1620 qspi_irq_tab[val].irq_handler, 0, 1621 name, 1622 &qspi->dev_ids[val]); 1623 if (ret < 0) { 1624 dev_err(&pdev->dev, "IRQ %s not found\n", name); 1625 goto qspi_unprepare_err; 1626 } 1627 1628 qspi->dev_ids[val].dev = qspi; 1629 qspi->dev_ids[val].irqp = &qspi_irq_tab[val]; 1630 num_ints++; 1631 dev_dbg(&pdev->dev, "registered IRQ %s %d\n", 1632 qspi_irq_tab[val].irq_name, 1633 irq); 1634 } 1635 } 1636 1637 if (!num_ints) { 1638 dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n"); 1639 ret = -EINVAL; 1640 goto qspi_unprepare_err; 1641 } 1642 1643 bcm_qspi_hw_init(qspi); 1644 init_completion(&qspi->mspi_done); 1645 init_completion(&qspi->bspi_done); 1646 qspi->curr_cs = -1; 1647 1648 platform_set_drvdata(pdev, qspi); 1649 1650 qspi->xfer_mode.width = -1; 1651 qspi->xfer_mode.addrlen = -1; 1652 qspi->xfer_mode.hp = -1; 1653 1654 ret = spi_register_master(master); 1655 if (ret < 0) { 1656 dev_err(dev, "can't register master\n"); 1657 goto qspi_reg_err; 1658 } 1659 1660 return 0; 1661 1662 qspi_reg_err: 1663 bcm_qspi_hw_uninit(qspi); 1664 qspi_unprepare_err: 1665 clk_disable_unprepare(qspi->clk); 1666 qspi_probe_err: 1667 kfree(qspi->dev_ids); 1668 return ret; 1669 } 1670 /* probe function to be called by SoC specific platform driver probe */ 1671 EXPORT_SYMBOL_GPL(bcm_qspi_probe); 1672 1673 int bcm_qspi_remove(struct platform_device *pdev) 1674 { 1675 struct bcm_qspi *qspi = platform_get_drvdata(pdev); 1676 1677 spi_unregister_master(qspi->master); 1678 bcm_qspi_hw_uninit(qspi); 1679 clk_disable_unprepare(qspi->clk); 1680 kfree(qspi->dev_ids); 1681 1682 return 0; 1683 } 1684 /* function to be called by SoC specific platform driver remove() */ 1685 EXPORT_SYMBOL_GPL(bcm_qspi_remove); 1686 1687 static int __maybe_unused bcm_qspi_suspend(struct device *dev) 1688 { 1689 struct bcm_qspi *qspi = dev_get_drvdata(dev); 1690 1691 /* store the override strap value */ 1692 if (!bcm_qspi_bspi_ver_three(qspi)) 1693 qspi->s3_strap_override_ctrl = 1694 bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); 1695 1696 spi_master_suspend(qspi->master); 1697 clk_disable_unprepare(qspi->clk); 1698 bcm_qspi_hw_uninit(qspi); 1699 1700 return 0; 1701 }; 1702 1703 static int __maybe_unused bcm_qspi_resume(struct device *dev) 1704 { 1705 struct bcm_qspi *qspi = dev_get_drvdata(dev); 1706 int ret = 0; 1707 1708 bcm_qspi_hw_init(qspi); 1709 bcm_qspi_chip_select(qspi, qspi->curr_cs); 1710 if (qspi->soc_intc) 1711 /* enable MSPI interrupt */ 1712 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE, 1713 true); 1714 1715 ret = clk_prepare_enable(qspi->clk); 1716 if (!ret) 1717 spi_master_resume(qspi->master); 1718 1719 return ret; 1720 } 1721 1722 SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume); 1723 1724 /* pm_ops to be called by SoC specific platform driver */ 1725 EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops); 1726 1727 MODULE_AUTHOR("Kamal Dasu"); 1728 MODULE_DESCRIPTION("Broadcom QSPI driver"); 1729 MODULE_LICENSE("GPL v2"); 1730 MODULE_ALIAS("platform:" DRIVER_NAME); 1731