1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Atmel AT32 and AT91 SPI Controllers 4 * 5 * Copyright (C) 2006 Atmel Corporation 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/clk.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmaengine.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/spi/spi.h> 18 #include <linux/slab.h> 19 #include <linux/of.h> 20 21 #include <linux/io.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm_runtime.h> 25 #include <trace/events/spi.h> 26 27 /* SPI register offsets */ 28 #define SPI_CR 0x0000 29 #define SPI_MR 0x0004 30 #define SPI_RDR 0x0008 31 #define SPI_TDR 0x000c 32 #define SPI_SR 0x0010 33 #define SPI_IER 0x0014 34 #define SPI_IDR 0x0018 35 #define SPI_IMR 0x001c 36 #define SPI_CSR0 0x0030 37 #define SPI_CSR1 0x0034 38 #define SPI_CSR2 0x0038 39 #define SPI_CSR3 0x003c 40 #define SPI_FMR 0x0040 41 #define SPI_FLR 0x0044 42 #define SPI_VERSION 0x00fc 43 #define SPI_RPR 0x0100 44 #define SPI_RCR 0x0104 45 #define SPI_TPR 0x0108 46 #define SPI_TCR 0x010c 47 #define SPI_RNPR 0x0110 48 #define SPI_RNCR 0x0114 49 #define SPI_TNPR 0x0118 50 #define SPI_TNCR 0x011c 51 #define SPI_PTCR 0x0120 52 #define SPI_PTSR 0x0124 53 54 /* Bitfields in CR */ 55 #define SPI_SPIEN_OFFSET 0 56 #define SPI_SPIEN_SIZE 1 57 #define SPI_SPIDIS_OFFSET 1 58 #define SPI_SPIDIS_SIZE 1 59 #define SPI_SWRST_OFFSET 7 60 #define SPI_SWRST_SIZE 1 61 #define SPI_LASTXFER_OFFSET 24 62 #define SPI_LASTXFER_SIZE 1 63 #define SPI_TXFCLR_OFFSET 16 64 #define SPI_TXFCLR_SIZE 1 65 #define SPI_RXFCLR_OFFSET 17 66 #define SPI_RXFCLR_SIZE 1 67 #define SPI_FIFOEN_OFFSET 30 68 #define SPI_FIFOEN_SIZE 1 69 #define SPI_FIFODIS_OFFSET 31 70 #define SPI_FIFODIS_SIZE 1 71 72 /* Bitfields in MR */ 73 #define SPI_MSTR_OFFSET 0 74 #define SPI_MSTR_SIZE 1 75 #define SPI_PS_OFFSET 1 76 #define SPI_PS_SIZE 1 77 #define SPI_PCSDEC_OFFSET 2 78 #define SPI_PCSDEC_SIZE 1 79 #define SPI_FDIV_OFFSET 3 80 #define SPI_FDIV_SIZE 1 81 #define SPI_MODFDIS_OFFSET 4 82 #define SPI_MODFDIS_SIZE 1 83 #define SPI_WDRBT_OFFSET 5 84 #define SPI_WDRBT_SIZE 1 85 #define SPI_LLB_OFFSET 7 86 #define SPI_LLB_SIZE 1 87 #define SPI_PCS_OFFSET 16 88 #define SPI_PCS_SIZE 4 89 #define SPI_DLYBCS_OFFSET 24 90 #define SPI_DLYBCS_SIZE 8 91 92 /* Bitfields in RDR */ 93 #define SPI_RD_OFFSET 0 94 #define SPI_RD_SIZE 16 95 96 /* Bitfields in TDR */ 97 #define SPI_TD_OFFSET 0 98 #define SPI_TD_SIZE 16 99 100 /* Bitfields in SR */ 101 #define SPI_RDRF_OFFSET 0 102 #define SPI_RDRF_SIZE 1 103 #define SPI_TDRE_OFFSET 1 104 #define SPI_TDRE_SIZE 1 105 #define SPI_MODF_OFFSET 2 106 #define SPI_MODF_SIZE 1 107 #define SPI_OVRES_OFFSET 3 108 #define SPI_OVRES_SIZE 1 109 #define SPI_ENDRX_OFFSET 4 110 #define SPI_ENDRX_SIZE 1 111 #define SPI_ENDTX_OFFSET 5 112 #define SPI_ENDTX_SIZE 1 113 #define SPI_RXBUFF_OFFSET 6 114 #define SPI_RXBUFF_SIZE 1 115 #define SPI_TXBUFE_OFFSET 7 116 #define SPI_TXBUFE_SIZE 1 117 #define SPI_NSSR_OFFSET 8 118 #define SPI_NSSR_SIZE 1 119 #define SPI_TXEMPTY_OFFSET 9 120 #define SPI_TXEMPTY_SIZE 1 121 #define SPI_SPIENS_OFFSET 16 122 #define SPI_SPIENS_SIZE 1 123 #define SPI_TXFEF_OFFSET 24 124 #define SPI_TXFEF_SIZE 1 125 #define SPI_TXFFF_OFFSET 25 126 #define SPI_TXFFF_SIZE 1 127 #define SPI_TXFTHF_OFFSET 26 128 #define SPI_TXFTHF_SIZE 1 129 #define SPI_RXFEF_OFFSET 27 130 #define SPI_RXFEF_SIZE 1 131 #define SPI_RXFFF_OFFSET 28 132 #define SPI_RXFFF_SIZE 1 133 #define SPI_RXFTHF_OFFSET 29 134 #define SPI_RXFTHF_SIZE 1 135 #define SPI_TXFPTEF_OFFSET 30 136 #define SPI_TXFPTEF_SIZE 1 137 #define SPI_RXFPTEF_OFFSET 31 138 #define SPI_RXFPTEF_SIZE 1 139 140 /* Bitfields in CSR0 */ 141 #define SPI_CPOL_OFFSET 0 142 #define SPI_CPOL_SIZE 1 143 #define SPI_NCPHA_OFFSET 1 144 #define SPI_NCPHA_SIZE 1 145 #define SPI_CSAAT_OFFSET 3 146 #define SPI_CSAAT_SIZE 1 147 #define SPI_BITS_OFFSET 4 148 #define SPI_BITS_SIZE 4 149 #define SPI_SCBR_OFFSET 8 150 #define SPI_SCBR_SIZE 8 151 #define SPI_DLYBS_OFFSET 16 152 #define SPI_DLYBS_SIZE 8 153 #define SPI_DLYBCT_OFFSET 24 154 #define SPI_DLYBCT_SIZE 8 155 156 /* Bitfields in RCR */ 157 #define SPI_RXCTR_OFFSET 0 158 #define SPI_RXCTR_SIZE 16 159 160 /* Bitfields in TCR */ 161 #define SPI_TXCTR_OFFSET 0 162 #define SPI_TXCTR_SIZE 16 163 164 /* Bitfields in RNCR */ 165 #define SPI_RXNCR_OFFSET 0 166 #define SPI_RXNCR_SIZE 16 167 168 /* Bitfields in TNCR */ 169 #define SPI_TXNCR_OFFSET 0 170 #define SPI_TXNCR_SIZE 16 171 172 /* Bitfields in PTCR */ 173 #define SPI_RXTEN_OFFSET 0 174 #define SPI_RXTEN_SIZE 1 175 #define SPI_RXTDIS_OFFSET 1 176 #define SPI_RXTDIS_SIZE 1 177 #define SPI_TXTEN_OFFSET 8 178 #define SPI_TXTEN_SIZE 1 179 #define SPI_TXTDIS_OFFSET 9 180 #define SPI_TXTDIS_SIZE 1 181 182 /* Bitfields in FMR */ 183 #define SPI_TXRDYM_OFFSET 0 184 #define SPI_TXRDYM_SIZE 2 185 #define SPI_RXRDYM_OFFSET 4 186 #define SPI_RXRDYM_SIZE 2 187 #define SPI_TXFTHRES_OFFSET 16 188 #define SPI_TXFTHRES_SIZE 6 189 #define SPI_RXFTHRES_OFFSET 24 190 #define SPI_RXFTHRES_SIZE 6 191 192 /* Bitfields in FLR */ 193 #define SPI_TXFL_OFFSET 0 194 #define SPI_TXFL_SIZE 6 195 #define SPI_RXFL_OFFSET 16 196 #define SPI_RXFL_SIZE 6 197 198 /* Constants for BITS */ 199 #define SPI_BITS_8_BPT 0 200 #define SPI_BITS_9_BPT 1 201 #define SPI_BITS_10_BPT 2 202 #define SPI_BITS_11_BPT 3 203 #define SPI_BITS_12_BPT 4 204 #define SPI_BITS_13_BPT 5 205 #define SPI_BITS_14_BPT 6 206 #define SPI_BITS_15_BPT 7 207 #define SPI_BITS_16_BPT 8 208 #define SPI_ONE_DATA 0 209 #define SPI_TWO_DATA 1 210 #define SPI_FOUR_DATA 2 211 212 /* Bit manipulation macros */ 213 #define SPI_BIT(name) \ 214 (1 << SPI_##name##_OFFSET) 215 #define SPI_BF(name, value) \ 216 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) 217 #define SPI_BFEXT(name, value) \ 218 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) 219 #define SPI_BFINS(name, value, old) \ 220 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ 221 | SPI_BF(name, value)) 222 223 /* Register access macros */ 224 #define spi_readl(port, reg) \ 225 readl_relaxed((port)->regs + SPI_##reg) 226 #define spi_writel(port, reg, value) \ 227 writel_relaxed((value), (port)->regs + SPI_##reg) 228 #define spi_writew(port, reg, value) \ 229 writew_relaxed((value), (port)->regs + SPI_##reg) 230 231 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 232 * cache operations; better heuristics consider wordsize and bitrate. 233 */ 234 #define DMA_MIN_BYTES 16 235 236 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) 237 238 #define AUTOSUSPEND_TIMEOUT 2000 239 240 struct atmel_spi_caps { 241 bool is_spi2; 242 bool has_wdrbt; 243 bool has_dma_support; 244 bool has_pdc_support; 245 }; 246 247 /* 248 * The core SPI transfer engine just talks to a register bank to set up 249 * DMA transfers; transfer queue progress is driven by IRQs. The clock 250 * framework provides the base clock, subdivided for each spi_device. 251 */ 252 struct atmel_spi { 253 spinlock_t lock; 254 unsigned long flags; 255 256 phys_addr_t phybase; 257 void __iomem *regs; 258 int irq; 259 struct clk *clk; 260 struct platform_device *pdev; 261 unsigned long spi_clk; 262 263 struct spi_transfer *current_transfer; 264 int current_remaining_bytes; 265 int done_status; 266 dma_addr_t dma_addr_rx_bbuf; 267 dma_addr_t dma_addr_tx_bbuf; 268 void *addr_rx_bbuf; 269 void *addr_tx_bbuf; 270 271 struct completion xfer_completion; 272 273 struct atmel_spi_caps caps; 274 275 bool use_dma; 276 bool use_pdc; 277 278 bool keep_cs; 279 280 u32 fifo_size; 281 u8 native_cs_free; 282 u8 native_cs_for_gpio; 283 }; 284 285 /* Controller-specific per-slave state */ 286 struct atmel_spi_device { 287 u32 csr; 288 }; 289 290 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */ 291 #define INVALID_DMA_ADDRESS 0xffffffff 292 293 /* 294 * Version 2 of the SPI controller has 295 * - CR.LASTXFER 296 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) 297 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) 298 * - SPI_CSRx.CSAAT 299 * - SPI_CSRx.SBCR allows faster clocking 300 */ 301 static bool atmel_spi_is_v2(struct atmel_spi *as) 302 { 303 return as->caps.is_spi2; 304 } 305 306 /* 307 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby 308 * they assume that spi slave device state will not change on deselect, so 309 * that automagic deselection is OK. ("NPCSx rises if no data is to be 310 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer 311 * controllers have CSAAT and friends. 312 * 313 * Even controller newer than ar91rm9200, using GPIOs can make sens as 314 * it lets us support active-high chipselects despite the controller's 315 * belief that only active-low devices/systems exists. 316 * 317 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work 318 * right when driven with GPIO. ("Mode Fault does not allow more than one 319 * Master on Chip Select 0.") No workaround exists for that ... so for 320 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, 321 * and (c) will trigger that first erratum in some cases. 322 */ 323 324 static void cs_activate(struct atmel_spi *as, struct spi_device *spi) 325 { 326 struct atmel_spi_device *asd = spi->controller_state; 327 int chip_select; 328 u32 mr; 329 330 if (spi->cs_gpiod) 331 chip_select = as->native_cs_for_gpio; 332 else 333 chip_select = spi->chip_select; 334 335 if (atmel_spi_is_v2(as)) { 336 spi_writel(as, CSR0 + 4 * chip_select, asd->csr); 337 /* For the low SPI version, there is a issue that PDC transfer 338 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS 339 */ 340 spi_writel(as, CSR0, asd->csr); 341 if (as->caps.has_wdrbt) { 342 spi_writel(as, MR, 343 SPI_BF(PCS, ~(0x01 << chip_select)) 344 | SPI_BIT(WDRBT) 345 | SPI_BIT(MODFDIS) 346 | SPI_BIT(MSTR)); 347 } else { 348 spi_writel(as, MR, 349 SPI_BF(PCS, ~(0x01 << chip_select)) 350 | SPI_BIT(MODFDIS) 351 | SPI_BIT(MSTR)); 352 } 353 354 mr = spi_readl(as, MR); 355 } else { 356 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; 357 int i; 358 u32 csr; 359 360 /* Make sure clock polarity is correct */ 361 for (i = 0; i < spi->master->num_chipselect; i++) { 362 csr = spi_readl(as, CSR0 + 4 * i); 363 if ((csr ^ cpol) & SPI_BIT(CPOL)) 364 spi_writel(as, CSR0 + 4 * i, 365 csr ^ SPI_BIT(CPOL)); 366 } 367 368 mr = spi_readl(as, MR); 369 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr); 370 spi_writel(as, MR, mr); 371 } 372 373 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr); 374 } 375 376 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) 377 { 378 int chip_select; 379 u32 mr; 380 381 if (spi->cs_gpiod) 382 chip_select = as->native_cs_for_gpio; 383 else 384 chip_select = spi->chip_select; 385 386 /* only deactivate *this* device; sometimes transfers to 387 * another device may be active when this routine is called. 388 */ 389 mr = spi_readl(as, MR); 390 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) { 391 mr = SPI_BFINS(PCS, 0xf, mr); 392 spi_writel(as, MR, mr); 393 } 394 395 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr); 396 397 if (!spi->cs_gpiod) 398 spi_writel(as, CR, SPI_BIT(LASTXFER)); 399 } 400 401 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock) 402 { 403 spin_lock_irqsave(&as->lock, as->flags); 404 } 405 406 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock) 407 { 408 spin_unlock_irqrestore(&as->lock, as->flags); 409 } 410 411 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer) 412 { 413 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf); 414 } 415 416 static inline bool atmel_spi_use_dma(struct atmel_spi *as, 417 struct spi_transfer *xfer) 418 { 419 return as->use_dma && xfer->len >= DMA_MIN_BYTES; 420 } 421 422 static bool atmel_spi_can_dma(struct spi_master *master, 423 struct spi_device *spi, 424 struct spi_transfer *xfer) 425 { 426 struct atmel_spi *as = spi_master_get_devdata(master); 427 428 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) 429 return atmel_spi_use_dma(as, xfer) && 430 !atmel_spi_is_vmalloc_xfer(xfer); 431 else 432 return atmel_spi_use_dma(as, xfer); 433 434 } 435 436 static int atmel_spi_dma_slave_config(struct atmel_spi *as, 437 struct dma_slave_config *slave_config, 438 u8 bits_per_word) 439 { 440 struct spi_master *master = platform_get_drvdata(as->pdev); 441 int err = 0; 442 443 if (bits_per_word > 8) { 444 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 445 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 446 } else { 447 slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 448 slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 449 } 450 451 slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR; 452 slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR; 453 slave_config->src_maxburst = 1; 454 slave_config->dst_maxburst = 1; 455 slave_config->device_fc = false; 456 457 /* 458 * This driver uses fixed peripheral select mode (PS bit set to '0' in 459 * the Mode Register). 460 * So according to the datasheet, when FIFOs are available (and 461 * enabled), the Transmit FIFO operates in Multiple Data Mode. 462 * In this mode, up to 2 data, not 4, can be written into the Transmit 463 * Data Register in a single access. 464 * However, the first data has to be written into the lowest 16 bits and 465 * the second data into the highest 16 bits of the Transmit 466 * Data Register. For 8bit data (the most frequent case), it would 467 * require to rework tx_buf so each data would actualy fit 16 bits. 468 * So we'd rather write only one data at the time. Hence the transmit 469 * path works the same whether FIFOs are available (and enabled) or not. 470 */ 471 slave_config->direction = DMA_MEM_TO_DEV; 472 if (dmaengine_slave_config(master->dma_tx, slave_config)) { 473 dev_err(&as->pdev->dev, 474 "failed to configure tx dma channel\n"); 475 err = -EINVAL; 476 } 477 478 /* 479 * This driver configures the spi controller for master mode (MSTR bit 480 * set to '1' in the Mode Register). 481 * So according to the datasheet, when FIFOs are available (and 482 * enabled), the Receive FIFO operates in Single Data Mode. 483 * So the receive path works the same whether FIFOs are available (and 484 * enabled) or not. 485 */ 486 slave_config->direction = DMA_DEV_TO_MEM; 487 if (dmaengine_slave_config(master->dma_rx, slave_config)) { 488 dev_err(&as->pdev->dev, 489 "failed to configure rx dma channel\n"); 490 err = -EINVAL; 491 } 492 493 return err; 494 } 495 496 static int atmel_spi_configure_dma(struct spi_master *master, 497 struct atmel_spi *as) 498 { 499 struct dma_slave_config slave_config; 500 struct device *dev = &as->pdev->dev; 501 int err; 502 503 master->dma_tx = dma_request_chan(dev, "tx"); 504 if (IS_ERR(master->dma_tx)) { 505 err = PTR_ERR(master->dma_tx); 506 dev_dbg(dev, "No TX DMA channel, DMA is disabled\n"); 507 goto error_clear; 508 } 509 510 master->dma_rx = dma_request_chan(dev, "rx"); 511 if (IS_ERR(master->dma_rx)) { 512 err = PTR_ERR(master->dma_rx); 513 /* 514 * No reason to check EPROBE_DEFER here since we have already 515 * requested tx channel. 516 */ 517 dev_dbg(dev, "No RX DMA channel, DMA is disabled\n"); 518 goto error; 519 } 520 521 err = atmel_spi_dma_slave_config(as, &slave_config, 8); 522 if (err) 523 goto error; 524 525 dev_info(&as->pdev->dev, 526 "Using %s (tx) and %s (rx) for DMA transfers\n", 527 dma_chan_name(master->dma_tx), 528 dma_chan_name(master->dma_rx)); 529 530 return 0; 531 error: 532 if (!IS_ERR(master->dma_rx)) 533 dma_release_channel(master->dma_rx); 534 if (!IS_ERR(master->dma_tx)) 535 dma_release_channel(master->dma_tx); 536 error_clear: 537 master->dma_tx = master->dma_rx = NULL; 538 return err; 539 } 540 541 static void atmel_spi_stop_dma(struct spi_master *master) 542 { 543 if (master->dma_rx) 544 dmaengine_terminate_all(master->dma_rx); 545 if (master->dma_tx) 546 dmaengine_terminate_all(master->dma_tx); 547 } 548 549 static void atmel_spi_release_dma(struct spi_master *master) 550 { 551 if (master->dma_rx) { 552 dma_release_channel(master->dma_rx); 553 master->dma_rx = NULL; 554 } 555 if (master->dma_tx) { 556 dma_release_channel(master->dma_tx); 557 master->dma_tx = NULL; 558 } 559 } 560 561 /* This function is called by the DMA driver from tasklet context */ 562 static void dma_callback(void *data) 563 { 564 struct spi_master *master = data; 565 struct atmel_spi *as = spi_master_get_devdata(master); 566 567 if (is_vmalloc_addr(as->current_transfer->rx_buf) && 568 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 569 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf, 570 as->current_transfer->len); 571 } 572 complete(&as->xfer_completion); 573 } 574 575 /* 576 * Next transfer using PIO without FIFO. 577 */ 578 static void atmel_spi_next_xfer_single(struct spi_master *master, 579 struct spi_transfer *xfer) 580 { 581 struct atmel_spi *as = spi_master_get_devdata(master); 582 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 583 584 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n"); 585 586 /* Make sure data is not remaining in RDR */ 587 spi_readl(as, RDR); 588 while (spi_readl(as, SR) & SPI_BIT(RDRF)) { 589 spi_readl(as, RDR); 590 cpu_relax(); 591 } 592 593 if (xfer->bits_per_word > 8) 594 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); 595 else 596 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos)); 597 598 dev_dbg(master->dev.parent, 599 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", 600 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 601 xfer->bits_per_word); 602 603 /* Enable relevant interrupts */ 604 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES)); 605 } 606 607 /* 608 * Next transfer using PIO with FIFO. 609 */ 610 static void atmel_spi_next_xfer_fifo(struct spi_master *master, 611 struct spi_transfer *xfer) 612 { 613 struct atmel_spi *as = spi_master_get_devdata(master); 614 u32 current_remaining_data, num_data; 615 u32 offset = xfer->len - as->current_remaining_bytes; 616 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset); 617 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset); 618 u16 td0, td1; 619 u32 fifomr; 620 621 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n"); 622 623 /* Compute the number of data to transfer in the current iteration */ 624 current_remaining_data = ((xfer->bits_per_word > 8) ? 625 ((u32)as->current_remaining_bytes >> 1) : 626 (u32)as->current_remaining_bytes); 627 num_data = min(current_remaining_data, as->fifo_size); 628 629 /* Flush RX and TX FIFOs */ 630 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR)); 631 while (spi_readl(as, FLR)) 632 cpu_relax(); 633 634 /* Set RX FIFO Threshold to the number of data to transfer */ 635 fifomr = spi_readl(as, FMR); 636 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr)); 637 638 /* Clear FIFO flags in the Status Register, especially RXFTHF */ 639 (void)spi_readl(as, SR); 640 641 /* Fill TX FIFO */ 642 while (num_data >= 2) { 643 if (xfer->bits_per_word > 8) { 644 td0 = *words++; 645 td1 = *words++; 646 } else { 647 td0 = *bytes++; 648 td1 = *bytes++; 649 } 650 651 spi_writel(as, TDR, (td1 << 16) | td0); 652 num_data -= 2; 653 } 654 655 if (num_data) { 656 if (xfer->bits_per_word > 8) 657 td0 = *words++; 658 else 659 td0 = *bytes++; 660 661 spi_writew(as, TDR, td0); 662 num_data--; 663 } 664 665 dev_dbg(master->dev.parent, 666 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n", 667 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 668 xfer->bits_per_word); 669 670 /* 671 * Enable RX FIFO Threshold Flag interrupt to be notified about 672 * transfer completion. 673 */ 674 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES)); 675 } 676 677 /* 678 * Next transfer using PIO. 679 */ 680 static void atmel_spi_next_xfer_pio(struct spi_master *master, 681 struct spi_transfer *xfer) 682 { 683 struct atmel_spi *as = spi_master_get_devdata(master); 684 685 if (as->fifo_size) 686 atmel_spi_next_xfer_fifo(master, xfer); 687 else 688 atmel_spi_next_xfer_single(master, xfer); 689 } 690 691 /* 692 * Submit next transfer for DMA. 693 */ 694 static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, 695 struct spi_transfer *xfer, 696 u32 *plen) 697 { 698 struct atmel_spi *as = spi_master_get_devdata(master); 699 struct dma_chan *rxchan = master->dma_rx; 700 struct dma_chan *txchan = master->dma_tx; 701 struct dma_async_tx_descriptor *rxdesc; 702 struct dma_async_tx_descriptor *txdesc; 703 struct dma_slave_config slave_config; 704 dma_cookie_t cookie; 705 706 dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); 707 708 /* Check that the channels are available */ 709 if (!rxchan || !txchan) 710 return -ENODEV; 711 712 713 *plen = xfer->len; 714 715 if (atmel_spi_dma_slave_config(as, &slave_config, 716 xfer->bits_per_word)) 717 goto err_exit; 718 719 /* Send both scatterlists */ 720 if (atmel_spi_is_vmalloc_xfer(xfer) && 721 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 722 rxdesc = dmaengine_prep_slave_single(rxchan, 723 as->dma_addr_rx_bbuf, 724 xfer->len, 725 DMA_DEV_TO_MEM, 726 DMA_PREP_INTERRUPT | 727 DMA_CTRL_ACK); 728 } else { 729 rxdesc = dmaengine_prep_slave_sg(rxchan, 730 xfer->rx_sg.sgl, 731 xfer->rx_sg.nents, 732 DMA_DEV_TO_MEM, 733 DMA_PREP_INTERRUPT | 734 DMA_CTRL_ACK); 735 } 736 if (!rxdesc) 737 goto err_dma; 738 739 if (atmel_spi_is_vmalloc_xfer(xfer) && 740 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 741 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len); 742 txdesc = dmaengine_prep_slave_single(txchan, 743 as->dma_addr_tx_bbuf, 744 xfer->len, DMA_MEM_TO_DEV, 745 DMA_PREP_INTERRUPT | 746 DMA_CTRL_ACK); 747 } else { 748 txdesc = dmaengine_prep_slave_sg(txchan, 749 xfer->tx_sg.sgl, 750 xfer->tx_sg.nents, 751 DMA_MEM_TO_DEV, 752 DMA_PREP_INTERRUPT | 753 DMA_CTRL_ACK); 754 } 755 if (!txdesc) 756 goto err_dma; 757 758 dev_dbg(master->dev.parent, 759 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 760 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma, 761 xfer->rx_buf, (unsigned long long)xfer->rx_dma); 762 763 /* Enable relevant interrupts */ 764 spi_writel(as, IER, SPI_BIT(OVRES)); 765 766 /* Put the callback on the RX transfer only, that should finish last */ 767 rxdesc->callback = dma_callback; 768 rxdesc->callback_param = master; 769 770 /* Submit and fire RX and TX with TX last so we're ready to read! */ 771 cookie = rxdesc->tx_submit(rxdesc); 772 if (dma_submit_error(cookie)) 773 goto err_dma; 774 cookie = txdesc->tx_submit(txdesc); 775 if (dma_submit_error(cookie)) 776 goto err_dma; 777 rxchan->device->device_issue_pending(rxchan); 778 txchan->device->device_issue_pending(txchan); 779 780 return 0; 781 782 err_dma: 783 spi_writel(as, IDR, SPI_BIT(OVRES)); 784 atmel_spi_stop_dma(master); 785 err_exit: 786 return -ENOMEM; 787 } 788 789 static void atmel_spi_next_xfer_data(struct spi_master *master, 790 struct spi_transfer *xfer, 791 dma_addr_t *tx_dma, 792 dma_addr_t *rx_dma, 793 u32 *plen) 794 { 795 *rx_dma = xfer->rx_dma + xfer->len - *plen; 796 *tx_dma = xfer->tx_dma + xfer->len - *plen; 797 if (*plen > master->max_dma_len) 798 *plen = master->max_dma_len; 799 } 800 801 static int atmel_spi_set_xfer_speed(struct atmel_spi *as, 802 struct spi_device *spi, 803 struct spi_transfer *xfer) 804 { 805 u32 scbr, csr; 806 unsigned long bus_hz; 807 int chip_select; 808 809 if (spi->cs_gpiod) 810 chip_select = as->native_cs_for_gpio; 811 else 812 chip_select = spi->chip_select; 813 814 /* v1 chips start out at half the peripheral bus speed. */ 815 bus_hz = as->spi_clk; 816 if (!atmel_spi_is_v2(as)) 817 bus_hz /= 2; 818 819 /* 820 * Calculate the lowest divider that satisfies the 821 * constraint, assuming div32/fdiv/mbz == 0. 822 */ 823 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz); 824 825 /* 826 * If the resulting divider doesn't fit into the 827 * register bitfield, we can't satisfy the constraint. 828 */ 829 if (scbr >= (1 << SPI_SCBR_SIZE)) { 830 dev_err(&spi->dev, 831 "setup: %d Hz too slow, scbr %u; min %ld Hz\n", 832 xfer->speed_hz, scbr, bus_hz/255); 833 return -EINVAL; 834 } 835 if (scbr == 0) { 836 dev_err(&spi->dev, 837 "setup: %d Hz too high, scbr %u; max %ld Hz\n", 838 xfer->speed_hz, scbr, bus_hz); 839 return -EINVAL; 840 } 841 csr = spi_readl(as, CSR0 + 4 * chip_select); 842 csr = SPI_BFINS(SCBR, scbr, csr); 843 spi_writel(as, CSR0 + 4 * chip_select, csr); 844 xfer->effective_speed_hz = bus_hz / scbr; 845 846 return 0; 847 } 848 849 /* 850 * Submit next transfer for PDC. 851 * lock is held, spi irq is blocked 852 */ 853 static void atmel_spi_pdc_next_xfer(struct spi_master *master, 854 struct spi_transfer *xfer) 855 { 856 struct atmel_spi *as = spi_master_get_devdata(master); 857 u32 len; 858 dma_addr_t tx_dma, rx_dma; 859 860 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 861 862 len = as->current_remaining_bytes; 863 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); 864 as->current_remaining_bytes -= len; 865 866 spi_writel(as, RPR, rx_dma); 867 spi_writel(as, TPR, tx_dma); 868 869 if (xfer->bits_per_word > 8) 870 len >>= 1; 871 spi_writel(as, RCR, len); 872 spi_writel(as, TCR, len); 873 874 dev_dbg(&master->dev, 875 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 876 xfer, xfer->len, xfer->tx_buf, 877 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 878 (unsigned long long)xfer->rx_dma); 879 880 if (as->current_remaining_bytes) { 881 len = as->current_remaining_bytes; 882 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len); 883 as->current_remaining_bytes -= len; 884 885 spi_writel(as, RNPR, rx_dma); 886 spi_writel(as, TNPR, tx_dma); 887 888 if (xfer->bits_per_word > 8) 889 len >>= 1; 890 spi_writel(as, RNCR, len); 891 spi_writel(as, TNCR, len); 892 893 dev_dbg(&master->dev, 894 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 895 xfer, xfer->len, xfer->tx_buf, 896 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 897 (unsigned long long)xfer->rx_dma); 898 } 899 900 /* REVISIT: We're waiting for RXBUFF before we start the next 901 * transfer because we need to handle some difficult timing 902 * issues otherwise. If we wait for TXBUFE in one transfer and 903 * then starts waiting for RXBUFF in the next, it's difficult 904 * to tell the difference between the RXBUFF interrupt we're 905 * actually waiting for and the RXBUFF interrupt of the 906 * previous transfer. 907 * 908 * It should be doable, though. Just not now... 909 */ 910 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES)); 911 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); 912 } 913 914 /* 915 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: 916 * - The buffer is either valid for CPU access, else NULL 917 * - If the buffer is valid, so is its DMA address 918 * 919 * This driver manages the dma address unless message->is_dma_mapped. 920 */ 921 static int 922 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) 923 { 924 struct device *dev = &as->pdev->dev; 925 926 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; 927 if (xfer->tx_buf) { 928 /* tx_buf is a const void* where we need a void * for the dma 929 * mapping */ 930 void *nonconst_tx = (void *)xfer->tx_buf; 931 932 xfer->tx_dma = dma_map_single(dev, 933 nonconst_tx, xfer->len, 934 DMA_TO_DEVICE); 935 if (dma_mapping_error(dev, xfer->tx_dma)) 936 return -ENOMEM; 937 } 938 if (xfer->rx_buf) { 939 xfer->rx_dma = dma_map_single(dev, 940 xfer->rx_buf, xfer->len, 941 DMA_FROM_DEVICE); 942 if (dma_mapping_error(dev, xfer->rx_dma)) { 943 if (xfer->tx_buf) 944 dma_unmap_single(dev, 945 xfer->tx_dma, xfer->len, 946 DMA_TO_DEVICE); 947 return -ENOMEM; 948 } 949 } 950 return 0; 951 } 952 953 static void atmel_spi_dma_unmap_xfer(struct spi_master *master, 954 struct spi_transfer *xfer) 955 { 956 if (xfer->tx_dma != INVALID_DMA_ADDRESS) 957 dma_unmap_single(master->dev.parent, xfer->tx_dma, 958 xfer->len, DMA_TO_DEVICE); 959 if (xfer->rx_dma != INVALID_DMA_ADDRESS) 960 dma_unmap_single(master->dev.parent, xfer->rx_dma, 961 xfer->len, DMA_FROM_DEVICE); 962 } 963 964 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as) 965 { 966 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 967 } 968 969 static void 970 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer) 971 { 972 u8 *rxp; 973 u16 *rxp16; 974 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 975 976 if (xfer->bits_per_word > 8) { 977 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); 978 *rxp16 = spi_readl(as, RDR); 979 } else { 980 rxp = ((u8 *)xfer->rx_buf) + xfer_pos; 981 *rxp = spi_readl(as, RDR); 982 } 983 if (xfer->bits_per_word > 8) { 984 if (as->current_remaining_bytes > 2) 985 as->current_remaining_bytes -= 2; 986 else 987 as->current_remaining_bytes = 0; 988 } else { 989 as->current_remaining_bytes--; 990 } 991 } 992 993 static void 994 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer) 995 { 996 u32 fifolr = spi_readl(as, FLR); 997 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr); 998 u32 offset = xfer->len - as->current_remaining_bytes; 999 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset); 1000 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset); 1001 u16 rd; /* RD field is the lowest 16 bits of RDR */ 1002 1003 /* Update the number of remaining bytes to transfer */ 1004 num_bytes = ((xfer->bits_per_word > 8) ? 1005 (num_data << 1) : 1006 num_data); 1007 1008 if (as->current_remaining_bytes > num_bytes) 1009 as->current_remaining_bytes -= num_bytes; 1010 else 1011 as->current_remaining_bytes = 0; 1012 1013 /* Handle odd number of bytes when data are more than 8bit width */ 1014 if (xfer->bits_per_word > 8) 1015 as->current_remaining_bytes &= ~0x1; 1016 1017 /* Read data */ 1018 while (num_data) { 1019 rd = spi_readl(as, RDR); 1020 if (xfer->bits_per_word > 8) 1021 *words++ = rd; 1022 else 1023 *bytes++ = rd; 1024 num_data--; 1025 } 1026 } 1027 1028 /* Called from IRQ 1029 * 1030 * Must update "current_remaining_bytes" to keep track of data 1031 * to transfer. 1032 */ 1033 static void 1034 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) 1035 { 1036 if (as->fifo_size) 1037 atmel_spi_pump_fifo_data(as, xfer); 1038 else 1039 atmel_spi_pump_single_data(as, xfer); 1040 } 1041 1042 /* Interrupt 1043 * 1044 */ 1045 static irqreturn_t 1046 atmel_spi_pio_interrupt(int irq, void *dev_id) 1047 { 1048 struct spi_master *master = dev_id; 1049 struct atmel_spi *as = spi_master_get_devdata(master); 1050 u32 status, pending, imr; 1051 struct spi_transfer *xfer; 1052 int ret = IRQ_NONE; 1053 1054 imr = spi_readl(as, IMR); 1055 status = spi_readl(as, SR); 1056 pending = status & imr; 1057 1058 if (pending & SPI_BIT(OVRES)) { 1059 ret = IRQ_HANDLED; 1060 spi_writel(as, IDR, SPI_BIT(OVRES)); 1061 dev_warn(master->dev.parent, "overrun\n"); 1062 1063 /* 1064 * When we get an overrun, we disregard the current 1065 * transfer. Data will not be copied back from any 1066 * bounce buffer and msg->actual_len will not be 1067 * updated with the last xfer. 1068 * 1069 * We will also not process any remaning transfers in 1070 * the message. 1071 */ 1072 as->done_status = -EIO; 1073 smp_wmb(); 1074 1075 /* Clear any overrun happening while cleaning up */ 1076 spi_readl(as, SR); 1077 1078 complete(&as->xfer_completion); 1079 1080 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) { 1081 atmel_spi_lock(as); 1082 1083 if (as->current_remaining_bytes) { 1084 ret = IRQ_HANDLED; 1085 xfer = as->current_transfer; 1086 atmel_spi_pump_pio_data(as, xfer); 1087 if (!as->current_remaining_bytes) 1088 spi_writel(as, IDR, pending); 1089 1090 complete(&as->xfer_completion); 1091 } 1092 1093 atmel_spi_unlock(as); 1094 } else { 1095 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending); 1096 ret = IRQ_HANDLED; 1097 spi_writel(as, IDR, pending); 1098 } 1099 1100 return ret; 1101 } 1102 1103 static irqreturn_t 1104 atmel_spi_pdc_interrupt(int irq, void *dev_id) 1105 { 1106 struct spi_master *master = dev_id; 1107 struct atmel_spi *as = spi_master_get_devdata(master); 1108 u32 status, pending, imr; 1109 int ret = IRQ_NONE; 1110 1111 imr = spi_readl(as, IMR); 1112 status = spi_readl(as, SR); 1113 pending = status & imr; 1114 1115 if (pending & SPI_BIT(OVRES)) { 1116 1117 ret = IRQ_HANDLED; 1118 1119 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) 1120 | SPI_BIT(OVRES))); 1121 1122 /* Clear any overrun happening while cleaning up */ 1123 spi_readl(as, SR); 1124 1125 as->done_status = -EIO; 1126 1127 complete(&as->xfer_completion); 1128 1129 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { 1130 ret = IRQ_HANDLED; 1131 1132 spi_writel(as, IDR, pending); 1133 1134 complete(&as->xfer_completion); 1135 } 1136 1137 return ret; 1138 } 1139 1140 static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as) 1141 { 1142 struct spi_delay *delay = &spi->word_delay; 1143 u32 value = delay->value; 1144 1145 switch (delay->unit) { 1146 case SPI_DELAY_UNIT_NSECS: 1147 value /= 1000; 1148 break; 1149 case SPI_DELAY_UNIT_USECS: 1150 break; 1151 default: 1152 return -EINVAL; 1153 } 1154 1155 return (as->spi_clk / 1000000 * value) >> 5; 1156 } 1157 1158 static void initialize_native_cs_for_gpio(struct atmel_spi *as) 1159 { 1160 int i; 1161 struct spi_master *master = platform_get_drvdata(as->pdev); 1162 1163 if (!as->native_cs_free) 1164 return; /* already initialized */ 1165 1166 if (!master->cs_gpiods) 1167 return; /* No CS GPIO */ 1168 1169 /* 1170 * On the first version of the controller (AT91RM9200), CS0 1171 * can't be used associated with GPIO 1172 */ 1173 if (atmel_spi_is_v2(as)) 1174 i = 0; 1175 else 1176 i = 1; 1177 1178 for (; i < 4; i++) 1179 if (master->cs_gpiods[i]) 1180 as->native_cs_free |= BIT(i); 1181 1182 if (as->native_cs_free) 1183 as->native_cs_for_gpio = ffs(as->native_cs_free); 1184 } 1185 1186 static int atmel_spi_setup(struct spi_device *spi) 1187 { 1188 struct atmel_spi *as; 1189 struct atmel_spi_device *asd; 1190 u32 csr; 1191 unsigned int bits = spi->bits_per_word; 1192 int chip_select; 1193 int word_delay_csr; 1194 1195 as = spi_master_get_devdata(spi->master); 1196 1197 /* see notes above re chipselect */ 1198 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH)) { 1199 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); 1200 return -EINVAL; 1201 } 1202 1203 /* Setup() is called during spi_register_controller(aka 1204 * spi_register_master) but after all membmers of the cs_gpiod 1205 * array have been filled, so we can looked for which native 1206 * CS will be free for using with GPIO 1207 */ 1208 initialize_native_cs_for_gpio(as); 1209 1210 if (spi->cs_gpiod && as->native_cs_free) { 1211 dev_err(&spi->dev, 1212 "No native CS available to support this GPIO CS\n"); 1213 return -EBUSY; 1214 } 1215 1216 if (spi->cs_gpiod) 1217 chip_select = as->native_cs_for_gpio; 1218 else 1219 chip_select = spi->chip_select; 1220 1221 csr = SPI_BF(BITS, bits - 8); 1222 if (spi->mode & SPI_CPOL) 1223 csr |= SPI_BIT(CPOL); 1224 if (!(spi->mode & SPI_CPHA)) 1225 csr |= SPI_BIT(NCPHA); 1226 1227 if (!spi->cs_gpiod) 1228 csr |= SPI_BIT(CSAAT); 1229 csr |= SPI_BF(DLYBS, 0); 1230 1231 word_delay_csr = atmel_word_delay_csr(spi, as); 1232 if (word_delay_csr < 0) 1233 return word_delay_csr; 1234 1235 /* DLYBCT adds delays between words. This is useful for slow devices 1236 * that need a bit of time to setup the next transfer. 1237 */ 1238 csr |= SPI_BF(DLYBCT, word_delay_csr); 1239 1240 asd = spi->controller_state; 1241 if (!asd) { 1242 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); 1243 if (!asd) 1244 return -ENOMEM; 1245 1246 spi->controller_state = asd; 1247 } 1248 1249 asd->csr = csr; 1250 1251 dev_dbg(&spi->dev, 1252 "setup: bpw %u mode 0x%x -> csr%d %08x\n", 1253 bits, spi->mode, spi->chip_select, csr); 1254 1255 if (!atmel_spi_is_v2(as)) 1256 spi_writel(as, CSR0 + 4 * chip_select, csr); 1257 1258 return 0; 1259 } 1260 1261 static void atmel_spi_set_cs(struct spi_device *spi, bool enable) 1262 { 1263 struct atmel_spi *as = spi_master_get_devdata(spi->master); 1264 /* the core doesn't really pass us enable/disable, but CS HIGH vs CS LOW 1265 * since we already have routines for activate/deactivate translate 1266 * high/low to active/inactive 1267 */ 1268 enable = (!!(spi->mode & SPI_CS_HIGH) == enable); 1269 1270 if (enable) { 1271 cs_activate(as, spi); 1272 } else { 1273 cs_deactivate(as, spi); 1274 } 1275 1276 } 1277 1278 static int atmel_spi_one_transfer(struct spi_master *master, 1279 struct spi_device *spi, 1280 struct spi_transfer *xfer) 1281 { 1282 struct atmel_spi *as; 1283 u8 bits; 1284 u32 len; 1285 struct atmel_spi_device *asd; 1286 int timeout; 1287 int ret; 1288 unsigned long dma_timeout; 1289 1290 as = spi_master_get_devdata(master); 1291 1292 asd = spi->controller_state; 1293 bits = (asd->csr >> 4) & 0xf; 1294 if (bits != xfer->bits_per_word - 8) { 1295 dev_dbg(&spi->dev, 1296 "you can't yet change bits_per_word in transfers\n"); 1297 return -ENOPROTOOPT; 1298 } 1299 1300 /* 1301 * DMA map early, for performance (empties dcache ASAP) and 1302 * better fault reporting. 1303 */ 1304 if ((!master->cur_msg->is_dma_mapped) 1305 && as->use_pdc) { 1306 if (atmel_spi_dma_map_xfer(as, xfer) < 0) 1307 return -ENOMEM; 1308 } 1309 1310 atmel_spi_set_xfer_speed(as, spi, xfer); 1311 1312 as->done_status = 0; 1313 as->current_transfer = xfer; 1314 as->current_remaining_bytes = xfer->len; 1315 while (as->current_remaining_bytes) { 1316 reinit_completion(&as->xfer_completion); 1317 1318 if (as->use_pdc) { 1319 atmel_spi_lock(as); 1320 atmel_spi_pdc_next_xfer(master, xfer); 1321 atmel_spi_unlock(as); 1322 } else if (atmel_spi_use_dma(as, xfer)) { 1323 len = as->current_remaining_bytes; 1324 ret = atmel_spi_next_xfer_dma_submit(master, 1325 xfer, &len); 1326 if (ret) { 1327 dev_err(&spi->dev, 1328 "unable to use DMA, fallback to PIO\n"); 1329 as->done_status = ret; 1330 break; 1331 } else { 1332 as->current_remaining_bytes -= len; 1333 if (as->current_remaining_bytes < 0) 1334 as->current_remaining_bytes = 0; 1335 } 1336 } else { 1337 atmel_spi_lock(as); 1338 atmel_spi_next_xfer_pio(master, xfer); 1339 atmel_spi_unlock(as); 1340 } 1341 1342 dma_timeout = wait_for_completion_timeout(&as->xfer_completion, 1343 SPI_DMA_TIMEOUT); 1344 if (WARN_ON(dma_timeout == 0)) { 1345 dev_err(&spi->dev, "spi transfer timeout\n"); 1346 as->done_status = -EIO; 1347 } 1348 1349 if (as->done_status) 1350 break; 1351 } 1352 1353 if (as->done_status) { 1354 if (as->use_pdc) { 1355 dev_warn(master->dev.parent, 1356 "overrun (%u/%u remaining)\n", 1357 spi_readl(as, TCR), spi_readl(as, RCR)); 1358 1359 /* 1360 * Clean up DMA registers and make sure the data 1361 * registers are empty. 1362 */ 1363 spi_writel(as, RNCR, 0); 1364 spi_writel(as, TNCR, 0); 1365 spi_writel(as, RCR, 0); 1366 spi_writel(as, TCR, 0); 1367 for (timeout = 1000; timeout; timeout--) 1368 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) 1369 break; 1370 if (!timeout) 1371 dev_warn(master->dev.parent, 1372 "timeout waiting for TXEMPTY"); 1373 while (spi_readl(as, SR) & SPI_BIT(RDRF)) 1374 spi_readl(as, RDR); 1375 1376 /* Clear any overrun happening while cleaning up */ 1377 spi_readl(as, SR); 1378 1379 } else if (atmel_spi_use_dma(as, xfer)) { 1380 atmel_spi_stop_dma(master); 1381 } 1382 } 1383 1384 if (!master->cur_msg->is_dma_mapped 1385 && as->use_pdc) 1386 atmel_spi_dma_unmap_xfer(master, xfer); 1387 1388 if (as->use_pdc) 1389 atmel_spi_disable_pdc_transfer(as); 1390 1391 return as->done_status; 1392 } 1393 1394 static void atmel_spi_cleanup(struct spi_device *spi) 1395 { 1396 struct atmel_spi_device *asd = spi->controller_state; 1397 1398 if (!asd) 1399 return; 1400 1401 spi->controller_state = NULL; 1402 kfree(asd); 1403 } 1404 1405 static inline unsigned int atmel_get_version(struct atmel_spi *as) 1406 { 1407 return spi_readl(as, VERSION) & 0x00000fff; 1408 } 1409 1410 static void atmel_get_caps(struct atmel_spi *as) 1411 { 1412 unsigned int version; 1413 1414 version = atmel_get_version(as); 1415 1416 as->caps.is_spi2 = version > 0x121; 1417 as->caps.has_wdrbt = version >= 0x210; 1418 as->caps.has_dma_support = version >= 0x212; 1419 as->caps.has_pdc_support = version < 0x212; 1420 } 1421 1422 static void atmel_spi_init(struct atmel_spi *as) 1423 { 1424 spi_writel(as, CR, SPI_BIT(SWRST)); 1425 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1426 1427 /* It is recommended to enable FIFOs first thing after reset */ 1428 if (as->fifo_size) 1429 spi_writel(as, CR, SPI_BIT(FIFOEN)); 1430 1431 if (as->caps.has_wdrbt) { 1432 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) 1433 | SPI_BIT(MSTR)); 1434 } else { 1435 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); 1436 } 1437 1438 if (as->use_pdc) 1439 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 1440 spi_writel(as, CR, SPI_BIT(SPIEN)); 1441 } 1442 1443 static int atmel_spi_probe(struct platform_device *pdev) 1444 { 1445 struct resource *regs; 1446 int irq; 1447 struct clk *clk; 1448 int ret; 1449 struct spi_master *master; 1450 struct atmel_spi *as; 1451 1452 /* Select default pin state */ 1453 pinctrl_pm_select_default_state(&pdev->dev); 1454 1455 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1456 if (!regs) 1457 return -ENXIO; 1458 1459 irq = platform_get_irq(pdev, 0); 1460 if (irq < 0) 1461 return irq; 1462 1463 clk = devm_clk_get(&pdev->dev, "spi_clk"); 1464 if (IS_ERR(clk)) 1465 return PTR_ERR(clk); 1466 1467 /* setup spi core then atmel-specific driver state */ 1468 master = spi_alloc_master(&pdev->dev, sizeof(*as)); 1469 if (!master) 1470 return -ENOMEM; 1471 1472 /* the spi->mode bits understood by this driver: */ 1473 master->use_gpio_descriptors = true; 1474 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1475 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); 1476 master->dev.of_node = pdev->dev.of_node; 1477 master->bus_num = pdev->id; 1478 master->num_chipselect = 4; 1479 master->setup = atmel_spi_setup; 1480 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX | 1481 SPI_MASTER_GPIO_SS); 1482 master->transfer_one = atmel_spi_one_transfer; 1483 master->set_cs = atmel_spi_set_cs; 1484 master->cleanup = atmel_spi_cleanup; 1485 master->auto_runtime_pm = true; 1486 master->max_dma_len = SPI_MAX_DMA_XFER; 1487 master->can_dma = atmel_spi_can_dma; 1488 platform_set_drvdata(pdev, master); 1489 1490 as = spi_master_get_devdata(master); 1491 1492 spin_lock_init(&as->lock); 1493 1494 as->pdev = pdev; 1495 as->regs = devm_ioremap_resource(&pdev->dev, regs); 1496 if (IS_ERR(as->regs)) { 1497 ret = PTR_ERR(as->regs); 1498 goto out_unmap_regs; 1499 } 1500 as->phybase = regs->start; 1501 as->irq = irq; 1502 as->clk = clk; 1503 1504 init_completion(&as->xfer_completion); 1505 1506 atmel_get_caps(as); 1507 1508 as->use_dma = false; 1509 as->use_pdc = false; 1510 if (as->caps.has_dma_support) { 1511 ret = atmel_spi_configure_dma(master, as); 1512 if (ret == 0) { 1513 as->use_dma = true; 1514 } else if (ret == -EPROBE_DEFER) { 1515 goto out_unmap_regs; 1516 } 1517 } else if (as->caps.has_pdc_support) { 1518 as->use_pdc = true; 1519 } 1520 1521 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 1522 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev, 1523 SPI_MAX_DMA_XFER, 1524 &as->dma_addr_rx_bbuf, 1525 GFP_KERNEL | GFP_DMA); 1526 if (!as->addr_rx_bbuf) { 1527 as->use_dma = false; 1528 } else { 1529 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev, 1530 SPI_MAX_DMA_XFER, 1531 &as->dma_addr_tx_bbuf, 1532 GFP_KERNEL | GFP_DMA); 1533 if (!as->addr_tx_bbuf) { 1534 as->use_dma = false; 1535 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1536 as->addr_rx_bbuf, 1537 as->dma_addr_rx_bbuf); 1538 } 1539 } 1540 if (!as->use_dma) 1541 dev_info(master->dev.parent, 1542 " can not allocate dma coherent memory\n"); 1543 } 1544 1545 if (as->caps.has_dma_support && !as->use_dma) 1546 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); 1547 1548 if (as->use_pdc) { 1549 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt, 1550 0, dev_name(&pdev->dev), master); 1551 } else { 1552 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt, 1553 0, dev_name(&pdev->dev), master); 1554 } 1555 if (ret) 1556 goto out_unmap_regs; 1557 1558 /* Initialize the hardware */ 1559 ret = clk_prepare_enable(clk); 1560 if (ret) 1561 goto out_free_irq; 1562 1563 as->spi_clk = clk_get_rate(clk); 1564 1565 as->fifo_size = 0; 1566 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", 1567 &as->fifo_size)) { 1568 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size); 1569 } 1570 1571 atmel_spi_init(as); 1572 1573 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1574 pm_runtime_use_autosuspend(&pdev->dev); 1575 pm_runtime_set_active(&pdev->dev); 1576 pm_runtime_enable(&pdev->dev); 1577 1578 ret = devm_spi_register_master(&pdev->dev, master); 1579 if (ret) 1580 goto out_free_dma; 1581 1582 /* go! */ 1583 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n", 1584 atmel_get_version(as), (unsigned long)regs->start, 1585 irq); 1586 1587 return 0; 1588 1589 out_free_dma: 1590 pm_runtime_disable(&pdev->dev); 1591 pm_runtime_set_suspended(&pdev->dev); 1592 1593 if (as->use_dma) 1594 atmel_spi_release_dma(master); 1595 1596 spi_writel(as, CR, SPI_BIT(SWRST)); 1597 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1598 clk_disable_unprepare(clk); 1599 out_free_irq: 1600 out_unmap_regs: 1601 spi_master_put(master); 1602 return ret; 1603 } 1604 1605 static int atmel_spi_remove(struct platform_device *pdev) 1606 { 1607 struct spi_master *master = platform_get_drvdata(pdev); 1608 struct atmel_spi *as = spi_master_get_devdata(master); 1609 1610 pm_runtime_get_sync(&pdev->dev); 1611 1612 /* reset the hardware and block queue progress */ 1613 if (as->use_dma) { 1614 atmel_spi_stop_dma(master); 1615 atmel_spi_release_dma(master); 1616 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 1617 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1618 as->addr_tx_bbuf, 1619 as->dma_addr_tx_bbuf); 1620 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1621 as->addr_rx_bbuf, 1622 as->dma_addr_rx_bbuf); 1623 } 1624 } 1625 1626 spin_lock_irq(&as->lock); 1627 spi_writel(as, CR, SPI_BIT(SWRST)); 1628 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1629 spi_readl(as, SR); 1630 spin_unlock_irq(&as->lock); 1631 1632 clk_disable_unprepare(as->clk); 1633 1634 pm_runtime_put_noidle(&pdev->dev); 1635 pm_runtime_disable(&pdev->dev); 1636 1637 return 0; 1638 } 1639 1640 #ifdef CONFIG_PM 1641 static int atmel_spi_runtime_suspend(struct device *dev) 1642 { 1643 struct spi_master *master = dev_get_drvdata(dev); 1644 struct atmel_spi *as = spi_master_get_devdata(master); 1645 1646 clk_disable_unprepare(as->clk); 1647 pinctrl_pm_select_sleep_state(dev); 1648 1649 return 0; 1650 } 1651 1652 static int atmel_spi_runtime_resume(struct device *dev) 1653 { 1654 struct spi_master *master = dev_get_drvdata(dev); 1655 struct atmel_spi *as = spi_master_get_devdata(master); 1656 1657 pinctrl_pm_select_default_state(dev); 1658 1659 return clk_prepare_enable(as->clk); 1660 } 1661 1662 #ifdef CONFIG_PM_SLEEP 1663 static int atmel_spi_suspend(struct device *dev) 1664 { 1665 struct spi_master *master = dev_get_drvdata(dev); 1666 int ret; 1667 1668 /* Stop the queue running */ 1669 ret = spi_master_suspend(master); 1670 if (ret) 1671 return ret; 1672 1673 if (!pm_runtime_suspended(dev)) 1674 atmel_spi_runtime_suspend(dev); 1675 1676 return 0; 1677 } 1678 1679 static int atmel_spi_resume(struct device *dev) 1680 { 1681 struct spi_master *master = dev_get_drvdata(dev); 1682 struct atmel_spi *as = spi_master_get_devdata(master); 1683 int ret; 1684 1685 ret = clk_prepare_enable(as->clk); 1686 if (ret) 1687 return ret; 1688 1689 atmel_spi_init(as); 1690 1691 clk_disable_unprepare(as->clk); 1692 1693 if (!pm_runtime_suspended(dev)) { 1694 ret = atmel_spi_runtime_resume(dev); 1695 if (ret) 1696 return ret; 1697 } 1698 1699 /* Start the queue running */ 1700 return spi_master_resume(master); 1701 } 1702 #endif 1703 1704 static const struct dev_pm_ops atmel_spi_pm_ops = { 1705 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume) 1706 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend, 1707 atmel_spi_runtime_resume, NULL) 1708 }; 1709 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops) 1710 #else 1711 #define ATMEL_SPI_PM_OPS NULL 1712 #endif 1713 1714 static const struct of_device_id atmel_spi_dt_ids[] = { 1715 { .compatible = "atmel,at91rm9200-spi" }, 1716 { /* sentinel */ } 1717 }; 1718 1719 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); 1720 1721 static struct platform_driver atmel_spi_driver = { 1722 .driver = { 1723 .name = "atmel_spi", 1724 .pm = ATMEL_SPI_PM_OPS, 1725 .of_match_table = atmel_spi_dt_ids, 1726 }, 1727 .probe = atmel_spi_probe, 1728 .remove = atmel_spi_remove, 1729 }; 1730 module_platform_driver(atmel_spi_driver); 1731 1732 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); 1733 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1734 MODULE_LICENSE("GPL"); 1735 MODULE_ALIAS("platform:atmel_spi"); 1736