1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for Atmel AT32 and AT91 SPI Controllers 4 * 5 * Copyright (C) 2006 Atmel Corporation 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/clk.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmaengine.h> 15 #include <linux/err.h> 16 #include <linux/interrupt.h> 17 #include <linux/spi/spi.h> 18 #include <linux/slab.h> 19 #include <linux/of.h> 20 21 #include <linux/io.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm_runtime.h> 25 #include <trace/events/spi.h> 26 27 /* SPI register offsets */ 28 #define SPI_CR 0x0000 29 #define SPI_MR 0x0004 30 #define SPI_RDR 0x0008 31 #define SPI_TDR 0x000c 32 #define SPI_SR 0x0010 33 #define SPI_IER 0x0014 34 #define SPI_IDR 0x0018 35 #define SPI_IMR 0x001c 36 #define SPI_CSR0 0x0030 37 #define SPI_CSR1 0x0034 38 #define SPI_CSR2 0x0038 39 #define SPI_CSR3 0x003c 40 #define SPI_FMR 0x0040 41 #define SPI_FLR 0x0044 42 #define SPI_VERSION 0x00fc 43 #define SPI_RPR 0x0100 44 #define SPI_RCR 0x0104 45 #define SPI_TPR 0x0108 46 #define SPI_TCR 0x010c 47 #define SPI_RNPR 0x0110 48 #define SPI_RNCR 0x0114 49 #define SPI_TNPR 0x0118 50 #define SPI_TNCR 0x011c 51 #define SPI_PTCR 0x0120 52 #define SPI_PTSR 0x0124 53 54 /* Bitfields in CR */ 55 #define SPI_SPIEN_OFFSET 0 56 #define SPI_SPIEN_SIZE 1 57 #define SPI_SPIDIS_OFFSET 1 58 #define SPI_SPIDIS_SIZE 1 59 #define SPI_SWRST_OFFSET 7 60 #define SPI_SWRST_SIZE 1 61 #define SPI_LASTXFER_OFFSET 24 62 #define SPI_LASTXFER_SIZE 1 63 #define SPI_TXFCLR_OFFSET 16 64 #define SPI_TXFCLR_SIZE 1 65 #define SPI_RXFCLR_OFFSET 17 66 #define SPI_RXFCLR_SIZE 1 67 #define SPI_FIFOEN_OFFSET 30 68 #define SPI_FIFOEN_SIZE 1 69 #define SPI_FIFODIS_OFFSET 31 70 #define SPI_FIFODIS_SIZE 1 71 72 /* Bitfields in MR */ 73 #define SPI_MSTR_OFFSET 0 74 #define SPI_MSTR_SIZE 1 75 #define SPI_PS_OFFSET 1 76 #define SPI_PS_SIZE 1 77 #define SPI_PCSDEC_OFFSET 2 78 #define SPI_PCSDEC_SIZE 1 79 #define SPI_FDIV_OFFSET 3 80 #define SPI_FDIV_SIZE 1 81 #define SPI_MODFDIS_OFFSET 4 82 #define SPI_MODFDIS_SIZE 1 83 #define SPI_WDRBT_OFFSET 5 84 #define SPI_WDRBT_SIZE 1 85 #define SPI_LLB_OFFSET 7 86 #define SPI_LLB_SIZE 1 87 #define SPI_PCS_OFFSET 16 88 #define SPI_PCS_SIZE 4 89 #define SPI_DLYBCS_OFFSET 24 90 #define SPI_DLYBCS_SIZE 8 91 92 /* Bitfields in RDR */ 93 #define SPI_RD_OFFSET 0 94 #define SPI_RD_SIZE 16 95 96 /* Bitfields in TDR */ 97 #define SPI_TD_OFFSET 0 98 #define SPI_TD_SIZE 16 99 100 /* Bitfields in SR */ 101 #define SPI_RDRF_OFFSET 0 102 #define SPI_RDRF_SIZE 1 103 #define SPI_TDRE_OFFSET 1 104 #define SPI_TDRE_SIZE 1 105 #define SPI_MODF_OFFSET 2 106 #define SPI_MODF_SIZE 1 107 #define SPI_OVRES_OFFSET 3 108 #define SPI_OVRES_SIZE 1 109 #define SPI_ENDRX_OFFSET 4 110 #define SPI_ENDRX_SIZE 1 111 #define SPI_ENDTX_OFFSET 5 112 #define SPI_ENDTX_SIZE 1 113 #define SPI_RXBUFF_OFFSET 6 114 #define SPI_RXBUFF_SIZE 1 115 #define SPI_TXBUFE_OFFSET 7 116 #define SPI_TXBUFE_SIZE 1 117 #define SPI_NSSR_OFFSET 8 118 #define SPI_NSSR_SIZE 1 119 #define SPI_TXEMPTY_OFFSET 9 120 #define SPI_TXEMPTY_SIZE 1 121 #define SPI_SPIENS_OFFSET 16 122 #define SPI_SPIENS_SIZE 1 123 #define SPI_TXFEF_OFFSET 24 124 #define SPI_TXFEF_SIZE 1 125 #define SPI_TXFFF_OFFSET 25 126 #define SPI_TXFFF_SIZE 1 127 #define SPI_TXFTHF_OFFSET 26 128 #define SPI_TXFTHF_SIZE 1 129 #define SPI_RXFEF_OFFSET 27 130 #define SPI_RXFEF_SIZE 1 131 #define SPI_RXFFF_OFFSET 28 132 #define SPI_RXFFF_SIZE 1 133 #define SPI_RXFTHF_OFFSET 29 134 #define SPI_RXFTHF_SIZE 1 135 #define SPI_TXFPTEF_OFFSET 30 136 #define SPI_TXFPTEF_SIZE 1 137 #define SPI_RXFPTEF_OFFSET 31 138 #define SPI_RXFPTEF_SIZE 1 139 140 /* Bitfields in CSR0 */ 141 #define SPI_CPOL_OFFSET 0 142 #define SPI_CPOL_SIZE 1 143 #define SPI_NCPHA_OFFSET 1 144 #define SPI_NCPHA_SIZE 1 145 #define SPI_CSAAT_OFFSET 3 146 #define SPI_CSAAT_SIZE 1 147 #define SPI_BITS_OFFSET 4 148 #define SPI_BITS_SIZE 4 149 #define SPI_SCBR_OFFSET 8 150 #define SPI_SCBR_SIZE 8 151 #define SPI_DLYBS_OFFSET 16 152 #define SPI_DLYBS_SIZE 8 153 #define SPI_DLYBCT_OFFSET 24 154 #define SPI_DLYBCT_SIZE 8 155 156 /* Bitfields in RCR */ 157 #define SPI_RXCTR_OFFSET 0 158 #define SPI_RXCTR_SIZE 16 159 160 /* Bitfields in TCR */ 161 #define SPI_TXCTR_OFFSET 0 162 #define SPI_TXCTR_SIZE 16 163 164 /* Bitfields in RNCR */ 165 #define SPI_RXNCR_OFFSET 0 166 #define SPI_RXNCR_SIZE 16 167 168 /* Bitfields in TNCR */ 169 #define SPI_TXNCR_OFFSET 0 170 #define SPI_TXNCR_SIZE 16 171 172 /* Bitfields in PTCR */ 173 #define SPI_RXTEN_OFFSET 0 174 #define SPI_RXTEN_SIZE 1 175 #define SPI_RXTDIS_OFFSET 1 176 #define SPI_RXTDIS_SIZE 1 177 #define SPI_TXTEN_OFFSET 8 178 #define SPI_TXTEN_SIZE 1 179 #define SPI_TXTDIS_OFFSET 9 180 #define SPI_TXTDIS_SIZE 1 181 182 /* Bitfields in FMR */ 183 #define SPI_TXRDYM_OFFSET 0 184 #define SPI_TXRDYM_SIZE 2 185 #define SPI_RXRDYM_OFFSET 4 186 #define SPI_RXRDYM_SIZE 2 187 #define SPI_TXFTHRES_OFFSET 16 188 #define SPI_TXFTHRES_SIZE 6 189 #define SPI_RXFTHRES_OFFSET 24 190 #define SPI_RXFTHRES_SIZE 6 191 192 /* Bitfields in FLR */ 193 #define SPI_TXFL_OFFSET 0 194 #define SPI_TXFL_SIZE 6 195 #define SPI_RXFL_OFFSET 16 196 #define SPI_RXFL_SIZE 6 197 198 /* Constants for BITS */ 199 #define SPI_BITS_8_BPT 0 200 #define SPI_BITS_9_BPT 1 201 #define SPI_BITS_10_BPT 2 202 #define SPI_BITS_11_BPT 3 203 #define SPI_BITS_12_BPT 4 204 #define SPI_BITS_13_BPT 5 205 #define SPI_BITS_14_BPT 6 206 #define SPI_BITS_15_BPT 7 207 #define SPI_BITS_16_BPT 8 208 #define SPI_ONE_DATA 0 209 #define SPI_TWO_DATA 1 210 #define SPI_FOUR_DATA 2 211 212 /* Bit manipulation macros */ 213 #define SPI_BIT(name) \ 214 (1 << SPI_##name##_OFFSET) 215 #define SPI_BF(name, value) \ 216 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) 217 #define SPI_BFEXT(name, value) \ 218 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) 219 #define SPI_BFINS(name, value, old) \ 220 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ 221 | SPI_BF(name, value)) 222 223 /* Register access macros */ 224 #define spi_readl(port, reg) \ 225 readl_relaxed((port)->regs + SPI_##reg) 226 #define spi_writel(port, reg, value) \ 227 writel_relaxed((value), (port)->regs + SPI_##reg) 228 #define spi_writew(port, reg, value) \ 229 writew_relaxed((value), (port)->regs + SPI_##reg) 230 231 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and 232 * cache operations; better heuristics consider wordsize and bitrate. 233 */ 234 #define DMA_MIN_BYTES 16 235 236 #define SPI_DMA_MIN_TIMEOUT (msecs_to_jiffies(1000)) 237 #define SPI_DMA_TIMEOUT_PER_10K (msecs_to_jiffies(4)) 238 239 #define AUTOSUSPEND_TIMEOUT 2000 240 241 struct atmel_spi_caps { 242 bool is_spi2; 243 bool has_wdrbt; 244 bool has_dma_support; 245 bool has_pdc_support; 246 }; 247 248 /* 249 * The core SPI transfer engine just talks to a register bank to set up 250 * DMA transfers; transfer queue progress is driven by IRQs. The clock 251 * framework provides the base clock, subdivided for each spi_device. 252 */ 253 struct atmel_spi { 254 spinlock_t lock; 255 unsigned long flags; 256 257 phys_addr_t phybase; 258 void __iomem *regs; 259 int irq; 260 struct clk *clk; 261 struct platform_device *pdev; 262 unsigned long spi_clk; 263 264 struct spi_transfer *current_transfer; 265 int current_remaining_bytes; 266 int done_status; 267 dma_addr_t dma_addr_rx_bbuf; 268 dma_addr_t dma_addr_tx_bbuf; 269 void *addr_rx_bbuf; 270 void *addr_tx_bbuf; 271 272 struct completion xfer_completion; 273 274 struct atmel_spi_caps caps; 275 276 bool use_dma; 277 bool use_pdc; 278 279 bool keep_cs; 280 281 u32 fifo_size; 282 u8 native_cs_free; 283 u8 native_cs_for_gpio; 284 }; 285 286 /* Controller-specific per-slave state */ 287 struct atmel_spi_device { 288 u32 csr; 289 }; 290 291 #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */ 292 #define INVALID_DMA_ADDRESS 0xffffffff 293 294 /* 295 * Version 2 of the SPI controller has 296 * - CR.LASTXFER 297 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) 298 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) 299 * - SPI_CSRx.CSAAT 300 * - SPI_CSRx.SBCR allows faster clocking 301 */ 302 static bool atmel_spi_is_v2(struct atmel_spi *as) 303 { 304 return as->caps.is_spi2; 305 } 306 307 /* 308 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby 309 * they assume that spi slave device state will not change on deselect, so 310 * that automagic deselection is OK. ("NPCSx rises if no data is to be 311 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer 312 * controllers have CSAAT and friends. 313 * 314 * Even controller newer than ar91rm9200, using GPIOs can make sens as 315 * it lets us support active-high chipselects despite the controller's 316 * belief that only active-low devices/systems exists. 317 * 318 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work 319 * right when driven with GPIO. ("Mode Fault does not allow more than one 320 * Master on Chip Select 0.") No workaround exists for that ... so for 321 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, 322 * and (c) will trigger that first erratum in some cases. 323 */ 324 325 static void cs_activate(struct atmel_spi *as, struct spi_device *spi) 326 { 327 struct atmel_spi_device *asd = spi->controller_state; 328 int chip_select; 329 u32 mr; 330 331 if (spi_get_csgpiod(spi, 0)) 332 chip_select = as->native_cs_for_gpio; 333 else 334 chip_select = spi_get_chipselect(spi, 0); 335 336 if (atmel_spi_is_v2(as)) { 337 spi_writel(as, CSR0 + 4 * chip_select, asd->csr); 338 /* For the low SPI version, there is a issue that PDC transfer 339 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS 340 */ 341 spi_writel(as, CSR0, asd->csr); 342 if (as->caps.has_wdrbt) { 343 spi_writel(as, MR, 344 SPI_BF(PCS, ~(0x01 << chip_select)) 345 | SPI_BIT(WDRBT) 346 | SPI_BIT(MODFDIS) 347 | SPI_BIT(MSTR)); 348 } else { 349 spi_writel(as, MR, 350 SPI_BF(PCS, ~(0x01 << chip_select)) 351 | SPI_BIT(MODFDIS) 352 | SPI_BIT(MSTR)); 353 } 354 355 mr = spi_readl(as, MR); 356 } else { 357 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; 358 int i; 359 u32 csr; 360 361 /* Make sure clock polarity is correct */ 362 for (i = 0; i < spi->controller->num_chipselect; i++) { 363 csr = spi_readl(as, CSR0 + 4 * i); 364 if ((csr ^ cpol) & SPI_BIT(CPOL)) 365 spi_writel(as, CSR0 + 4 * i, 366 csr ^ SPI_BIT(CPOL)); 367 } 368 369 mr = spi_readl(as, MR); 370 mr = SPI_BFINS(PCS, ~(1 << chip_select), mr); 371 spi_writel(as, MR, mr); 372 } 373 374 dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr); 375 } 376 377 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) 378 { 379 int chip_select; 380 u32 mr; 381 382 if (spi_get_csgpiod(spi, 0)) 383 chip_select = as->native_cs_for_gpio; 384 else 385 chip_select = spi_get_chipselect(spi, 0); 386 387 /* only deactivate *this* device; sometimes transfers to 388 * another device may be active when this routine is called. 389 */ 390 mr = spi_readl(as, MR); 391 if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) { 392 mr = SPI_BFINS(PCS, 0xf, mr); 393 spi_writel(as, MR, mr); 394 } 395 396 dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr); 397 398 if (!spi_get_csgpiod(spi, 0)) 399 spi_writel(as, CR, SPI_BIT(LASTXFER)); 400 } 401 402 static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock) 403 { 404 spin_lock_irqsave(&as->lock, as->flags); 405 } 406 407 static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock) 408 { 409 spin_unlock_irqrestore(&as->lock, as->flags); 410 } 411 412 static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer) 413 { 414 return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf); 415 } 416 417 static inline bool atmel_spi_use_dma(struct atmel_spi *as, 418 struct spi_transfer *xfer) 419 { 420 return as->use_dma && xfer->len >= DMA_MIN_BYTES; 421 } 422 423 static bool atmel_spi_can_dma(struct spi_controller *host, 424 struct spi_device *spi, 425 struct spi_transfer *xfer) 426 { 427 struct atmel_spi *as = spi_controller_get_devdata(host); 428 429 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) 430 return atmel_spi_use_dma(as, xfer) && 431 !atmel_spi_is_vmalloc_xfer(xfer); 432 else 433 return atmel_spi_use_dma(as, xfer); 434 435 } 436 437 static int atmel_spi_dma_slave_config(struct atmel_spi *as, u8 bits_per_word) 438 { 439 struct spi_controller *host = platform_get_drvdata(as->pdev); 440 struct dma_slave_config slave_config; 441 int err = 0; 442 443 if (bits_per_word > 8) { 444 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 445 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 446 } else { 447 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 448 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 449 } 450 451 slave_config.dst_addr = (dma_addr_t)as->phybase + SPI_TDR; 452 slave_config.src_addr = (dma_addr_t)as->phybase + SPI_RDR; 453 slave_config.src_maxburst = 1; 454 slave_config.dst_maxburst = 1; 455 slave_config.device_fc = false; 456 457 /* 458 * This driver uses fixed peripheral select mode (PS bit set to '0' in 459 * the Mode Register). 460 * So according to the datasheet, when FIFOs are available (and 461 * enabled), the Transmit FIFO operates in Multiple Data Mode. 462 * In this mode, up to 2 data, not 4, can be written into the Transmit 463 * Data Register in a single access. 464 * However, the first data has to be written into the lowest 16 bits and 465 * the second data into the highest 16 bits of the Transmit 466 * Data Register. For 8bit data (the most frequent case), it would 467 * require to rework tx_buf so each data would actually fit 16 bits. 468 * So we'd rather write only one data at the time. Hence the transmit 469 * path works the same whether FIFOs are available (and enabled) or not. 470 */ 471 if (dmaengine_slave_config(host->dma_tx, &slave_config)) { 472 dev_err(&as->pdev->dev, 473 "failed to configure tx dma channel\n"); 474 err = -EINVAL; 475 } 476 477 /* 478 * This driver configures the spi controller for host mode (MSTR bit 479 * set to '1' in the Mode Register). 480 * So according to the datasheet, when FIFOs are available (and 481 * enabled), the Receive FIFO operates in Single Data Mode. 482 * So the receive path works the same whether FIFOs are available (and 483 * enabled) or not. 484 */ 485 if (dmaengine_slave_config(host->dma_rx, &slave_config)) { 486 dev_err(&as->pdev->dev, 487 "failed to configure rx dma channel\n"); 488 err = -EINVAL; 489 } 490 491 return err; 492 } 493 494 static int atmel_spi_configure_dma(struct spi_controller *host, 495 struct atmel_spi *as) 496 { 497 struct device *dev = &as->pdev->dev; 498 int err; 499 500 host->dma_tx = dma_request_chan(dev, "tx"); 501 if (IS_ERR(host->dma_tx)) { 502 err = PTR_ERR(host->dma_tx); 503 dev_dbg(dev, "No TX DMA channel, DMA is disabled\n"); 504 goto error_clear; 505 } 506 507 host->dma_rx = dma_request_chan(dev, "rx"); 508 if (IS_ERR(host->dma_rx)) { 509 err = PTR_ERR(host->dma_rx); 510 /* 511 * No reason to check EPROBE_DEFER here since we have already 512 * requested tx channel. 513 */ 514 dev_dbg(dev, "No RX DMA channel, DMA is disabled\n"); 515 goto error; 516 } 517 518 err = atmel_spi_dma_slave_config(as, 8); 519 if (err) 520 goto error; 521 522 dev_info(&as->pdev->dev, 523 "Using %s (tx) and %s (rx) for DMA transfers\n", 524 dma_chan_name(host->dma_tx), 525 dma_chan_name(host->dma_rx)); 526 527 return 0; 528 error: 529 if (!IS_ERR(host->dma_rx)) 530 dma_release_channel(host->dma_rx); 531 if (!IS_ERR(host->dma_tx)) 532 dma_release_channel(host->dma_tx); 533 error_clear: 534 host->dma_tx = host->dma_rx = NULL; 535 return err; 536 } 537 538 static void atmel_spi_stop_dma(struct spi_controller *host) 539 { 540 if (host->dma_rx) 541 dmaengine_terminate_all(host->dma_rx); 542 if (host->dma_tx) 543 dmaengine_terminate_all(host->dma_tx); 544 } 545 546 static void atmel_spi_release_dma(struct spi_controller *host) 547 { 548 if (host->dma_rx) { 549 dma_release_channel(host->dma_rx); 550 host->dma_rx = NULL; 551 } 552 if (host->dma_tx) { 553 dma_release_channel(host->dma_tx); 554 host->dma_tx = NULL; 555 } 556 } 557 558 /* This function is called by the DMA driver from tasklet context */ 559 static void dma_callback(void *data) 560 { 561 struct spi_controller *host = data; 562 struct atmel_spi *as = spi_controller_get_devdata(host); 563 564 if (is_vmalloc_addr(as->current_transfer->rx_buf) && 565 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 566 memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf, 567 as->current_transfer->len); 568 } 569 complete(&as->xfer_completion); 570 } 571 572 /* 573 * Next transfer using PIO without FIFO. 574 */ 575 static void atmel_spi_next_xfer_single(struct spi_controller *host, 576 struct spi_transfer *xfer) 577 { 578 struct atmel_spi *as = spi_controller_get_devdata(host); 579 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 580 581 dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_pio\n"); 582 583 /* Make sure data is not remaining in RDR */ 584 spi_readl(as, RDR); 585 while (spi_readl(as, SR) & SPI_BIT(RDRF)) { 586 spi_readl(as, RDR); 587 cpu_relax(); 588 } 589 590 if (xfer->bits_per_word > 8) 591 spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); 592 else 593 spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos)); 594 595 dev_dbg(host->dev.parent, 596 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", 597 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 598 xfer->bits_per_word); 599 600 /* Enable relevant interrupts */ 601 spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES)); 602 } 603 604 /* 605 * Next transfer using PIO with FIFO. 606 */ 607 static void atmel_spi_next_xfer_fifo(struct spi_controller *host, 608 struct spi_transfer *xfer) 609 { 610 struct atmel_spi *as = spi_controller_get_devdata(host); 611 u32 current_remaining_data, num_data; 612 u32 offset = xfer->len - as->current_remaining_bytes; 613 const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset); 614 const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset); 615 u16 td0, td1; 616 u32 fifomr; 617 618 dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_fifo\n"); 619 620 /* Compute the number of data to transfer in the current iteration */ 621 current_remaining_data = ((xfer->bits_per_word > 8) ? 622 ((u32)as->current_remaining_bytes >> 1) : 623 (u32)as->current_remaining_bytes); 624 num_data = min(current_remaining_data, as->fifo_size); 625 626 /* Flush RX and TX FIFOs */ 627 spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR)); 628 while (spi_readl(as, FLR)) 629 cpu_relax(); 630 631 /* Set RX FIFO Threshold to the number of data to transfer */ 632 fifomr = spi_readl(as, FMR); 633 spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr)); 634 635 /* Clear FIFO flags in the Status Register, especially RXFTHF */ 636 (void)spi_readl(as, SR); 637 638 /* Fill TX FIFO */ 639 while (num_data >= 2) { 640 if (xfer->bits_per_word > 8) { 641 td0 = *words++; 642 td1 = *words++; 643 } else { 644 td0 = *bytes++; 645 td1 = *bytes++; 646 } 647 648 spi_writel(as, TDR, (td1 << 16) | td0); 649 num_data -= 2; 650 } 651 652 if (num_data) { 653 if (xfer->bits_per_word > 8) 654 td0 = *words++; 655 else 656 td0 = *bytes++; 657 658 spi_writew(as, TDR, td0); 659 num_data--; 660 } 661 662 dev_dbg(host->dev.parent, 663 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n", 664 xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 665 xfer->bits_per_word); 666 667 /* 668 * Enable RX FIFO Threshold Flag interrupt to be notified about 669 * transfer completion. 670 */ 671 spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES)); 672 } 673 674 /* 675 * Next transfer using PIO. 676 */ 677 static void atmel_spi_next_xfer_pio(struct spi_controller *host, 678 struct spi_transfer *xfer) 679 { 680 struct atmel_spi *as = spi_controller_get_devdata(host); 681 682 if (as->fifo_size) 683 atmel_spi_next_xfer_fifo(host, xfer); 684 else 685 atmel_spi_next_xfer_single(host, xfer); 686 } 687 688 /* 689 * Submit next transfer for DMA. 690 */ 691 static int atmel_spi_next_xfer_dma_submit(struct spi_controller *host, 692 struct spi_transfer *xfer, 693 u32 *plen) 694 { 695 struct atmel_spi *as = spi_controller_get_devdata(host); 696 struct dma_chan *rxchan = host->dma_rx; 697 struct dma_chan *txchan = host->dma_tx; 698 struct dma_async_tx_descriptor *rxdesc; 699 struct dma_async_tx_descriptor *txdesc; 700 dma_cookie_t cookie; 701 702 dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); 703 704 /* Check that the channels are available */ 705 if (!rxchan || !txchan) 706 return -ENODEV; 707 708 709 *plen = xfer->len; 710 711 if (atmel_spi_dma_slave_config(as, xfer->bits_per_word)) 712 goto err_exit; 713 714 /* Send both scatterlists */ 715 if (atmel_spi_is_vmalloc_xfer(xfer) && 716 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 717 rxdesc = dmaengine_prep_slave_single(rxchan, 718 as->dma_addr_rx_bbuf, 719 xfer->len, 720 DMA_DEV_TO_MEM, 721 DMA_PREP_INTERRUPT | 722 DMA_CTRL_ACK); 723 } else { 724 rxdesc = dmaengine_prep_slave_sg(rxchan, 725 xfer->rx_sg.sgl, 726 xfer->rx_sg.nents, 727 DMA_DEV_TO_MEM, 728 DMA_PREP_INTERRUPT | 729 DMA_CTRL_ACK); 730 } 731 if (!rxdesc) 732 goto err_dma; 733 734 if (atmel_spi_is_vmalloc_xfer(xfer) && 735 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 736 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len); 737 txdesc = dmaengine_prep_slave_single(txchan, 738 as->dma_addr_tx_bbuf, 739 xfer->len, DMA_MEM_TO_DEV, 740 DMA_PREP_INTERRUPT | 741 DMA_CTRL_ACK); 742 } else { 743 txdesc = dmaengine_prep_slave_sg(txchan, 744 xfer->tx_sg.sgl, 745 xfer->tx_sg.nents, 746 DMA_MEM_TO_DEV, 747 DMA_PREP_INTERRUPT | 748 DMA_CTRL_ACK); 749 } 750 if (!txdesc) 751 goto err_dma; 752 753 dev_dbg(host->dev.parent, 754 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 755 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma, 756 xfer->rx_buf, (unsigned long long)xfer->rx_dma); 757 758 /* Enable relevant interrupts */ 759 spi_writel(as, IER, SPI_BIT(OVRES)); 760 761 /* Put the callback on the RX transfer only, that should finish last */ 762 rxdesc->callback = dma_callback; 763 rxdesc->callback_param = host; 764 765 /* Submit and fire RX and TX with TX last so we're ready to read! */ 766 cookie = rxdesc->tx_submit(rxdesc); 767 if (dma_submit_error(cookie)) 768 goto err_dma; 769 cookie = txdesc->tx_submit(txdesc); 770 if (dma_submit_error(cookie)) 771 goto err_dma; 772 rxchan->device->device_issue_pending(rxchan); 773 txchan->device->device_issue_pending(txchan); 774 775 return 0; 776 777 err_dma: 778 spi_writel(as, IDR, SPI_BIT(OVRES)); 779 atmel_spi_stop_dma(host); 780 err_exit: 781 return -ENOMEM; 782 } 783 784 static void atmel_spi_next_xfer_data(struct spi_controller *host, 785 struct spi_transfer *xfer, 786 dma_addr_t *tx_dma, 787 dma_addr_t *rx_dma, 788 u32 *plen) 789 { 790 *rx_dma = xfer->rx_dma + xfer->len - *plen; 791 *tx_dma = xfer->tx_dma + xfer->len - *plen; 792 if (*plen > host->max_dma_len) 793 *plen = host->max_dma_len; 794 } 795 796 static int atmel_spi_set_xfer_speed(struct atmel_spi *as, 797 struct spi_device *spi, 798 struct spi_transfer *xfer) 799 { 800 u32 scbr, csr; 801 unsigned long bus_hz; 802 int chip_select; 803 804 if (spi_get_csgpiod(spi, 0)) 805 chip_select = as->native_cs_for_gpio; 806 else 807 chip_select = spi_get_chipselect(spi, 0); 808 809 /* v1 chips start out at half the peripheral bus speed. */ 810 bus_hz = as->spi_clk; 811 if (!atmel_spi_is_v2(as)) 812 bus_hz /= 2; 813 814 /* 815 * Calculate the lowest divider that satisfies the 816 * constraint, assuming div32/fdiv/mbz == 0. 817 */ 818 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz); 819 820 /* 821 * If the resulting divider doesn't fit into the 822 * register bitfield, we can't satisfy the constraint. 823 */ 824 if (scbr >= (1 << SPI_SCBR_SIZE)) { 825 dev_err(&spi->dev, 826 "setup: %d Hz too slow, scbr %u; min %ld Hz\n", 827 xfer->speed_hz, scbr, bus_hz/255); 828 return -EINVAL; 829 } 830 if (scbr == 0) { 831 dev_err(&spi->dev, 832 "setup: %d Hz too high, scbr %u; max %ld Hz\n", 833 xfer->speed_hz, scbr, bus_hz); 834 return -EINVAL; 835 } 836 csr = spi_readl(as, CSR0 + 4 * chip_select); 837 csr = SPI_BFINS(SCBR, scbr, csr); 838 spi_writel(as, CSR0 + 4 * chip_select, csr); 839 xfer->effective_speed_hz = bus_hz / scbr; 840 841 return 0; 842 } 843 844 /* 845 * Submit next transfer for PDC. 846 * lock is held, spi irq is blocked 847 */ 848 static void atmel_spi_pdc_next_xfer(struct spi_controller *host, 849 struct spi_transfer *xfer) 850 { 851 struct atmel_spi *as = spi_controller_get_devdata(host); 852 u32 len; 853 dma_addr_t tx_dma, rx_dma; 854 855 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 856 857 len = as->current_remaining_bytes; 858 atmel_spi_next_xfer_data(host, xfer, &tx_dma, &rx_dma, &len); 859 as->current_remaining_bytes -= len; 860 861 spi_writel(as, RPR, rx_dma); 862 spi_writel(as, TPR, tx_dma); 863 864 if (xfer->bits_per_word > 8) 865 len >>= 1; 866 spi_writel(as, RCR, len); 867 spi_writel(as, TCR, len); 868 869 dev_dbg(&host->dev, 870 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 871 xfer, xfer->len, xfer->tx_buf, 872 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 873 (unsigned long long)xfer->rx_dma); 874 875 if (as->current_remaining_bytes) { 876 len = as->current_remaining_bytes; 877 atmel_spi_next_xfer_data(host, xfer, &tx_dma, &rx_dma, &len); 878 as->current_remaining_bytes -= len; 879 880 spi_writel(as, RNPR, rx_dma); 881 spi_writel(as, TNPR, tx_dma); 882 883 if (xfer->bits_per_word > 8) 884 len >>= 1; 885 spi_writel(as, RNCR, len); 886 spi_writel(as, TNCR, len); 887 888 dev_dbg(&host->dev, 889 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 890 xfer, xfer->len, xfer->tx_buf, 891 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 892 (unsigned long long)xfer->rx_dma); 893 } 894 895 /* REVISIT: We're waiting for RXBUFF before we start the next 896 * transfer because we need to handle some difficult timing 897 * issues otherwise. If we wait for TXBUFE in one transfer and 898 * then starts waiting for RXBUFF in the next, it's difficult 899 * to tell the difference between the RXBUFF interrupt we're 900 * actually waiting for and the RXBUFF interrupt of the 901 * previous transfer. 902 * 903 * It should be doable, though. Just not now... 904 */ 905 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES)); 906 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); 907 } 908 909 /* 910 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: 911 * - The buffer is either valid for CPU access, else NULL 912 * - If the buffer is valid, so is its DMA address 913 * 914 * This driver manages the dma address unless message->is_dma_mapped. 915 */ 916 static int 917 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) 918 { 919 struct device *dev = &as->pdev->dev; 920 921 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; 922 if (xfer->tx_buf) { 923 /* tx_buf is a const void* where we need a void * for the dma 924 * mapping */ 925 void *nonconst_tx = (void *)xfer->tx_buf; 926 927 xfer->tx_dma = dma_map_single(dev, 928 nonconst_tx, xfer->len, 929 DMA_TO_DEVICE); 930 if (dma_mapping_error(dev, xfer->tx_dma)) 931 return -ENOMEM; 932 } 933 if (xfer->rx_buf) { 934 xfer->rx_dma = dma_map_single(dev, 935 xfer->rx_buf, xfer->len, 936 DMA_FROM_DEVICE); 937 if (dma_mapping_error(dev, xfer->rx_dma)) { 938 if (xfer->tx_buf) 939 dma_unmap_single(dev, 940 xfer->tx_dma, xfer->len, 941 DMA_TO_DEVICE); 942 return -ENOMEM; 943 } 944 } 945 return 0; 946 } 947 948 static void atmel_spi_dma_unmap_xfer(struct spi_controller *host, 949 struct spi_transfer *xfer) 950 { 951 if (xfer->tx_dma != INVALID_DMA_ADDRESS) 952 dma_unmap_single(host->dev.parent, xfer->tx_dma, 953 xfer->len, DMA_TO_DEVICE); 954 if (xfer->rx_dma != INVALID_DMA_ADDRESS) 955 dma_unmap_single(host->dev.parent, xfer->rx_dma, 956 xfer->len, DMA_FROM_DEVICE); 957 } 958 959 static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as) 960 { 961 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 962 } 963 964 static void 965 atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer) 966 { 967 u8 *rxp; 968 u16 *rxp16; 969 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 970 971 if (xfer->bits_per_word > 8) { 972 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); 973 *rxp16 = spi_readl(as, RDR); 974 } else { 975 rxp = ((u8 *)xfer->rx_buf) + xfer_pos; 976 *rxp = spi_readl(as, RDR); 977 } 978 if (xfer->bits_per_word > 8) { 979 if (as->current_remaining_bytes > 2) 980 as->current_remaining_bytes -= 2; 981 else 982 as->current_remaining_bytes = 0; 983 } else { 984 as->current_remaining_bytes--; 985 } 986 } 987 988 static void 989 atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer) 990 { 991 u32 fifolr = spi_readl(as, FLR); 992 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr); 993 u32 offset = xfer->len - as->current_remaining_bytes; 994 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset); 995 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset); 996 u16 rd; /* RD field is the lowest 16 bits of RDR */ 997 998 /* Update the number of remaining bytes to transfer */ 999 num_bytes = ((xfer->bits_per_word > 8) ? 1000 (num_data << 1) : 1001 num_data); 1002 1003 if (as->current_remaining_bytes > num_bytes) 1004 as->current_remaining_bytes -= num_bytes; 1005 else 1006 as->current_remaining_bytes = 0; 1007 1008 /* Handle odd number of bytes when data are more than 8bit width */ 1009 if (xfer->bits_per_word > 8) 1010 as->current_remaining_bytes &= ~0x1; 1011 1012 /* Read data */ 1013 while (num_data) { 1014 rd = spi_readl(as, RDR); 1015 if (xfer->bits_per_word > 8) 1016 *words++ = rd; 1017 else 1018 *bytes++ = rd; 1019 num_data--; 1020 } 1021 } 1022 1023 /* Called from IRQ 1024 * 1025 * Must update "current_remaining_bytes" to keep track of data 1026 * to transfer. 1027 */ 1028 static void 1029 atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) 1030 { 1031 if (as->fifo_size) 1032 atmel_spi_pump_fifo_data(as, xfer); 1033 else 1034 atmel_spi_pump_single_data(as, xfer); 1035 } 1036 1037 /* Interrupt 1038 * 1039 */ 1040 static irqreturn_t 1041 atmel_spi_pio_interrupt(int irq, void *dev_id) 1042 { 1043 struct spi_controller *host = dev_id; 1044 struct atmel_spi *as = spi_controller_get_devdata(host); 1045 u32 status, pending, imr; 1046 struct spi_transfer *xfer; 1047 int ret = IRQ_NONE; 1048 1049 imr = spi_readl(as, IMR); 1050 status = spi_readl(as, SR); 1051 pending = status & imr; 1052 1053 if (pending & SPI_BIT(OVRES)) { 1054 ret = IRQ_HANDLED; 1055 spi_writel(as, IDR, SPI_BIT(OVRES)); 1056 dev_warn(host->dev.parent, "overrun\n"); 1057 1058 /* 1059 * When we get an overrun, we disregard the current 1060 * transfer. Data will not be copied back from any 1061 * bounce buffer and msg->actual_len will not be 1062 * updated with the last xfer. 1063 * 1064 * We will also not process any remaning transfers in 1065 * the message. 1066 */ 1067 as->done_status = -EIO; 1068 smp_wmb(); 1069 1070 /* Clear any overrun happening while cleaning up */ 1071 spi_readl(as, SR); 1072 1073 complete(&as->xfer_completion); 1074 1075 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) { 1076 atmel_spi_lock(as); 1077 1078 if (as->current_remaining_bytes) { 1079 ret = IRQ_HANDLED; 1080 xfer = as->current_transfer; 1081 atmel_spi_pump_pio_data(as, xfer); 1082 if (!as->current_remaining_bytes) 1083 spi_writel(as, IDR, pending); 1084 1085 complete(&as->xfer_completion); 1086 } 1087 1088 atmel_spi_unlock(as); 1089 } else { 1090 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending); 1091 ret = IRQ_HANDLED; 1092 spi_writel(as, IDR, pending); 1093 } 1094 1095 return ret; 1096 } 1097 1098 static irqreturn_t 1099 atmel_spi_pdc_interrupt(int irq, void *dev_id) 1100 { 1101 struct spi_controller *host = dev_id; 1102 struct atmel_spi *as = spi_controller_get_devdata(host); 1103 u32 status, pending, imr; 1104 int ret = IRQ_NONE; 1105 1106 imr = spi_readl(as, IMR); 1107 status = spi_readl(as, SR); 1108 pending = status & imr; 1109 1110 if (pending & SPI_BIT(OVRES)) { 1111 1112 ret = IRQ_HANDLED; 1113 1114 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) 1115 | SPI_BIT(OVRES))); 1116 1117 /* Clear any overrun happening while cleaning up */ 1118 spi_readl(as, SR); 1119 1120 as->done_status = -EIO; 1121 1122 complete(&as->xfer_completion); 1123 1124 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { 1125 ret = IRQ_HANDLED; 1126 1127 spi_writel(as, IDR, pending); 1128 1129 complete(&as->xfer_completion); 1130 } 1131 1132 return ret; 1133 } 1134 1135 static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as) 1136 { 1137 struct spi_delay *delay = &spi->word_delay; 1138 u32 value = delay->value; 1139 1140 switch (delay->unit) { 1141 case SPI_DELAY_UNIT_NSECS: 1142 value /= 1000; 1143 break; 1144 case SPI_DELAY_UNIT_USECS: 1145 break; 1146 default: 1147 return -EINVAL; 1148 } 1149 1150 return (as->spi_clk / 1000000 * value) >> 5; 1151 } 1152 1153 static void initialize_native_cs_for_gpio(struct atmel_spi *as) 1154 { 1155 int i; 1156 struct spi_controller *host = platform_get_drvdata(as->pdev); 1157 1158 if (!as->native_cs_free) 1159 return; /* already initialized */ 1160 1161 if (!host->cs_gpiods) 1162 return; /* No CS GPIO */ 1163 1164 /* 1165 * On the first version of the controller (AT91RM9200), CS0 1166 * can't be used associated with GPIO 1167 */ 1168 if (atmel_spi_is_v2(as)) 1169 i = 0; 1170 else 1171 i = 1; 1172 1173 for (; i < 4; i++) 1174 if (host->cs_gpiods[i]) 1175 as->native_cs_free |= BIT(i); 1176 1177 if (as->native_cs_free) 1178 as->native_cs_for_gpio = ffs(as->native_cs_free); 1179 } 1180 1181 static int atmel_spi_setup(struct spi_device *spi) 1182 { 1183 struct atmel_spi *as; 1184 struct atmel_spi_device *asd; 1185 u32 csr; 1186 unsigned int bits = spi->bits_per_word; 1187 int chip_select; 1188 int word_delay_csr; 1189 1190 as = spi_controller_get_devdata(spi->controller); 1191 1192 /* see notes above re chipselect */ 1193 if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH)) { 1194 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); 1195 return -EINVAL; 1196 } 1197 1198 /* Setup() is called during spi_register_controller(aka 1199 * spi_register_master) but after all membmers of the cs_gpiod 1200 * array have been filled, so we can looked for which native 1201 * CS will be free for using with GPIO 1202 */ 1203 initialize_native_cs_for_gpio(as); 1204 1205 if (spi_get_csgpiod(spi, 0) && as->native_cs_free) { 1206 dev_err(&spi->dev, 1207 "No native CS available to support this GPIO CS\n"); 1208 return -EBUSY; 1209 } 1210 1211 if (spi_get_csgpiod(spi, 0)) 1212 chip_select = as->native_cs_for_gpio; 1213 else 1214 chip_select = spi_get_chipselect(spi, 0); 1215 1216 csr = SPI_BF(BITS, bits - 8); 1217 if (spi->mode & SPI_CPOL) 1218 csr |= SPI_BIT(CPOL); 1219 if (!(spi->mode & SPI_CPHA)) 1220 csr |= SPI_BIT(NCPHA); 1221 1222 if (!spi_get_csgpiod(spi, 0)) 1223 csr |= SPI_BIT(CSAAT); 1224 csr |= SPI_BF(DLYBS, 0); 1225 1226 word_delay_csr = atmel_word_delay_csr(spi, as); 1227 if (word_delay_csr < 0) 1228 return word_delay_csr; 1229 1230 /* DLYBCT adds delays between words. This is useful for slow devices 1231 * that need a bit of time to setup the next transfer. 1232 */ 1233 csr |= SPI_BF(DLYBCT, word_delay_csr); 1234 1235 asd = spi->controller_state; 1236 if (!asd) { 1237 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); 1238 if (!asd) 1239 return -ENOMEM; 1240 1241 spi->controller_state = asd; 1242 } 1243 1244 asd->csr = csr; 1245 1246 dev_dbg(&spi->dev, 1247 "setup: bpw %u mode 0x%x -> csr%d %08x\n", 1248 bits, spi->mode, spi_get_chipselect(spi, 0), csr); 1249 1250 if (!atmel_spi_is_v2(as)) 1251 spi_writel(as, CSR0 + 4 * chip_select, csr); 1252 1253 return 0; 1254 } 1255 1256 static void atmel_spi_set_cs(struct spi_device *spi, bool enable) 1257 { 1258 struct atmel_spi *as = spi_controller_get_devdata(spi->controller); 1259 /* the core doesn't really pass us enable/disable, but CS HIGH vs CS LOW 1260 * since we already have routines for activate/deactivate translate 1261 * high/low to active/inactive 1262 */ 1263 enable = (!!(spi->mode & SPI_CS_HIGH) == enable); 1264 1265 if (enable) { 1266 cs_activate(as, spi); 1267 } else { 1268 cs_deactivate(as, spi); 1269 } 1270 1271 } 1272 1273 static int atmel_spi_one_transfer(struct spi_controller *host, 1274 struct spi_device *spi, 1275 struct spi_transfer *xfer) 1276 { 1277 struct atmel_spi *as; 1278 u8 bits; 1279 u32 len; 1280 struct atmel_spi_device *asd; 1281 int timeout; 1282 int ret; 1283 unsigned int dma_timeout; 1284 long ret_timeout; 1285 1286 as = spi_controller_get_devdata(host); 1287 1288 asd = spi->controller_state; 1289 bits = (asd->csr >> 4) & 0xf; 1290 if (bits != xfer->bits_per_word - 8) { 1291 dev_dbg(&spi->dev, 1292 "you can't yet change bits_per_word in transfers\n"); 1293 return -ENOPROTOOPT; 1294 } 1295 1296 /* 1297 * DMA map early, for performance (empties dcache ASAP) and 1298 * better fault reporting. 1299 */ 1300 if ((!host->cur_msg->is_dma_mapped) 1301 && as->use_pdc) { 1302 if (atmel_spi_dma_map_xfer(as, xfer) < 0) 1303 return -ENOMEM; 1304 } 1305 1306 atmel_spi_set_xfer_speed(as, spi, xfer); 1307 1308 as->done_status = 0; 1309 as->current_transfer = xfer; 1310 as->current_remaining_bytes = xfer->len; 1311 while (as->current_remaining_bytes) { 1312 reinit_completion(&as->xfer_completion); 1313 1314 if (as->use_pdc) { 1315 atmel_spi_lock(as); 1316 atmel_spi_pdc_next_xfer(host, xfer); 1317 atmel_spi_unlock(as); 1318 } else if (atmel_spi_use_dma(as, xfer)) { 1319 len = as->current_remaining_bytes; 1320 ret = atmel_spi_next_xfer_dma_submit(host, 1321 xfer, &len); 1322 if (ret) { 1323 dev_err(&spi->dev, 1324 "unable to use DMA, fallback to PIO\n"); 1325 as->done_status = ret; 1326 break; 1327 } else { 1328 as->current_remaining_bytes -= len; 1329 if (as->current_remaining_bytes < 0) 1330 as->current_remaining_bytes = 0; 1331 } 1332 } else { 1333 atmel_spi_lock(as); 1334 atmel_spi_next_xfer_pio(host, xfer); 1335 atmel_spi_unlock(as); 1336 } 1337 1338 dma_timeout = msecs_to_jiffies(spi_controller_xfer_timeout(host, xfer)); 1339 ret_timeout = wait_for_completion_interruptible_timeout(&as->xfer_completion, 1340 dma_timeout); 1341 if (ret_timeout <= 0) { 1342 dev_err(&spi->dev, "spi transfer %s\n", 1343 !ret_timeout ? "timeout" : "canceled"); 1344 as->done_status = ret_timeout < 0 ? ret_timeout : -EIO; 1345 } 1346 1347 if (as->done_status) 1348 break; 1349 } 1350 1351 if (as->done_status) { 1352 if (as->use_pdc) { 1353 dev_warn(host->dev.parent, 1354 "overrun (%u/%u remaining)\n", 1355 spi_readl(as, TCR), spi_readl(as, RCR)); 1356 1357 /* 1358 * Clean up DMA registers and make sure the data 1359 * registers are empty. 1360 */ 1361 spi_writel(as, RNCR, 0); 1362 spi_writel(as, TNCR, 0); 1363 spi_writel(as, RCR, 0); 1364 spi_writel(as, TCR, 0); 1365 for (timeout = 1000; timeout; timeout--) 1366 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) 1367 break; 1368 if (!timeout) 1369 dev_warn(host->dev.parent, 1370 "timeout waiting for TXEMPTY"); 1371 while (spi_readl(as, SR) & SPI_BIT(RDRF)) 1372 spi_readl(as, RDR); 1373 1374 /* Clear any overrun happening while cleaning up */ 1375 spi_readl(as, SR); 1376 1377 } else if (atmel_spi_use_dma(as, xfer)) { 1378 atmel_spi_stop_dma(host); 1379 } 1380 } 1381 1382 if (!host->cur_msg->is_dma_mapped 1383 && as->use_pdc) 1384 atmel_spi_dma_unmap_xfer(host, xfer); 1385 1386 if (as->use_pdc) 1387 atmel_spi_disable_pdc_transfer(as); 1388 1389 return as->done_status; 1390 } 1391 1392 static void atmel_spi_cleanup(struct spi_device *spi) 1393 { 1394 struct atmel_spi_device *asd = spi->controller_state; 1395 1396 if (!asd) 1397 return; 1398 1399 spi->controller_state = NULL; 1400 kfree(asd); 1401 } 1402 1403 static inline unsigned int atmel_get_version(struct atmel_spi *as) 1404 { 1405 return spi_readl(as, VERSION) & 0x00000fff; 1406 } 1407 1408 static void atmel_get_caps(struct atmel_spi *as) 1409 { 1410 unsigned int version; 1411 1412 version = atmel_get_version(as); 1413 1414 as->caps.is_spi2 = version > 0x121; 1415 as->caps.has_wdrbt = version >= 0x210; 1416 as->caps.has_dma_support = version >= 0x212; 1417 as->caps.has_pdc_support = version < 0x212; 1418 } 1419 1420 static void atmel_spi_init(struct atmel_spi *as) 1421 { 1422 spi_writel(as, CR, SPI_BIT(SWRST)); 1423 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1424 1425 /* It is recommended to enable FIFOs first thing after reset */ 1426 if (as->fifo_size) 1427 spi_writel(as, CR, SPI_BIT(FIFOEN)); 1428 1429 if (as->caps.has_wdrbt) { 1430 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) 1431 | SPI_BIT(MSTR)); 1432 } else { 1433 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); 1434 } 1435 1436 if (as->use_pdc) 1437 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 1438 spi_writel(as, CR, SPI_BIT(SPIEN)); 1439 } 1440 1441 static int atmel_spi_probe(struct platform_device *pdev) 1442 { 1443 struct resource *regs; 1444 int irq; 1445 struct clk *clk; 1446 int ret; 1447 struct spi_controller *host; 1448 struct atmel_spi *as; 1449 1450 /* Select default pin state */ 1451 pinctrl_pm_select_default_state(&pdev->dev); 1452 1453 irq = platform_get_irq(pdev, 0); 1454 if (irq < 0) 1455 return irq; 1456 1457 clk = devm_clk_get(&pdev->dev, "spi_clk"); 1458 if (IS_ERR(clk)) 1459 return PTR_ERR(clk); 1460 1461 /* setup spi core then atmel-specific driver state */ 1462 host = spi_alloc_host(&pdev->dev, sizeof(*as)); 1463 if (!host) 1464 return -ENOMEM; 1465 1466 /* the spi->mode bits understood by this driver: */ 1467 host->use_gpio_descriptors = true; 1468 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1469 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); 1470 host->dev.of_node = pdev->dev.of_node; 1471 host->bus_num = pdev->id; 1472 host->num_chipselect = 4; 1473 host->setup = atmel_spi_setup; 1474 host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX | 1475 SPI_CONTROLLER_GPIO_SS); 1476 host->transfer_one = atmel_spi_one_transfer; 1477 host->set_cs = atmel_spi_set_cs; 1478 host->cleanup = atmel_spi_cleanup; 1479 host->auto_runtime_pm = true; 1480 host->max_dma_len = SPI_MAX_DMA_XFER; 1481 host->can_dma = atmel_spi_can_dma; 1482 platform_set_drvdata(pdev, host); 1483 1484 as = spi_controller_get_devdata(host); 1485 1486 spin_lock_init(&as->lock); 1487 1488 as->pdev = pdev; 1489 as->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 1490 if (IS_ERR(as->regs)) { 1491 ret = PTR_ERR(as->regs); 1492 goto out_unmap_regs; 1493 } 1494 as->phybase = regs->start; 1495 as->irq = irq; 1496 as->clk = clk; 1497 1498 init_completion(&as->xfer_completion); 1499 1500 atmel_get_caps(as); 1501 1502 as->use_dma = false; 1503 as->use_pdc = false; 1504 if (as->caps.has_dma_support) { 1505 ret = atmel_spi_configure_dma(host, as); 1506 if (ret == 0) { 1507 as->use_dma = true; 1508 } else if (ret == -EPROBE_DEFER) { 1509 goto out_unmap_regs; 1510 } 1511 } else if (as->caps.has_pdc_support) { 1512 as->use_pdc = true; 1513 } 1514 1515 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 1516 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev, 1517 SPI_MAX_DMA_XFER, 1518 &as->dma_addr_rx_bbuf, 1519 GFP_KERNEL | GFP_DMA); 1520 if (!as->addr_rx_bbuf) { 1521 as->use_dma = false; 1522 } else { 1523 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev, 1524 SPI_MAX_DMA_XFER, 1525 &as->dma_addr_tx_bbuf, 1526 GFP_KERNEL | GFP_DMA); 1527 if (!as->addr_tx_bbuf) { 1528 as->use_dma = false; 1529 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1530 as->addr_rx_bbuf, 1531 as->dma_addr_rx_bbuf); 1532 } 1533 } 1534 if (!as->use_dma) 1535 dev_info(host->dev.parent, 1536 " can not allocate dma coherent memory\n"); 1537 } 1538 1539 if (as->caps.has_dma_support && !as->use_dma) 1540 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); 1541 1542 if (as->use_pdc) { 1543 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt, 1544 0, dev_name(&pdev->dev), host); 1545 } else { 1546 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt, 1547 0, dev_name(&pdev->dev), host); 1548 } 1549 if (ret) 1550 goto out_unmap_regs; 1551 1552 /* Initialize the hardware */ 1553 ret = clk_prepare_enable(clk); 1554 if (ret) 1555 goto out_free_irq; 1556 1557 as->spi_clk = clk_get_rate(clk); 1558 1559 as->fifo_size = 0; 1560 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", 1561 &as->fifo_size)) { 1562 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size); 1563 } 1564 1565 atmel_spi_init(as); 1566 1567 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1568 pm_runtime_use_autosuspend(&pdev->dev); 1569 pm_runtime_set_active(&pdev->dev); 1570 pm_runtime_enable(&pdev->dev); 1571 1572 ret = devm_spi_register_controller(&pdev->dev, host); 1573 if (ret) 1574 goto out_free_dma; 1575 1576 /* go! */ 1577 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n", 1578 atmel_get_version(as), (unsigned long)regs->start, 1579 irq); 1580 1581 return 0; 1582 1583 out_free_dma: 1584 pm_runtime_disable(&pdev->dev); 1585 pm_runtime_set_suspended(&pdev->dev); 1586 1587 if (as->use_dma) 1588 atmel_spi_release_dma(host); 1589 1590 spi_writel(as, CR, SPI_BIT(SWRST)); 1591 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1592 clk_disable_unprepare(clk); 1593 out_free_irq: 1594 out_unmap_regs: 1595 spi_controller_put(host); 1596 return ret; 1597 } 1598 1599 static void atmel_spi_remove(struct platform_device *pdev) 1600 { 1601 struct spi_controller *host = platform_get_drvdata(pdev); 1602 struct atmel_spi *as = spi_controller_get_devdata(host); 1603 1604 pm_runtime_get_sync(&pdev->dev); 1605 1606 /* reset the hardware and block queue progress */ 1607 if (as->use_dma) { 1608 atmel_spi_stop_dma(host); 1609 atmel_spi_release_dma(host); 1610 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 1611 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1612 as->addr_tx_bbuf, 1613 as->dma_addr_tx_bbuf); 1614 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1615 as->addr_rx_bbuf, 1616 as->dma_addr_rx_bbuf); 1617 } 1618 } 1619 1620 spin_lock_irq(&as->lock); 1621 spi_writel(as, CR, SPI_BIT(SWRST)); 1622 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1623 spi_readl(as, SR); 1624 spin_unlock_irq(&as->lock); 1625 1626 clk_disable_unprepare(as->clk); 1627 1628 pm_runtime_put_noidle(&pdev->dev); 1629 pm_runtime_disable(&pdev->dev); 1630 } 1631 1632 static int atmel_spi_runtime_suspend(struct device *dev) 1633 { 1634 struct spi_controller *host = dev_get_drvdata(dev); 1635 struct atmel_spi *as = spi_controller_get_devdata(host); 1636 1637 clk_disable_unprepare(as->clk); 1638 pinctrl_pm_select_sleep_state(dev); 1639 1640 return 0; 1641 } 1642 1643 static int atmel_spi_runtime_resume(struct device *dev) 1644 { 1645 struct spi_controller *host = dev_get_drvdata(dev); 1646 struct atmel_spi *as = spi_controller_get_devdata(host); 1647 1648 pinctrl_pm_select_default_state(dev); 1649 1650 return clk_prepare_enable(as->clk); 1651 } 1652 1653 static int atmel_spi_suspend(struct device *dev) 1654 { 1655 struct spi_controller *host = dev_get_drvdata(dev); 1656 int ret; 1657 1658 /* Stop the queue running */ 1659 ret = spi_controller_suspend(host); 1660 if (ret) 1661 return ret; 1662 1663 if (!pm_runtime_suspended(dev)) 1664 atmel_spi_runtime_suspend(dev); 1665 1666 return 0; 1667 } 1668 1669 static int atmel_spi_resume(struct device *dev) 1670 { 1671 struct spi_controller *host = dev_get_drvdata(dev); 1672 struct atmel_spi *as = spi_controller_get_devdata(host); 1673 int ret; 1674 1675 ret = clk_prepare_enable(as->clk); 1676 if (ret) 1677 return ret; 1678 1679 atmel_spi_init(as); 1680 1681 clk_disable_unprepare(as->clk); 1682 1683 if (!pm_runtime_suspended(dev)) { 1684 ret = atmel_spi_runtime_resume(dev); 1685 if (ret) 1686 return ret; 1687 } 1688 1689 /* Start the queue running */ 1690 return spi_controller_resume(host); 1691 } 1692 1693 static const struct dev_pm_ops atmel_spi_pm_ops = { 1694 SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume) 1695 RUNTIME_PM_OPS(atmel_spi_runtime_suspend, 1696 atmel_spi_runtime_resume, NULL) 1697 }; 1698 1699 static const struct of_device_id atmel_spi_dt_ids[] = { 1700 { .compatible = "atmel,at91rm9200-spi" }, 1701 { /* sentinel */ } 1702 }; 1703 1704 MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); 1705 1706 static struct platform_driver atmel_spi_driver = { 1707 .driver = { 1708 .name = "atmel_spi", 1709 .pm = pm_ptr(&atmel_spi_pm_ops), 1710 .of_match_table = atmel_spi_dt_ids, 1711 }, 1712 .probe = atmel_spi_probe, 1713 .remove_new = atmel_spi_remove, 1714 }; 1715 module_platform_driver(atmel_spi_driver); 1716 1717 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); 1718 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1719 MODULE_LICENSE("GPL"); 1720 MODULE_ALIAS("platform:atmel_spi"); 1721