1 /* 2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs 3 * 4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 5 * 6 * This driver has been based on the spi-gpio.c: 7 * Copyright (C) 2006,2008 David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/spinlock.h> 20 #include <linux/workqueue.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/spi/spi.h> 24 #include <linux/spi/spi_bitbang.h> 25 #include <linux/bitops.h> 26 #include <linux/gpio.h> 27 #include <linux/clk.h> 28 #include <linux/err.h> 29 30 #include <asm/mach-ath79/ar71xx_regs.h> 31 #include <asm/mach-ath79/ath79_spi_platform.h> 32 33 #define DRV_NAME "ath79-spi" 34 35 #define ATH79_SPI_RRW_DELAY_FACTOR 12000 36 #define MHZ (1000 * 1000) 37 38 struct ath79_spi { 39 struct spi_bitbang bitbang; 40 u32 ioc_base; 41 u32 reg_ctrl; 42 void __iomem *base; 43 struct clk *clk; 44 unsigned rrw_delay; 45 }; 46 47 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) 48 { 49 return ioread32(sp->base + reg); 50 } 51 52 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) 53 { 54 iowrite32(val, sp->base + reg); 55 } 56 57 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi) 58 { 59 return spi_master_get_devdata(spi->master); 60 } 61 62 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs) 63 { 64 if (nsecs > sp->rrw_delay) 65 ndelay(nsecs - sp->rrw_delay); 66 } 67 68 static void ath79_spi_chipselect(struct spi_device *spi, int is_active) 69 { 70 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 71 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; 72 73 if (is_active) { 74 /* set initial clock polarity */ 75 if (spi->mode & SPI_CPOL) 76 sp->ioc_base |= AR71XX_SPI_IOC_CLK; 77 else 78 sp->ioc_base &= ~AR71XX_SPI_IOC_CLK; 79 80 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 81 } 82 83 if (spi->chip_select) { 84 struct ath79_spi_controller_data *cdata = spi->controller_data; 85 86 /* SPI is normally active-low */ 87 gpio_set_value(cdata->gpio, cs_high); 88 } else { 89 if (cs_high) 90 sp->ioc_base |= AR71XX_SPI_IOC_CS0; 91 else 92 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; 93 94 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 95 } 96 97 } 98 99 static void ath79_spi_enable(struct ath79_spi *sp) 100 { 101 /* enable GPIO mode */ 102 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); 103 104 /* save CTRL register */ 105 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); 106 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); 107 108 /* TODO: setup speed? */ 109 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); 110 } 111 112 static void ath79_spi_disable(struct ath79_spi *sp) 113 { 114 /* restore CTRL register */ 115 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); 116 /* disable GPIO mode */ 117 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); 118 } 119 120 static int ath79_spi_setup_cs(struct spi_device *spi) 121 { 122 struct ath79_spi_controller_data *cdata; 123 int status; 124 125 cdata = spi->controller_data; 126 if (spi->chip_select && !cdata) 127 return -EINVAL; 128 129 status = 0; 130 if (spi->chip_select) { 131 unsigned long flags; 132 133 flags = GPIOF_DIR_OUT; 134 if (spi->mode & SPI_CS_HIGH) 135 flags |= GPIOF_INIT_HIGH; 136 else 137 flags |= GPIOF_INIT_LOW; 138 139 status = gpio_request_one(cdata->gpio, flags, 140 dev_name(&spi->dev)); 141 } 142 143 return status; 144 } 145 146 static void ath79_spi_cleanup_cs(struct spi_device *spi) 147 { 148 if (spi->chip_select) { 149 struct ath79_spi_controller_data *cdata = spi->controller_data; 150 gpio_free(cdata->gpio); 151 } 152 } 153 154 static int ath79_spi_setup(struct spi_device *spi) 155 { 156 int status = 0; 157 158 if (spi->bits_per_word > 32) 159 return -EINVAL; 160 161 if (!spi->controller_state) { 162 status = ath79_spi_setup_cs(spi); 163 if (status) 164 return status; 165 } 166 167 status = spi_bitbang_setup(spi); 168 if (status && !spi->controller_state) 169 ath79_spi_cleanup_cs(spi); 170 171 return status; 172 } 173 174 static void ath79_spi_cleanup(struct spi_device *spi) 175 { 176 ath79_spi_cleanup_cs(spi); 177 spi_bitbang_cleanup(spi); 178 } 179 180 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, 181 u32 word, u8 bits) 182 { 183 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 184 u32 ioc = sp->ioc_base; 185 186 /* clock starts at inactive polarity */ 187 for (word <<= (32 - bits); likely(bits); bits--) { 188 u32 out; 189 190 if (word & (1 << 31)) 191 out = ioc | AR71XX_SPI_IOC_DO; 192 else 193 out = ioc & ~AR71XX_SPI_IOC_DO; 194 195 /* setup MSB (to slave) on trailing edge */ 196 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); 197 ath79_spi_delay(sp, nsecs); 198 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); 199 ath79_spi_delay(sp, nsecs); 200 if (bits == 1) 201 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); 202 203 word <<= 1; 204 } 205 206 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); 207 } 208 209 static int ath79_spi_probe(struct platform_device *pdev) 210 { 211 struct spi_master *master; 212 struct ath79_spi *sp; 213 struct ath79_spi_platform_data *pdata; 214 struct resource *r; 215 unsigned long rate; 216 int ret; 217 218 master = spi_alloc_master(&pdev->dev, sizeof(*sp)); 219 if (master == NULL) { 220 dev_err(&pdev->dev, "failed to allocate spi master\n"); 221 return -ENOMEM; 222 } 223 224 sp = spi_master_get_devdata(master); 225 platform_set_drvdata(pdev, sp); 226 227 pdata = pdev->dev.platform_data; 228 229 master->setup = ath79_spi_setup; 230 master->cleanup = ath79_spi_cleanup; 231 if (pdata) { 232 master->bus_num = pdata->bus_num; 233 master->num_chipselect = pdata->num_chipselect; 234 } 235 236 sp->bitbang.master = spi_master_get(master); 237 sp->bitbang.chipselect = ath79_spi_chipselect; 238 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; 239 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; 240 sp->bitbang.flags = SPI_CS_HIGH; 241 242 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 243 if (r == NULL) { 244 ret = -ENOENT; 245 goto err_put_master; 246 } 247 248 sp->base = ioremap(r->start, resource_size(r)); 249 if (!sp->base) { 250 ret = -ENXIO; 251 goto err_put_master; 252 } 253 254 sp->clk = clk_get(&pdev->dev, "ahb"); 255 if (IS_ERR(sp->clk)) { 256 ret = PTR_ERR(sp->clk); 257 goto err_unmap; 258 } 259 260 ret = clk_enable(sp->clk); 261 if (ret) 262 goto err_clk_put; 263 264 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); 265 if (!rate) { 266 ret = -EINVAL; 267 goto err_clk_disable; 268 } 269 270 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; 271 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", 272 sp->rrw_delay); 273 274 ath79_spi_enable(sp); 275 ret = spi_bitbang_start(&sp->bitbang); 276 if (ret) 277 goto err_disable; 278 279 return 0; 280 281 err_disable: 282 ath79_spi_disable(sp); 283 err_clk_disable: 284 clk_disable(sp->clk); 285 err_clk_put: 286 clk_put(sp->clk); 287 err_unmap: 288 iounmap(sp->base); 289 err_put_master: 290 platform_set_drvdata(pdev, NULL); 291 spi_master_put(sp->bitbang.master); 292 293 return ret; 294 } 295 296 static int ath79_spi_remove(struct platform_device *pdev) 297 { 298 struct ath79_spi *sp = platform_get_drvdata(pdev); 299 300 spi_bitbang_stop(&sp->bitbang); 301 ath79_spi_disable(sp); 302 clk_disable(sp->clk); 303 clk_put(sp->clk); 304 iounmap(sp->base); 305 platform_set_drvdata(pdev, NULL); 306 spi_master_put(sp->bitbang.master); 307 308 return 0; 309 } 310 311 static void ath79_spi_shutdown(struct platform_device *pdev) 312 { 313 ath79_spi_remove(pdev); 314 } 315 316 static struct platform_driver ath79_spi_driver = { 317 .probe = ath79_spi_probe, 318 .remove = ath79_spi_remove, 319 .shutdown = ath79_spi_shutdown, 320 .driver = { 321 .name = DRV_NAME, 322 .owner = THIS_MODULE, 323 }, 324 }; 325 module_platform_driver(ath79_spi_driver); 326 327 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X"); 328 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); 329 MODULE_LICENSE("GPL v2"); 330 MODULE_ALIAS("platform:" DRV_NAME); 331