1 /* 2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs 3 * 4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 5 * 6 * This driver has been based on the spi-gpio.c: 7 * Copyright (C) 2006,2008 David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/spinlock.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi_bitbang.h> 23 #include <linux/bitops.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 #include <linux/platform_data/spi-ath79.h> 27 28 #define DRV_NAME "ath79-spi" 29 30 #define ATH79_SPI_RRW_DELAY_FACTOR 12000 31 #define MHZ (1000 * 1000) 32 33 #define AR71XX_SPI_REG_FS 0x00 /* Function Select */ 34 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ 35 #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ 36 #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ 37 38 #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ 39 40 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ 41 #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ 42 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 43 44 struct ath79_spi { 45 struct spi_bitbang bitbang; 46 u32 ioc_base; 47 u32 reg_ctrl; 48 void __iomem *base; 49 struct clk *clk; 50 unsigned int rrw_delay; 51 }; 52 53 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg) 54 { 55 return ioread32(sp->base + reg); 56 } 57 58 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val) 59 { 60 iowrite32(val, sp->base + reg); 61 } 62 63 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi) 64 { 65 return spi_master_get_devdata(spi->master); 66 } 67 68 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs) 69 { 70 if (nsecs > sp->rrw_delay) 71 ndelay(nsecs - sp->rrw_delay); 72 } 73 74 static void ath79_spi_chipselect(struct spi_device *spi, int is_active) 75 { 76 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 77 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; 78 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); 79 80 if (cs_high) 81 sp->ioc_base |= cs_bit; 82 else 83 sp->ioc_base &= ~cs_bit; 84 85 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 86 } 87 88 static void ath79_spi_enable(struct ath79_spi *sp) 89 { 90 /* enable GPIO mode */ 91 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); 92 93 /* save CTRL register */ 94 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); 95 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); 96 97 /* clear clk and mosi in the base state */ 98 sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK); 99 100 /* TODO: setup speed? */ 101 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); 102 } 103 104 static void ath79_spi_disable(struct ath79_spi *sp) 105 { 106 /* restore CTRL register */ 107 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); 108 /* disable GPIO mode */ 109 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); 110 } 111 112 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs, 113 u32 word, u8 bits, unsigned flags) 114 { 115 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 116 u32 ioc = sp->ioc_base; 117 118 /* clock starts at inactive polarity */ 119 for (word <<= (32 - bits); likely(bits); bits--) { 120 u32 out; 121 122 if (word & (1 << 31)) 123 out = ioc | AR71XX_SPI_IOC_DO; 124 else 125 out = ioc & ~AR71XX_SPI_IOC_DO; 126 127 /* setup MSB (to slave) on trailing edge */ 128 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); 129 ath79_spi_delay(sp, nsecs); 130 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); 131 ath79_spi_delay(sp, nsecs); 132 if (bits == 1) 133 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); 134 135 word <<= 1; 136 } 137 138 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); 139 } 140 141 static int ath79_spi_probe(struct platform_device *pdev) 142 { 143 struct spi_master *master; 144 struct ath79_spi *sp; 145 struct ath79_spi_platform_data *pdata; 146 struct resource *r; 147 unsigned long rate; 148 int ret; 149 150 master = spi_alloc_master(&pdev->dev, sizeof(*sp)); 151 if (master == NULL) { 152 dev_err(&pdev->dev, "failed to allocate spi master\n"); 153 return -ENOMEM; 154 } 155 156 sp = spi_master_get_devdata(master); 157 master->dev.of_node = pdev->dev.of_node; 158 platform_set_drvdata(pdev, sp); 159 160 pdata = dev_get_platdata(&pdev->dev); 161 162 master->use_gpio_descriptors = true; 163 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 164 master->setup = spi_bitbang_setup; 165 master->cleanup = spi_bitbang_cleanup; 166 if (pdata) { 167 master->bus_num = pdata->bus_num; 168 master->num_chipselect = pdata->num_chipselect; 169 } 170 171 sp->bitbang.master = master; 172 sp->bitbang.chipselect = ath79_spi_chipselect; 173 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; 174 sp->bitbang.flags = SPI_CS_HIGH; 175 176 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 177 sp->base = devm_ioremap_resource(&pdev->dev, r); 178 if (IS_ERR(sp->base)) { 179 ret = PTR_ERR(sp->base); 180 goto err_put_master; 181 } 182 183 sp->clk = devm_clk_get(&pdev->dev, "ahb"); 184 if (IS_ERR(sp->clk)) { 185 ret = PTR_ERR(sp->clk); 186 goto err_put_master; 187 } 188 189 ret = clk_prepare_enable(sp->clk); 190 if (ret) 191 goto err_put_master; 192 193 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); 194 if (!rate) { 195 ret = -EINVAL; 196 goto err_clk_disable; 197 } 198 199 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; 200 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", 201 sp->rrw_delay); 202 203 ath79_spi_enable(sp); 204 ret = spi_bitbang_start(&sp->bitbang); 205 if (ret) 206 goto err_disable; 207 208 return 0; 209 210 err_disable: 211 ath79_spi_disable(sp); 212 err_clk_disable: 213 clk_disable_unprepare(sp->clk); 214 err_put_master: 215 spi_master_put(sp->bitbang.master); 216 217 return ret; 218 } 219 220 static int ath79_spi_remove(struct platform_device *pdev) 221 { 222 struct ath79_spi *sp = platform_get_drvdata(pdev); 223 224 spi_bitbang_stop(&sp->bitbang); 225 ath79_spi_disable(sp); 226 clk_disable_unprepare(sp->clk); 227 spi_master_put(sp->bitbang.master); 228 229 return 0; 230 } 231 232 static void ath79_spi_shutdown(struct platform_device *pdev) 233 { 234 ath79_spi_remove(pdev); 235 } 236 237 static const struct of_device_id ath79_spi_of_match[] = { 238 { .compatible = "qca,ar7100-spi", }, 239 { }, 240 }; 241 MODULE_DEVICE_TABLE(of, ath79_spi_of_match); 242 243 static struct platform_driver ath79_spi_driver = { 244 .probe = ath79_spi_probe, 245 .remove = ath79_spi_remove, 246 .shutdown = ath79_spi_shutdown, 247 .driver = { 248 .name = DRV_NAME, 249 .of_match_table = ath79_spi_of_match, 250 }, 251 }; 252 module_platform_driver(ath79_spi_driver); 253 254 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X"); 255 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); 256 MODULE_LICENSE("GPL v2"); 257 MODULE_ALIAS("platform:" DRV_NAME); 258