1 /* 2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs 3 * 4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 5 * 6 * This driver has been based on the spi-gpio.c: 7 * Copyright (C) 2006,2008 David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/spinlock.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi_bitbang.h> 23 #include <linux/bitops.h> 24 #include <linux/gpio.h> 25 #include <linux/clk.h> 26 #include <linux/err.h> 27 28 #include <asm/mach-ath79/ar71xx_regs.h> 29 #include <asm/mach-ath79/ath79_spi_platform.h> 30 31 #define DRV_NAME "ath79-spi" 32 33 #define ATH79_SPI_RRW_DELAY_FACTOR 12000 34 #define MHZ (1000 * 1000) 35 36 struct ath79_spi { 37 struct spi_bitbang bitbang; 38 u32 ioc_base; 39 u32 reg_ctrl; 40 void __iomem *base; 41 struct clk *clk; 42 unsigned rrw_delay; 43 }; 44 45 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) 46 { 47 return ioread32(sp->base + reg); 48 } 49 50 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) 51 { 52 iowrite32(val, sp->base + reg); 53 } 54 55 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi) 56 { 57 return spi_master_get_devdata(spi->master); 58 } 59 60 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs) 61 { 62 if (nsecs > sp->rrw_delay) 63 ndelay(nsecs - sp->rrw_delay); 64 } 65 66 static void ath79_spi_chipselect(struct spi_device *spi, int is_active) 67 { 68 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 69 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; 70 71 if (is_active) { 72 /* set initial clock polarity */ 73 if (spi->mode & SPI_CPOL) 74 sp->ioc_base |= AR71XX_SPI_IOC_CLK; 75 else 76 sp->ioc_base &= ~AR71XX_SPI_IOC_CLK; 77 78 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 79 } 80 81 if (spi->chip_select) { 82 /* SPI is normally active-low */ 83 gpio_set_value(spi->cs_gpio, cs_high); 84 } else { 85 if (cs_high) 86 sp->ioc_base |= AR71XX_SPI_IOC_CS0; 87 else 88 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; 89 90 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 91 } 92 93 } 94 95 static void ath79_spi_enable(struct ath79_spi *sp) 96 { 97 /* enable GPIO mode */ 98 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); 99 100 /* save CTRL register */ 101 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); 102 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); 103 104 /* TODO: setup speed? */ 105 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); 106 } 107 108 static void ath79_spi_disable(struct ath79_spi *sp) 109 { 110 /* restore CTRL register */ 111 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); 112 /* disable GPIO mode */ 113 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); 114 } 115 116 static int ath79_spi_setup_cs(struct spi_device *spi) 117 { 118 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 119 int status; 120 121 if (spi->chip_select && !gpio_is_valid(spi->cs_gpio)) 122 return -EINVAL; 123 124 status = 0; 125 if (spi->chip_select) { 126 unsigned long flags; 127 128 flags = GPIOF_DIR_OUT; 129 if (spi->mode & SPI_CS_HIGH) 130 flags |= GPIOF_INIT_LOW; 131 else 132 flags |= GPIOF_INIT_HIGH; 133 134 status = gpio_request_one(spi->cs_gpio, flags, 135 dev_name(&spi->dev)); 136 } else { 137 if (spi->mode & SPI_CS_HIGH) 138 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0; 139 else 140 sp->ioc_base |= AR71XX_SPI_IOC_CS0; 141 142 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 143 } 144 145 return status; 146 } 147 148 static void ath79_spi_cleanup_cs(struct spi_device *spi) 149 { 150 if (spi->chip_select) { 151 gpio_free(spi->cs_gpio); 152 } 153 } 154 155 static int ath79_spi_setup(struct spi_device *spi) 156 { 157 int status = 0; 158 159 if (!spi->controller_state) { 160 status = ath79_spi_setup_cs(spi); 161 if (status) 162 return status; 163 } 164 165 status = spi_bitbang_setup(spi); 166 if (status && !spi->controller_state) 167 ath79_spi_cleanup_cs(spi); 168 169 return status; 170 } 171 172 static void ath79_spi_cleanup(struct spi_device *spi) 173 { 174 ath79_spi_cleanup_cs(spi); 175 spi_bitbang_cleanup(spi); 176 } 177 178 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, 179 u32 word, u8 bits) 180 { 181 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 182 u32 ioc = sp->ioc_base; 183 184 /* clock starts at inactive polarity */ 185 for (word <<= (32 - bits); likely(bits); bits--) { 186 u32 out; 187 188 if (word & (1 << 31)) 189 out = ioc | AR71XX_SPI_IOC_DO; 190 else 191 out = ioc & ~AR71XX_SPI_IOC_DO; 192 193 /* setup MSB (to slave) on trailing edge */ 194 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); 195 ath79_spi_delay(sp, nsecs); 196 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); 197 ath79_spi_delay(sp, nsecs); 198 if (bits == 1) 199 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); 200 201 word <<= 1; 202 } 203 204 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); 205 } 206 207 static int ath79_spi_probe(struct platform_device *pdev) 208 { 209 struct spi_master *master; 210 struct ath79_spi *sp; 211 struct ath79_spi_platform_data *pdata; 212 struct resource *r; 213 unsigned long rate; 214 int ret; 215 216 master = spi_alloc_master(&pdev->dev, sizeof(*sp)); 217 if (master == NULL) { 218 dev_err(&pdev->dev, "failed to allocate spi master\n"); 219 return -ENOMEM; 220 } 221 222 sp = spi_master_get_devdata(master); 223 master->dev.of_node = pdev->dev.of_node; 224 platform_set_drvdata(pdev, sp); 225 226 pdata = dev_get_platdata(&pdev->dev); 227 228 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 229 master->setup = ath79_spi_setup; 230 master->cleanup = ath79_spi_cleanup; 231 if (pdata) { 232 master->bus_num = pdata->bus_num; 233 master->num_chipselect = pdata->num_chipselect; 234 } 235 236 sp->bitbang.master = master; 237 sp->bitbang.chipselect = ath79_spi_chipselect; 238 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; 239 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; 240 sp->bitbang.flags = SPI_CS_HIGH; 241 242 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 243 if (r == NULL) { 244 ret = -ENOENT; 245 goto err_put_master; 246 } 247 248 sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 249 if (!sp->base) { 250 ret = -ENXIO; 251 goto err_put_master; 252 } 253 254 sp->clk = devm_clk_get(&pdev->dev, "ahb"); 255 if (IS_ERR(sp->clk)) { 256 ret = PTR_ERR(sp->clk); 257 goto err_put_master; 258 } 259 260 ret = clk_prepare_enable(sp->clk); 261 if (ret) 262 goto err_put_master; 263 264 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); 265 if (!rate) { 266 ret = -EINVAL; 267 goto err_clk_disable; 268 } 269 270 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; 271 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", 272 sp->rrw_delay); 273 274 ath79_spi_enable(sp); 275 ret = spi_bitbang_start(&sp->bitbang); 276 if (ret) 277 goto err_disable; 278 279 return 0; 280 281 err_disable: 282 ath79_spi_disable(sp); 283 err_clk_disable: 284 clk_disable_unprepare(sp->clk); 285 err_put_master: 286 spi_master_put(sp->bitbang.master); 287 288 return ret; 289 } 290 291 static int ath79_spi_remove(struct platform_device *pdev) 292 { 293 struct ath79_spi *sp = platform_get_drvdata(pdev); 294 295 spi_bitbang_stop(&sp->bitbang); 296 ath79_spi_disable(sp); 297 clk_disable_unprepare(sp->clk); 298 spi_master_put(sp->bitbang.master); 299 300 return 0; 301 } 302 303 static void ath79_spi_shutdown(struct platform_device *pdev) 304 { 305 ath79_spi_remove(pdev); 306 } 307 308 static const struct of_device_id ath79_spi_of_match[] = { 309 { .compatible = "qca,ar7100-spi", }, 310 { }, 311 }; 312 313 static struct platform_driver ath79_spi_driver = { 314 .probe = ath79_spi_probe, 315 .remove = ath79_spi_remove, 316 .shutdown = ath79_spi_shutdown, 317 .driver = { 318 .name = DRV_NAME, 319 .of_match_table = ath79_spi_of_match, 320 }, 321 }; 322 module_platform_driver(ath79_spi_driver); 323 324 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X"); 325 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); 326 MODULE_LICENSE("GPL v2"); 327 MODULE_ALIAS("platform:" DRV_NAME); 328