1 /* 2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs 3 * 4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 5 * 6 * This driver has been based on the spi-gpio.c: 7 * Copyright (C) 2006,2008 David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/spinlock.h> 19 #include <linux/platform_device.h> 20 #include <linux/io.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi_bitbang.h> 23 #include <linux/bitops.h> 24 #include <linux/clk.h> 25 #include <linux/err.h> 26 27 #include <asm/mach-ath79/ar71xx_regs.h> 28 #include <asm/mach-ath79/ath79_spi_platform.h> 29 30 #define DRV_NAME "ath79-spi" 31 32 #define ATH79_SPI_RRW_DELAY_FACTOR 12000 33 #define MHZ (1000 * 1000) 34 35 struct ath79_spi { 36 struct spi_bitbang bitbang; 37 u32 ioc_base; 38 u32 reg_ctrl; 39 void __iomem *base; 40 struct clk *clk; 41 unsigned int rrw_delay; 42 }; 43 44 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg) 45 { 46 return ioread32(sp->base + reg); 47 } 48 49 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val) 50 { 51 iowrite32(val, sp->base + reg); 52 } 53 54 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi) 55 { 56 return spi_master_get_devdata(spi->master); 57 } 58 59 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs) 60 { 61 if (nsecs > sp->rrw_delay) 62 ndelay(nsecs - sp->rrw_delay); 63 } 64 65 static void ath79_spi_chipselect(struct spi_device *spi, int is_active) 66 { 67 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 68 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; 69 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); 70 71 if (cs_high) 72 sp->ioc_base |= cs_bit; 73 else 74 sp->ioc_base &= ~cs_bit; 75 76 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 77 } 78 79 static void ath79_spi_enable(struct ath79_spi *sp) 80 { 81 /* enable GPIO mode */ 82 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); 83 84 /* save CTRL register */ 85 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); 86 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); 87 88 /* clear clk and mosi in the base state */ 89 sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK); 90 91 /* TODO: setup speed? */ 92 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); 93 } 94 95 static void ath79_spi_disable(struct ath79_spi *sp) 96 { 97 /* restore CTRL register */ 98 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); 99 /* disable GPIO mode */ 100 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); 101 } 102 103 static int ath79_spi_setup_cs(struct spi_device *spi) 104 { 105 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 106 107 if (!spi->cs_gpiod) { 108 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); 109 110 if (spi->mode & SPI_CS_HIGH) 111 sp->ioc_base &= ~cs_bit; 112 else 113 sp->ioc_base |= cs_bit; 114 115 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); 116 } 117 118 return 0; 119 } 120 121 static int ath79_spi_setup(struct spi_device *spi) 122 { 123 int status = 0; 124 125 if (!spi->controller_state) { 126 status = ath79_spi_setup_cs(spi); 127 if (status) 128 return status; 129 } 130 131 status = spi_bitbang_setup(spi); 132 133 return status; 134 } 135 136 static void ath79_spi_cleanup(struct spi_device *spi) 137 { 138 spi_bitbang_cleanup(spi); 139 } 140 141 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs, 142 u32 word, u8 bits, unsigned flags) 143 { 144 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 145 u32 ioc = sp->ioc_base; 146 147 /* clock starts at inactive polarity */ 148 for (word <<= (32 - bits); likely(bits); bits--) { 149 u32 out; 150 151 if (word & (1 << 31)) 152 out = ioc | AR71XX_SPI_IOC_DO; 153 else 154 out = ioc & ~AR71XX_SPI_IOC_DO; 155 156 /* setup MSB (to slave) on trailing edge */ 157 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); 158 ath79_spi_delay(sp, nsecs); 159 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); 160 ath79_spi_delay(sp, nsecs); 161 if (bits == 1) 162 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); 163 164 word <<= 1; 165 } 166 167 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); 168 } 169 170 static int ath79_spi_probe(struct platform_device *pdev) 171 { 172 struct spi_master *master; 173 struct ath79_spi *sp; 174 struct ath79_spi_platform_data *pdata; 175 struct resource *r; 176 unsigned long rate; 177 int ret; 178 179 master = spi_alloc_master(&pdev->dev, sizeof(*sp)); 180 if (master == NULL) { 181 dev_err(&pdev->dev, "failed to allocate spi master\n"); 182 return -ENOMEM; 183 } 184 185 sp = spi_master_get_devdata(master); 186 master->dev.of_node = pdev->dev.of_node; 187 platform_set_drvdata(pdev, sp); 188 189 pdata = dev_get_platdata(&pdev->dev); 190 191 master->use_gpio_descriptors = true; 192 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); 193 master->setup = ath79_spi_setup; 194 master->cleanup = ath79_spi_cleanup; 195 if (pdata) { 196 master->bus_num = pdata->bus_num; 197 master->num_chipselect = pdata->num_chipselect; 198 } 199 200 sp->bitbang.master = master; 201 sp->bitbang.chipselect = ath79_spi_chipselect; 202 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; 203 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; 204 sp->bitbang.flags = SPI_CS_HIGH; 205 206 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 207 sp->base = devm_ioremap_resource(&pdev->dev, r); 208 if (IS_ERR(sp->base)) { 209 ret = PTR_ERR(sp->base); 210 goto err_put_master; 211 } 212 213 sp->clk = devm_clk_get(&pdev->dev, "ahb"); 214 if (IS_ERR(sp->clk)) { 215 ret = PTR_ERR(sp->clk); 216 goto err_put_master; 217 } 218 219 ret = clk_prepare_enable(sp->clk); 220 if (ret) 221 goto err_put_master; 222 223 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); 224 if (!rate) { 225 ret = -EINVAL; 226 goto err_clk_disable; 227 } 228 229 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; 230 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", 231 sp->rrw_delay); 232 233 ath79_spi_enable(sp); 234 ret = spi_bitbang_start(&sp->bitbang); 235 if (ret) 236 goto err_disable; 237 238 return 0; 239 240 err_disable: 241 ath79_spi_disable(sp); 242 err_clk_disable: 243 clk_disable_unprepare(sp->clk); 244 err_put_master: 245 spi_master_put(sp->bitbang.master); 246 247 return ret; 248 } 249 250 static int ath79_spi_remove(struct platform_device *pdev) 251 { 252 struct ath79_spi *sp = platform_get_drvdata(pdev); 253 254 spi_bitbang_stop(&sp->bitbang); 255 ath79_spi_disable(sp); 256 clk_disable_unprepare(sp->clk); 257 spi_master_put(sp->bitbang.master); 258 259 return 0; 260 } 261 262 static void ath79_spi_shutdown(struct platform_device *pdev) 263 { 264 ath79_spi_remove(pdev); 265 } 266 267 static const struct of_device_id ath79_spi_of_match[] = { 268 { .compatible = "qca,ar7100-spi", }, 269 { }, 270 }; 271 MODULE_DEVICE_TABLE(of, ath79_spi_of_match); 272 273 static struct platform_driver ath79_spi_driver = { 274 .probe = ath79_spi_probe, 275 .remove = ath79_spi_remove, 276 .shutdown = ath79_spi_shutdown, 277 .driver = { 278 .name = DRV_NAME, 279 .of_match_table = ath79_spi_of_match, 280 }, 281 }; 282 module_platform_driver(ath79_spi_driver); 283 284 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X"); 285 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); 286 MODULE_LICENSE("GPL v2"); 287 MODULE_ALIAS("platform:" DRV_NAME); 288