1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Marvell Armada-3700 SPI controller driver 4 * 5 * Copyright (C) 2016 Marvell Ltd. 6 * 7 * Author: Wilson Ding <dingwei@marvell.com> 8 * Author: Romain Perier <romain.perier@free-electrons.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_device.h> 22 #include <linux/pinctrl/consumer.h> 23 #include <linux/spi/spi.h> 24 25 #define DRIVER_NAME "armada_3700_spi" 26 27 #define A3700_SPI_MAX_SPEED_HZ 100000000 28 #define A3700_SPI_MAX_PRESCALE 30 29 #define A3700_SPI_TIMEOUT 10 30 31 /* SPI Register Offest */ 32 #define A3700_SPI_IF_CTRL_REG 0x00 33 #define A3700_SPI_IF_CFG_REG 0x04 34 #define A3700_SPI_DATA_OUT_REG 0x08 35 #define A3700_SPI_DATA_IN_REG 0x0C 36 #define A3700_SPI_IF_INST_REG 0x10 37 #define A3700_SPI_IF_ADDR_REG 0x14 38 #define A3700_SPI_IF_RMODE_REG 0x18 39 #define A3700_SPI_IF_HDR_CNT_REG 0x1C 40 #define A3700_SPI_IF_DIN_CNT_REG 0x20 41 #define A3700_SPI_IF_TIME_REG 0x24 42 #define A3700_SPI_INT_STAT_REG 0x28 43 #define A3700_SPI_INT_MASK_REG 0x2C 44 45 /* A3700_SPI_IF_CTRL_REG */ 46 #define A3700_SPI_EN BIT(16) 47 #define A3700_SPI_ADDR_NOT_CONFIG BIT(12) 48 #define A3700_SPI_WFIFO_OVERFLOW BIT(11) 49 #define A3700_SPI_WFIFO_UNDERFLOW BIT(10) 50 #define A3700_SPI_RFIFO_OVERFLOW BIT(9) 51 #define A3700_SPI_RFIFO_UNDERFLOW BIT(8) 52 #define A3700_SPI_WFIFO_FULL BIT(7) 53 #define A3700_SPI_WFIFO_EMPTY BIT(6) 54 #define A3700_SPI_RFIFO_FULL BIT(5) 55 #define A3700_SPI_RFIFO_EMPTY BIT(4) 56 #define A3700_SPI_WFIFO_RDY BIT(3) 57 #define A3700_SPI_RFIFO_RDY BIT(2) 58 #define A3700_SPI_XFER_RDY BIT(1) 59 #define A3700_SPI_XFER_DONE BIT(0) 60 61 /* A3700_SPI_IF_CFG_REG */ 62 #define A3700_SPI_WFIFO_THRS BIT(28) 63 #define A3700_SPI_RFIFO_THRS BIT(24) 64 #define A3700_SPI_AUTO_CS BIT(20) 65 #define A3700_SPI_DMA_RD_EN BIT(18) 66 #define A3700_SPI_FIFO_MODE BIT(17) 67 #define A3700_SPI_SRST BIT(16) 68 #define A3700_SPI_XFER_START BIT(15) 69 #define A3700_SPI_XFER_STOP BIT(14) 70 #define A3700_SPI_INST_PIN BIT(13) 71 #define A3700_SPI_ADDR_PIN BIT(12) 72 #define A3700_SPI_DATA_PIN1 BIT(11) 73 #define A3700_SPI_DATA_PIN0 BIT(10) 74 #define A3700_SPI_FIFO_FLUSH BIT(9) 75 #define A3700_SPI_RW_EN BIT(8) 76 #define A3700_SPI_CLK_POL BIT(7) 77 #define A3700_SPI_CLK_PHA BIT(6) 78 #define A3700_SPI_BYTE_LEN BIT(5) 79 #define A3700_SPI_CLK_PRESCALE BIT(0) 80 #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) 81 #define A3700_SPI_CLK_EVEN_OFFS (0x10) 82 83 #define A3700_SPI_WFIFO_THRS_BIT 28 84 #define A3700_SPI_RFIFO_THRS_BIT 24 85 #define A3700_SPI_FIFO_THRS_MASK 0x7 86 87 #define A3700_SPI_DATA_PIN_MASK 0x3 88 89 /* A3700_SPI_IF_HDR_CNT_REG */ 90 #define A3700_SPI_DUMMY_CNT_BIT 12 91 #define A3700_SPI_DUMMY_CNT_MASK 0x7 92 #define A3700_SPI_RMODE_CNT_BIT 8 93 #define A3700_SPI_RMODE_CNT_MASK 0x3 94 #define A3700_SPI_ADDR_CNT_BIT 4 95 #define A3700_SPI_ADDR_CNT_MASK 0x7 96 #define A3700_SPI_INSTR_CNT_BIT 0 97 #define A3700_SPI_INSTR_CNT_MASK 0x3 98 99 /* A3700_SPI_IF_TIME_REG */ 100 #define A3700_SPI_CLK_CAPT_EDGE BIT(7) 101 102 struct a3700_spi { 103 struct spi_master *master; 104 void __iomem *base; 105 struct clk *clk; 106 unsigned int irq; 107 unsigned int flags; 108 bool xmit_data; 109 const u8 *tx_buf; 110 u8 *rx_buf; 111 size_t buf_len; 112 u8 byte_len; 113 u32 wait_mask; 114 struct completion done; 115 }; 116 117 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) 118 { 119 return readl(a3700_spi->base + offset); 120 } 121 122 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) 123 { 124 writel(data, a3700_spi->base + offset); 125 } 126 127 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) 128 { 129 u32 val; 130 131 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 132 val &= ~A3700_SPI_AUTO_CS; 133 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 134 } 135 136 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) 137 { 138 u32 val; 139 140 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 141 val |= (A3700_SPI_EN << cs); 142 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 143 } 144 145 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, 146 unsigned int cs) 147 { 148 u32 val; 149 150 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 151 val &= ~(A3700_SPI_EN << cs); 152 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 153 } 154 155 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, 156 unsigned int pin_mode, bool receiving) 157 { 158 u32 val; 159 160 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 161 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); 162 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); 163 164 switch (pin_mode) { 165 case SPI_NBITS_SINGLE: 166 break; 167 case SPI_NBITS_DUAL: 168 val |= A3700_SPI_DATA_PIN0; 169 break; 170 case SPI_NBITS_QUAD: 171 val |= A3700_SPI_DATA_PIN1; 172 /* RX during address reception uses 4-pin */ 173 if (receiving) 174 val |= A3700_SPI_ADDR_PIN; 175 break; 176 default: 177 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); 178 return -EINVAL; 179 } 180 181 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 182 183 return 0; 184 } 185 186 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable) 187 { 188 u32 val; 189 190 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 191 if (enable) 192 val |= A3700_SPI_FIFO_MODE; 193 else 194 val &= ~A3700_SPI_FIFO_MODE; 195 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 196 } 197 198 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, 199 unsigned int mode_bits) 200 { 201 u32 val; 202 203 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 204 205 if (mode_bits & SPI_CPOL) 206 val |= A3700_SPI_CLK_POL; 207 else 208 val &= ~A3700_SPI_CLK_POL; 209 210 if (mode_bits & SPI_CPHA) 211 val |= A3700_SPI_CLK_PHA; 212 else 213 val &= ~A3700_SPI_CLK_PHA; 214 215 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 216 } 217 218 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, 219 unsigned int speed_hz) 220 { 221 u32 val; 222 u32 prescale; 223 224 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); 225 226 /* For prescaler values over 15, we can only set it by steps of 2. 227 * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to 228 * 30. We only use this range from 16 to 30. 229 */ 230 if (prescale > 15) 231 prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2); 232 233 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 234 val = val & ~A3700_SPI_CLK_PRESCALE_MASK; 235 236 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); 237 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 238 239 if (prescale <= 2) { 240 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); 241 val |= A3700_SPI_CLK_CAPT_EDGE; 242 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); 243 } 244 } 245 246 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) 247 { 248 u32 val; 249 250 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 251 if (len == 4) 252 val |= A3700_SPI_BYTE_LEN; 253 else 254 val &= ~A3700_SPI_BYTE_LEN; 255 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 256 257 a3700_spi->byte_len = len; 258 } 259 260 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) 261 { 262 int timeout = A3700_SPI_TIMEOUT; 263 u32 val; 264 265 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 266 val |= A3700_SPI_FIFO_FLUSH; 267 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 268 269 while (--timeout) { 270 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 271 if (!(val & A3700_SPI_FIFO_FLUSH)) 272 return 0; 273 udelay(1); 274 } 275 276 return -ETIMEDOUT; 277 } 278 279 static void a3700_spi_init(struct a3700_spi *a3700_spi) 280 { 281 struct spi_master *master = a3700_spi->master; 282 u32 val; 283 int i; 284 285 /* Reset SPI unit */ 286 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 287 val |= A3700_SPI_SRST; 288 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 289 290 udelay(A3700_SPI_TIMEOUT); 291 292 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 293 val &= ~A3700_SPI_SRST; 294 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 295 296 /* Disable AUTO_CS and deactivate all chip-selects */ 297 a3700_spi_auto_cs_unset(a3700_spi); 298 for (i = 0; i < master->num_chipselect; i++) 299 a3700_spi_deactivate_cs(a3700_spi, i); 300 301 /* Enable FIFO mode */ 302 a3700_spi_fifo_mode_set(a3700_spi, true); 303 304 /* Set SPI mode */ 305 a3700_spi_mode_set(a3700_spi, master->mode_bits); 306 307 /* Reset counters */ 308 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 309 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); 310 311 /* Mask the interrupts and clear cause bits */ 312 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 313 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); 314 } 315 316 static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) 317 { 318 struct spi_master *master = dev_id; 319 struct a3700_spi *a3700_spi; 320 u32 cause; 321 322 a3700_spi = spi_master_get_devdata(master); 323 324 /* Get interrupt causes */ 325 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); 326 327 if (!cause || !(a3700_spi->wait_mask & cause)) 328 return IRQ_NONE; 329 330 /* mask and acknowledge the SPI interrupts */ 331 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 332 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); 333 334 /* Wake up the transfer */ 335 complete(&a3700_spi->done); 336 337 return IRQ_HANDLED; 338 } 339 340 static bool a3700_spi_wait_completion(struct spi_device *spi) 341 { 342 struct a3700_spi *a3700_spi; 343 unsigned int timeout; 344 unsigned int ctrl_reg; 345 unsigned long timeout_jiffies; 346 347 a3700_spi = spi_master_get_devdata(spi->master); 348 349 /* SPI interrupt is edge-triggered, which means an interrupt will 350 * be generated only when detecting a specific status bit changed 351 * from '0' to '1'. So when we start waiting for a interrupt, we 352 * need to check status bit in control reg first, if it is already 1, 353 * then we do not need to wait for interrupt 354 */ 355 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 356 if (a3700_spi->wait_mask & ctrl_reg) 357 return true; 358 359 reinit_completion(&a3700_spi->done); 360 361 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 362 a3700_spi->wait_mask); 363 364 timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); 365 timeout = wait_for_completion_timeout(&a3700_spi->done, 366 timeout_jiffies); 367 368 a3700_spi->wait_mask = 0; 369 370 if (timeout) 371 return true; 372 373 /* there might be the case that right after we checked the 374 * status bits in this routine and before start to wait for 375 * interrupt by wait_for_completion_timeout, the interrupt 376 * happens, to avoid missing it we need to double check 377 * status bits in control reg, if it is already 1, then 378 * consider that we have the interrupt successfully and 379 * return true. 380 */ 381 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 382 if (a3700_spi->wait_mask & ctrl_reg) 383 return true; 384 385 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 386 387 /* Timeout was reached */ 388 return false; 389 } 390 391 static bool a3700_spi_transfer_wait(struct spi_device *spi, 392 unsigned int bit_mask) 393 { 394 struct a3700_spi *a3700_spi; 395 396 a3700_spi = spi_master_get_devdata(spi->master); 397 a3700_spi->wait_mask = bit_mask; 398 399 return a3700_spi_wait_completion(spi); 400 } 401 402 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, 403 unsigned int bytes) 404 { 405 u32 val; 406 407 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 408 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); 409 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; 410 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); 411 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; 412 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 413 } 414 415 static void a3700_spi_transfer_setup(struct spi_device *spi, 416 struct spi_transfer *xfer) 417 { 418 struct a3700_spi *a3700_spi; 419 420 a3700_spi = spi_master_get_devdata(spi->master); 421 422 a3700_spi_clock_set(a3700_spi, xfer->speed_hz); 423 424 /* Use 4 bytes long transfers. Each transfer method has its way to deal 425 * with the remaining bytes for non 4-bytes aligned transfers. 426 */ 427 a3700_spi_bytelen_set(a3700_spi, 4); 428 429 /* Initialize the working buffers */ 430 a3700_spi->tx_buf = xfer->tx_buf; 431 a3700_spi->rx_buf = xfer->rx_buf; 432 a3700_spi->buf_len = xfer->len; 433 } 434 435 static void a3700_spi_set_cs(struct spi_device *spi, bool enable) 436 { 437 struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); 438 439 if (!enable) 440 a3700_spi_activate_cs(a3700_spi, spi->chip_select); 441 else 442 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); 443 } 444 445 static void a3700_spi_header_set(struct a3700_spi *a3700_spi) 446 { 447 unsigned int addr_cnt; 448 u32 val = 0; 449 450 /* Clear the header registers */ 451 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); 452 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); 453 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); 454 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 455 456 /* Set header counters */ 457 if (a3700_spi->tx_buf) { 458 /* 459 * when tx data is not 4 bytes aligned, there will be unexpected 460 * bytes out of SPI output register, since it always shifts out 461 * as whole 4 bytes. This might cause incorrect transaction with 462 * some devices. To avoid that, use SPI header count feature to 463 * transfer up to 3 bytes of data first, and then make the rest 464 * of data 4-byte aligned. 465 */ 466 addr_cnt = a3700_spi->buf_len % 4; 467 if (addr_cnt) { 468 val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) 469 << A3700_SPI_ADDR_CNT_BIT; 470 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); 471 472 /* Update the buffer length to be transferred */ 473 a3700_spi->buf_len -= addr_cnt; 474 475 /* transfer 1~3 bytes through address count */ 476 val = 0; 477 while (addr_cnt--) { 478 val = (val << 8) | a3700_spi->tx_buf[0]; 479 a3700_spi->tx_buf++; 480 } 481 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); 482 } 483 } 484 } 485 486 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) 487 { 488 u32 val; 489 490 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 491 return (val & A3700_SPI_WFIFO_FULL); 492 } 493 494 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) 495 { 496 u32 val; 497 498 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { 499 val = *(u32 *)a3700_spi->tx_buf; 500 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); 501 a3700_spi->buf_len -= 4; 502 a3700_spi->tx_buf += 4; 503 } 504 505 return 0; 506 } 507 508 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) 509 { 510 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 511 512 return (val & A3700_SPI_RFIFO_EMPTY); 513 } 514 515 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) 516 { 517 u32 val; 518 519 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { 520 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); 521 if (a3700_spi->buf_len >= 4) { 522 523 memcpy(a3700_spi->rx_buf, &val, 4); 524 525 a3700_spi->buf_len -= 4; 526 a3700_spi->rx_buf += 4; 527 } else { 528 /* 529 * When remain bytes is not larger than 4, we should 530 * avoid memory overwriting and just write the left rx 531 * buffer bytes. 532 */ 533 while (a3700_spi->buf_len) { 534 *a3700_spi->rx_buf = val & 0xff; 535 val >>= 8; 536 537 a3700_spi->buf_len--; 538 a3700_spi->rx_buf++; 539 } 540 } 541 } 542 543 return 0; 544 } 545 546 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) 547 { 548 int timeout = A3700_SPI_TIMEOUT; 549 u32 val; 550 551 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 552 val |= A3700_SPI_XFER_STOP; 553 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 554 555 while (--timeout) { 556 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 557 if (!(val & A3700_SPI_XFER_START)) 558 break; 559 udelay(1); 560 } 561 562 a3700_spi_fifo_flush(a3700_spi); 563 564 val &= ~A3700_SPI_XFER_STOP; 565 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 566 } 567 568 static int a3700_spi_prepare_message(struct spi_master *master, 569 struct spi_message *message) 570 { 571 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 572 struct spi_device *spi = message->spi; 573 int ret; 574 575 ret = clk_enable(a3700_spi->clk); 576 if (ret) { 577 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); 578 return ret; 579 } 580 581 /* Flush the FIFOs */ 582 ret = a3700_spi_fifo_flush(a3700_spi); 583 if (ret) 584 return ret; 585 586 a3700_spi_mode_set(a3700_spi, spi->mode); 587 588 return 0; 589 } 590 591 static int a3700_spi_transfer_one_fifo(struct spi_master *master, 592 struct spi_device *spi, 593 struct spi_transfer *xfer) 594 { 595 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 596 int ret = 0, timeout = A3700_SPI_TIMEOUT; 597 unsigned int nbits = 0, byte_len; 598 u32 val; 599 600 /* Make sure we use FIFO mode */ 601 a3700_spi_fifo_mode_set(a3700_spi, true); 602 603 /* Configure FIFO thresholds */ 604 byte_len = xfer->bits_per_word >> 3; 605 a3700_spi_fifo_thres_set(a3700_spi, byte_len); 606 607 if (xfer->tx_buf) 608 nbits = xfer->tx_nbits; 609 else if (xfer->rx_buf) 610 nbits = xfer->rx_nbits; 611 612 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); 613 614 /* Flush the FIFOs */ 615 a3700_spi_fifo_flush(a3700_spi); 616 617 /* Transfer first bytes of data when buffer is not 4-byte aligned */ 618 a3700_spi_header_set(a3700_spi); 619 620 if (xfer->rx_buf) { 621 /* Clear WFIFO, since it's last 2 bytes are shifted out during 622 * a read operation 623 */ 624 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0); 625 626 /* Set read data length */ 627 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 628 a3700_spi->buf_len); 629 /* Start READ transfer */ 630 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 631 val &= ~A3700_SPI_RW_EN; 632 val |= A3700_SPI_XFER_START; 633 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 634 } else if (xfer->tx_buf) { 635 /* Start Write transfer */ 636 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 637 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); 638 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 639 640 /* 641 * If there are data to be written to the SPI device, xmit_data 642 * flag is set true; otherwise the instruction in SPI_INSTR does 643 * not require data to be written to the SPI device, then 644 * xmit_data flag is set false. 645 */ 646 a3700_spi->xmit_data = (a3700_spi->buf_len != 0); 647 } 648 649 while (a3700_spi->buf_len) { 650 if (a3700_spi->tx_buf) { 651 /* Wait wfifo ready */ 652 if (!a3700_spi_transfer_wait(spi, 653 A3700_SPI_WFIFO_RDY)) { 654 dev_err(&spi->dev, 655 "wait wfifo ready timed out\n"); 656 ret = -ETIMEDOUT; 657 goto error; 658 } 659 /* Fill up the wfifo */ 660 ret = a3700_spi_fifo_write(a3700_spi); 661 if (ret) 662 goto error; 663 } else if (a3700_spi->rx_buf) { 664 /* Wait rfifo ready */ 665 if (!a3700_spi_transfer_wait(spi, 666 A3700_SPI_RFIFO_RDY)) { 667 dev_err(&spi->dev, 668 "wait rfifo ready timed out\n"); 669 ret = -ETIMEDOUT; 670 goto error; 671 } 672 /* Drain out the rfifo */ 673 ret = a3700_spi_fifo_read(a3700_spi); 674 if (ret) 675 goto error; 676 } 677 } 678 679 /* 680 * Stop a write transfer in fifo mode: 681 * - wait all the bytes in wfifo to be shifted out 682 * - set XFER_STOP bit 683 * - wait XFER_START bit clear 684 * - clear XFER_STOP bit 685 * Stop a read transfer in fifo mode: 686 * - the hardware is to reset the XFER_START bit 687 * after the number of bytes indicated in DIN_CNT 688 * register 689 * - just wait XFER_START bit clear 690 */ 691 if (a3700_spi->tx_buf) { 692 if (a3700_spi->xmit_data) { 693 /* 694 * If there are data written to the SPI device, wait 695 * until SPI_WFIFO_EMPTY is 1 to wait for all data to 696 * transfer out of write FIFO. 697 */ 698 if (!a3700_spi_transfer_wait(spi, 699 A3700_SPI_WFIFO_EMPTY)) { 700 dev_err(&spi->dev, "wait wfifo empty timed out\n"); 701 return -ETIMEDOUT; 702 } 703 } 704 705 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { 706 dev_err(&spi->dev, "wait xfer ready timed out\n"); 707 return -ETIMEDOUT; 708 } 709 710 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 711 val |= A3700_SPI_XFER_STOP; 712 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 713 } 714 715 while (--timeout) { 716 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 717 if (!(val & A3700_SPI_XFER_START)) 718 break; 719 udelay(1); 720 } 721 722 if (timeout == 0) { 723 dev_err(&spi->dev, "wait transfer start clear timed out\n"); 724 ret = -ETIMEDOUT; 725 goto error; 726 } 727 728 val &= ~A3700_SPI_XFER_STOP; 729 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 730 goto out; 731 732 error: 733 a3700_spi_transfer_abort_fifo(a3700_spi); 734 out: 735 spi_finalize_current_transfer(master); 736 737 return ret; 738 } 739 740 static int a3700_spi_transfer_one_full_duplex(struct spi_master *master, 741 struct spi_device *spi, 742 struct spi_transfer *xfer) 743 { 744 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 745 u32 val; 746 747 /* Disable FIFO mode */ 748 a3700_spi_fifo_mode_set(a3700_spi, false); 749 750 while (a3700_spi->buf_len) { 751 752 /* When we have less than 4 bytes to transfer, switch to 1 byte 753 * mode. This is reset after each transfer 754 */ 755 if (a3700_spi->buf_len < 4) 756 a3700_spi_bytelen_set(a3700_spi, 1); 757 758 if (a3700_spi->byte_len == 1) 759 val = *a3700_spi->tx_buf; 760 else 761 val = *(u32 *)a3700_spi->tx_buf; 762 763 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); 764 765 /* Wait for all the data to be shifted in / out */ 766 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) & 767 A3700_SPI_XFER_DONE)) 768 cpu_relax(); 769 770 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); 771 772 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len); 773 774 a3700_spi->buf_len -= a3700_spi->byte_len; 775 a3700_spi->tx_buf += a3700_spi->byte_len; 776 a3700_spi->rx_buf += a3700_spi->byte_len; 777 778 } 779 780 spi_finalize_current_transfer(master); 781 782 return 0; 783 } 784 785 static int a3700_spi_transfer_one(struct spi_master *master, 786 struct spi_device *spi, 787 struct spi_transfer *xfer) 788 { 789 a3700_spi_transfer_setup(spi, xfer); 790 791 if (xfer->tx_buf && xfer->rx_buf) 792 return a3700_spi_transfer_one_full_duplex(master, spi, xfer); 793 794 return a3700_spi_transfer_one_fifo(master, spi, xfer); 795 } 796 797 static int a3700_spi_unprepare_message(struct spi_master *master, 798 struct spi_message *message) 799 { 800 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 801 802 clk_disable(a3700_spi->clk); 803 804 return 0; 805 } 806 807 static const struct of_device_id a3700_spi_dt_ids[] = { 808 { .compatible = "marvell,armada-3700-spi", .data = NULL }, 809 {}, 810 }; 811 812 MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); 813 814 static int a3700_spi_probe(struct platform_device *pdev) 815 { 816 struct device *dev = &pdev->dev; 817 struct device_node *of_node = dev->of_node; 818 struct spi_master *master; 819 struct a3700_spi *spi; 820 u32 num_cs = 0; 821 int irq, ret = 0; 822 823 master = spi_alloc_master(dev, sizeof(*spi)); 824 if (!master) { 825 dev_err(dev, "master allocation failed\n"); 826 ret = -ENOMEM; 827 goto out; 828 } 829 830 if (of_property_read_u32(of_node, "num-cs", &num_cs)) { 831 dev_err(dev, "could not find num-cs\n"); 832 ret = -ENXIO; 833 goto error; 834 } 835 836 master->bus_num = pdev->id; 837 master->dev.of_node = of_node; 838 master->mode_bits = SPI_MODE_3; 839 master->num_chipselect = num_cs; 840 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); 841 master->prepare_message = a3700_spi_prepare_message; 842 master->transfer_one = a3700_spi_transfer_one; 843 master->unprepare_message = a3700_spi_unprepare_message; 844 master->set_cs = a3700_spi_set_cs; 845 master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL | 846 SPI_RX_QUAD | SPI_TX_QUAD); 847 848 platform_set_drvdata(pdev, master); 849 850 spi = spi_master_get_devdata(master); 851 852 spi->master = master; 853 854 spi->base = devm_platform_ioremap_resource(pdev, 0); 855 if (IS_ERR(spi->base)) { 856 ret = PTR_ERR(spi->base); 857 goto error; 858 } 859 860 irq = platform_get_irq(pdev, 0); 861 if (irq < 0) { 862 ret = -ENXIO; 863 goto error; 864 } 865 spi->irq = irq; 866 867 init_completion(&spi->done); 868 869 spi->clk = devm_clk_get(dev, NULL); 870 if (IS_ERR(spi->clk)) { 871 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); 872 goto error; 873 } 874 875 ret = clk_prepare(spi->clk); 876 if (ret) { 877 dev_err(dev, "could not prepare clk: %d\n", ret); 878 goto error; 879 } 880 881 master->max_speed_hz = min_t(unsigned long, A3700_SPI_MAX_SPEED_HZ, 882 clk_get_rate(spi->clk)); 883 master->min_speed_hz = DIV_ROUND_UP(clk_get_rate(spi->clk), 884 A3700_SPI_MAX_PRESCALE); 885 886 a3700_spi_init(spi); 887 888 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, 889 dev_name(dev), master); 890 if (ret) { 891 dev_err(dev, "could not request IRQ: %d\n", ret); 892 goto error_clk; 893 } 894 895 ret = devm_spi_register_master(dev, master); 896 if (ret) { 897 dev_err(dev, "Failed to register master\n"); 898 goto error_clk; 899 } 900 901 return 0; 902 903 error_clk: 904 clk_unprepare(spi->clk); 905 error: 906 spi_master_put(master); 907 out: 908 return ret; 909 } 910 911 static int a3700_spi_remove(struct platform_device *pdev) 912 { 913 struct spi_master *master = platform_get_drvdata(pdev); 914 struct a3700_spi *spi = spi_master_get_devdata(master); 915 916 clk_unprepare(spi->clk); 917 918 return 0; 919 } 920 921 static struct platform_driver a3700_spi_driver = { 922 .driver = { 923 .name = DRIVER_NAME, 924 .of_match_table = of_match_ptr(a3700_spi_dt_ids), 925 }, 926 .probe = a3700_spi_probe, 927 .remove = a3700_spi_remove, 928 }; 929 930 module_platform_driver(a3700_spi_driver); 931 932 MODULE_DESCRIPTION("Armada-3700 SPI driver"); 933 MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); 934 MODULE_LICENSE("GPL"); 935 MODULE_ALIAS("platform:" DRIVER_NAME); 936