1 /* 2 * Marvell Armada-3700 SPI controller driver 3 * 4 * Copyright (C) 2016 Marvell Ltd. 5 * 6 * Author: Wilson Ding <dingwei@marvell.com> 7 * Author: Romain Perier <romain.perier@free-electrons.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/completion.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/spi/spi.h> 27 28 #define DRIVER_NAME "armada_3700_spi" 29 30 #define A3700_SPI_TIMEOUT 10 31 32 /* SPI Register Offest */ 33 #define A3700_SPI_IF_CTRL_REG 0x00 34 #define A3700_SPI_IF_CFG_REG 0x04 35 #define A3700_SPI_DATA_OUT_REG 0x08 36 #define A3700_SPI_DATA_IN_REG 0x0C 37 #define A3700_SPI_IF_INST_REG 0x10 38 #define A3700_SPI_IF_ADDR_REG 0x14 39 #define A3700_SPI_IF_RMODE_REG 0x18 40 #define A3700_SPI_IF_HDR_CNT_REG 0x1C 41 #define A3700_SPI_IF_DIN_CNT_REG 0x20 42 #define A3700_SPI_IF_TIME_REG 0x24 43 #define A3700_SPI_INT_STAT_REG 0x28 44 #define A3700_SPI_INT_MASK_REG 0x2C 45 46 /* A3700_SPI_IF_CTRL_REG */ 47 #define A3700_SPI_EN BIT(16) 48 #define A3700_SPI_ADDR_NOT_CONFIG BIT(12) 49 #define A3700_SPI_WFIFO_OVERFLOW BIT(11) 50 #define A3700_SPI_WFIFO_UNDERFLOW BIT(10) 51 #define A3700_SPI_RFIFO_OVERFLOW BIT(9) 52 #define A3700_SPI_RFIFO_UNDERFLOW BIT(8) 53 #define A3700_SPI_WFIFO_FULL BIT(7) 54 #define A3700_SPI_WFIFO_EMPTY BIT(6) 55 #define A3700_SPI_RFIFO_FULL BIT(5) 56 #define A3700_SPI_RFIFO_EMPTY BIT(4) 57 #define A3700_SPI_WFIFO_RDY BIT(3) 58 #define A3700_SPI_RFIFO_RDY BIT(2) 59 #define A3700_SPI_XFER_RDY BIT(1) 60 #define A3700_SPI_XFER_DONE BIT(0) 61 62 /* A3700_SPI_IF_CFG_REG */ 63 #define A3700_SPI_WFIFO_THRS BIT(28) 64 #define A3700_SPI_RFIFO_THRS BIT(24) 65 #define A3700_SPI_AUTO_CS BIT(20) 66 #define A3700_SPI_DMA_RD_EN BIT(18) 67 #define A3700_SPI_FIFO_MODE BIT(17) 68 #define A3700_SPI_SRST BIT(16) 69 #define A3700_SPI_XFER_START BIT(15) 70 #define A3700_SPI_XFER_STOP BIT(14) 71 #define A3700_SPI_INST_PIN BIT(13) 72 #define A3700_SPI_ADDR_PIN BIT(12) 73 #define A3700_SPI_DATA_PIN1 BIT(11) 74 #define A3700_SPI_DATA_PIN0 BIT(10) 75 #define A3700_SPI_FIFO_FLUSH BIT(9) 76 #define A3700_SPI_RW_EN BIT(8) 77 #define A3700_SPI_CLK_POL BIT(7) 78 #define A3700_SPI_CLK_PHA BIT(6) 79 #define A3700_SPI_BYTE_LEN BIT(5) 80 #define A3700_SPI_CLK_PRESCALE BIT(0) 81 #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) 82 #define A3700_SPI_CLK_EVEN_OFFS (0x10) 83 84 #define A3700_SPI_WFIFO_THRS_BIT 28 85 #define A3700_SPI_RFIFO_THRS_BIT 24 86 #define A3700_SPI_FIFO_THRS_MASK 0x7 87 88 #define A3700_SPI_DATA_PIN_MASK 0x3 89 90 /* A3700_SPI_IF_HDR_CNT_REG */ 91 #define A3700_SPI_DUMMY_CNT_BIT 12 92 #define A3700_SPI_DUMMY_CNT_MASK 0x7 93 #define A3700_SPI_RMODE_CNT_BIT 8 94 #define A3700_SPI_RMODE_CNT_MASK 0x3 95 #define A3700_SPI_ADDR_CNT_BIT 4 96 #define A3700_SPI_ADDR_CNT_MASK 0x7 97 #define A3700_SPI_INSTR_CNT_BIT 0 98 #define A3700_SPI_INSTR_CNT_MASK 0x3 99 100 /* A3700_SPI_IF_TIME_REG */ 101 #define A3700_SPI_CLK_CAPT_EDGE BIT(7) 102 103 struct a3700_spi { 104 struct spi_master *master; 105 void __iomem *base; 106 struct clk *clk; 107 unsigned int irq; 108 unsigned int flags; 109 bool xmit_data; 110 const u8 *tx_buf; 111 u8 *rx_buf; 112 size_t buf_len; 113 u8 byte_len; 114 u32 wait_mask; 115 struct completion done; 116 }; 117 118 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) 119 { 120 return readl(a3700_spi->base + offset); 121 } 122 123 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) 124 { 125 writel(data, a3700_spi->base + offset); 126 } 127 128 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) 129 { 130 u32 val; 131 132 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 133 val &= ~A3700_SPI_AUTO_CS; 134 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 135 } 136 137 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) 138 { 139 u32 val; 140 141 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 142 val |= (A3700_SPI_EN << cs); 143 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 144 } 145 146 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, 147 unsigned int cs) 148 { 149 u32 val; 150 151 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 152 val &= ~(A3700_SPI_EN << cs); 153 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 154 } 155 156 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, 157 unsigned int pin_mode, bool receiving) 158 { 159 u32 val; 160 161 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 162 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); 163 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); 164 165 switch (pin_mode) { 166 case SPI_NBITS_SINGLE: 167 break; 168 case SPI_NBITS_DUAL: 169 val |= A3700_SPI_DATA_PIN0; 170 break; 171 case SPI_NBITS_QUAD: 172 val |= A3700_SPI_DATA_PIN1; 173 /* RX during address reception uses 4-pin */ 174 if (receiving) 175 val |= A3700_SPI_ADDR_PIN; 176 break; 177 default: 178 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); 179 return -EINVAL; 180 } 181 182 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 183 184 return 0; 185 } 186 187 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi) 188 { 189 u32 val; 190 191 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 192 val |= A3700_SPI_FIFO_MODE; 193 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 194 } 195 196 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, 197 unsigned int mode_bits) 198 { 199 u32 val; 200 201 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 202 203 if (mode_bits & SPI_CPOL) 204 val |= A3700_SPI_CLK_POL; 205 else 206 val &= ~A3700_SPI_CLK_POL; 207 208 if (mode_bits & SPI_CPHA) 209 val |= A3700_SPI_CLK_PHA; 210 else 211 val &= ~A3700_SPI_CLK_PHA; 212 213 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 214 } 215 216 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, 217 unsigned int speed_hz) 218 { 219 u32 val; 220 u32 prescale; 221 222 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); 223 224 /* For prescaler values over 15, we can only set it by steps of 2. 225 * Starting from A3700_SPI_CLK_EVEN_OFFS, we set values from 0 up to 226 * 30. We only use this range from 16 to 30. 227 */ 228 if (prescale > 15) 229 prescale = A3700_SPI_CLK_EVEN_OFFS + DIV_ROUND_UP(prescale, 2); 230 231 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 232 val = val & ~A3700_SPI_CLK_PRESCALE_MASK; 233 234 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); 235 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 236 237 if (prescale <= 2) { 238 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); 239 val |= A3700_SPI_CLK_CAPT_EDGE; 240 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); 241 } 242 } 243 244 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) 245 { 246 u32 val; 247 248 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 249 if (len == 4) 250 val |= A3700_SPI_BYTE_LEN; 251 else 252 val &= ~A3700_SPI_BYTE_LEN; 253 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 254 255 a3700_spi->byte_len = len; 256 } 257 258 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) 259 { 260 int timeout = A3700_SPI_TIMEOUT; 261 u32 val; 262 263 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 264 val |= A3700_SPI_FIFO_FLUSH; 265 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 266 267 while (--timeout) { 268 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 269 if (!(val & A3700_SPI_FIFO_FLUSH)) 270 return 0; 271 udelay(1); 272 } 273 274 return -ETIMEDOUT; 275 } 276 277 static int a3700_spi_init(struct a3700_spi *a3700_spi) 278 { 279 struct spi_master *master = a3700_spi->master; 280 u32 val; 281 int i, ret = 0; 282 283 /* Reset SPI unit */ 284 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 285 val |= A3700_SPI_SRST; 286 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 287 288 udelay(A3700_SPI_TIMEOUT); 289 290 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 291 val &= ~A3700_SPI_SRST; 292 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 293 294 /* Disable AUTO_CS and deactivate all chip-selects */ 295 a3700_spi_auto_cs_unset(a3700_spi); 296 for (i = 0; i < master->num_chipselect; i++) 297 a3700_spi_deactivate_cs(a3700_spi, i); 298 299 /* Enable FIFO mode */ 300 a3700_spi_fifo_mode_set(a3700_spi); 301 302 /* Set SPI mode */ 303 a3700_spi_mode_set(a3700_spi, master->mode_bits); 304 305 /* Reset counters */ 306 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 307 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); 308 309 /* Mask the interrupts and clear cause bits */ 310 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 311 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); 312 313 return ret; 314 } 315 316 static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) 317 { 318 struct spi_master *master = dev_id; 319 struct a3700_spi *a3700_spi; 320 u32 cause; 321 322 a3700_spi = spi_master_get_devdata(master); 323 324 /* Get interrupt causes */ 325 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); 326 327 if (!cause || !(a3700_spi->wait_mask & cause)) 328 return IRQ_NONE; 329 330 /* mask and acknowledge the SPI interrupts */ 331 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 332 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); 333 334 /* Wake up the transfer */ 335 complete(&a3700_spi->done); 336 337 return IRQ_HANDLED; 338 } 339 340 static bool a3700_spi_wait_completion(struct spi_device *spi) 341 { 342 struct a3700_spi *a3700_spi; 343 unsigned int timeout; 344 unsigned int ctrl_reg; 345 unsigned long timeout_jiffies; 346 347 a3700_spi = spi_master_get_devdata(spi->master); 348 349 /* SPI interrupt is edge-triggered, which means an interrupt will 350 * be generated only when detecting a specific status bit changed 351 * from '0' to '1'. So when we start waiting for a interrupt, we 352 * need to check status bit in control reg first, if it is already 1, 353 * then we do not need to wait for interrupt 354 */ 355 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 356 if (a3700_spi->wait_mask & ctrl_reg) 357 return true; 358 359 reinit_completion(&a3700_spi->done); 360 361 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 362 a3700_spi->wait_mask); 363 364 timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); 365 timeout = wait_for_completion_timeout(&a3700_spi->done, 366 timeout_jiffies); 367 368 a3700_spi->wait_mask = 0; 369 370 if (timeout) 371 return true; 372 373 /* there might be the case that right after we checked the 374 * status bits in this routine and before start to wait for 375 * interrupt by wait_for_completion_timeout, the interrupt 376 * happens, to avoid missing it we need to double check 377 * status bits in control reg, if it is already 1, then 378 * consider that we have the interrupt successfully and 379 * return true. 380 */ 381 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 382 if (a3700_spi->wait_mask & ctrl_reg) 383 return true; 384 385 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 386 387 /* Timeout was reached */ 388 return false; 389 } 390 391 static bool a3700_spi_transfer_wait(struct spi_device *spi, 392 unsigned int bit_mask) 393 { 394 struct a3700_spi *a3700_spi; 395 396 a3700_spi = spi_master_get_devdata(spi->master); 397 a3700_spi->wait_mask = bit_mask; 398 399 return a3700_spi_wait_completion(spi); 400 } 401 402 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, 403 unsigned int bytes) 404 { 405 u32 val; 406 407 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 408 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); 409 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; 410 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); 411 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; 412 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 413 } 414 415 static void a3700_spi_transfer_setup(struct spi_device *spi, 416 struct spi_transfer *xfer) 417 { 418 struct a3700_spi *a3700_spi; 419 unsigned int byte_len; 420 421 a3700_spi = spi_master_get_devdata(spi->master); 422 423 a3700_spi_clock_set(a3700_spi, xfer->speed_hz); 424 425 byte_len = xfer->bits_per_word >> 3; 426 427 a3700_spi_fifo_thres_set(a3700_spi, byte_len); 428 } 429 430 static void a3700_spi_set_cs(struct spi_device *spi, bool enable) 431 { 432 struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); 433 434 if (!enable) 435 a3700_spi_activate_cs(a3700_spi, spi->chip_select); 436 else 437 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); 438 } 439 440 static void a3700_spi_header_set(struct a3700_spi *a3700_spi) 441 { 442 unsigned int addr_cnt; 443 u32 val = 0; 444 445 /* Clear the header registers */ 446 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); 447 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); 448 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); 449 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 450 451 /* Set header counters */ 452 if (a3700_spi->tx_buf) { 453 /* 454 * when tx data is not 4 bytes aligned, there will be unexpected 455 * bytes out of SPI output register, since it always shifts out 456 * as whole 4 bytes. This might cause incorrect transaction with 457 * some devices. To avoid that, use SPI header count feature to 458 * transfer up to 3 bytes of data first, and then make the rest 459 * of data 4-byte aligned. 460 */ 461 addr_cnt = a3700_spi->buf_len % 4; 462 if (addr_cnt) { 463 val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) 464 << A3700_SPI_ADDR_CNT_BIT; 465 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); 466 467 /* Update the buffer length to be transferred */ 468 a3700_spi->buf_len -= addr_cnt; 469 470 /* transfer 1~3 bytes through address count */ 471 val = 0; 472 while (addr_cnt--) { 473 val = (val << 8) | a3700_spi->tx_buf[0]; 474 a3700_spi->tx_buf++; 475 } 476 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); 477 } 478 } 479 } 480 481 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) 482 { 483 u32 val; 484 485 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 486 return (val & A3700_SPI_WFIFO_FULL); 487 } 488 489 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) 490 { 491 u32 val; 492 493 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { 494 val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf); 495 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); 496 a3700_spi->buf_len -= 4; 497 a3700_spi->tx_buf += 4; 498 } 499 500 return 0; 501 } 502 503 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) 504 { 505 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 506 507 return (val & A3700_SPI_RFIFO_EMPTY); 508 } 509 510 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) 511 { 512 u32 val; 513 514 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { 515 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); 516 if (a3700_spi->buf_len >= 4) { 517 u32 data = le32_to_cpu(val); 518 519 memcpy(a3700_spi->rx_buf, &data, 4); 520 521 a3700_spi->buf_len -= 4; 522 a3700_spi->rx_buf += 4; 523 } else { 524 /* 525 * When remain bytes is not larger than 4, we should 526 * avoid memory overwriting and just write the left rx 527 * buffer bytes. 528 */ 529 while (a3700_spi->buf_len) { 530 *a3700_spi->rx_buf = val & 0xff; 531 val >>= 8; 532 533 a3700_spi->buf_len--; 534 a3700_spi->rx_buf++; 535 } 536 } 537 } 538 539 return 0; 540 } 541 542 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) 543 { 544 int timeout = A3700_SPI_TIMEOUT; 545 u32 val; 546 547 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 548 val |= A3700_SPI_XFER_STOP; 549 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 550 551 while (--timeout) { 552 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 553 if (!(val & A3700_SPI_XFER_START)) 554 break; 555 udelay(1); 556 } 557 558 a3700_spi_fifo_flush(a3700_spi); 559 560 val &= ~A3700_SPI_XFER_STOP; 561 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 562 } 563 564 static int a3700_spi_prepare_message(struct spi_master *master, 565 struct spi_message *message) 566 { 567 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 568 struct spi_device *spi = message->spi; 569 int ret; 570 571 ret = clk_enable(a3700_spi->clk); 572 if (ret) { 573 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); 574 return ret; 575 } 576 577 /* Flush the FIFOs */ 578 ret = a3700_spi_fifo_flush(a3700_spi); 579 if (ret) 580 return ret; 581 582 a3700_spi_bytelen_set(a3700_spi, 4); 583 584 a3700_spi_mode_set(a3700_spi, spi->mode); 585 586 return 0; 587 } 588 589 static int a3700_spi_transfer_one(struct spi_master *master, 590 struct spi_device *spi, 591 struct spi_transfer *xfer) 592 { 593 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 594 int ret = 0, timeout = A3700_SPI_TIMEOUT; 595 unsigned int nbits = 0; 596 u32 val; 597 598 a3700_spi_transfer_setup(spi, xfer); 599 600 a3700_spi->tx_buf = xfer->tx_buf; 601 a3700_spi->rx_buf = xfer->rx_buf; 602 a3700_spi->buf_len = xfer->len; 603 604 if (xfer->tx_buf) 605 nbits = xfer->tx_nbits; 606 else if (xfer->rx_buf) 607 nbits = xfer->rx_nbits; 608 609 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); 610 611 /* Flush the FIFOs */ 612 a3700_spi_fifo_flush(a3700_spi); 613 614 /* Transfer first bytes of data when buffer is not 4-byte aligned */ 615 a3700_spi_header_set(a3700_spi); 616 617 if (xfer->rx_buf) { 618 /* Set read data length */ 619 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 620 a3700_spi->buf_len); 621 /* Start READ transfer */ 622 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 623 val &= ~A3700_SPI_RW_EN; 624 val |= A3700_SPI_XFER_START; 625 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 626 } else if (xfer->tx_buf) { 627 /* Start Write transfer */ 628 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 629 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); 630 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 631 632 /* 633 * If there are data to be written to the SPI device, xmit_data 634 * flag is set true; otherwise the instruction in SPI_INSTR does 635 * not require data to be written to the SPI device, then 636 * xmit_data flag is set false. 637 */ 638 a3700_spi->xmit_data = (a3700_spi->buf_len != 0); 639 } 640 641 while (a3700_spi->buf_len) { 642 if (a3700_spi->tx_buf) { 643 /* Wait wfifo ready */ 644 if (!a3700_spi_transfer_wait(spi, 645 A3700_SPI_WFIFO_RDY)) { 646 dev_err(&spi->dev, 647 "wait wfifo ready timed out\n"); 648 ret = -ETIMEDOUT; 649 goto error; 650 } 651 /* Fill up the wfifo */ 652 ret = a3700_spi_fifo_write(a3700_spi); 653 if (ret) 654 goto error; 655 } else if (a3700_spi->rx_buf) { 656 /* Wait rfifo ready */ 657 if (!a3700_spi_transfer_wait(spi, 658 A3700_SPI_RFIFO_RDY)) { 659 dev_err(&spi->dev, 660 "wait rfifo ready timed out\n"); 661 ret = -ETIMEDOUT; 662 goto error; 663 } 664 /* Drain out the rfifo */ 665 ret = a3700_spi_fifo_read(a3700_spi); 666 if (ret) 667 goto error; 668 } 669 } 670 671 /* 672 * Stop a write transfer in fifo mode: 673 * - wait all the bytes in wfifo to be shifted out 674 * - set XFER_STOP bit 675 * - wait XFER_START bit clear 676 * - clear XFER_STOP bit 677 * Stop a read transfer in fifo mode: 678 * - the hardware is to reset the XFER_START bit 679 * after the number of bytes indicated in DIN_CNT 680 * register 681 * - just wait XFER_START bit clear 682 */ 683 if (a3700_spi->tx_buf) { 684 if (a3700_spi->xmit_data) { 685 /* 686 * If there are data written to the SPI device, wait 687 * until SPI_WFIFO_EMPTY is 1 to wait for all data to 688 * transfer out of write FIFO. 689 */ 690 if (!a3700_spi_transfer_wait(spi, 691 A3700_SPI_WFIFO_EMPTY)) { 692 dev_err(&spi->dev, "wait wfifo empty timed out\n"); 693 return -ETIMEDOUT; 694 } 695 } 696 697 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { 698 dev_err(&spi->dev, "wait xfer ready timed out\n"); 699 return -ETIMEDOUT; 700 } 701 702 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 703 val |= A3700_SPI_XFER_STOP; 704 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 705 } 706 707 while (--timeout) { 708 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 709 if (!(val & A3700_SPI_XFER_START)) 710 break; 711 udelay(1); 712 } 713 714 if (timeout == 0) { 715 dev_err(&spi->dev, "wait transfer start clear timed out\n"); 716 ret = -ETIMEDOUT; 717 goto error; 718 } 719 720 val &= ~A3700_SPI_XFER_STOP; 721 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 722 goto out; 723 724 error: 725 a3700_spi_transfer_abort_fifo(a3700_spi); 726 out: 727 spi_finalize_current_transfer(master); 728 729 return ret; 730 } 731 732 static int a3700_spi_unprepare_message(struct spi_master *master, 733 struct spi_message *message) 734 { 735 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 736 737 clk_disable(a3700_spi->clk); 738 739 return 0; 740 } 741 742 static const struct of_device_id a3700_spi_dt_ids[] = { 743 { .compatible = "marvell,armada-3700-spi", .data = NULL }, 744 {}, 745 }; 746 747 MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); 748 749 static int a3700_spi_probe(struct platform_device *pdev) 750 { 751 struct device *dev = &pdev->dev; 752 struct device_node *of_node = dev->of_node; 753 struct resource *res; 754 struct spi_master *master; 755 struct a3700_spi *spi; 756 u32 num_cs = 0; 757 int irq, ret = 0; 758 759 master = spi_alloc_master(dev, sizeof(*spi)); 760 if (!master) { 761 dev_err(dev, "master allocation failed\n"); 762 ret = -ENOMEM; 763 goto out; 764 } 765 766 if (of_property_read_u32(of_node, "num-cs", &num_cs)) { 767 dev_err(dev, "could not find num-cs\n"); 768 ret = -ENXIO; 769 goto error; 770 } 771 772 master->bus_num = pdev->id; 773 master->dev.of_node = of_node; 774 master->mode_bits = SPI_MODE_3; 775 master->num_chipselect = num_cs; 776 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); 777 master->prepare_message = a3700_spi_prepare_message; 778 master->transfer_one = a3700_spi_transfer_one; 779 master->unprepare_message = a3700_spi_unprepare_message; 780 master->set_cs = a3700_spi_set_cs; 781 master->flags = SPI_MASTER_HALF_DUPLEX; 782 master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL | 783 SPI_RX_QUAD | SPI_TX_QUAD); 784 785 platform_set_drvdata(pdev, master); 786 787 spi = spi_master_get_devdata(master); 788 memset(spi, 0, sizeof(struct a3700_spi)); 789 790 spi->master = master; 791 792 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 793 spi->base = devm_ioremap_resource(dev, res); 794 if (IS_ERR(spi->base)) { 795 ret = PTR_ERR(spi->base); 796 goto error; 797 } 798 799 irq = platform_get_irq(pdev, 0); 800 if (irq < 0) { 801 dev_err(dev, "could not get irq: %d\n", irq); 802 ret = -ENXIO; 803 goto error; 804 } 805 spi->irq = irq; 806 807 init_completion(&spi->done); 808 809 spi->clk = devm_clk_get(dev, NULL); 810 if (IS_ERR(spi->clk)) { 811 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); 812 goto error; 813 } 814 815 ret = clk_prepare(spi->clk); 816 if (ret) { 817 dev_err(dev, "could not prepare clk: %d\n", ret); 818 goto error; 819 } 820 821 ret = a3700_spi_init(spi); 822 if (ret) 823 goto error_clk; 824 825 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, 826 dev_name(dev), master); 827 if (ret) { 828 dev_err(dev, "could not request IRQ: %d\n", ret); 829 goto error_clk; 830 } 831 832 ret = devm_spi_register_master(dev, master); 833 if (ret) { 834 dev_err(dev, "Failed to register master\n"); 835 goto error_clk; 836 } 837 838 return 0; 839 840 error_clk: 841 clk_disable_unprepare(spi->clk); 842 error: 843 spi_master_put(master); 844 out: 845 return ret; 846 } 847 848 static int a3700_spi_remove(struct platform_device *pdev) 849 { 850 struct spi_master *master = platform_get_drvdata(pdev); 851 struct a3700_spi *spi = spi_master_get_devdata(master); 852 853 clk_unprepare(spi->clk); 854 855 return 0; 856 } 857 858 static struct platform_driver a3700_spi_driver = { 859 .driver = { 860 .name = DRIVER_NAME, 861 .of_match_table = of_match_ptr(a3700_spi_dt_ids), 862 }, 863 .probe = a3700_spi_probe, 864 .remove = a3700_spi_remove, 865 }; 866 867 module_platform_driver(a3700_spi_driver); 868 869 MODULE_DESCRIPTION("Armada-3700 SPI driver"); 870 MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); 871 MODULE_LICENSE("GPL"); 872 MODULE_ALIAS("platform:" DRIVER_NAME); 873