1 /* 2 * Marvell Armada-3700 SPI controller driver 3 * 4 * Copyright (C) 2016 Marvell Ltd. 5 * 6 * Author: Wilson Ding <dingwei@marvell.com> 7 * Author: Romain Perier <romain.perier@free-electrons.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/completion.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_device.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/spi/spi.h> 27 28 #define DRIVER_NAME "armada_3700_spi" 29 30 #define A3700_SPI_TIMEOUT 10 31 32 /* SPI Register Offest */ 33 #define A3700_SPI_IF_CTRL_REG 0x00 34 #define A3700_SPI_IF_CFG_REG 0x04 35 #define A3700_SPI_DATA_OUT_REG 0x08 36 #define A3700_SPI_DATA_IN_REG 0x0C 37 #define A3700_SPI_IF_INST_REG 0x10 38 #define A3700_SPI_IF_ADDR_REG 0x14 39 #define A3700_SPI_IF_RMODE_REG 0x18 40 #define A3700_SPI_IF_HDR_CNT_REG 0x1C 41 #define A3700_SPI_IF_DIN_CNT_REG 0x20 42 #define A3700_SPI_IF_TIME_REG 0x24 43 #define A3700_SPI_INT_STAT_REG 0x28 44 #define A3700_SPI_INT_MASK_REG 0x2C 45 46 /* A3700_SPI_IF_CTRL_REG */ 47 #define A3700_SPI_EN BIT(16) 48 #define A3700_SPI_ADDR_NOT_CONFIG BIT(12) 49 #define A3700_SPI_WFIFO_OVERFLOW BIT(11) 50 #define A3700_SPI_WFIFO_UNDERFLOW BIT(10) 51 #define A3700_SPI_RFIFO_OVERFLOW BIT(9) 52 #define A3700_SPI_RFIFO_UNDERFLOW BIT(8) 53 #define A3700_SPI_WFIFO_FULL BIT(7) 54 #define A3700_SPI_WFIFO_EMPTY BIT(6) 55 #define A3700_SPI_RFIFO_FULL BIT(5) 56 #define A3700_SPI_RFIFO_EMPTY BIT(4) 57 #define A3700_SPI_WFIFO_RDY BIT(3) 58 #define A3700_SPI_RFIFO_RDY BIT(2) 59 #define A3700_SPI_XFER_RDY BIT(1) 60 #define A3700_SPI_XFER_DONE BIT(0) 61 62 /* A3700_SPI_IF_CFG_REG */ 63 #define A3700_SPI_WFIFO_THRS BIT(28) 64 #define A3700_SPI_RFIFO_THRS BIT(24) 65 #define A3700_SPI_AUTO_CS BIT(20) 66 #define A3700_SPI_DMA_RD_EN BIT(18) 67 #define A3700_SPI_FIFO_MODE BIT(17) 68 #define A3700_SPI_SRST BIT(16) 69 #define A3700_SPI_XFER_START BIT(15) 70 #define A3700_SPI_XFER_STOP BIT(14) 71 #define A3700_SPI_INST_PIN BIT(13) 72 #define A3700_SPI_ADDR_PIN BIT(12) 73 #define A3700_SPI_DATA_PIN1 BIT(11) 74 #define A3700_SPI_DATA_PIN0 BIT(10) 75 #define A3700_SPI_FIFO_FLUSH BIT(9) 76 #define A3700_SPI_RW_EN BIT(8) 77 #define A3700_SPI_CLK_POL BIT(7) 78 #define A3700_SPI_CLK_PHA BIT(6) 79 #define A3700_SPI_BYTE_LEN BIT(5) 80 #define A3700_SPI_CLK_PRESCALE BIT(0) 81 #define A3700_SPI_CLK_PRESCALE_MASK (0x1f) 82 83 #define A3700_SPI_WFIFO_THRS_BIT 28 84 #define A3700_SPI_RFIFO_THRS_BIT 24 85 #define A3700_SPI_FIFO_THRS_MASK 0x7 86 87 #define A3700_SPI_DATA_PIN_MASK 0x3 88 89 /* A3700_SPI_IF_HDR_CNT_REG */ 90 #define A3700_SPI_DUMMY_CNT_BIT 12 91 #define A3700_SPI_DUMMY_CNT_MASK 0x7 92 #define A3700_SPI_RMODE_CNT_BIT 8 93 #define A3700_SPI_RMODE_CNT_MASK 0x3 94 #define A3700_SPI_ADDR_CNT_BIT 4 95 #define A3700_SPI_ADDR_CNT_MASK 0x7 96 #define A3700_SPI_INSTR_CNT_BIT 0 97 #define A3700_SPI_INSTR_CNT_MASK 0x3 98 99 /* A3700_SPI_IF_TIME_REG */ 100 #define A3700_SPI_CLK_CAPT_EDGE BIT(7) 101 102 struct a3700_spi { 103 struct spi_master *master; 104 void __iomem *base; 105 struct clk *clk; 106 unsigned int irq; 107 unsigned int flags; 108 bool xmit_data; 109 const u8 *tx_buf; 110 u8 *rx_buf; 111 size_t buf_len; 112 u8 byte_len; 113 u32 wait_mask; 114 struct completion done; 115 }; 116 117 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) 118 { 119 return readl(a3700_spi->base + offset); 120 } 121 122 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) 123 { 124 writel(data, a3700_spi->base + offset); 125 } 126 127 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) 128 { 129 u32 val; 130 131 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 132 val &= ~A3700_SPI_AUTO_CS; 133 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 134 } 135 136 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) 137 { 138 u32 val; 139 140 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 141 val |= (A3700_SPI_EN << cs); 142 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 143 } 144 145 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, 146 unsigned int cs) 147 { 148 u32 val; 149 150 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 151 val &= ~(A3700_SPI_EN << cs); 152 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); 153 } 154 155 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, 156 unsigned int pin_mode, bool receiving) 157 { 158 u32 val; 159 160 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 161 val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); 162 val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); 163 164 switch (pin_mode) { 165 case SPI_NBITS_SINGLE: 166 break; 167 case SPI_NBITS_DUAL: 168 val |= A3700_SPI_DATA_PIN0; 169 break; 170 case SPI_NBITS_QUAD: 171 val |= A3700_SPI_DATA_PIN1; 172 /* RX during address reception uses 4-pin */ 173 if (receiving) 174 val |= A3700_SPI_ADDR_PIN; 175 break; 176 default: 177 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); 178 return -EINVAL; 179 } 180 181 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 182 183 return 0; 184 } 185 186 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi) 187 { 188 u32 val; 189 190 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 191 val |= A3700_SPI_FIFO_MODE; 192 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 193 } 194 195 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, 196 unsigned int mode_bits) 197 { 198 u32 val; 199 200 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 201 202 if (mode_bits & SPI_CPOL) 203 val |= A3700_SPI_CLK_POL; 204 else 205 val &= ~A3700_SPI_CLK_POL; 206 207 if (mode_bits & SPI_CPHA) 208 val |= A3700_SPI_CLK_PHA; 209 else 210 val &= ~A3700_SPI_CLK_PHA; 211 212 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 213 } 214 215 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, 216 unsigned int speed_hz) 217 { 218 u32 val; 219 u32 prescale; 220 221 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); 222 223 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 224 val = val & ~A3700_SPI_CLK_PRESCALE_MASK; 225 226 val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); 227 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 228 229 if (prescale <= 2) { 230 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); 231 val |= A3700_SPI_CLK_CAPT_EDGE; 232 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); 233 } 234 } 235 236 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) 237 { 238 u32 val; 239 240 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 241 if (len == 4) 242 val |= A3700_SPI_BYTE_LEN; 243 else 244 val &= ~A3700_SPI_BYTE_LEN; 245 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 246 247 a3700_spi->byte_len = len; 248 } 249 250 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) 251 { 252 int timeout = A3700_SPI_TIMEOUT; 253 u32 val; 254 255 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 256 val |= A3700_SPI_FIFO_FLUSH; 257 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 258 259 while (--timeout) { 260 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 261 if (!(val & A3700_SPI_FIFO_FLUSH)) 262 return 0; 263 udelay(1); 264 } 265 266 return -ETIMEDOUT; 267 } 268 269 static int a3700_spi_init(struct a3700_spi *a3700_spi) 270 { 271 struct spi_master *master = a3700_spi->master; 272 u32 val; 273 int i, ret = 0; 274 275 /* Reset SPI unit */ 276 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 277 val |= A3700_SPI_SRST; 278 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 279 280 udelay(A3700_SPI_TIMEOUT); 281 282 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 283 val &= ~A3700_SPI_SRST; 284 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 285 286 /* Disable AUTO_CS and deactivate all chip-selects */ 287 a3700_spi_auto_cs_unset(a3700_spi); 288 for (i = 0; i < master->num_chipselect; i++) 289 a3700_spi_deactivate_cs(a3700_spi, i); 290 291 /* Enable FIFO mode */ 292 a3700_spi_fifo_mode_set(a3700_spi); 293 294 /* Set SPI mode */ 295 a3700_spi_mode_set(a3700_spi, master->mode_bits); 296 297 /* Reset counters */ 298 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 299 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); 300 301 /* Mask the interrupts and clear cause bits */ 302 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 303 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); 304 305 return ret; 306 } 307 308 static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) 309 { 310 struct spi_master *master = dev_id; 311 struct a3700_spi *a3700_spi; 312 u32 cause; 313 314 a3700_spi = spi_master_get_devdata(master); 315 316 /* Get interrupt causes */ 317 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); 318 319 if (!cause || !(a3700_spi->wait_mask & cause)) 320 return IRQ_NONE; 321 322 /* mask and acknowledge the SPI interrupts */ 323 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 324 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); 325 326 /* Wake up the transfer */ 327 complete(&a3700_spi->done); 328 329 return IRQ_HANDLED; 330 } 331 332 static bool a3700_spi_wait_completion(struct spi_device *spi) 333 { 334 struct a3700_spi *a3700_spi; 335 unsigned int timeout; 336 unsigned int ctrl_reg; 337 unsigned long timeout_jiffies; 338 339 a3700_spi = spi_master_get_devdata(spi->master); 340 341 /* SPI interrupt is edge-triggered, which means an interrupt will 342 * be generated only when detecting a specific status bit changed 343 * from '0' to '1'. So when we start waiting for a interrupt, we 344 * need to check status bit in control reg first, if it is already 1, 345 * then we do not need to wait for interrupt 346 */ 347 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 348 if (a3700_spi->wait_mask & ctrl_reg) 349 return true; 350 351 reinit_completion(&a3700_spi->done); 352 353 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 354 a3700_spi->wait_mask); 355 356 timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); 357 timeout = wait_for_completion_timeout(&a3700_spi->done, 358 timeout_jiffies); 359 360 a3700_spi->wait_mask = 0; 361 362 if (timeout) 363 return true; 364 365 /* there might be the case that right after we checked the 366 * status bits in this routine and before start to wait for 367 * interrupt by wait_for_completion_timeout, the interrupt 368 * happens, to avoid missing it we need to double check 369 * status bits in control reg, if it is already 1, then 370 * consider that we have the interrupt successfully and 371 * return true. 372 */ 373 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 374 if (a3700_spi->wait_mask & ctrl_reg) 375 return true; 376 377 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); 378 379 /* Timeout was reached */ 380 return false; 381 } 382 383 static bool a3700_spi_transfer_wait(struct spi_device *spi, 384 unsigned int bit_mask) 385 { 386 struct a3700_spi *a3700_spi; 387 388 a3700_spi = spi_master_get_devdata(spi->master); 389 a3700_spi->wait_mask = bit_mask; 390 391 return a3700_spi_wait_completion(spi); 392 } 393 394 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, 395 unsigned int bytes) 396 { 397 u32 val; 398 399 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 400 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); 401 val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; 402 val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); 403 val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; 404 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 405 } 406 407 static void a3700_spi_transfer_setup(struct spi_device *spi, 408 struct spi_transfer *xfer) 409 { 410 struct a3700_spi *a3700_spi; 411 unsigned int byte_len; 412 413 a3700_spi = spi_master_get_devdata(spi->master); 414 415 a3700_spi_clock_set(a3700_spi, xfer->speed_hz); 416 417 byte_len = xfer->bits_per_word >> 3; 418 419 a3700_spi_fifo_thres_set(a3700_spi, byte_len); 420 } 421 422 static void a3700_spi_set_cs(struct spi_device *spi, bool enable) 423 { 424 struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); 425 426 if (!enable) 427 a3700_spi_activate_cs(a3700_spi, spi->chip_select); 428 else 429 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); 430 } 431 432 static void a3700_spi_header_set(struct a3700_spi *a3700_spi) 433 { 434 unsigned int addr_cnt; 435 u32 val = 0; 436 437 /* Clear the header registers */ 438 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); 439 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); 440 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); 441 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); 442 443 /* Set header counters */ 444 if (a3700_spi->tx_buf) { 445 /* 446 * when tx data is not 4 bytes aligned, there will be unexpected 447 * bytes out of SPI output register, since it always shifts out 448 * as whole 4 bytes. This might cause incorrect transaction with 449 * some devices. To avoid that, use SPI header count feature to 450 * transfer up to 3 bytes of data first, and then make the rest 451 * of data 4-byte aligned. 452 */ 453 addr_cnt = a3700_spi->buf_len % 4; 454 if (addr_cnt) { 455 val = (addr_cnt & A3700_SPI_ADDR_CNT_MASK) 456 << A3700_SPI_ADDR_CNT_BIT; 457 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); 458 459 /* Update the buffer length to be transferred */ 460 a3700_spi->buf_len -= addr_cnt; 461 462 /* transfer 1~3 bytes through address count */ 463 val = 0; 464 while (addr_cnt--) { 465 val = (val << 8) | a3700_spi->tx_buf[0]; 466 a3700_spi->tx_buf++; 467 } 468 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); 469 } 470 } 471 } 472 473 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) 474 { 475 u32 val; 476 477 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 478 return (val & A3700_SPI_WFIFO_FULL); 479 } 480 481 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) 482 { 483 u32 val; 484 485 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { 486 val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf); 487 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); 488 a3700_spi->buf_len -= 4; 489 a3700_spi->tx_buf += 4; 490 } 491 492 return 0; 493 } 494 495 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) 496 { 497 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); 498 499 return (val & A3700_SPI_RFIFO_EMPTY); 500 } 501 502 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) 503 { 504 u32 val; 505 506 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { 507 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); 508 if (a3700_spi->buf_len >= 4) { 509 u32 data = le32_to_cpu(val); 510 511 memcpy(a3700_spi->rx_buf, &data, 4); 512 513 a3700_spi->buf_len -= 4; 514 a3700_spi->rx_buf += 4; 515 } else { 516 /* 517 * When remain bytes is not larger than 4, we should 518 * avoid memory overwriting and just write the left rx 519 * buffer bytes. 520 */ 521 while (a3700_spi->buf_len) { 522 *a3700_spi->rx_buf = val & 0xff; 523 val >>= 8; 524 525 a3700_spi->buf_len--; 526 a3700_spi->rx_buf++; 527 } 528 } 529 } 530 531 return 0; 532 } 533 534 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) 535 { 536 int timeout = A3700_SPI_TIMEOUT; 537 u32 val; 538 539 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 540 val |= A3700_SPI_XFER_STOP; 541 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 542 543 while (--timeout) { 544 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 545 if (!(val & A3700_SPI_XFER_START)) 546 break; 547 udelay(1); 548 } 549 550 a3700_spi_fifo_flush(a3700_spi); 551 552 val &= ~A3700_SPI_XFER_STOP; 553 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 554 } 555 556 static int a3700_spi_prepare_message(struct spi_master *master, 557 struct spi_message *message) 558 { 559 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 560 struct spi_device *spi = message->spi; 561 int ret; 562 563 ret = clk_enable(a3700_spi->clk); 564 if (ret) { 565 dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); 566 return ret; 567 } 568 569 /* Flush the FIFOs */ 570 ret = a3700_spi_fifo_flush(a3700_spi); 571 if (ret) 572 return ret; 573 574 a3700_spi_bytelen_set(a3700_spi, 4); 575 576 a3700_spi_mode_set(a3700_spi, spi->mode); 577 578 return 0; 579 } 580 581 static int a3700_spi_transfer_one(struct spi_master *master, 582 struct spi_device *spi, 583 struct spi_transfer *xfer) 584 { 585 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 586 int ret = 0, timeout = A3700_SPI_TIMEOUT; 587 unsigned int nbits = 0; 588 u32 val; 589 590 a3700_spi_transfer_setup(spi, xfer); 591 592 a3700_spi->tx_buf = xfer->tx_buf; 593 a3700_spi->rx_buf = xfer->rx_buf; 594 a3700_spi->buf_len = xfer->len; 595 596 if (xfer->tx_buf) 597 nbits = xfer->tx_nbits; 598 else if (xfer->rx_buf) 599 nbits = xfer->rx_nbits; 600 601 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); 602 603 /* Flush the FIFOs */ 604 a3700_spi_fifo_flush(a3700_spi); 605 606 /* Transfer first bytes of data when buffer is not 4-byte aligned */ 607 a3700_spi_header_set(a3700_spi); 608 609 if (xfer->rx_buf) { 610 /* Set read data length */ 611 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 612 a3700_spi->buf_len); 613 /* Start READ transfer */ 614 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 615 val &= ~A3700_SPI_RW_EN; 616 val |= A3700_SPI_XFER_START; 617 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 618 } else if (xfer->tx_buf) { 619 /* Start Write transfer */ 620 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 621 val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); 622 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 623 624 /* 625 * If there are data to be written to the SPI device, xmit_data 626 * flag is set true; otherwise the instruction in SPI_INSTR does 627 * not require data to be written to the SPI device, then 628 * xmit_data flag is set false. 629 */ 630 a3700_spi->xmit_data = (a3700_spi->buf_len != 0); 631 } 632 633 while (a3700_spi->buf_len) { 634 if (a3700_spi->tx_buf) { 635 /* Wait wfifo ready */ 636 if (!a3700_spi_transfer_wait(spi, 637 A3700_SPI_WFIFO_RDY)) { 638 dev_err(&spi->dev, 639 "wait wfifo ready timed out\n"); 640 ret = -ETIMEDOUT; 641 goto error; 642 } 643 /* Fill up the wfifo */ 644 ret = a3700_spi_fifo_write(a3700_spi); 645 if (ret) 646 goto error; 647 } else if (a3700_spi->rx_buf) { 648 /* Wait rfifo ready */ 649 if (!a3700_spi_transfer_wait(spi, 650 A3700_SPI_RFIFO_RDY)) { 651 dev_err(&spi->dev, 652 "wait rfifo ready timed out\n"); 653 ret = -ETIMEDOUT; 654 goto error; 655 } 656 /* Drain out the rfifo */ 657 ret = a3700_spi_fifo_read(a3700_spi); 658 if (ret) 659 goto error; 660 } 661 } 662 663 /* 664 * Stop a write transfer in fifo mode: 665 * - wait all the bytes in wfifo to be shifted out 666 * - set XFER_STOP bit 667 * - wait XFER_START bit clear 668 * - clear XFER_STOP bit 669 * Stop a read transfer in fifo mode: 670 * - the hardware is to reset the XFER_START bit 671 * after the number of bytes indicated in DIN_CNT 672 * register 673 * - just wait XFER_START bit clear 674 */ 675 if (a3700_spi->tx_buf) { 676 if (a3700_spi->xmit_data) { 677 /* 678 * If there are data written to the SPI device, wait 679 * until SPI_WFIFO_EMPTY is 1 to wait for all data to 680 * transfer out of write FIFO. 681 */ 682 if (!a3700_spi_transfer_wait(spi, 683 A3700_SPI_WFIFO_EMPTY)) { 684 dev_err(&spi->dev, "wait wfifo empty timed out\n"); 685 return -ETIMEDOUT; 686 } 687 } 688 689 if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { 690 dev_err(&spi->dev, "wait xfer ready timed out\n"); 691 return -ETIMEDOUT; 692 } 693 694 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 695 val |= A3700_SPI_XFER_STOP; 696 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 697 } 698 699 while (--timeout) { 700 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); 701 if (!(val & A3700_SPI_XFER_START)) 702 break; 703 udelay(1); 704 } 705 706 if (timeout == 0) { 707 dev_err(&spi->dev, "wait transfer start clear timed out\n"); 708 ret = -ETIMEDOUT; 709 goto error; 710 } 711 712 val &= ~A3700_SPI_XFER_STOP; 713 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); 714 goto out; 715 716 error: 717 a3700_spi_transfer_abort_fifo(a3700_spi); 718 out: 719 spi_finalize_current_transfer(master); 720 721 return ret; 722 } 723 724 static int a3700_spi_unprepare_message(struct spi_master *master, 725 struct spi_message *message) 726 { 727 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); 728 729 clk_disable(a3700_spi->clk); 730 731 return 0; 732 } 733 734 static const struct of_device_id a3700_spi_dt_ids[] = { 735 { .compatible = "marvell,armada-3700-spi", .data = NULL }, 736 {}, 737 }; 738 739 MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); 740 741 static int a3700_spi_probe(struct platform_device *pdev) 742 { 743 struct device *dev = &pdev->dev; 744 struct device_node *of_node = dev->of_node; 745 struct resource *res; 746 struct spi_master *master; 747 struct a3700_spi *spi; 748 u32 num_cs = 0; 749 int irq, ret = 0; 750 751 master = spi_alloc_master(dev, sizeof(*spi)); 752 if (!master) { 753 dev_err(dev, "master allocation failed\n"); 754 ret = -ENOMEM; 755 goto out; 756 } 757 758 if (of_property_read_u32(of_node, "num-cs", &num_cs)) { 759 dev_err(dev, "could not find num-cs\n"); 760 ret = -ENXIO; 761 goto error; 762 } 763 764 master->bus_num = pdev->id; 765 master->dev.of_node = of_node; 766 master->mode_bits = SPI_MODE_3; 767 master->num_chipselect = num_cs; 768 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); 769 master->prepare_message = a3700_spi_prepare_message; 770 master->transfer_one = a3700_spi_transfer_one; 771 master->unprepare_message = a3700_spi_unprepare_message; 772 master->set_cs = a3700_spi_set_cs; 773 master->flags = SPI_MASTER_HALF_DUPLEX; 774 master->mode_bits |= (SPI_RX_DUAL | SPI_TX_DUAL | 775 SPI_RX_QUAD | SPI_TX_QUAD); 776 777 platform_set_drvdata(pdev, master); 778 779 spi = spi_master_get_devdata(master); 780 memset(spi, 0, sizeof(struct a3700_spi)); 781 782 spi->master = master; 783 784 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 785 spi->base = devm_ioremap_resource(dev, res); 786 if (IS_ERR(spi->base)) { 787 ret = PTR_ERR(spi->base); 788 goto error; 789 } 790 791 irq = platform_get_irq(pdev, 0); 792 if (irq < 0) { 793 dev_err(dev, "could not get irq: %d\n", irq); 794 ret = -ENXIO; 795 goto error; 796 } 797 spi->irq = irq; 798 799 init_completion(&spi->done); 800 801 spi->clk = devm_clk_get(dev, NULL); 802 if (IS_ERR(spi->clk)) { 803 dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); 804 goto error; 805 } 806 807 ret = clk_prepare(spi->clk); 808 if (ret) { 809 dev_err(dev, "could not prepare clk: %d\n", ret); 810 goto error; 811 } 812 813 ret = a3700_spi_init(spi); 814 if (ret) 815 goto error_clk; 816 817 ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, 818 dev_name(dev), master); 819 if (ret) { 820 dev_err(dev, "could not request IRQ: %d\n", ret); 821 goto error_clk; 822 } 823 824 ret = devm_spi_register_master(dev, master); 825 if (ret) { 826 dev_err(dev, "Failed to register master\n"); 827 goto error_clk; 828 } 829 830 return 0; 831 832 error_clk: 833 clk_disable_unprepare(spi->clk); 834 error: 835 spi_master_put(master); 836 out: 837 return ret; 838 } 839 840 static int a3700_spi_remove(struct platform_device *pdev) 841 { 842 struct spi_master *master = platform_get_drvdata(pdev); 843 struct a3700_spi *spi = spi_master_get_devdata(master); 844 845 clk_unprepare(spi->clk); 846 847 return 0; 848 } 849 850 static struct platform_driver a3700_spi_driver = { 851 .driver = { 852 .name = DRIVER_NAME, 853 .of_match_table = of_match_ptr(a3700_spi_dt_ids), 854 }, 855 .probe = a3700_spi_probe, 856 .remove = a3700_spi_remove, 857 }; 858 859 module_platform_driver(a3700_spi_driver); 860 861 MODULE_DESCRIPTION("Armada-3700 SPI driver"); 862 MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); 863 MODULE_LICENSE("GPL"); 864 MODULE_ALIAS("platform:" DRIVER_NAME); 865