1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // 3 // AMD SPI controller driver 4 // 5 // Copyright (c) 2020, Advanced Micro Devices, Inc. 6 // 7 // Author: Sanjay R Mehta <sanju.mehta@amd.com> 8 9 #include <linux/acpi.h> 10 #include <linux/init.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/delay.h> 14 #include <linux/spi/spi.h> 15 #include <linux/iopoll.h> 16 17 #define AMD_SPI_CTRL0_REG 0x00 18 #define AMD_SPI_EXEC_CMD BIT(16) 19 #define AMD_SPI_FIFO_CLEAR BIT(20) 20 #define AMD_SPI_BUSY BIT(31) 21 22 #define AMD_SPI_OPCODE_REG 0x45 23 #define AMD_SPI_CMD_TRIGGER_REG 0x47 24 #define AMD_SPI_TRIGGER_CMD BIT(7) 25 26 #define AMD_SPI_OPCODE_MASK 0xFF 27 28 #define AMD_SPI_ALT_CS_REG 0x1D 29 #define AMD_SPI_ALT_CS_MASK 0x3 30 31 #define AMD_SPI_FIFO_BASE 0x80 32 #define AMD_SPI_TX_COUNT_REG 0x48 33 #define AMD_SPI_RX_COUNT_REG 0x4B 34 #define AMD_SPI_STATUS_REG 0x4C 35 36 #define AMD_SPI_MEM_SIZE 200 37 38 /* M_CMD OP codes for SPI */ 39 #define AMD_SPI_XFER_TX 1 40 #define AMD_SPI_XFER_RX 2 41 42 enum amd_spi_versions { 43 AMD_SPI_V1 = 1, /* AMDI0061 */ 44 AMD_SPI_V2, /* AMDI0062 */ 45 }; 46 47 struct amd_spi { 48 void __iomem *io_remap_addr; 49 unsigned long io_base_addr; 50 enum amd_spi_versions version; 51 }; 52 53 static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx) 54 { 55 return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx); 56 } 57 58 static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val) 59 { 60 iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); 61 } 62 63 static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear) 64 { 65 u8 tmp = amd_spi_readreg8(amd_spi, idx); 66 67 tmp = (tmp & ~clear) | set; 68 amd_spi_writereg8(amd_spi, idx, tmp); 69 } 70 71 static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx) 72 { 73 return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx); 74 } 75 76 static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val) 77 { 78 iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx)); 79 } 80 81 static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear) 82 { 83 u32 tmp = amd_spi_readreg32(amd_spi, idx); 84 85 tmp = (tmp & ~clear) | set; 86 amd_spi_writereg32(amd_spi, idx, tmp); 87 } 88 89 static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs) 90 { 91 amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK); 92 } 93 94 static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select) 95 { 96 amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK); 97 } 98 99 static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi) 100 { 101 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR); 102 } 103 104 static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode) 105 { 106 switch (amd_spi->version) { 107 case AMD_SPI_V1: 108 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode, 109 AMD_SPI_OPCODE_MASK); 110 return 0; 111 case AMD_SPI_V2: 112 amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode); 113 return 0; 114 default: 115 return -ENODEV; 116 } 117 } 118 119 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count) 120 { 121 amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff); 122 } 123 124 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count) 125 { 126 amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff); 127 } 128 129 static int amd_spi_busy_wait(struct amd_spi *amd_spi) 130 { 131 u32 val; 132 int reg; 133 134 switch (amd_spi->version) { 135 case AMD_SPI_V1: 136 reg = AMD_SPI_CTRL0_REG; 137 break; 138 case AMD_SPI_V2: 139 reg = AMD_SPI_STATUS_REG; 140 break; 141 default: 142 return -ENODEV; 143 } 144 145 return readl_poll_timeout(amd_spi->io_remap_addr + reg, val, 146 !(val & AMD_SPI_BUSY), 20, 2000000); 147 } 148 149 static int amd_spi_execute_opcode(struct amd_spi *amd_spi) 150 { 151 int ret; 152 153 ret = amd_spi_busy_wait(amd_spi); 154 if (ret) 155 return ret; 156 157 switch (amd_spi->version) { 158 case AMD_SPI_V1: 159 /* Set ExecuteOpCode bit in the CTRL0 register */ 160 amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, 161 AMD_SPI_EXEC_CMD); 162 return 0; 163 case AMD_SPI_V2: 164 /* Trigger the command execution */ 165 amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG, 166 AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD); 167 return 0; 168 default: 169 return -ENODEV; 170 } 171 } 172 173 static int amd_spi_master_setup(struct spi_device *spi) 174 { 175 struct amd_spi *amd_spi = spi_master_get_devdata(spi->master); 176 177 amd_spi_clear_fifo_ptr(amd_spi); 178 179 return 0; 180 } 181 182 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi, 183 struct spi_master *master, 184 struct spi_message *message) 185 { 186 struct spi_transfer *xfer = NULL; 187 u8 cmd_opcode; 188 u8 *buf = NULL; 189 u32 m_cmd = 0; 190 u32 i = 0; 191 u32 tx_len = 0, rx_len = 0; 192 193 list_for_each_entry(xfer, &message->transfers, 194 transfer_list) { 195 if (xfer->rx_buf) 196 m_cmd = AMD_SPI_XFER_RX; 197 if (xfer->tx_buf) 198 m_cmd = AMD_SPI_XFER_TX; 199 200 if (m_cmd & AMD_SPI_XFER_TX) { 201 buf = (u8 *)xfer->tx_buf; 202 tx_len = xfer->len - 1; 203 cmd_opcode = *(u8 *)xfer->tx_buf; 204 buf++; 205 amd_spi_set_opcode(amd_spi, cmd_opcode); 206 207 /* Write data into the FIFO. */ 208 for (i = 0; i < tx_len; i++) { 209 iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr + 210 AMD_SPI_FIFO_BASE + i)); 211 } 212 213 amd_spi_set_tx_count(amd_spi, tx_len); 214 amd_spi_clear_fifo_ptr(amd_spi); 215 /* Execute command */ 216 amd_spi_execute_opcode(amd_spi); 217 } 218 if (m_cmd & AMD_SPI_XFER_RX) { 219 /* 220 * Store no. of bytes to be received from 221 * FIFO 222 */ 223 rx_len = xfer->len; 224 buf = (u8 *)xfer->rx_buf; 225 amd_spi_set_rx_count(amd_spi, rx_len); 226 amd_spi_clear_fifo_ptr(amd_spi); 227 /* Execute command */ 228 amd_spi_execute_opcode(amd_spi); 229 amd_spi_busy_wait(amd_spi); 230 /* Read data from FIFO to receive buffer */ 231 for (i = 0; i < rx_len; i++) 232 buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i); 233 } 234 } 235 236 /* Update statistics */ 237 message->actual_length = tx_len + rx_len + 1; 238 /* complete the transaction */ 239 message->status = 0; 240 241 switch (amd_spi->version) { 242 case AMD_SPI_V1: 243 break; 244 case AMD_SPI_V2: 245 amd_spi_clear_chip(amd_spi, message->spi->chip_select); 246 break; 247 default: 248 return -ENODEV; 249 } 250 251 spi_finalize_current_message(master); 252 253 return 0; 254 } 255 256 static int amd_spi_master_transfer(struct spi_master *master, 257 struct spi_message *msg) 258 { 259 struct amd_spi *amd_spi = spi_master_get_devdata(master); 260 struct spi_device *spi = msg->spi; 261 262 amd_spi_select_chip(amd_spi, spi->chip_select); 263 264 /* 265 * Extract spi_transfers from the spi message and 266 * program the controller. 267 */ 268 amd_spi_fifo_xfer(amd_spi, master, msg); 269 270 return 0; 271 } 272 273 static int amd_spi_probe(struct platform_device *pdev) 274 { 275 struct device *dev = &pdev->dev; 276 struct spi_master *master; 277 struct amd_spi *amd_spi; 278 int err = 0; 279 280 /* Allocate storage for spi_master and driver private data */ 281 master = spi_alloc_master(dev, sizeof(struct amd_spi)); 282 if (!master) { 283 dev_err(dev, "Error allocating SPI master\n"); 284 return -ENOMEM; 285 } 286 287 amd_spi = spi_master_get_devdata(master); 288 amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0); 289 if (IS_ERR(amd_spi->io_remap_addr)) { 290 err = PTR_ERR(amd_spi->io_remap_addr); 291 dev_err(dev, "error %d ioremap of SPI registers failed\n", err); 292 goto err_free_master; 293 } 294 dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr); 295 296 amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev); 297 298 /* Initialize the spi_master fields */ 299 master->bus_num = 0; 300 master->num_chipselect = 4; 301 master->mode_bits = 0; 302 master->flags = SPI_MASTER_HALF_DUPLEX; 303 master->setup = amd_spi_master_setup; 304 master->transfer_one_message = amd_spi_master_transfer; 305 306 /* Register the controller with SPI framework */ 307 err = devm_spi_register_master(dev, master); 308 if (err) { 309 dev_err(dev, "error %d registering SPI controller\n", err); 310 goto err_free_master; 311 } 312 313 return 0; 314 315 err_free_master: 316 spi_master_put(master); 317 318 return err; 319 } 320 321 #ifdef CONFIG_ACPI 322 static const struct acpi_device_id spi_acpi_match[] = { 323 { "AMDI0061", AMD_SPI_V1 }, 324 { "AMDI0062", AMD_SPI_V2 }, 325 {}, 326 }; 327 MODULE_DEVICE_TABLE(acpi, spi_acpi_match); 328 #endif 329 330 static struct platform_driver amd_spi_driver = { 331 .driver = { 332 .name = "amd_spi", 333 .acpi_match_table = ACPI_PTR(spi_acpi_match), 334 }, 335 .probe = amd_spi_probe, 336 }; 337 338 module_platform_driver(amd_spi_driver); 339 340 MODULE_LICENSE("Dual BSD/GPL"); 341 MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>"); 342 MODULE_DESCRIPTION("AMD SPI Master Controller Driver"); 343