1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // DFL bus driver for Altera SPI Master 4 // 5 // Copyright (C) 2020 Intel Corporation, Inc. 6 // 7 // Authors: 8 // Matthew Gerlach <matthew.gerlach@linux.intel.com> 9 // 10 11 #include <linux/types.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/stddef.h> 15 #include <linux/errno.h> 16 #include <linux/platform_device.h> 17 #include <linux/io.h> 18 #include <linux/bitfield.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 #include <linux/regmap.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/altera.h> 23 #include <linux/dfl.h> 24 25 #define FME_FEATURE_ID_MAX10_SPI 0xe 26 #define FME_FEATURE_REV_MAX10_SPI_N5010 0x1 27 28 #define SPI_CORE_PARAMETER 0x8 29 #define SHIFT_MODE BIT_ULL(1) 30 #define SHIFT_MODE_MSB 0 31 #define SHIFT_MODE_LSB 1 32 #define DATA_WIDTH GENMASK_ULL(7, 2) 33 #define NUM_CHIPSELECT GENMASK_ULL(13, 8) 34 #define CLK_POLARITY BIT_ULL(14) 35 #define CLK_PHASE BIT_ULL(15) 36 #define PERIPHERAL_ID GENMASK_ULL(47, 32) 37 #define SPI_CLK GENMASK_ULL(31, 22) 38 #define SPI_INDIRECT_ACC_OFST 0x10 39 40 #define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0) 41 #define INDIRECT_WR BIT_ULL(8) 42 #define INDIRECT_RD BIT_ULL(9) 43 #define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8) 44 #define INDIRECT_DATA_MASK GENMASK_ULL(31, 0) 45 #define INDIRECT_DEBUG BIT_ULL(32) 46 #define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10) 47 #define INDIRECT_TIMEOUT 10000 48 49 static int indirect_bus_reg_read(void *context, unsigned int reg, 50 unsigned int *val) 51 { 52 void __iomem *base = context; 53 int loops; 54 u64 v; 55 56 writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR); 57 58 loops = 0; 59 while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) && 60 (loops++ < INDIRECT_TIMEOUT)) 61 cpu_relax(); 62 63 if (loops >= INDIRECT_TIMEOUT) { 64 pr_err("%s timed out %d\n", __func__, loops); 65 return -ETIME; 66 } 67 68 v = readq(base + INDIRECT_RD_DATA); 69 70 *val = v & INDIRECT_DATA_MASK; 71 72 return 0; 73 } 74 75 static int indirect_bus_reg_write(void *context, unsigned int reg, 76 unsigned int val) 77 { 78 void __iomem *base = context; 79 int loops; 80 81 writeq(val, base + INDIRECT_WR_DATA); 82 writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR); 83 84 loops = 0; 85 while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) && 86 (loops++ < INDIRECT_TIMEOUT)) 87 cpu_relax(); 88 89 if (loops >= INDIRECT_TIMEOUT) { 90 pr_err("%s timed out %d\n", __func__, loops); 91 return -ETIME; 92 } 93 return 0; 94 } 95 96 static const struct regmap_config indirect_regbus_cfg = { 97 .reg_bits = 32, 98 .reg_stride = 4, 99 .val_bits = 32, 100 .fast_io = true, 101 .max_register = 24, 102 103 .reg_write = indirect_bus_reg_write, 104 .reg_read = indirect_bus_reg_read, 105 }; 106 107 static void config_spi_master(void __iomem *base, struct spi_master *master) 108 { 109 u64 v; 110 111 v = readq(base + SPI_CORE_PARAMETER); 112 113 master->mode_bits = SPI_CS_HIGH; 114 if (FIELD_GET(CLK_POLARITY, v)) 115 master->mode_bits |= SPI_CPOL; 116 if (FIELD_GET(CLK_PHASE, v)) 117 master->mode_bits |= SPI_CPHA; 118 119 master->num_chipselect = FIELD_GET(NUM_CHIPSELECT, v); 120 master->bits_per_word_mask = 121 SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v)); 122 } 123 124 static int dfl_spi_altera_probe(struct dfl_device *dfl_dev) 125 { 126 struct spi_board_info board_info = { 0 }; 127 struct device *dev = &dfl_dev->dev; 128 struct spi_master *master; 129 struct altera_spi *hw; 130 void __iomem *base; 131 int err = -ENODEV; 132 133 master = spi_alloc_master(dev, sizeof(struct altera_spi)); 134 if (!master) 135 return -ENOMEM; 136 137 master->bus_num = dfl_dev->id; 138 139 hw = spi_master_get_devdata(master); 140 141 hw->dev = dev; 142 143 base = devm_ioremap_resource(dev, &dfl_dev->mmio_res); 144 145 if (IS_ERR(base)) 146 return PTR_ERR(base); 147 148 config_spi_master(base, master); 149 dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__, 150 master->num_chipselect, master->bits_per_word_mask, 151 master->mode_bits); 152 153 hw->regmap = devm_regmap_init(dev, NULL, base, &indirect_regbus_cfg); 154 if (IS_ERR(hw->regmap)) 155 return PTR_ERR(hw->regmap); 156 157 hw->irq = -EINVAL; 158 159 altera_spi_init_master(master); 160 161 err = devm_spi_register_master(dev, master); 162 if (err) { 163 dev_err(dev, "%s failed to register spi master %d\n", __func__, err); 164 goto exit; 165 } 166 167 if (dfl_dev->revision == FME_FEATURE_REV_MAX10_SPI_N5010) 168 strscpy(board_info.modalias, "m10-n5010", SPI_NAME_SIZE); 169 else 170 strscpy(board_info.modalias, "m10-d5005", SPI_NAME_SIZE); 171 172 board_info.max_speed_hz = 12500000; 173 board_info.bus_num = 0; 174 board_info.chip_select = 0; 175 176 if (!spi_new_device(master, &board_info)) { 177 dev_err(dev, "%s failed to create SPI device: %s\n", 178 __func__, board_info.modalias); 179 } 180 181 return 0; 182 exit: 183 spi_master_put(master); 184 return err; 185 } 186 187 static const struct dfl_device_id dfl_spi_altera_ids[] = { 188 { FME_ID, FME_FEATURE_ID_MAX10_SPI }, 189 { } 190 }; 191 192 static struct dfl_driver dfl_spi_altera_driver = { 193 .drv = { 194 .name = "dfl-spi-altera", 195 }, 196 .id_table = dfl_spi_altera_ids, 197 .probe = dfl_spi_altera_probe, 198 }; 199 200 module_dfl_driver(dfl_spi_altera_driver); 201 202 MODULE_DEVICE_TABLE(dfl, dfl_spi_altera_ids); 203 MODULE_DESCRIPTION("DFL spi altera driver"); 204 MODULE_AUTHOR("Intel Corporation"); 205 MODULE_LICENSE("GPL v2"); 206