1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Atmel QSPI Controller 4 * 5 * Copyright (C) 2015 Atmel Corporation 6 * Copyright (C) 2018 Cryptera A/S 7 * 8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com> 9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com> 10 * 11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/platform_device.h> 24 #include <linux/spi/spi-mem.h> 25 26 /* QSPI register offsets */ 27 #define QSPI_CR 0x0000 /* Control Register */ 28 #define QSPI_MR 0x0004 /* Mode Register */ 29 #define QSPI_RD 0x0008 /* Receive Data Register */ 30 #define QSPI_TD 0x000c /* Transmit Data Register */ 31 #define QSPI_SR 0x0010 /* Status Register */ 32 #define QSPI_IER 0x0014 /* Interrupt Enable Register */ 33 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */ 34 #define QSPI_IMR 0x001c /* Interrupt Mask Register */ 35 #define QSPI_SCR 0x0020 /* Serial Clock Register */ 36 37 #define QSPI_IAR 0x0030 /* Instruction Address Register */ 38 #define QSPI_ICR 0x0034 /* Instruction Code Register */ 39 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */ 40 #define QSPI_IFR 0x0038 /* Instruction Frame Register */ 41 #define QSPI_RICR 0x003C /* Read Instruction Code Register */ 42 43 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */ 44 #define QSPI_SKR 0x0044 /* Scrambling Key Register */ 45 46 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */ 47 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */ 48 49 #define QSPI_VERSION 0x00FC /* Version Register */ 50 51 52 /* Bitfields in QSPI_CR (Control Register) */ 53 #define QSPI_CR_QSPIEN BIT(0) 54 #define QSPI_CR_QSPIDIS BIT(1) 55 #define QSPI_CR_SWRST BIT(7) 56 #define QSPI_CR_LASTXFER BIT(24) 57 58 /* Bitfields in QSPI_MR (Mode Register) */ 59 #define QSPI_MR_SMM BIT(0) 60 #define QSPI_MR_LLB BIT(1) 61 #define QSPI_MR_WDRBT BIT(2) 62 #define QSPI_MR_SMRM BIT(3) 63 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4) 64 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4) 65 #define QSPI_MR_CSMODE_LASTXFER (1 << 4) 66 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4) 67 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8) 68 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK) 69 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16) 70 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK) 71 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24) 72 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK) 73 74 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */ 75 #define QSPI_SR_RDRF BIT(0) 76 #define QSPI_SR_TDRE BIT(1) 77 #define QSPI_SR_TXEMPTY BIT(2) 78 #define QSPI_SR_OVRES BIT(3) 79 #define QSPI_SR_CSR BIT(8) 80 #define QSPI_SR_CSS BIT(9) 81 #define QSPI_SR_INSTRE BIT(10) 82 #define QSPI_SR_QSPIENS BIT(24) 83 84 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR) 85 86 /* Bitfields in QSPI_SCR (Serial Clock Register) */ 87 #define QSPI_SCR_CPOL BIT(0) 88 #define QSPI_SCR_CPHA BIT(1) 89 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8) 90 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK) 91 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16) 92 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK) 93 94 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */ 95 #define QSPI_ICR_INST_MASK GENMASK(7, 0) 96 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK) 97 #define QSPI_ICR_OPT_MASK GENMASK(23, 16) 98 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK) 99 100 /* Bitfields in QSPI_IFR (Instruction Frame Register) */ 101 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0) 102 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0) 103 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0) 104 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0) 105 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0) 106 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0) 107 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0) 108 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0) 109 #define QSPI_IFR_INSTEN BIT(4) 110 #define QSPI_IFR_ADDREN BIT(5) 111 #define QSPI_IFR_OPTEN BIT(6) 112 #define QSPI_IFR_DATAEN BIT(7) 113 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8) 114 #define QSPI_IFR_OPTL_1BIT (0 << 8) 115 #define QSPI_IFR_OPTL_2BIT (1 << 8) 116 #define QSPI_IFR_OPTL_4BIT (2 << 8) 117 #define QSPI_IFR_OPTL_8BIT (3 << 8) 118 #define QSPI_IFR_ADDRL BIT(10) 119 #define QSPI_IFR_TFRTYP_MEM BIT(12) 120 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) 121 #define QSPI_IFR_CRM BIT(14) 122 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) 123 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK) 124 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */ 125 126 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */ 127 #define QSPI_SMR_SCREN BIT(0) 128 #define QSPI_SMR_RVDIS BIT(1) 129 130 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */ 131 #define QSPI_WPMR_WPEN BIT(0) 132 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8) 133 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK) 134 135 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */ 136 #define QSPI_WPSR_WPVS BIT(0) 137 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8) 138 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC) 139 140 struct atmel_qspi_caps { 141 bool has_qspick; 142 bool has_ricr; 143 }; 144 145 struct atmel_qspi { 146 void __iomem *regs; 147 void __iomem *mem; 148 struct clk *pclk; 149 struct clk *qspick; 150 struct platform_device *pdev; 151 const struct atmel_qspi_caps *caps; 152 resource_size_t mmap_size; 153 u32 pending; 154 u32 mr; 155 u32 scr; 156 struct completion cmd_completion; 157 }; 158 159 struct atmel_qspi_mode { 160 u8 cmd_buswidth; 161 u8 addr_buswidth; 162 u8 data_buswidth; 163 u32 config; 164 }; 165 166 static const struct atmel_qspi_mode atmel_qspi_modes[] = { 167 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI }, 168 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT }, 169 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT }, 170 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO }, 171 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO }, 172 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD }, 173 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, 174 }; 175 176 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, 177 const struct atmel_qspi_mode *mode) 178 { 179 if (op->cmd.buswidth != mode->cmd_buswidth) 180 return false; 181 182 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth) 183 return false; 184 185 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth) 186 return false; 187 188 return true; 189 } 190 191 static int atmel_qspi_find_mode(const struct spi_mem_op *op) 192 { 193 u32 i; 194 195 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++) 196 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i])) 197 return i; 198 199 return -ENOTSUPP; 200 } 201 202 static bool atmel_qspi_supports_op(struct spi_mem *mem, 203 const struct spi_mem_op *op) 204 { 205 if (atmel_qspi_find_mode(op) < 0) 206 return false; 207 208 /* special case not supported by hardware */ 209 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth && 210 op->dummy.nbytes == 0) 211 return false; 212 213 return true; 214 } 215 216 static int atmel_qspi_set_cfg(struct atmel_qspi *aq, 217 const struct spi_mem_op *op, u32 *offset) 218 { 219 u32 iar, icr, ifr; 220 u32 dummy_cycles = 0; 221 int mode; 222 223 iar = 0; 224 icr = QSPI_ICR_INST(op->cmd.opcode); 225 ifr = QSPI_IFR_INSTEN; 226 227 mode = atmel_qspi_find_mode(op); 228 if (mode < 0) 229 return mode; 230 ifr |= atmel_qspi_modes[mode].config; 231 232 if (op->dummy.buswidth && op->dummy.nbytes) 233 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; 234 235 /* 236 * The controller allows 24 and 32-bit addressing while NAND-flash 237 * requires 16-bit long. Handling 8-bit long addresses is done using 238 * the option field. For the 16-bit addresses, the workaround depends 239 * of the number of requested dummy bits. If there are 8 or more dummy 240 * cycles, the address is shifted and sent with the first dummy byte. 241 * Otherwise opcode is disabled and the first byte of the address 242 * contains the command opcode (works only if the opcode and address 243 * use the same buswidth). The limitation is when the 16-bit address is 244 * used without enough dummy cycles and the opcode is using a different 245 * buswidth than the address. 246 */ 247 if (op->addr.buswidth) { 248 switch (op->addr.nbytes) { 249 case 0: 250 break; 251 case 1: 252 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT; 253 icr |= QSPI_ICR_OPT(op->addr.val & 0xff); 254 break; 255 case 2: 256 if (dummy_cycles < 8 / op->addr.buswidth) { 257 ifr &= ~QSPI_IFR_INSTEN; 258 ifr |= QSPI_IFR_ADDREN; 259 iar = (op->cmd.opcode << 16) | 260 (op->addr.val & 0xffff); 261 } else { 262 ifr |= QSPI_IFR_ADDREN; 263 iar = (op->addr.val << 8) & 0xffffff; 264 dummy_cycles -= 8 / op->addr.buswidth; 265 } 266 break; 267 case 3: 268 ifr |= QSPI_IFR_ADDREN; 269 iar = op->addr.val & 0xffffff; 270 break; 271 case 4: 272 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL; 273 iar = op->addr.val & 0x7ffffff; 274 break; 275 default: 276 return -ENOTSUPP; 277 } 278 } 279 280 /* offset of the data access in the QSPI memory space */ 281 *offset = iar; 282 283 /* Set number of dummy cycles */ 284 if (dummy_cycles) 285 ifr |= QSPI_IFR_NBDUM(dummy_cycles); 286 287 /* Set data enable */ 288 if (op->data.nbytes) 289 ifr |= QSPI_IFR_DATAEN; 290 291 /* 292 * If the QSPI controller is set in regular SPI mode, set it in 293 * Serial Memory Mode (SMM). 294 */ 295 if (aq->mr != QSPI_MR_SMM) { 296 writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR); 297 aq->mr = QSPI_MR_SMM; 298 } 299 300 /* Clear pending interrupts */ 301 (void)readl_relaxed(aq->regs + QSPI_SR); 302 303 if (aq->caps->has_ricr) { 304 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN) 305 ifr |= QSPI_IFR_APBTFRTYP_READ; 306 307 /* Set QSPI Instruction Frame registers */ 308 writel_relaxed(iar, aq->regs + QSPI_IAR); 309 if (op->data.dir == SPI_MEM_DATA_IN) 310 writel_relaxed(icr, aq->regs + QSPI_RICR); 311 else 312 writel_relaxed(icr, aq->regs + QSPI_WICR); 313 writel_relaxed(ifr, aq->regs + QSPI_IFR); 314 } else { 315 if (op->data.dir == SPI_MEM_DATA_OUT) 316 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR; 317 318 /* Set QSPI Instruction Frame registers */ 319 writel_relaxed(iar, aq->regs + QSPI_IAR); 320 writel_relaxed(icr, aq->regs + QSPI_ICR); 321 writel_relaxed(ifr, aq->regs + QSPI_IFR); 322 } 323 324 return 0; 325 } 326 327 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 328 { 329 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master); 330 u32 sr, offset; 331 int err; 332 333 /* 334 * Check if the address exceeds the MMIO window size. An improvement 335 * would be to add support for regular SPI mode and fall back to it 336 * when the flash memories overrun the controller's memory space. 337 */ 338 if (op->addr.val + op->data.nbytes > aq->mmap_size) 339 return -ENOTSUPP; 340 341 err = atmel_qspi_set_cfg(aq, op, &offset); 342 if (err) 343 return err; 344 345 /* Skip to the final steps if there is no data */ 346 if (op->data.nbytes) { 347 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ 348 (void)readl_relaxed(aq->regs + QSPI_IFR); 349 350 /* Send/Receive data */ 351 if (op->data.dir == SPI_MEM_DATA_IN) 352 _memcpy_fromio(op->data.buf.in, aq->mem + offset, 353 op->data.nbytes); 354 else 355 _memcpy_toio(aq->mem + offset, op->data.buf.out, 356 op->data.nbytes); 357 358 /* Release the chip-select */ 359 writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR); 360 } 361 362 /* Poll INSTRuction End status */ 363 sr = readl_relaxed(aq->regs + QSPI_SR); 364 if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) 365 return err; 366 367 /* Wait for INSTRuction End interrupt */ 368 reinit_completion(&aq->cmd_completion); 369 aq->pending = sr & QSPI_SR_CMD_COMPLETED; 370 writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER); 371 if (!wait_for_completion_timeout(&aq->cmd_completion, 372 msecs_to_jiffies(1000))) 373 err = -ETIMEDOUT; 374 writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR); 375 376 return err; 377 } 378 379 static const char *atmel_qspi_get_name(struct spi_mem *spimem) 380 { 381 return dev_name(spimem->spi->dev.parent); 382 } 383 384 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = { 385 .supports_op = atmel_qspi_supports_op, 386 .exec_op = atmel_qspi_exec_op, 387 .get_name = atmel_qspi_get_name 388 }; 389 390 static int atmel_qspi_setup(struct spi_device *spi) 391 { 392 struct spi_controller *ctrl = spi->master; 393 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 394 unsigned long src_rate; 395 u32 scbr; 396 397 if (ctrl->busy) 398 return -EBUSY; 399 400 if (!spi->max_speed_hz) 401 return -EINVAL; 402 403 src_rate = clk_get_rate(aq->pclk); 404 if (!src_rate) 405 return -EINVAL; 406 407 /* Compute the QSPI baudrate */ 408 scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz); 409 if (scbr > 0) 410 scbr--; 411 412 aq->scr = QSPI_SCR_SCBR(scbr); 413 writel_relaxed(aq->scr, aq->regs + QSPI_SCR); 414 415 return 0; 416 } 417 418 static void atmel_qspi_init(struct atmel_qspi *aq) 419 { 420 /* Reset the QSPI controller */ 421 writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR); 422 423 /* Set the QSPI controller by default in Serial Memory Mode */ 424 writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR); 425 aq->mr = QSPI_MR_SMM; 426 427 /* Enable the QSPI controller */ 428 writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR); 429 } 430 431 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) 432 { 433 struct atmel_qspi *aq = dev_id; 434 u32 status, mask, pending; 435 436 status = readl_relaxed(aq->regs + QSPI_SR); 437 mask = readl_relaxed(aq->regs + QSPI_IMR); 438 pending = status & mask; 439 440 if (!pending) 441 return IRQ_NONE; 442 443 aq->pending |= pending; 444 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) 445 complete(&aq->cmd_completion); 446 447 return IRQ_HANDLED; 448 } 449 450 static int atmel_qspi_probe(struct platform_device *pdev) 451 { 452 struct spi_controller *ctrl; 453 struct atmel_qspi *aq; 454 struct resource *res; 455 int irq, err = 0; 456 457 ctrl = spi_alloc_master(&pdev->dev, sizeof(*aq)); 458 if (!ctrl) 459 return -ENOMEM; 460 461 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; 462 ctrl->setup = atmel_qspi_setup; 463 ctrl->bus_num = -1; 464 ctrl->mem_ops = &atmel_qspi_mem_ops; 465 ctrl->num_chipselect = 1; 466 ctrl->dev.of_node = pdev->dev.of_node; 467 platform_set_drvdata(pdev, ctrl); 468 469 aq = spi_controller_get_devdata(ctrl); 470 471 init_completion(&aq->cmd_completion); 472 aq->pdev = pdev; 473 474 /* Map the registers */ 475 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); 476 aq->regs = devm_ioremap_resource(&pdev->dev, res); 477 if (IS_ERR(aq->regs)) { 478 dev_err(&pdev->dev, "missing registers\n"); 479 err = PTR_ERR(aq->regs); 480 goto exit; 481 } 482 483 /* Map the AHB memory */ 484 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap"); 485 aq->mem = devm_ioremap_resource(&pdev->dev, res); 486 if (IS_ERR(aq->mem)) { 487 dev_err(&pdev->dev, "missing AHB memory\n"); 488 err = PTR_ERR(aq->mem); 489 goto exit; 490 } 491 492 aq->mmap_size = resource_size(res); 493 494 /* Get the peripheral clock */ 495 aq->pclk = devm_clk_get(&pdev->dev, "pclk"); 496 if (IS_ERR(aq->pclk)) 497 aq->pclk = devm_clk_get(&pdev->dev, NULL); 498 499 if (IS_ERR(aq->pclk)) { 500 dev_err(&pdev->dev, "missing peripheral clock\n"); 501 err = PTR_ERR(aq->pclk); 502 goto exit; 503 } 504 505 /* Enable the peripheral clock */ 506 err = clk_prepare_enable(aq->pclk); 507 if (err) { 508 dev_err(&pdev->dev, "failed to enable the peripheral clock\n"); 509 goto exit; 510 } 511 512 aq->caps = of_device_get_match_data(&pdev->dev); 513 if (!aq->caps) { 514 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n"); 515 err = -EINVAL; 516 goto exit; 517 } 518 519 if (aq->caps->has_qspick) { 520 /* Get the QSPI system clock */ 521 aq->qspick = devm_clk_get(&pdev->dev, "qspick"); 522 if (IS_ERR(aq->qspick)) { 523 dev_err(&pdev->dev, "missing system clock\n"); 524 err = PTR_ERR(aq->qspick); 525 goto disable_pclk; 526 } 527 528 /* Enable the QSPI system clock */ 529 err = clk_prepare_enable(aq->qspick); 530 if (err) { 531 dev_err(&pdev->dev, 532 "failed to enable the QSPI system clock\n"); 533 goto disable_pclk; 534 } 535 } 536 537 /* Request the IRQ */ 538 irq = platform_get_irq(pdev, 0); 539 if (irq < 0) { 540 err = irq; 541 goto disable_qspick; 542 } 543 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, 544 0, dev_name(&pdev->dev), aq); 545 if (err) 546 goto disable_qspick; 547 548 atmel_qspi_init(aq); 549 550 err = spi_register_controller(ctrl); 551 if (err) 552 goto disable_qspick; 553 554 return 0; 555 556 disable_qspick: 557 clk_disable_unprepare(aq->qspick); 558 disable_pclk: 559 clk_disable_unprepare(aq->pclk); 560 exit: 561 spi_controller_put(ctrl); 562 563 return err; 564 } 565 566 static int atmel_qspi_remove(struct platform_device *pdev) 567 { 568 struct spi_controller *ctrl = platform_get_drvdata(pdev); 569 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 570 571 spi_unregister_controller(ctrl); 572 writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR); 573 clk_disable_unprepare(aq->qspick); 574 clk_disable_unprepare(aq->pclk); 575 return 0; 576 } 577 578 static int __maybe_unused atmel_qspi_suspend(struct device *dev) 579 { 580 struct spi_controller *ctrl = dev_get_drvdata(dev); 581 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 582 583 clk_disable_unprepare(aq->qspick); 584 clk_disable_unprepare(aq->pclk); 585 586 return 0; 587 } 588 589 static int __maybe_unused atmel_qspi_resume(struct device *dev) 590 { 591 struct spi_controller *ctrl = dev_get_drvdata(dev); 592 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 593 594 clk_prepare_enable(aq->pclk); 595 clk_prepare_enable(aq->qspick); 596 597 atmel_qspi_init(aq); 598 599 writel_relaxed(aq->scr, aq->regs + QSPI_SCR); 600 601 return 0; 602 } 603 604 static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend, 605 atmel_qspi_resume); 606 607 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {}; 608 609 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = { 610 .has_qspick = true, 611 .has_ricr = true, 612 }; 613 614 static const struct of_device_id atmel_qspi_dt_ids[] = { 615 { 616 .compatible = "atmel,sama5d2-qspi", 617 .data = &atmel_sama5d2_qspi_caps, 618 }, 619 { 620 .compatible = "microchip,sam9x60-qspi", 621 .data = &atmel_sam9x60_qspi_caps, 622 }, 623 { /* sentinel */ } 624 }; 625 626 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids); 627 628 static struct platform_driver atmel_qspi_driver = { 629 .driver = { 630 .name = "atmel_qspi", 631 .of_match_table = atmel_qspi_dt_ids, 632 .pm = &atmel_qspi_pm_ops, 633 }, 634 .probe = atmel_qspi_probe, 635 .remove = atmel_qspi_remove, 636 }; 637 module_platform_driver(atmel_qspi_driver); 638 639 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>"); 640 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com"); 641 MODULE_DESCRIPTION("Atmel QSPI Controller driver"); 642 MODULE_LICENSE("GPL v2"); 643