1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Atmel QSPI Controller 4 * 5 * Copyright (C) 2015 Atmel Corporation 6 * Copyright (C) 2018 Cryptera A/S 7 * 8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com> 9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com> 10 * 11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_platform.h> 23 #include <linux/platform_device.h> 24 #include <linux/spi/spi-mem.h> 25 26 /* QSPI register offsets */ 27 #define QSPI_CR 0x0000 /* Control Register */ 28 #define QSPI_MR 0x0004 /* Mode Register */ 29 #define QSPI_RD 0x0008 /* Receive Data Register */ 30 #define QSPI_TD 0x000c /* Transmit Data Register */ 31 #define QSPI_SR 0x0010 /* Status Register */ 32 #define QSPI_IER 0x0014 /* Interrupt Enable Register */ 33 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */ 34 #define QSPI_IMR 0x001c /* Interrupt Mask Register */ 35 #define QSPI_SCR 0x0020 /* Serial Clock Register */ 36 37 #define QSPI_IAR 0x0030 /* Instruction Address Register */ 38 #define QSPI_ICR 0x0034 /* Instruction Code Register */ 39 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */ 40 #define QSPI_IFR 0x0038 /* Instruction Frame Register */ 41 #define QSPI_RICR 0x003C /* Read Instruction Code Register */ 42 43 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */ 44 #define QSPI_SKR 0x0044 /* Scrambling Key Register */ 45 46 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */ 47 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */ 48 49 #define QSPI_VERSION 0x00FC /* Version Register */ 50 51 52 /* Bitfields in QSPI_CR (Control Register) */ 53 #define QSPI_CR_QSPIEN BIT(0) 54 #define QSPI_CR_QSPIDIS BIT(1) 55 #define QSPI_CR_SWRST BIT(7) 56 #define QSPI_CR_LASTXFER BIT(24) 57 58 /* Bitfields in QSPI_MR (Mode Register) */ 59 #define QSPI_MR_SMM BIT(0) 60 #define QSPI_MR_LLB BIT(1) 61 #define QSPI_MR_WDRBT BIT(2) 62 #define QSPI_MR_SMRM BIT(3) 63 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4) 64 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4) 65 #define QSPI_MR_CSMODE_LASTXFER (1 << 4) 66 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4) 67 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8) 68 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK) 69 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16) 70 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK) 71 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24) 72 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK) 73 74 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */ 75 #define QSPI_SR_RDRF BIT(0) 76 #define QSPI_SR_TDRE BIT(1) 77 #define QSPI_SR_TXEMPTY BIT(2) 78 #define QSPI_SR_OVRES BIT(3) 79 #define QSPI_SR_CSR BIT(8) 80 #define QSPI_SR_CSS BIT(9) 81 #define QSPI_SR_INSTRE BIT(10) 82 #define QSPI_SR_QSPIENS BIT(24) 83 84 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR) 85 86 /* Bitfields in QSPI_SCR (Serial Clock Register) */ 87 #define QSPI_SCR_CPOL BIT(0) 88 #define QSPI_SCR_CPHA BIT(1) 89 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8) 90 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK) 91 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16) 92 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK) 93 94 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */ 95 #define QSPI_ICR_INST_MASK GENMASK(7, 0) 96 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK) 97 #define QSPI_ICR_OPT_MASK GENMASK(23, 16) 98 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK) 99 100 /* Bitfields in QSPI_IFR (Instruction Frame Register) */ 101 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0) 102 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0) 103 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0) 104 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0) 105 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0) 106 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0) 107 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0) 108 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0) 109 #define QSPI_IFR_INSTEN BIT(4) 110 #define QSPI_IFR_ADDREN BIT(5) 111 #define QSPI_IFR_OPTEN BIT(6) 112 #define QSPI_IFR_DATAEN BIT(7) 113 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8) 114 #define QSPI_IFR_OPTL_1BIT (0 << 8) 115 #define QSPI_IFR_OPTL_2BIT (1 << 8) 116 #define QSPI_IFR_OPTL_4BIT (2 << 8) 117 #define QSPI_IFR_OPTL_8BIT (3 << 8) 118 #define QSPI_IFR_ADDRL BIT(10) 119 #define QSPI_IFR_TFRTYP_MEM BIT(12) 120 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) 121 #define QSPI_IFR_CRM BIT(14) 122 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) 123 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK) 124 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */ 125 126 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */ 127 #define QSPI_SMR_SCREN BIT(0) 128 #define QSPI_SMR_RVDIS BIT(1) 129 130 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */ 131 #define QSPI_WPMR_WPEN BIT(0) 132 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8) 133 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK) 134 135 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */ 136 #define QSPI_WPSR_WPVS BIT(0) 137 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8) 138 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC) 139 140 struct atmel_qspi_caps { 141 bool has_qspick; 142 bool has_ricr; 143 }; 144 145 struct atmel_qspi { 146 void __iomem *regs; 147 void __iomem *mem; 148 struct clk *pclk; 149 struct clk *qspick; 150 struct platform_device *pdev; 151 const struct atmel_qspi_caps *caps; 152 resource_size_t mmap_size; 153 u32 pending; 154 u32 mr; 155 u32 scr; 156 struct completion cmd_completion; 157 }; 158 159 struct atmel_qspi_mode { 160 u8 cmd_buswidth; 161 u8 addr_buswidth; 162 u8 data_buswidth; 163 u32 config; 164 }; 165 166 static const struct atmel_qspi_mode atmel_qspi_modes[] = { 167 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI }, 168 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT }, 169 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT }, 170 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO }, 171 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO }, 172 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD }, 173 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, 174 }; 175 176 #ifdef VERBOSE_DEBUG 177 static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz) 178 { 179 switch (offset) { 180 case QSPI_CR: 181 return "CR"; 182 case QSPI_MR: 183 return "MR"; 184 case QSPI_RD: 185 return "MR"; 186 case QSPI_TD: 187 return "TD"; 188 case QSPI_SR: 189 return "SR"; 190 case QSPI_IER: 191 return "IER"; 192 case QSPI_IDR: 193 return "IDR"; 194 case QSPI_IMR: 195 return "IMR"; 196 case QSPI_SCR: 197 return "SCR"; 198 case QSPI_IAR: 199 return "IAR"; 200 case QSPI_ICR: 201 return "ICR/WICR"; 202 case QSPI_IFR: 203 return "IFR"; 204 case QSPI_RICR: 205 return "RICR"; 206 case QSPI_SMR: 207 return "SMR"; 208 case QSPI_SKR: 209 return "SKR"; 210 case QSPI_WPMR: 211 return "WPMR"; 212 case QSPI_WPSR: 213 return "WPSR"; 214 case QSPI_VERSION: 215 return "VERSION"; 216 default: 217 snprintf(tmp, sz, "0x%02x", offset); 218 break; 219 } 220 221 return tmp; 222 } 223 #endif /* VERBOSE_DEBUG */ 224 225 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset) 226 { 227 u32 value = readl_relaxed(aq->regs + offset); 228 229 #ifdef VERBOSE_DEBUG 230 char tmp[8]; 231 232 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value, 233 atmel_qspi_reg_name(offset, tmp, sizeof(tmp))); 234 #endif /* VERBOSE_DEBUG */ 235 236 return value; 237 } 238 239 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset) 240 { 241 #ifdef VERBOSE_DEBUG 242 char tmp[8]; 243 244 dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value, 245 atmel_qspi_reg_name(offset, tmp, sizeof(tmp))); 246 #endif /* VERBOSE_DEBUG */ 247 248 writel_relaxed(value, aq->regs + offset); 249 } 250 251 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, 252 const struct atmel_qspi_mode *mode) 253 { 254 if (op->cmd.buswidth != mode->cmd_buswidth) 255 return false; 256 257 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth) 258 return false; 259 260 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth) 261 return false; 262 263 return true; 264 } 265 266 static int atmel_qspi_find_mode(const struct spi_mem_op *op) 267 { 268 u32 i; 269 270 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++) 271 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i])) 272 return i; 273 274 return -ENOTSUPP; 275 } 276 277 static bool atmel_qspi_supports_op(struct spi_mem *mem, 278 const struct spi_mem_op *op) 279 { 280 if (!spi_mem_default_supports_op(mem, op)) 281 return false; 282 283 if (atmel_qspi_find_mode(op) < 0) 284 return false; 285 286 /* special case not supported by hardware */ 287 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth && 288 op->dummy.nbytes == 0) 289 return false; 290 291 /* DTR ops not supported. */ 292 if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) 293 return false; 294 if (op->cmd.nbytes != 1) 295 return false; 296 297 return true; 298 } 299 300 static int atmel_qspi_set_cfg(struct atmel_qspi *aq, 301 const struct spi_mem_op *op, u32 *offset) 302 { 303 u32 iar, icr, ifr; 304 u32 dummy_cycles = 0; 305 int mode; 306 307 iar = 0; 308 icr = QSPI_ICR_INST(op->cmd.opcode); 309 ifr = QSPI_IFR_INSTEN; 310 311 mode = atmel_qspi_find_mode(op); 312 if (mode < 0) 313 return mode; 314 ifr |= atmel_qspi_modes[mode].config; 315 316 if (op->dummy.nbytes) 317 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth; 318 319 /* 320 * The controller allows 24 and 32-bit addressing while NAND-flash 321 * requires 16-bit long. Handling 8-bit long addresses is done using 322 * the option field. For the 16-bit addresses, the workaround depends 323 * of the number of requested dummy bits. If there are 8 or more dummy 324 * cycles, the address is shifted and sent with the first dummy byte. 325 * Otherwise opcode is disabled and the first byte of the address 326 * contains the command opcode (works only if the opcode and address 327 * use the same buswidth). The limitation is when the 16-bit address is 328 * used without enough dummy cycles and the opcode is using a different 329 * buswidth than the address. 330 */ 331 if (op->addr.buswidth) { 332 switch (op->addr.nbytes) { 333 case 0: 334 break; 335 case 1: 336 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT; 337 icr |= QSPI_ICR_OPT(op->addr.val & 0xff); 338 break; 339 case 2: 340 if (dummy_cycles < 8 / op->addr.buswidth) { 341 ifr &= ~QSPI_IFR_INSTEN; 342 ifr |= QSPI_IFR_ADDREN; 343 iar = (op->cmd.opcode << 16) | 344 (op->addr.val & 0xffff); 345 } else { 346 ifr |= QSPI_IFR_ADDREN; 347 iar = (op->addr.val << 8) & 0xffffff; 348 dummy_cycles -= 8 / op->addr.buswidth; 349 } 350 break; 351 case 3: 352 ifr |= QSPI_IFR_ADDREN; 353 iar = op->addr.val & 0xffffff; 354 break; 355 case 4: 356 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL; 357 iar = op->addr.val & 0x7ffffff; 358 break; 359 default: 360 return -ENOTSUPP; 361 } 362 } 363 364 /* offset of the data access in the QSPI memory space */ 365 *offset = iar; 366 367 /* Set number of dummy cycles */ 368 if (dummy_cycles) 369 ifr |= QSPI_IFR_NBDUM(dummy_cycles); 370 371 /* Set data enable and data transfer type. */ 372 if (op->data.nbytes) { 373 ifr |= QSPI_IFR_DATAEN; 374 375 if (op->addr.nbytes) 376 ifr |= QSPI_IFR_TFRTYP_MEM; 377 } 378 379 /* 380 * If the QSPI controller is set in regular SPI mode, set it in 381 * Serial Memory Mode (SMM). 382 */ 383 if (aq->mr != QSPI_MR_SMM) { 384 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); 385 aq->mr = QSPI_MR_SMM; 386 } 387 388 /* Clear pending interrupts */ 389 (void)atmel_qspi_read(aq, QSPI_SR); 390 391 /* Set QSPI Instruction Frame registers. */ 392 if (op->addr.nbytes && !op->data.nbytes) 393 atmel_qspi_write(iar, aq, QSPI_IAR); 394 395 if (aq->caps->has_ricr) { 396 if (op->data.dir == SPI_MEM_DATA_IN) 397 atmel_qspi_write(icr, aq, QSPI_RICR); 398 else 399 atmel_qspi_write(icr, aq, QSPI_WICR); 400 } else { 401 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 402 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR; 403 404 atmel_qspi_write(icr, aq, QSPI_ICR); 405 } 406 407 atmel_qspi_write(ifr, aq, QSPI_IFR); 408 409 return 0; 410 } 411 412 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 413 { 414 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master); 415 u32 sr, offset; 416 int err; 417 418 /* 419 * Check if the address exceeds the MMIO window size. An improvement 420 * would be to add support for regular SPI mode and fall back to it 421 * when the flash memories overrun the controller's memory space. 422 */ 423 if (op->addr.val + op->data.nbytes > aq->mmap_size) 424 return -ENOTSUPP; 425 426 err = atmel_qspi_set_cfg(aq, op, &offset); 427 if (err) 428 return err; 429 430 /* Skip to the final steps if there is no data */ 431 if (op->data.nbytes) { 432 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ 433 (void)atmel_qspi_read(aq, QSPI_IFR); 434 435 /* Send/Receive data */ 436 if (op->data.dir == SPI_MEM_DATA_IN) 437 memcpy_fromio(op->data.buf.in, aq->mem + offset, 438 op->data.nbytes); 439 else 440 memcpy_toio(aq->mem + offset, op->data.buf.out, 441 op->data.nbytes); 442 443 /* Release the chip-select */ 444 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); 445 } 446 447 /* Poll INSTRuction End status */ 448 sr = atmel_qspi_read(aq, QSPI_SR); 449 if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) 450 return err; 451 452 /* Wait for INSTRuction End interrupt */ 453 reinit_completion(&aq->cmd_completion); 454 aq->pending = sr & QSPI_SR_CMD_COMPLETED; 455 atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER); 456 if (!wait_for_completion_timeout(&aq->cmd_completion, 457 msecs_to_jiffies(1000))) 458 err = -ETIMEDOUT; 459 atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR); 460 461 return err; 462 } 463 464 static const char *atmel_qspi_get_name(struct spi_mem *spimem) 465 { 466 return dev_name(spimem->spi->dev.parent); 467 } 468 469 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = { 470 .supports_op = atmel_qspi_supports_op, 471 .exec_op = atmel_qspi_exec_op, 472 .get_name = atmel_qspi_get_name 473 }; 474 475 static int atmel_qspi_setup(struct spi_device *spi) 476 { 477 struct spi_controller *ctrl = spi->master; 478 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 479 unsigned long src_rate; 480 u32 scbr; 481 482 if (ctrl->busy) 483 return -EBUSY; 484 485 if (!spi->max_speed_hz) 486 return -EINVAL; 487 488 src_rate = clk_get_rate(aq->pclk); 489 if (!src_rate) 490 return -EINVAL; 491 492 /* Compute the QSPI baudrate */ 493 scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz); 494 if (scbr > 0) 495 scbr--; 496 497 aq->scr = QSPI_SCR_SCBR(scbr); 498 atmel_qspi_write(aq->scr, aq, QSPI_SCR); 499 500 return 0; 501 } 502 503 static void atmel_qspi_init(struct atmel_qspi *aq) 504 { 505 /* Reset the QSPI controller */ 506 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); 507 508 /* Set the QSPI controller by default in Serial Memory Mode */ 509 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); 510 aq->mr = QSPI_MR_SMM; 511 512 /* Enable the QSPI controller */ 513 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); 514 } 515 516 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) 517 { 518 struct atmel_qspi *aq = dev_id; 519 u32 status, mask, pending; 520 521 status = atmel_qspi_read(aq, QSPI_SR); 522 mask = atmel_qspi_read(aq, QSPI_IMR); 523 pending = status & mask; 524 525 if (!pending) 526 return IRQ_NONE; 527 528 aq->pending |= pending; 529 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) 530 complete(&aq->cmd_completion); 531 532 return IRQ_HANDLED; 533 } 534 535 static int atmel_qspi_probe(struct platform_device *pdev) 536 { 537 struct spi_controller *ctrl; 538 struct atmel_qspi *aq; 539 struct resource *res; 540 int irq, err = 0; 541 542 ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*aq)); 543 if (!ctrl) 544 return -ENOMEM; 545 546 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; 547 ctrl->setup = atmel_qspi_setup; 548 ctrl->bus_num = -1; 549 ctrl->mem_ops = &atmel_qspi_mem_ops; 550 ctrl->num_chipselect = 1; 551 ctrl->dev.of_node = pdev->dev.of_node; 552 platform_set_drvdata(pdev, ctrl); 553 554 aq = spi_controller_get_devdata(ctrl); 555 556 init_completion(&aq->cmd_completion); 557 aq->pdev = pdev; 558 559 /* Map the registers */ 560 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); 561 aq->regs = devm_ioremap_resource(&pdev->dev, res); 562 if (IS_ERR(aq->regs)) { 563 dev_err(&pdev->dev, "missing registers\n"); 564 return PTR_ERR(aq->regs); 565 } 566 567 /* Map the AHB memory */ 568 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap"); 569 aq->mem = devm_ioremap_resource(&pdev->dev, res); 570 if (IS_ERR(aq->mem)) { 571 dev_err(&pdev->dev, "missing AHB memory\n"); 572 return PTR_ERR(aq->mem); 573 } 574 575 aq->mmap_size = resource_size(res); 576 577 /* Get the peripheral clock */ 578 aq->pclk = devm_clk_get(&pdev->dev, "pclk"); 579 if (IS_ERR(aq->pclk)) 580 aq->pclk = devm_clk_get(&pdev->dev, NULL); 581 582 if (IS_ERR(aq->pclk)) { 583 dev_err(&pdev->dev, "missing peripheral clock\n"); 584 return PTR_ERR(aq->pclk); 585 } 586 587 /* Enable the peripheral clock */ 588 err = clk_prepare_enable(aq->pclk); 589 if (err) { 590 dev_err(&pdev->dev, "failed to enable the peripheral clock\n"); 591 return err; 592 } 593 594 aq->caps = of_device_get_match_data(&pdev->dev); 595 if (!aq->caps) { 596 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n"); 597 err = -EINVAL; 598 goto disable_pclk; 599 } 600 601 if (aq->caps->has_qspick) { 602 /* Get the QSPI system clock */ 603 aq->qspick = devm_clk_get(&pdev->dev, "qspick"); 604 if (IS_ERR(aq->qspick)) { 605 dev_err(&pdev->dev, "missing system clock\n"); 606 err = PTR_ERR(aq->qspick); 607 goto disable_pclk; 608 } 609 610 /* Enable the QSPI system clock */ 611 err = clk_prepare_enable(aq->qspick); 612 if (err) { 613 dev_err(&pdev->dev, 614 "failed to enable the QSPI system clock\n"); 615 goto disable_pclk; 616 } 617 } 618 619 /* Request the IRQ */ 620 irq = platform_get_irq(pdev, 0); 621 if (irq < 0) { 622 err = irq; 623 goto disable_qspick; 624 } 625 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, 626 0, dev_name(&pdev->dev), aq); 627 if (err) 628 goto disable_qspick; 629 630 atmel_qspi_init(aq); 631 632 err = spi_register_controller(ctrl); 633 if (err) 634 goto disable_qspick; 635 636 return 0; 637 638 disable_qspick: 639 clk_disable_unprepare(aq->qspick); 640 disable_pclk: 641 clk_disable_unprepare(aq->pclk); 642 643 return err; 644 } 645 646 static int atmel_qspi_remove(struct platform_device *pdev) 647 { 648 struct spi_controller *ctrl = platform_get_drvdata(pdev); 649 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 650 651 spi_unregister_controller(ctrl); 652 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); 653 clk_disable_unprepare(aq->qspick); 654 clk_disable_unprepare(aq->pclk); 655 return 0; 656 } 657 658 static int __maybe_unused atmel_qspi_suspend(struct device *dev) 659 { 660 struct spi_controller *ctrl = dev_get_drvdata(dev); 661 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 662 663 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); 664 clk_disable_unprepare(aq->qspick); 665 clk_disable_unprepare(aq->pclk); 666 667 return 0; 668 } 669 670 static int __maybe_unused atmel_qspi_resume(struct device *dev) 671 { 672 struct spi_controller *ctrl = dev_get_drvdata(dev); 673 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); 674 675 clk_prepare_enable(aq->pclk); 676 clk_prepare_enable(aq->qspick); 677 678 atmel_qspi_init(aq); 679 680 atmel_qspi_write(aq->scr, aq, QSPI_SCR); 681 682 return 0; 683 } 684 685 static SIMPLE_DEV_PM_OPS(atmel_qspi_pm_ops, atmel_qspi_suspend, 686 atmel_qspi_resume); 687 688 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {}; 689 690 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = { 691 .has_qspick = true, 692 .has_ricr = true, 693 }; 694 695 static const struct of_device_id atmel_qspi_dt_ids[] = { 696 { 697 .compatible = "atmel,sama5d2-qspi", 698 .data = &atmel_sama5d2_qspi_caps, 699 }, 700 { 701 .compatible = "microchip,sam9x60-qspi", 702 .data = &atmel_sam9x60_qspi_caps, 703 }, 704 { /* sentinel */ } 705 }; 706 707 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids); 708 709 static struct platform_driver atmel_qspi_driver = { 710 .driver = { 711 .name = "atmel_qspi", 712 .of_match_table = atmel_qspi_dt_ids, 713 .pm = &atmel_qspi_pm_ops, 714 }, 715 .probe = atmel_qspi_probe, 716 .remove = atmel_qspi_remove, 717 }; 718 module_platform_driver(atmel_qspi_driver); 719 720 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>"); 721 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com"); 722 MODULE_DESCRIPTION("Atmel QSPI Controller driver"); 723 MODULE_LICENSE("GPL v2"); 724