189e59053SSanyog Kale // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 289e59053SSanyog Kale // Copyright(c) 2015-18 Intel Corporation. 389e59053SSanyog Kale 489e59053SSanyog Kale /* 589e59053SSanyog Kale * stream.c - SoundWire Bus stream operations. 689e59053SSanyog Kale */ 789e59053SSanyog Kale 889e59053SSanyog Kale #include <linux/delay.h> 989e59053SSanyog Kale #include <linux/device.h> 1089e59053SSanyog Kale #include <linux/init.h> 1189e59053SSanyog Kale #include <linux/module.h> 1289e59053SSanyog Kale #include <linux/mod_devicetable.h> 1389e59053SSanyog Kale #include <linux/slab.h> 14f8101c74SSanyog Kale #include <linux/soundwire/sdw_registers.h> 1589e59053SSanyog Kale #include <linux/soundwire/sdw.h> 164550569bSPierre-Louis Bossart #include <sound/soc.h> 1789e59053SSanyog Kale #include "bus.h" 1889e59053SSanyog Kale 1999b8a5d6SSanyog Kale /* 2099b8a5d6SSanyog Kale * Array of supported rows and columns as per MIPI SoundWire Specification 1.1 2199b8a5d6SSanyog Kale * 2299b8a5d6SSanyog Kale * The rows are arranged as per the array index value programmed 2399b8a5d6SSanyog Kale * in register. The index 15 has dummy value 0 in order to fill hole. 2499b8a5d6SSanyog Kale */ 25fe4b70f2SPierre-Louis Bossart int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147, 2699b8a5d6SSanyog Kale 96, 100, 120, 128, 150, 160, 250, 0, 2799b8a5d6SSanyog Kale 192, 200, 240, 256, 72, 144, 90, 180}; 289026118fSBard Liao EXPORT_SYMBOL(sdw_rows); 2999b8a5d6SSanyog Kale 30fe4b70f2SPierre-Louis Bossart int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16}; 319026118fSBard Liao EXPORT_SYMBOL(sdw_cols); 3299b8a5d6SSanyog Kale 33fe4b70f2SPierre-Louis Bossart int sdw_find_col_index(int col) 3499b8a5d6SSanyog Kale { 3599b8a5d6SSanyog Kale int i; 3699b8a5d6SSanyog Kale 3799b8a5d6SSanyog Kale for (i = 0; i < SDW_FRAME_COLS; i++) { 38fe4b70f2SPierre-Louis Bossart if (sdw_cols[i] == col) 3999b8a5d6SSanyog Kale return i; 4099b8a5d6SSanyog Kale } 4199b8a5d6SSanyog Kale 4299b8a5d6SSanyog Kale pr_warn("Requested column not found, selecting lowest column no: 2\n"); 4399b8a5d6SSanyog Kale return 0; 4499b8a5d6SSanyog Kale } 45fe4b70f2SPierre-Louis Bossart EXPORT_SYMBOL(sdw_find_col_index); 4699b8a5d6SSanyog Kale 47fe4b70f2SPierre-Louis Bossart int sdw_find_row_index(int row) 4899b8a5d6SSanyog Kale { 4999b8a5d6SSanyog Kale int i; 5099b8a5d6SSanyog Kale 5199b8a5d6SSanyog Kale for (i = 0; i < SDW_FRAME_ROWS; i++) { 52fe4b70f2SPierre-Louis Bossart if (sdw_rows[i] == row) 5399b8a5d6SSanyog Kale return i; 5499b8a5d6SSanyog Kale } 5599b8a5d6SSanyog Kale 5699b8a5d6SSanyog Kale pr_warn("Requested row not found, selecting lowest row no: 48\n"); 5799b8a5d6SSanyog Kale return 0; 5899b8a5d6SSanyog Kale } 59fe4b70f2SPierre-Louis Bossart EXPORT_SYMBOL(sdw_find_row_index); 60897fe40eSVinod Koul 61f8101c74SSanyog Kale static int _sdw_program_slave_port_params(struct sdw_bus *bus, 62f8101c74SSanyog Kale struct sdw_slave *slave, 63f8101c74SSanyog Kale struct sdw_transport_params *t_params, 64f8101c74SSanyog Kale enum sdw_dpn_type type) 65f8101c74SSanyog Kale { 66f8101c74SSanyog Kale u32 addr1, addr2, addr3, addr4; 67f8101c74SSanyog Kale int ret; 68f8101c74SSanyog Kale u16 wbuf; 69f8101c74SSanyog Kale 70f8101c74SSanyog Kale if (bus->params.next_bank) { 71f8101c74SSanyog Kale addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num); 72f8101c74SSanyog Kale addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num); 73f8101c74SSanyog Kale addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num); 74f8101c74SSanyog Kale addr4 = SDW_DPN_HCTRL_B1(t_params->port_num); 75f8101c74SSanyog Kale } else { 76f8101c74SSanyog Kale addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num); 77f8101c74SSanyog Kale addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num); 78f8101c74SSanyog Kale addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num); 79f8101c74SSanyog Kale addr4 = SDW_DPN_HCTRL_B0(t_params->port_num); 80f8101c74SSanyog Kale } 81f8101c74SSanyog Kale 82f8101c74SSanyog Kale /* Program DPN_OffsetCtrl2 registers */ 83f8101c74SSanyog Kale ret = sdw_write(slave, addr1, t_params->offset2); 84f8101c74SSanyog Kale if (ret < 0) { 8517ed5befSPierre-Louis Bossart dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n"); 86f8101c74SSanyog Kale return ret; 87f8101c74SSanyog Kale } 88f8101c74SSanyog Kale 89f8101c74SSanyog Kale /* Program DPN_BlockCtrl3 register */ 90f8101c74SSanyog Kale ret = sdw_write(slave, addr2, t_params->blk_pkg_mode); 91f8101c74SSanyog Kale if (ret < 0) { 9217ed5befSPierre-Louis Bossart dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n"); 93f8101c74SSanyog Kale return ret; 94f8101c74SSanyog Kale } 95f8101c74SSanyog Kale 96f8101c74SSanyog Kale /* 97f8101c74SSanyog Kale * Data ports are FULL, SIMPLE and REDUCED. This function handles 987d3b3cdfSVinod Koul * FULL and REDUCED only and beyond this point only FULL is 99f8101c74SSanyog Kale * handled, so bail out if we are not FULL data port type 100f8101c74SSanyog Kale */ 101f8101c74SSanyog Kale if (type != SDW_DPN_FULL) 102f8101c74SSanyog Kale return ret; 103f8101c74SSanyog Kale 104f8101c74SSanyog Kale /* Program DPN_SampleCtrl2 register */ 10541ff9174SVinod Koul wbuf = FIELD_GET(SDW_DPN_SAMPLECTRL_HIGH, t_params->sample_interval - 1); 106f8101c74SSanyog Kale 107f8101c74SSanyog Kale ret = sdw_write(slave, addr3, wbuf); 108f8101c74SSanyog Kale if (ret < 0) { 10917ed5befSPierre-Louis Bossart dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n"); 110f8101c74SSanyog Kale return ret; 111f8101c74SSanyog Kale } 112f8101c74SSanyog Kale 113f8101c74SSanyog Kale /* Program DPN_HCtrl register */ 11441ff9174SVinod Koul wbuf = FIELD_PREP(SDW_DPN_HCTRL_HSTART, t_params->hstart); 11541ff9174SVinod Koul wbuf |= FIELD_PREP(SDW_DPN_HCTRL_HSTOP, t_params->hstop); 116f8101c74SSanyog Kale 117f8101c74SSanyog Kale ret = sdw_write(slave, addr4, wbuf); 118f8101c74SSanyog Kale if (ret < 0) 11917ed5befSPierre-Louis Bossart dev_err(bus->dev, "DPN_HCtrl register write failed\n"); 120f8101c74SSanyog Kale 121f8101c74SSanyog Kale return ret; 122f8101c74SSanyog Kale } 123f8101c74SSanyog Kale 124f8101c74SSanyog Kale static int sdw_program_slave_port_params(struct sdw_bus *bus, 125f8101c74SSanyog Kale struct sdw_slave_runtime *s_rt, 126f8101c74SSanyog Kale struct sdw_port_runtime *p_rt) 127f8101c74SSanyog Kale { 128f8101c74SSanyog Kale struct sdw_transport_params *t_params = &p_rt->transport_params; 129f8101c74SSanyog Kale struct sdw_port_params *p_params = &p_rt->port_params; 130f8101c74SSanyog Kale struct sdw_slave_prop *slave_prop = &s_rt->slave->prop; 131f8101c74SSanyog Kale u32 addr1, addr2, addr3, addr4, addr5, addr6; 132f8101c74SSanyog Kale struct sdw_dpn_prop *dpn_prop; 133f8101c74SSanyog Kale int ret; 134f8101c74SSanyog Kale u8 wbuf; 135f8101c74SSanyog Kale 13624f08b3aSBard Liao if (s_rt->slave->is_mockup_device) 13724f08b3aSBard Liao return 0; 13824f08b3aSBard Liao 139f8101c74SSanyog Kale dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave, 140f8101c74SSanyog Kale s_rt->direction, 141f8101c74SSanyog Kale t_params->port_num); 142f8101c74SSanyog Kale if (!dpn_prop) 143f8101c74SSanyog Kale return -EINVAL; 144f8101c74SSanyog Kale 145f8101c74SSanyog Kale addr1 = SDW_DPN_PORTCTRL(t_params->port_num); 146f8101c74SSanyog Kale addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num); 147f8101c74SSanyog Kale 148f8101c74SSanyog Kale if (bus->params.next_bank) { 149f8101c74SSanyog Kale addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num); 150f8101c74SSanyog Kale addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num); 151f8101c74SSanyog Kale addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num); 152f8101c74SSanyog Kale addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num); 153f8101c74SSanyog Kale 154f8101c74SSanyog Kale } else { 155f8101c74SSanyog Kale addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num); 156f8101c74SSanyog Kale addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num); 157f8101c74SSanyog Kale addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num); 158f8101c74SSanyog Kale addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num); 159f8101c74SSanyog Kale } 160f8101c74SSanyog Kale 161f8101c74SSanyog Kale /* Program DPN_PortCtrl register */ 16241ff9174SVinod Koul wbuf = FIELD_PREP(SDW_DPN_PORTCTRL_DATAMODE, p_params->data_mode); 16341ff9174SVinod Koul wbuf |= FIELD_PREP(SDW_DPN_PORTCTRL_FLOWMODE, p_params->flow_mode); 164f8101c74SSanyog Kale 165f8101c74SSanyog Kale ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf); 166f8101c74SSanyog Kale if (ret < 0) { 167f8101c74SSanyog Kale dev_err(&s_rt->slave->dev, 16817ed5befSPierre-Louis Bossart "DPN_PortCtrl register write failed for port %d\n", 169f8101c74SSanyog Kale t_params->port_num); 170f8101c74SSanyog Kale return ret; 171f8101c74SSanyog Kale } 172f8101c74SSanyog Kale 173a9107de4SSrinivas Kandagatla if (!dpn_prop->read_only_wordlength) { 174f8101c74SSanyog Kale /* Program DPN_BlockCtrl1 register */ 175f8101c74SSanyog Kale ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1)); 176f8101c74SSanyog Kale if (ret < 0) { 177f8101c74SSanyog Kale dev_err(&s_rt->slave->dev, 17817ed5befSPierre-Louis Bossart "DPN_BlockCtrl1 register write failed for port %d\n", 179f8101c74SSanyog Kale t_params->port_num); 180f8101c74SSanyog Kale return ret; 181f8101c74SSanyog Kale } 182a9107de4SSrinivas Kandagatla } 183f8101c74SSanyog Kale 184f8101c74SSanyog Kale /* Program DPN_SampleCtrl1 register */ 185f8101c74SSanyog Kale wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW; 186f8101c74SSanyog Kale ret = sdw_write(s_rt->slave, addr3, wbuf); 187f8101c74SSanyog Kale if (ret < 0) { 188f8101c74SSanyog Kale dev_err(&s_rt->slave->dev, 18917ed5befSPierre-Louis Bossart "DPN_SampleCtrl1 register write failed for port %d\n", 190f8101c74SSanyog Kale t_params->port_num); 191f8101c74SSanyog Kale return ret; 192f8101c74SSanyog Kale } 193f8101c74SSanyog Kale 194f8101c74SSanyog Kale /* Program DPN_OffsetCtrl1 registers */ 195f8101c74SSanyog Kale ret = sdw_write(s_rt->slave, addr4, t_params->offset1); 196f8101c74SSanyog Kale if (ret < 0) { 197f8101c74SSanyog Kale dev_err(&s_rt->slave->dev, 19817ed5befSPierre-Louis Bossart "DPN_OffsetCtrl1 register write failed for port %d\n", 199f8101c74SSanyog Kale t_params->port_num); 200f8101c74SSanyog Kale return ret; 201f8101c74SSanyog Kale } 202f8101c74SSanyog Kale 203f8101c74SSanyog Kale /* Program DPN_BlockCtrl2 register*/ 204f8101c74SSanyog Kale if (t_params->blk_grp_ctrl_valid) { 205f8101c74SSanyog Kale ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl); 206f8101c74SSanyog Kale if (ret < 0) { 207f8101c74SSanyog Kale dev_err(&s_rt->slave->dev, 20817ed5befSPierre-Louis Bossart "DPN_BlockCtrl2 reg write failed for port %d\n", 209f8101c74SSanyog Kale t_params->port_num); 210f8101c74SSanyog Kale return ret; 211f8101c74SSanyog Kale } 212f8101c74SSanyog Kale } 213f8101c74SSanyog Kale 214f8101c74SSanyog Kale /* program DPN_LaneCtrl register */ 215f8101c74SSanyog Kale if (slave_prop->lane_control_support) { 216f8101c74SSanyog Kale ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl); 217f8101c74SSanyog Kale if (ret < 0) { 218f8101c74SSanyog Kale dev_err(&s_rt->slave->dev, 21917ed5befSPierre-Louis Bossart "DPN_LaneCtrl register write failed for port %d\n", 220f8101c74SSanyog Kale t_params->port_num); 221f8101c74SSanyog Kale return ret; 222f8101c74SSanyog Kale } 223f8101c74SSanyog Kale } 224f8101c74SSanyog Kale 225f8101c74SSanyog Kale if (dpn_prop->type != SDW_DPN_SIMPLE) { 226f8101c74SSanyog Kale ret = _sdw_program_slave_port_params(bus, s_rt->slave, 227f8101c74SSanyog Kale t_params, dpn_prop->type); 228f8101c74SSanyog Kale if (ret < 0) 229f8101c74SSanyog Kale dev_err(&s_rt->slave->dev, 23017ed5befSPierre-Louis Bossart "Transport reg write failed for port: %d\n", 231f8101c74SSanyog Kale t_params->port_num); 232f8101c74SSanyog Kale } 233f8101c74SSanyog Kale 234f8101c74SSanyog Kale return ret; 235f8101c74SSanyog Kale } 236f8101c74SSanyog Kale 237f8101c74SSanyog Kale static int sdw_program_master_port_params(struct sdw_bus *bus, 238f8101c74SSanyog Kale struct sdw_port_runtime *p_rt) 239f8101c74SSanyog Kale { 240f8101c74SSanyog Kale int ret; 241f8101c74SSanyog Kale 242f8101c74SSanyog Kale /* 243f8101c74SSanyog Kale * we need to set transport and port parameters for the port. 2447d3b3cdfSVinod Koul * Transport parameters refers to the sample interval, offsets and 245f8101c74SSanyog Kale * hstart/stop etc of the data. Port parameters refers to word 246f8101c74SSanyog Kale * length, flow mode etc of the port 247f8101c74SSanyog Kale */ 248f8101c74SSanyog Kale ret = bus->port_ops->dpn_set_port_transport_params(bus, 249f8101c74SSanyog Kale &p_rt->transport_params, 250f8101c74SSanyog Kale bus->params.next_bank); 251f8101c74SSanyog Kale if (ret < 0) 252f8101c74SSanyog Kale return ret; 253f8101c74SSanyog Kale 254f8101c74SSanyog Kale return bus->port_ops->dpn_set_port_params(bus, 255f8101c74SSanyog Kale &p_rt->port_params, 256f8101c74SSanyog Kale bus->params.next_bank); 257f8101c74SSanyog Kale } 258f8101c74SSanyog Kale 259f8101c74SSanyog Kale /** 260f8101c74SSanyog Kale * sdw_program_port_params() - Programs transport parameters of Master(s) 261f8101c74SSanyog Kale * and Slave(s) 262f8101c74SSanyog Kale * 263f8101c74SSanyog Kale * @m_rt: Master stream runtime 264f8101c74SSanyog Kale */ 265f8101c74SSanyog Kale static int sdw_program_port_params(struct sdw_master_runtime *m_rt) 266f8101c74SSanyog Kale { 2675920a29dSPierre-Louis Bossart struct sdw_slave_runtime *s_rt; 268f8101c74SSanyog Kale struct sdw_bus *bus = m_rt->bus; 269f8101c74SSanyog Kale struct sdw_port_runtime *p_rt; 270f8101c74SSanyog Kale int ret = 0; 271f8101c74SSanyog Kale 272f8101c74SSanyog Kale /* Program transport & port parameters for Slave(s) */ 273f8101c74SSanyog Kale list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 274f8101c74SSanyog Kale list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 275f8101c74SSanyog Kale ret = sdw_program_slave_port_params(bus, s_rt, p_rt); 276f8101c74SSanyog Kale if (ret < 0) 277f8101c74SSanyog Kale return ret; 278f8101c74SSanyog Kale } 279f8101c74SSanyog Kale } 280f8101c74SSanyog Kale 281f8101c74SSanyog Kale /* Program transport & port parameters for Master(s) */ 282f8101c74SSanyog Kale list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 283f8101c74SSanyog Kale ret = sdw_program_master_port_params(bus, p_rt); 284f8101c74SSanyog Kale if (ret < 0) 285f8101c74SSanyog Kale return ret; 286f8101c74SSanyog Kale } 287f8101c74SSanyog Kale 288f8101c74SSanyog Kale return 0; 289f8101c74SSanyog Kale } 290f8101c74SSanyog Kale 29189e59053SSanyog Kale /** 29279df15b7SSanyog Kale * sdw_enable_disable_slave_ports: Enable/disable slave data port 29379df15b7SSanyog Kale * 29479df15b7SSanyog Kale * @bus: bus instance 29579df15b7SSanyog Kale * @s_rt: slave runtime 29679df15b7SSanyog Kale * @p_rt: port runtime 29779df15b7SSanyog Kale * @en: enable or disable operation 29879df15b7SSanyog Kale * 29979df15b7SSanyog Kale * This function only sets the enable/disable bits in the relevant bank, the 30079df15b7SSanyog Kale * actual enable/disable is done with a bank switch 30179df15b7SSanyog Kale */ 30279df15b7SSanyog Kale static int sdw_enable_disable_slave_ports(struct sdw_bus *bus, 30379df15b7SSanyog Kale struct sdw_slave_runtime *s_rt, 3041fe74a5eSPierre-Louis Bossart struct sdw_port_runtime *p_rt, 3051fe74a5eSPierre-Louis Bossart bool en) 30679df15b7SSanyog Kale { 30779df15b7SSanyog Kale struct sdw_transport_params *t_params = &p_rt->transport_params; 30879df15b7SSanyog Kale u32 addr; 30979df15b7SSanyog Kale int ret; 31079df15b7SSanyog Kale 31179df15b7SSanyog Kale if (bus->params.next_bank) 31279df15b7SSanyog Kale addr = SDW_DPN_CHANNELEN_B1(p_rt->num); 31379df15b7SSanyog Kale else 31479df15b7SSanyog Kale addr = SDW_DPN_CHANNELEN_B0(p_rt->num); 31579df15b7SSanyog Kale 31679df15b7SSanyog Kale /* 31779df15b7SSanyog Kale * Since bus doesn't support sharing a port across two streams, 31879df15b7SSanyog Kale * it is safe to reset this register 31979df15b7SSanyog Kale */ 32079df15b7SSanyog Kale if (en) 3210b43fef9SSrinivas Kandagatla ret = sdw_write(s_rt->slave, addr, p_rt->ch_mask); 32279df15b7SSanyog Kale else 3230b43fef9SSrinivas Kandagatla ret = sdw_write(s_rt->slave, addr, 0x0); 32479df15b7SSanyog Kale 32579df15b7SSanyog Kale if (ret < 0) 32679df15b7SSanyog Kale dev_err(&s_rt->slave->dev, 32717ed5befSPierre-Louis Bossart "Slave chn_en reg write failed:%d port:%d\n", 32879df15b7SSanyog Kale ret, t_params->port_num); 32979df15b7SSanyog Kale 33079df15b7SSanyog Kale return ret; 33179df15b7SSanyog Kale } 33279df15b7SSanyog Kale 33379df15b7SSanyog Kale static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt, 3341fe74a5eSPierre-Louis Bossart struct sdw_port_runtime *p_rt, 3351fe74a5eSPierre-Louis Bossart bool en) 33679df15b7SSanyog Kale { 33779df15b7SSanyog Kale struct sdw_transport_params *t_params = &p_rt->transport_params; 33879df15b7SSanyog Kale struct sdw_bus *bus = m_rt->bus; 33979df15b7SSanyog Kale struct sdw_enable_ch enable_ch; 340a25eab29SPierre-Louis Bossart int ret; 34179df15b7SSanyog Kale 34279df15b7SSanyog Kale enable_ch.port_num = p_rt->num; 34379df15b7SSanyog Kale enable_ch.ch_mask = p_rt->ch_mask; 34479df15b7SSanyog Kale enable_ch.enable = en; 34579df15b7SSanyog Kale 34679df15b7SSanyog Kale /* Perform Master port channel(s) enable/disable */ 34779df15b7SSanyog Kale if (bus->port_ops->dpn_port_enable_ch) { 34879df15b7SSanyog Kale ret = bus->port_ops->dpn_port_enable_ch(bus, 3491fe74a5eSPierre-Louis Bossart &enable_ch, 3501fe74a5eSPierre-Louis Bossart bus->params.next_bank); 35179df15b7SSanyog Kale if (ret < 0) { 35279df15b7SSanyog Kale dev_err(bus->dev, 35317ed5befSPierre-Louis Bossart "Master chn_en write failed:%d port:%d\n", 35479df15b7SSanyog Kale ret, t_params->port_num); 35579df15b7SSanyog Kale return ret; 35679df15b7SSanyog Kale } 35779df15b7SSanyog Kale } else { 35879df15b7SSanyog Kale dev_err(bus->dev, 35979df15b7SSanyog Kale "dpn_port_enable_ch not supported, %s failed\n", 36079df15b7SSanyog Kale en ? "enable" : "disable"); 36179df15b7SSanyog Kale return -EINVAL; 36279df15b7SSanyog Kale } 36379df15b7SSanyog Kale 36479df15b7SSanyog Kale return 0; 36579df15b7SSanyog Kale } 36679df15b7SSanyog Kale 36779df15b7SSanyog Kale /** 36879df15b7SSanyog Kale * sdw_enable_disable_ports() - Enable/disable port(s) for Master and 36979df15b7SSanyog Kale * Slave(s) 37079df15b7SSanyog Kale * 37179df15b7SSanyog Kale * @m_rt: Master stream runtime 37279df15b7SSanyog Kale * @en: mode (enable/disable) 37379df15b7SSanyog Kale */ 37479df15b7SSanyog Kale static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en) 37579df15b7SSanyog Kale { 37679df15b7SSanyog Kale struct sdw_port_runtime *s_port, *m_port; 3773a0be1a6SPierre-Louis Bossart struct sdw_slave_runtime *s_rt; 37879df15b7SSanyog Kale int ret = 0; 37979df15b7SSanyog Kale 38079df15b7SSanyog Kale /* Enable/Disable Slave port(s) */ 38179df15b7SSanyog Kale list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 38279df15b7SSanyog Kale list_for_each_entry(s_port, &s_rt->port_list, port_node) { 38379df15b7SSanyog Kale ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt, 38479df15b7SSanyog Kale s_port, en); 38579df15b7SSanyog Kale if (ret < 0) 38679df15b7SSanyog Kale return ret; 38779df15b7SSanyog Kale } 38879df15b7SSanyog Kale } 38979df15b7SSanyog Kale 39079df15b7SSanyog Kale /* Enable/Disable Master port(s) */ 39179df15b7SSanyog Kale list_for_each_entry(m_port, &m_rt->port_list, port_node) { 39279df15b7SSanyog Kale ret = sdw_enable_disable_master_ports(m_rt, m_port, en); 39379df15b7SSanyog Kale if (ret < 0) 39479df15b7SSanyog Kale return ret; 39579df15b7SSanyog Kale } 39679df15b7SSanyog Kale 39779df15b7SSanyog Kale return 0; 39879df15b7SSanyog Kale } 39979df15b7SSanyog Kale 40079df15b7SSanyog Kale static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt, 4011fe74a5eSPierre-Louis Bossart struct sdw_prepare_ch prep_ch, 4021fe74a5eSPierre-Louis Bossart enum sdw_port_prep_ops cmd) 40379df15b7SSanyog Kale { 40479df15b7SSanyog Kale const struct sdw_slave_ops *ops = s_rt->slave->ops; 40579df15b7SSanyog Kale int ret; 40679df15b7SSanyog Kale 40779df15b7SSanyog Kale if (ops->port_prep) { 40879df15b7SSanyog Kale ret = ops->port_prep(s_rt->slave, &prep_ch, cmd); 40979df15b7SSanyog Kale if (ret < 0) { 41079df15b7SSanyog Kale dev_err(&s_rt->slave->dev, 41162f0cec3SVinod Koul "Slave Port Prep cmd %d failed: %d\n", 41262f0cec3SVinod Koul cmd, ret); 41379df15b7SSanyog Kale return ret; 41479df15b7SSanyog Kale } 41579df15b7SSanyog Kale } 41679df15b7SSanyog Kale 41779df15b7SSanyog Kale return 0; 41879df15b7SSanyog Kale } 41979df15b7SSanyog Kale 42079df15b7SSanyog Kale static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus, 42179df15b7SSanyog Kale struct sdw_slave_runtime *s_rt, 4221fe74a5eSPierre-Louis Bossart struct sdw_port_runtime *p_rt, 4231fe74a5eSPierre-Louis Bossart bool prep) 42479df15b7SSanyog Kale { 4253a0be1a6SPierre-Louis Bossart struct completion *port_ready; 42679df15b7SSanyog Kale struct sdw_dpn_prop *dpn_prop; 42779df15b7SSanyog Kale struct sdw_prepare_ch prep_ch; 42879df15b7SSanyog Kale bool intr = false; 42979df15b7SSanyog Kale int ret = 0, val; 43079df15b7SSanyog Kale u32 addr; 43179df15b7SSanyog Kale 43279df15b7SSanyog Kale prep_ch.num = p_rt->num; 43379df15b7SSanyog Kale prep_ch.ch_mask = p_rt->ch_mask; 43479df15b7SSanyog Kale 43579df15b7SSanyog Kale dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave, 43679df15b7SSanyog Kale s_rt->direction, 43779df15b7SSanyog Kale prep_ch.num); 43879df15b7SSanyog Kale if (!dpn_prop) { 43979df15b7SSanyog Kale dev_err(bus->dev, 44017ed5befSPierre-Louis Bossart "Slave Port:%d properties not found\n", prep_ch.num); 44179df15b7SSanyog Kale return -EINVAL; 44279df15b7SSanyog Kale } 44379df15b7SSanyog Kale 44479df15b7SSanyog Kale prep_ch.prepare = prep; 44579df15b7SSanyog Kale 44679df15b7SSanyog Kale prep_ch.bank = bus->params.next_bank; 44779df15b7SSanyog Kale 448dd87a72aSPierre-Louis Bossart if (dpn_prop->imp_def_interrupts || !dpn_prop->simple_ch_prep_sm || 449dd87a72aSPierre-Louis Bossart bus->params.s_data_mode != SDW_PORT_DATA_MODE_NORMAL) 45079df15b7SSanyog Kale intr = true; 45179df15b7SSanyog Kale 45279df15b7SSanyog Kale /* 45379df15b7SSanyog Kale * Enable interrupt before Port prepare. 45479df15b7SSanyog Kale * For Port de-prepare, it is assumed that port 45579df15b7SSanyog Kale * was prepared earlier 45679df15b7SSanyog Kale */ 45779df15b7SSanyog Kale if (prep && intr) { 45879df15b7SSanyog Kale ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep, 4598acbbfecSPierre-Louis Bossart dpn_prop->imp_def_interrupts); 46079df15b7SSanyog Kale if (ret < 0) 46179df15b7SSanyog Kale return ret; 46279df15b7SSanyog Kale } 46379df15b7SSanyog Kale 46479df15b7SSanyog Kale /* Inform slave about the impending port prepare */ 46579df15b7SSanyog Kale sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP); 46679df15b7SSanyog Kale 46779df15b7SSanyog Kale /* Prepare Slave port implementing CP_SM */ 46879df15b7SSanyog Kale if (!dpn_prop->simple_ch_prep_sm) { 46979df15b7SSanyog Kale addr = SDW_DPN_PREPARECTRL(p_rt->num); 47079df15b7SSanyog Kale 47179df15b7SSanyog Kale if (prep) 4720b43fef9SSrinivas Kandagatla ret = sdw_write(s_rt->slave, addr, p_rt->ch_mask); 47379df15b7SSanyog Kale else 4740b43fef9SSrinivas Kandagatla ret = sdw_write(s_rt->slave, addr, 0x0); 47579df15b7SSanyog Kale 47679df15b7SSanyog Kale if (ret < 0) { 47779df15b7SSanyog Kale dev_err(&s_rt->slave->dev, 47817ed5befSPierre-Louis Bossart "Slave prep_ctrl reg write failed\n"); 47979df15b7SSanyog Kale return ret; 48079df15b7SSanyog Kale } 48179df15b7SSanyog Kale 48279df15b7SSanyog Kale /* Wait for completion on port ready */ 48379df15b7SSanyog Kale port_ready = &s_rt->slave->port_ready[prep_ch.num]; 4843d3e88e3SRichard Fitzgerald wait_for_completion_timeout(port_ready, 48579df15b7SSanyog Kale msecs_to_jiffies(dpn_prop->ch_prep_timeout)); 48679df15b7SSanyog Kale 48779df15b7SSanyog Kale val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num)); 4883d3e88e3SRichard Fitzgerald if ((val < 0) || (val & p_rt->ch_mask)) { 4893d3e88e3SRichard Fitzgerald ret = (val < 0) ? val : -ETIMEDOUT; 49079df15b7SSanyog Kale dev_err(&s_rt->slave->dev, 4913d3e88e3SRichard Fitzgerald "Chn prep failed for port %d: %d\n", prep_ch.num, ret); 4923d3e88e3SRichard Fitzgerald return ret; 49379df15b7SSanyog Kale } 49479df15b7SSanyog Kale } 49579df15b7SSanyog Kale 49679df15b7SSanyog Kale /* Inform slaves about ports prepared */ 49779df15b7SSanyog Kale sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP); 49879df15b7SSanyog Kale 49979df15b7SSanyog Kale /* Disable interrupt after Port de-prepare */ 50079df15b7SSanyog Kale if (!prep && intr) 50179df15b7SSanyog Kale ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep, 5028acbbfecSPierre-Louis Bossart dpn_prop->imp_def_interrupts); 50379df15b7SSanyog Kale 50479df15b7SSanyog Kale return ret; 50579df15b7SSanyog Kale } 50679df15b7SSanyog Kale 50779df15b7SSanyog Kale static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt, 5081fe74a5eSPierre-Louis Bossart struct sdw_port_runtime *p_rt, 5091fe74a5eSPierre-Louis Bossart bool prep) 51079df15b7SSanyog Kale { 51179df15b7SSanyog Kale struct sdw_transport_params *t_params = &p_rt->transport_params; 51279df15b7SSanyog Kale struct sdw_bus *bus = m_rt->bus; 51379df15b7SSanyog Kale const struct sdw_master_port_ops *ops = bus->port_ops; 51479df15b7SSanyog Kale struct sdw_prepare_ch prep_ch; 51579df15b7SSanyog Kale int ret = 0; 51679df15b7SSanyog Kale 51779df15b7SSanyog Kale prep_ch.num = p_rt->num; 51879df15b7SSanyog Kale prep_ch.ch_mask = p_rt->ch_mask; 51979df15b7SSanyog Kale prep_ch.prepare = prep; /* Prepare/De-prepare */ 52079df15b7SSanyog Kale prep_ch.bank = bus->params.next_bank; 52179df15b7SSanyog Kale 52279df15b7SSanyog Kale /* Pre-prepare/Pre-deprepare port(s) */ 52379df15b7SSanyog Kale if (ops->dpn_port_prep) { 52479df15b7SSanyog Kale ret = ops->dpn_port_prep(bus, &prep_ch); 52579df15b7SSanyog Kale if (ret < 0) { 52617ed5befSPierre-Louis Bossart dev_err(bus->dev, "Port prepare failed for port:%d\n", 52779df15b7SSanyog Kale t_params->port_num); 52879df15b7SSanyog Kale return ret; 52979df15b7SSanyog Kale } 53079df15b7SSanyog Kale } 53179df15b7SSanyog Kale 53279df15b7SSanyog Kale return ret; 53379df15b7SSanyog Kale } 53479df15b7SSanyog Kale 53579df15b7SSanyog Kale /** 53679df15b7SSanyog Kale * sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and 53779df15b7SSanyog Kale * Slave(s) 53879df15b7SSanyog Kale * 53979df15b7SSanyog Kale * @m_rt: Master runtime handle 54079df15b7SSanyog Kale * @prep: Prepare or De-prepare 54179df15b7SSanyog Kale */ 54279df15b7SSanyog Kale static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep) 54379df15b7SSanyog Kale { 5443a0be1a6SPierre-Louis Bossart struct sdw_slave_runtime *s_rt; 54579df15b7SSanyog Kale struct sdw_port_runtime *p_rt; 54679df15b7SSanyog Kale int ret = 0; 54779df15b7SSanyog Kale 54879df15b7SSanyog Kale /* Prepare/De-prepare Slave port(s) */ 54979df15b7SSanyog Kale list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 55079df15b7SSanyog Kale list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 55179df15b7SSanyog Kale ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt, 55279df15b7SSanyog Kale p_rt, prep); 55379df15b7SSanyog Kale if (ret < 0) 55479df15b7SSanyog Kale return ret; 55579df15b7SSanyog Kale } 55679df15b7SSanyog Kale } 55779df15b7SSanyog Kale 55879df15b7SSanyog Kale /* Prepare/De-prepare Master port(s) */ 55979df15b7SSanyog Kale list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 56079df15b7SSanyog Kale ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep); 56179df15b7SSanyog Kale if (ret < 0) 56279df15b7SSanyog Kale return ret; 56379df15b7SSanyog Kale } 56479df15b7SSanyog Kale 56579df15b7SSanyog Kale return ret; 56679df15b7SSanyog Kale } 56779df15b7SSanyog Kale 56879df15b7SSanyog Kale /** 56999b8a5d6SSanyog Kale * sdw_notify_config() - Notify bus configuration 57099b8a5d6SSanyog Kale * 57199b8a5d6SSanyog Kale * @m_rt: Master runtime handle 57299b8a5d6SSanyog Kale * 57399b8a5d6SSanyog Kale * This function notifies the Master(s) and Slave(s) of the 57499b8a5d6SSanyog Kale * new bus configuration. 57599b8a5d6SSanyog Kale */ 57699b8a5d6SSanyog Kale static int sdw_notify_config(struct sdw_master_runtime *m_rt) 57799b8a5d6SSanyog Kale { 57899b8a5d6SSanyog Kale struct sdw_slave_runtime *s_rt; 57999b8a5d6SSanyog Kale struct sdw_bus *bus = m_rt->bus; 58099b8a5d6SSanyog Kale struct sdw_slave *slave; 58199b8a5d6SSanyog Kale int ret = 0; 58299b8a5d6SSanyog Kale 58399b8a5d6SSanyog Kale if (bus->ops->set_bus_conf) { 58499b8a5d6SSanyog Kale ret = bus->ops->set_bus_conf(bus, &bus->params); 58599b8a5d6SSanyog Kale if (ret < 0) 58699b8a5d6SSanyog Kale return ret; 58799b8a5d6SSanyog Kale } 58899b8a5d6SSanyog Kale 58999b8a5d6SSanyog Kale list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 59099b8a5d6SSanyog Kale slave = s_rt->slave; 59199b8a5d6SSanyog Kale 59299b8a5d6SSanyog Kale if (slave->ops->bus_config) { 59399b8a5d6SSanyog Kale ret = slave->ops->bus_config(slave, &bus->params); 59460835022SRander Wang if (ret < 0) { 59517ed5befSPierre-Louis Bossart dev_err(bus->dev, "Notify Slave: %d failed\n", 59699b8a5d6SSanyog Kale slave->dev_num); 59799b8a5d6SSanyog Kale return ret; 59899b8a5d6SSanyog Kale } 59999b8a5d6SSanyog Kale } 60060835022SRander Wang } 60199b8a5d6SSanyog Kale 60299b8a5d6SSanyog Kale return ret; 60399b8a5d6SSanyog Kale } 60499b8a5d6SSanyog Kale 60599b8a5d6SSanyog Kale /** 60699b8a5d6SSanyog Kale * sdw_program_params() - Program transport and port parameters for Master(s) 60799b8a5d6SSanyog Kale * and Slave(s) 60899b8a5d6SSanyog Kale * 60999b8a5d6SSanyog Kale * @bus: SDW bus instance 610bfaa3549SRander Wang * @prepare: true if sdw_program_params() is called by _prepare. 61199b8a5d6SSanyog Kale */ 612bfaa3549SRander Wang static int sdw_program_params(struct sdw_bus *bus, bool prepare) 61399b8a5d6SSanyog Kale { 6143a0be1a6SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 61599b8a5d6SSanyog Kale int ret = 0; 61699b8a5d6SSanyog Kale 61799b8a5d6SSanyog Kale list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 618bfaa3549SRander Wang 619bfaa3549SRander Wang /* 620bfaa3549SRander Wang * this loop walks through all master runtimes for a 621bfaa3549SRander Wang * bus, but the ports can only be configured while 622bfaa3549SRander Wang * explicitly preparing a stream or handling an 623bfaa3549SRander Wang * already-prepared stream otherwise. 624bfaa3549SRander Wang */ 625bfaa3549SRander Wang if (!prepare && 626bfaa3549SRander Wang m_rt->stream->state == SDW_STREAM_CONFIGURED) 627bfaa3549SRander Wang continue; 628bfaa3549SRander Wang 62999b8a5d6SSanyog Kale ret = sdw_program_port_params(m_rt); 63099b8a5d6SSanyog Kale if (ret < 0) { 63199b8a5d6SSanyog Kale dev_err(bus->dev, 63217ed5befSPierre-Louis Bossart "Program transport params failed: %d\n", ret); 63399b8a5d6SSanyog Kale return ret; 63499b8a5d6SSanyog Kale } 63599b8a5d6SSanyog Kale 63699b8a5d6SSanyog Kale ret = sdw_notify_config(m_rt); 63799b8a5d6SSanyog Kale if (ret < 0) { 63862f0cec3SVinod Koul dev_err(bus->dev, 63962f0cec3SVinod Koul "Notify bus config failed: %d\n", ret); 64099b8a5d6SSanyog Kale return ret; 64199b8a5d6SSanyog Kale } 64299b8a5d6SSanyog Kale 64399b8a5d6SSanyog Kale /* Enable port(s) on alternate bank for all active streams */ 64499b8a5d6SSanyog Kale if (m_rt->stream->state != SDW_STREAM_ENABLED) 64599b8a5d6SSanyog Kale continue; 64699b8a5d6SSanyog Kale 64799b8a5d6SSanyog Kale ret = sdw_enable_disable_ports(m_rt, true); 64899b8a5d6SSanyog Kale if (ret < 0) { 64917ed5befSPierre-Louis Bossart dev_err(bus->dev, "Enable channel failed: %d\n", ret); 65099b8a5d6SSanyog Kale return ret; 65199b8a5d6SSanyog Kale } 65299b8a5d6SSanyog Kale } 65399b8a5d6SSanyog Kale 65499b8a5d6SSanyog Kale return ret; 65599b8a5d6SSanyog Kale } 65699b8a5d6SSanyog Kale 657ce6e74d0SShreyas NC static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count) 65899b8a5d6SSanyog Kale { 65999b8a5d6SSanyog Kale int col_index, row_index; 660ce6e74d0SShreyas NC bool multi_link; 66199b8a5d6SSanyog Kale struct sdw_msg *wr_msg; 6623a0be1a6SPierre-Louis Bossart u8 *wbuf; 6633a0be1a6SPierre-Louis Bossart int ret; 66499b8a5d6SSanyog Kale u16 addr; 66599b8a5d6SSanyog Kale 66699b8a5d6SSanyog Kale wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL); 66799b8a5d6SSanyog Kale if (!wr_msg) 66899b8a5d6SSanyog Kale return -ENOMEM; 66999b8a5d6SSanyog Kale 670ce6e74d0SShreyas NC bus->defer_msg.msg = wr_msg; 671ce6e74d0SShreyas NC 67299b8a5d6SSanyog Kale wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL); 67399b8a5d6SSanyog Kale if (!wbuf) { 67499b8a5d6SSanyog Kale ret = -ENOMEM; 67599b8a5d6SSanyog Kale goto error_1; 67699b8a5d6SSanyog Kale } 67799b8a5d6SSanyog Kale 67899b8a5d6SSanyog Kale /* Get row and column index to program register */ 67999b8a5d6SSanyog Kale col_index = sdw_find_col_index(bus->params.col); 68099b8a5d6SSanyog Kale row_index = sdw_find_row_index(bus->params.row); 68199b8a5d6SSanyog Kale wbuf[0] = col_index | (row_index << 3); 68299b8a5d6SSanyog Kale 68399b8a5d6SSanyog Kale if (bus->params.next_bank) 68499b8a5d6SSanyog Kale addr = SDW_SCP_FRAMECTRL_B1; 68599b8a5d6SSanyog Kale else 68699b8a5d6SSanyog Kale addr = SDW_SCP_FRAMECTRL_B0; 68799b8a5d6SSanyog Kale 68899b8a5d6SSanyog Kale sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM, 68999b8a5d6SSanyog Kale SDW_MSG_FLAG_WRITE, wbuf); 69099b8a5d6SSanyog Kale wr_msg->ssp_sync = true; 69199b8a5d6SSanyog Kale 692ce6e74d0SShreyas NC /* 693ce6e74d0SShreyas NC * Set the multi_link flag only when both the hardware supports 694063ff4e5SPierre-Louis Bossart * and hardware-based sync is required 695ce6e74d0SShreyas NC */ 696063ff4e5SPierre-Louis Bossart multi_link = bus->multi_link && (m_rt_count >= bus->hw_sync_min_links); 697ce6e74d0SShreyas NC 698ce6e74d0SShreyas NC if (multi_link) 699ce6e74d0SShreyas NC ret = sdw_transfer_defer(bus, wr_msg, &bus->defer_msg); 700ce6e74d0SShreyas NC else 70199b8a5d6SSanyog Kale ret = sdw_transfer(bus, wr_msg); 702ce6e74d0SShreyas NC 703e6645314SBard Liao if (ret < 0 && ret != -ENODATA) { 70417ed5befSPierre-Louis Bossart dev_err(bus->dev, "Slave frame_ctrl reg write failed\n"); 70599b8a5d6SSanyog Kale goto error; 70699b8a5d6SSanyog Kale } 70799b8a5d6SSanyog Kale 708ce6e74d0SShreyas NC if (!multi_link) { 70999b8a5d6SSanyog Kale kfree(wr_msg); 71099b8a5d6SSanyog Kale kfree(wbuf); 71199b8a5d6SSanyog Kale bus->defer_msg.msg = NULL; 71299b8a5d6SSanyog Kale bus->params.curr_bank = !bus->params.curr_bank; 71399b8a5d6SSanyog Kale bus->params.next_bank = !bus->params.next_bank; 714ce6e74d0SShreyas NC } 71599b8a5d6SSanyog Kale 71699b8a5d6SSanyog Kale return 0; 71799b8a5d6SSanyog Kale 71899b8a5d6SSanyog Kale error: 71999b8a5d6SSanyog Kale kfree(wbuf); 72099b8a5d6SSanyog Kale error_1: 72199b8a5d6SSanyog Kale kfree(wr_msg); 7223fbbf214STom Rix bus->defer_msg.msg = NULL; 72399b8a5d6SSanyog Kale return ret; 72499b8a5d6SSanyog Kale } 72599b8a5d6SSanyog Kale 726ce6e74d0SShreyas NC /** 727ce6e74d0SShreyas NC * sdw_ml_sync_bank_switch: Multilink register bank switch 728ce6e74d0SShreyas NC * 729ce6e74d0SShreyas NC * @bus: SDW bus instance 730ce6e74d0SShreyas NC * 731ce6e74d0SShreyas NC * Caller function should free the buffers on error 732ce6e74d0SShreyas NC */ 733ce6e74d0SShreyas NC static int sdw_ml_sync_bank_switch(struct sdw_bus *bus) 734ce6e74d0SShreyas NC { 735ce6e74d0SShreyas NC unsigned long time_left; 736ce6e74d0SShreyas NC 737ce6e74d0SShreyas NC if (!bus->multi_link) 738ce6e74d0SShreyas NC return 0; 739ce6e74d0SShreyas NC 740ce6e74d0SShreyas NC /* Wait for completion of transfer */ 741ce6e74d0SShreyas NC time_left = wait_for_completion_timeout(&bus->defer_msg.complete, 742ce6e74d0SShreyas NC bus->bank_switch_timeout); 743ce6e74d0SShreyas NC 744ce6e74d0SShreyas NC if (!time_left) { 74517ed5befSPierre-Louis Bossart dev_err(bus->dev, "Controller Timed out on bank switch\n"); 746ce6e74d0SShreyas NC return -ETIMEDOUT; 747ce6e74d0SShreyas NC } 748ce6e74d0SShreyas NC 749ce6e74d0SShreyas NC bus->params.curr_bank = !bus->params.curr_bank; 750ce6e74d0SShreyas NC bus->params.next_bank = !bus->params.next_bank; 751ce6e74d0SShreyas NC 752ce6e74d0SShreyas NC if (bus->defer_msg.msg) { 753ce6e74d0SShreyas NC kfree(bus->defer_msg.msg->buf); 754ce6e74d0SShreyas NC kfree(bus->defer_msg.msg); 755ce6e74d0SShreyas NC } 756ce6e74d0SShreyas NC 757ce6e74d0SShreyas NC return 0; 758ce6e74d0SShreyas NC } 759ce6e74d0SShreyas NC 76099b8a5d6SSanyog Kale static int do_bank_switch(struct sdw_stream_runtime *stream) 76199b8a5d6SSanyog Kale { 7623a0be1a6SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 76399b8a5d6SSanyog Kale const struct sdw_master_ops *ops; 7643a0be1a6SPierre-Louis Bossart struct sdw_bus *bus; 765ce6e74d0SShreyas NC bool multi_link = false; 766063ff4e5SPierre-Louis Bossart int m_rt_count; 76799b8a5d6SSanyog Kale int ret = 0; 76899b8a5d6SSanyog Kale 769063ff4e5SPierre-Louis Bossart m_rt_count = stream->m_rt_count; 770063ff4e5SPierre-Louis Bossart 77148949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 77248949722SVinod Koul bus = m_rt->bus; 77399b8a5d6SSanyog Kale ops = bus->ops; 77499b8a5d6SSanyog Kale 775063ff4e5SPierre-Louis Bossart if (bus->multi_link && m_rt_count >= bus->hw_sync_min_links) { 776ce6e74d0SShreyas NC multi_link = true; 777ce6e74d0SShreyas NC mutex_lock(&bus->msg_lock); 778ce6e74d0SShreyas NC } 779ce6e74d0SShreyas NC 78099b8a5d6SSanyog Kale /* Pre-bank switch */ 78199b8a5d6SSanyog Kale if (ops->pre_bank_switch) { 78299b8a5d6SSanyog Kale ret = ops->pre_bank_switch(bus); 78399b8a5d6SSanyog Kale if (ret < 0) { 78448949722SVinod Koul dev_err(bus->dev, 78517ed5befSPierre-Louis Bossart "Pre bank switch op failed: %d\n", ret); 786ce6e74d0SShreyas NC goto msg_unlock; 78799b8a5d6SSanyog Kale } 78899b8a5d6SSanyog Kale } 78999b8a5d6SSanyog Kale 790ce6e74d0SShreyas NC /* 791ce6e74d0SShreyas NC * Perform Bank switch operation. 792ce6e74d0SShreyas NC * For multi link cases, the actual bank switch is 793ce6e74d0SShreyas NC * synchronized across all Masters and happens later as a 794ce6e74d0SShreyas NC * part of post_bank_switch ops. 795ce6e74d0SShreyas NC */ 796063ff4e5SPierre-Louis Bossart ret = sdw_bank_switch(bus, m_rt_count); 79799b8a5d6SSanyog Kale if (ret < 0) { 79817ed5befSPierre-Louis Bossart dev_err(bus->dev, "Bank switch failed: %d\n", ret); 799ce6e74d0SShreyas NC goto error; 80099b8a5d6SSanyog Kale } 80148949722SVinod Koul } 80248949722SVinod Koul 803ce6e74d0SShreyas NC /* 804ce6e74d0SShreyas NC * For multi link cases, it is expected that the bank switch is 805ce6e74d0SShreyas NC * triggered by the post_bank_switch for the first Master in the list 806ce6e74d0SShreyas NC * and for the other Masters the post_bank_switch() should return doing 807ce6e74d0SShreyas NC * nothing. 808ce6e74d0SShreyas NC */ 80948949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 81048949722SVinod Koul bus = m_rt->bus; 81148949722SVinod Koul ops = bus->ops; 81299b8a5d6SSanyog Kale 81399b8a5d6SSanyog Kale /* Post-bank switch */ 81499b8a5d6SSanyog Kale if (ops->post_bank_switch) { 81599b8a5d6SSanyog Kale ret = ops->post_bank_switch(bus); 81699b8a5d6SSanyog Kale if (ret < 0) { 81799b8a5d6SSanyog Kale dev_err(bus->dev, 81862f0cec3SVinod Koul "Post bank switch op failed: %d\n", 81962f0cec3SVinod Koul ret); 820ce6e74d0SShreyas NC goto error; 82199b8a5d6SSanyog Kale } 822063ff4e5SPierre-Louis Bossart } else if (multi_link) { 823ce6e74d0SShreyas NC dev_err(bus->dev, 82417ed5befSPierre-Louis Bossart "Post bank switch ops not implemented\n"); 825ce6e74d0SShreyas NC goto error; 826ce6e74d0SShreyas NC } 827ce6e74d0SShreyas NC 828ce6e74d0SShreyas NC /* Set the bank switch timeout to default, if not set */ 829ce6e74d0SShreyas NC if (!bus->bank_switch_timeout) 830ce6e74d0SShreyas NC bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT; 831ce6e74d0SShreyas NC 832ce6e74d0SShreyas NC /* Check if bank switch was successful */ 833ce6e74d0SShreyas NC ret = sdw_ml_sync_bank_switch(bus); 834ce6e74d0SShreyas NC if (ret < 0) { 835ce6e74d0SShreyas NC dev_err(bus->dev, 83617ed5befSPierre-Louis Bossart "multi link bank switch failed: %d\n", ret); 837ce6e74d0SShreyas NC goto error; 838ce6e74d0SShreyas NC } 839ce6e74d0SShreyas NC 840063ff4e5SPierre-Louis Bossart if (multi_link) 841ce6e74d0SShreyas NC mutex_unlock(&bus->msg_lock); 842ce6e74d0SShreyas NC } 843ce6e74d0SShreyas NC 844ce6e74d0SShreyas NC return ret; 845ce6e74d0SShreyas NC 846ce6e74d0SShreyas NC error: 847ce6e74d0SShreyas NC list_for_each_entry(m_rt, &stream->master_list, stream_node) { 848ce6e74d0SShreyas NC bus = m_rt->bus; 8493fbbf214STom Rix if (bus->defer_msg.msg) { 850ce6e74d0SShreyas NC kfree(bus->defer_msg.msg->buf); 851ce6e74d0SShreyas NC kfree(bus->defer_msg.msg); 852ce6e74d0SShreyas NC } 8533fbbf214STom Rix } 854ce6e74d0SShreyas NC 855ce6e74d0SShreyas NC msg_unlock: 856ce6e74d0SShreyas NC 857ce6e74d0SShreyas NC if (multi_link) { 858ce6e74d0SShreyas NC list_for_each_entry(m_rt, &stream->master_list, stream_node) { 859ce6e74d0SShreyas NC bus = m_rt->bus; 860ce6e74d0SShreyas NC if (mutex_is_locked(&bus->msg_lock)) 861ce6e74d0SShreyas NC mutex_unlock(&bus->msg_lock); 86299b8a5d6SSanyog Kale } 86348949722SVinod Koul } 86499b8a5d6SSanyog Kale 86599b8a5d6SSanyog Kale return ret; 86699b8a5d6SSanyog Kale } 86799b8a5d6SSanyog Kale 8686ccf3292SPierre-Louis Bossart static struct sdw_port_runtime *sdw_port_alloc(struct list_head *port_list) 8696ccf3292SPierre-Louis Bossart { 8706ccf3292SPierre-Louis Bossart struct sdw_port_runtime *p_rt; 8716ccf3292SPierre-Louis Bossart 8726ccf3292SPierre-Louis Bossart p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL); 8736ccf3292SPierre-Louis Bossart if (!p_rt) 8746ccf3292SPierre-Louis Bossart return NULL; 8756ccf3292SPierre-Louis Bossart 8766ccf3292SPierre-Louis Bossart list_add_tail(&p_rt->port_node, port_list); 8776ccf3292SPierre-Louis Bossart 8786ccf3292SPierre-Louis Bossart return p_rt; 8796ccf3292SPierre-Louis Bossart } 8806ccf3292SPierre-Louis Bossart 8816ccf3292SPierre-Louis Bossart static int sdw_port_config(struct sdw_port_runtime *p_rt, 8826ccf3292SPierre-Louis Bossart struct sdw_port_config *port_config, 8836ccf3292SPierre-Louis Bossart int port_index) 8846ccf3292SPierre-Louis Bossart { 8856ccf3292SPierre-Louis Bossart p_rt->ch_mask = port_config[port_index].ch_mask; 8866ccf3292SPierre-Louis Bossart p_rt->num = port_config[port_index].num; 8876ccf3292SPierre-Louis Bossart 8886ccf3292SPierre-Louis Bossart /* 8896ccf3292SPierre-Louis Bossart * TODO: Check port capabilities for requested configuration 8906ccf3292SPierre-Louis Bossart */ 8916ccf3292SPierre-Louis Bossart 8926ccf3292SPierre-Louis Bossart return 0; 8936ccf3292SPierre-Louis Bossart } 8946ccf3292SPierre-Louis Bossart 8956ccf3292SPierre-Louis Bossart static void sdw_port_free(struct sdw_port_runtime *p_rt) 8966ccf3292SPierre-Louis Bossart { 8976ccf3292SPierre-Louis Bossart list_del(&p_rt->port_node); 8986ccf3292SPierre-Louis Bossart kfree(p_rt); 8996ccf3292SPierre-Louis Bossart } 9006ccf3292SPierre-Louis Bossart 901c7aa9d77SPierre-Louis Bossart static void sdw_slave_port_free(struct sdw_slave *slave, 902c7aa9d77SPierre-Louis Bossart struct sdw_stream_runtime *stream) 903c7aa9d77SPierre-Louis Bossart { 904c7aa9d77SPierre-Louis Bossart struct sdw_port_runtime *p_rt, *_p_rt; 905c7aa9d77SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 906c7aa9d77SPierre-Louis Bossart struct sdw_slave_runtime *s_rt; 907c7aa9d77SPierre-Louis Bossart 908c7aa9d77SPierre-Louis Bossart list_for_each_entry(m_rt, &stream->master_list, stream_node) { 909c7aa9d77SPierre-Louis Bossart list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 910c7aa9d77SPierre-Louis Bossart if (s_rt->slave != slave) 911c7aa9d77SPierre-Louis Bossart continue; 912c7aa9d77SPierre-Louis Bossart 913c7aa9d77SPierre-Louis Bossart list_for_each_entry_safe(p_rt, _p_rt, 914c7aa9d77SPierre-Louis Bossart &s_rt->port_list, port_node) { 915c7aa9d77SPierre-Louis Bossart sdw_port_free(p_rt); 916c7aa9d77SPierre-Louis Bossart } 917c7aa9d77SPierre-Louis Bossart } 918c7aa9d77SPierre-Louis Bossart } 919c7aa9d77SPierre-Louis Bossart } 920c7aa9d77SPierre-Louis Bossart 921c7aa9d77SPierre-Louis Bossart static int sdw_slave_port_alloc(struct sdw_slave *slave, 922c7aa9d77SPierre-Louis Bossart struct sdw_slave_runtime *s_rt, 923c7aa9d77SPierre-Louis Bossart unsigned int num_config) 924c7aa9d77SPierre-Louis Bossart { 925c7aa9d77SPierre-Louis Bossart struct sdw_port_runtime *p_rt; 926c7aa9d77SPierre-Louis Bossart int i; 927c7aa9d77SPierre-Louis Bossart 928c7aa9d77SPierre-Louis Bossart /* Iterate for number of ports to perform initialization */ 929c7aa9d77SPierre-Louis Bossart for (i = 0; i < num_config; i++) { 930c7aa9d77SPierre-Louis Bossart p_rt = sdw_port_alloc(&s_rt->port_list); 931c7aa9d77SPierre-Louis Bossart if (!p_rt) 932c7aa9d77SPierre-Louis Bossart return -ENOMEM; 933c7aa9d77SPierre-Louis Bossart } 934c7aa9d77SPierre-Louis Bossart 935c7aa9d77SPierre-Louis Bossart return 0; 936c7aa9d77SPierre-Louis Bossart } 937c7aa9d77SPierre-Louis Bossart 938c7aa9d77SPierre-Louis Bossart static int sdw_slave_port_is_valid_range(struct device *dev, int num) 939c7aa9d77SPierre-Louis Bossart { 940c7aa9d77SPierre-Louis Bossart if (!SDW_VALID_PORT_RANGE(num)) { 941c7aa9d77SPierre-Louis Bossart dev_err(dev, "SoundWire: Invalid port number :%d\n", num); 942c7aa9d77SPierre-Louis Bossart return -EINVAL; 943c7aa9d77SPierre-Louis Bossart } 944c7aa9d77SPierre-Louis Bossart 945c7aa9d77SPierre-Louis Bossart return 0; 946c7aa9d77SPierre-Louis Bossart } 947c7aa9d77SPierre-Louis Bossart 948c7aa9d77SPierre-Louis Bossart static int sdw_slave_port_config(struct sdw_slave *slave, 949c7aa9d77SPierre-Louis Bossart struct sdw_slave_runtime *s_rt, 950c7aa9d77SPierre-Louis Bossart struct sdw_port_config *port_config) 951c7aa9d77SPierre-Louis Bossart { 952c7aa9d77SPierre-Louis Bossart struct sdw_port_runtime *p_rt; 953c7aa9d77SPierre-Louis Bossart int ret; 954c7aa9d77SPierre-Louis Bossart int i; 955c7aa9d77SPierre-Louis Bossart 956c7aa9d77SPierre-Louis Bossart i = 0; 957c7aa9d77SPierre-Louis Bossart list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 958c7aa9d77SPierre-Louis Bossart /* 959c7aa9d77SPierre-Louis Bossart * TODO: Check valid port range as defined by DisCo/ 960c7aa9d77SPierre-Louis Bossart * slave 961c7aa9d77SPierre-Louis Bossart */ 962c7aa9d77SPierre-Louis Bossart ret = sdw_slave_port_is_valid_range(&slave->dev, port_config[i].num); 963c7aa9d77SPierre-Louis Bossart if (ret < 0) 964c7aa9d77SPierre-Louis Bossart return ret; 965c7aa9d77SPierre-Louis Bossart 966c7aa9d77SPierre-Louis Bossart ret = sdw_port_config(p_rt, port_config, i); 967c7aa9d77SPierre-Louis Bossart if (ret < 0) 968c7aa9d77SPierre-Louis Bossart return ret; 969c7aa9d77SPierre-Louis Bossart i++; 970c7aa9d77SPierre-Louis Bossart } 971c7aa9d77SPierre-Louis Bossart 972c7aa9d77SPierre-Louis Bossart return 0; 973c7aa9d77SPierre-Louis Bossart } 974c7aa9d77SPierre-Louis Bossart 975c7aa9d77SPierre-Louis Bossart static void sdw_master_port_free(struct sdw_master_runtime *m_rt) 976c7aa9d77SPierre-Louis Bossart { 977c7aa9d77SPierre-Louis Bossart struct sdw_port_runtime *p_rt, *_p_rt; 978c7aa9d77SPierre-Louis Bossart 979c7aa9d77SPierre-Louis Bossart list_for_each_entry_safe(p_rt, _p_rt, &m_rt->port_list, port_node) { 980c7aa9d77SPierre-Louis Bossart sdw_port_free(p_rt); 981c7aa9d77SPierre-Louis Bossart } 982c7aa9d77SPierre-Louis Bossart } 983c7aa9d77SPierre-Louis Bossart 984c7aa9d77SPierre-Louis Bossart static int sdw_master_port_alloc(struct sdw_master_runtime *m_rt, 985c7aa9d77SPierre-Louis Bossart unsigned int num_ports) 986c7aa9d77SPierre-Louis Bossart { 987c7aa9d77SPierre-Louis Bossart struct sdw_port_runtime *p_rt; 988c7aa9d77SPierre-Louis Bossart int i; 989c7aa9d77SPierre-Louis Bossart 990c7aa9d77SPierre-Louis Bossart /* Iterate for number of ports to perform initialization */ 991c7aa9d77SPierre-Louis Bossart for (i = 0; i < num_ports; i++) { 992c7aa9d77SPierre-Louis Bossart p_rt = sdw_port_alloc(&m_rt->port_list); 993c7aa9d77SPierre-Louis Bossart if (!p_rt) 994c7aa9d77SPierre-Louis Bossart return -ENOMEM; 995c7aa9d77SPierre-Louis Bossart } 996c7aa9d77SPierre-Louis Bossart 997c7aa9d77SPierre-Louis Bossart return 0; 998c7aa9d77SPierre-Louis Bossart } 999c7aa9d77SPierre-Louis Bossart 1000c7aa9d77SPierre-Louis Bossart static int sdw_master_port_config(struct sdw_master_runtime *m_rt, 1001c7aa9d77SPierre-Louis Bossart struct sdw_port_config *port_config) 1002c7aa9d77SPierre-Louis Bossart { 1003c7aa9d77SPierre-Louis Bossart struct sdw_port_runtime *p_rt; 1004c7aa9d77SPierre-Louis Bossart int ret; 1005c7aa9d77SPierre-Louis Bossart int i; 1006c7aa9d77SPierre-Louis Bossart 1007c7aa9d77SPierre-Louis Bossart i = 0; 1008c7aa9d77SPierre-Louis Bossart list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 1009c7aa9d77SPierre-Louis Bossart ret = sdw_port_config(p_rt, port_config, i); 1010c7aa9d77SPierre-Louis Bossart if (ret < 0) 1011c7aa9d77SPierre-Louis Bossart return ret; 1012c7aa9d77SPierre-Louis Bossart i++; 1013c7aa9d77SPierre-Louis Bossart } 1014c7aa9d77SPierre-Louis Bossart 1015c7aa9d77SPierre-Louis Bossart return 0; 1016c7aa9d77SPierre-Louis Bossart } 1017c7aa9d77SPierre-Louis Bossart 101899b8a5d6SSanyog Kale /** 1019edd5cf99SPierre-Louis Bossart * sdw_slave_rt_alloc() - Allocate a Slave runtime handle. 1020bf75ba4bSPierre-Louis Bossart * 1021bf75ba4bSPierre-Louis Bossart * @slave: Slave handle 1022*42aad41eSPierre-Louis Bossart * @m_rt: Master runtime handle 1023bf75ba4bSPierre-Louis Bossart * 1024bf75ba4bSPierre-Louis Bossart * This function is to be called with bus_lock held. 1025bf75ba4bSPierre-Louis Bossart */ 1026bf75ba4bSPierre-Louis Bossart static struct sdw_slave_runtime 1027*42aad41eSPierre-Louis Bossart *sdw_slave_rt_alloc(struct sdw_slave *slave, 1028*42aad41eSPierre-Louis Bossart struct sdw_master_runtime *m_rt) 1029bf75ba4bSPierre-Louis Bossart { 1030bf75ba4bSPierre-Louis Bossart struct sdw_slave_runtime *s_rt; 1031bf75ba4bSPierre-Louis Bossart 1032bf75ba4bSPierre-Louis Bossart s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL); 1033bf75ba4bSPierre-Louis Bossart if (!s_rt) 1034bf75ba4bSPierre-Louis Bossart return NULL; 1035bf75ba4bSPierre-Louis Bossart 1036bf75ba4bSPierre-Louis Bossart INIT_LIST_HEAD(&s_rt->port_list); 1037bf75ba4bSPierre-Louis Bossart s_rt->slave = slave; 1038bf75ba4bSPierre-Louis Bossart 1039*42aad41eSPierre-Louis Bossart list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list); 1040*42aad41eSPierre-Louis Bossart 1041bf75ba4bSPierre-Louis Bossart return s_rt; 1042bf75ba4bSPierre-Louis Bossart } 1043bf75ba4bSPierre-Louis Bossart 1044edd5cf99SPierre-Louis Bossart /** 1045edd5cf99SPierre-Louis Bossart * sdw_slave_rt_config() - Configure a Slave runtime handle. 1046edd5cf99SPierre-Louis Bossart * 1047edd5cf99SPierre-Louis Bossart * @s_rt: Slave runtime handle 1048edd5cf99SPierre-Louis Bossart * @stream_config: Stream configuration 1049edd5cf99SPierre-Louis Bossart * 1050edd5cf99SPierre-Louis Bossart * This function is to be called with bus_lock held. 1051edd5cf99SPierre-Louis Bossart */ 1052edd5cf99SPierre-Louis Bossart static int sdw_slave_rt_config(struct sdw_slave_runtime *s_rt, 1053edd5cf99SPierre-Louis Bossart struct sdw_stream_config *stream_config) 1054edd5cf99SPierre-Louis Bossart { 1055edd5cf99SPierre-Louis Bossart s_rt->ch_count = stream_config->ch_count; 1056edd5cf99SPierre-Louis Bossart s_rt->direction = stream_config->direction; 1057edd5cf99SPierre-Louis Bossart 1058edd5cf99SPierre-Louis Bossart return 0; 1059edd5cf99SPierre-Louis Bossart } 1060edd5cf99SPierre-Louis Bossart 106100ce0d2aSPierre-Louis Bossart /** 106200ce0d2aSPierre-Louis Bossart * sdw_slave_rt_free() - Free Slave(s) runtime handle 106300ce0d2aSPierre-Louis Bossart * 106400ce0d2aSPierre-Louis Bossart * @slave: Slave handle. 106500ce0d2aSPierre-Louis Bossart * @stream: Stream runtime handle. 106600ce0d2aSPierre-Louis Bossart * 106700ce0d2aSPierre-Louis Bossart * This function is to be called with bus_lock held. 106800ce0d2aSPierre-Louis Bossart */ 106900ce0d2aSPierre-Louis Bossart static void sdw_slave_rt_free(struct sdw_slave *slave, 107000ce0d2aSPierre-Louis Bossart struct sdw_stream_runtime *stream) 107100ce0d2aSPierre-Louis Bossart { 107200ce0d2aSPierre-Louis Bossart struct sdw_slave_runtime *s_rt, *_s_rt; 107300ce0d2aSPierre-Louis Bossart struct sdw_master_runtime *m_rt; 107400ce0d2aSPierre-Louis Bossart 107500ce0d2aSPierre-Louis Bossart list_for_each_entry(m_rt, &stream->master_list, stream_node) { 107600ce0d2aSPierre-Louis Bossart /* Retrieve Slave runtime handle */ 107700ce0d2aSPierre-Louis Bossart list_for_each_entry_safe(s_rt, _s_rt, 107800ce0d2aSPierre-Louis Bossart &m_rt->slave_rt_list, m_rt_node) { 107900ce0d2aSPierre-Louis Bossart if (s_rt->slave == slave) { 108000ce0d2aSPierre-Louis Bossart list_del(&s_rt->m_rt_node); 108100ce0d2aSPierre-Louis Bossart kfree(s_rt); 108200ce0d2aSPierre-Louis Bossart return; 108300ce0d2aSPierre-Louis Bossart } 108400ce0d2aSPierre-Louis Bossart } 108500ce0d2aSPierre-Louis Bossart } 108600ce0d2aSPierre-Louis Bossart } 108700ce0d2aSPierre-Louis Bossart 108848949722SVinod Koul static struct sdw_master_runtime 1089bb10659aSPierre-Louis Bossart *sdw_master_rt_find(struct sdw_bus *bus, 109048949722SVinod Koul struct sdw_stream_runtime *stream) 109148949722SVinod Koul { 10923a0be1a6SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 109348949722SVinod Koul 109448949722SVinod Koul /* Retrieve Bus handle if already available */ 109548949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 109648949722SVinod Koul if (m_rt->bus == bus) 109748949722SVinod Koul return m_rt; 109848949722SVinod Koul } 109948949722SVinod Koul 110048949722SVinod Koul return NULL; 110148949722SVinod Koul } 110248949722SVinod Koul 110389e59053SSanyog Kale /** 1104bb10659aSPierre-Louis Bossart * sdw_master_rt_alloc() - Allocates a Master runtime handle 110589e59053SSanyog Kale * 110689e59053SSanyog Kale * @bus: SDW bus instance 110789e59053SSanyog Kale * @stream: Stream runtime handle. 110889e59053SSanyog Kale * 110989e59053SSanyog Kale * This function is to be called with bus_lock held. 111089e59053SSanyog Kale */ 111189e59053SSanyog Kale static struct sdw_master_runtime 1112bb10659aSPierre-Louis Bossart *sdw_master_rt_alloc(struct sdw_bus *bus, 111389e59053SSanyog Kale struct sdw_stream_runtime *stream) 111489e59053SSanyog Kale { 111589e59053SSanyog Kale struct sdw_master_runtime *m_rt; 111689e59053SSanyog Kale 111789e59053SSanyog Kale m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL); 111889e59053SSanyog Kale if (!m_rt) 111989e59053SSanyog Kale return NULL; 112089e59053SSanyog Kale 112189e59053SSanyog Kale /* Initialization of Master runtime handle */ 1122bbe7379dSSanyog Kale INIT_LIST_HEAD(&m_rt->port_list); 112389e59053SSanyog Kale INIT_LIST_HEAD(&m_rt->slave_rt_list); 112448949722SVinod Koul list_add_tail(&m_rt->stream_node, &stream->master_list); 112589e59053SSanyog Kale 112689e59053SSanyog Kale list_add_tail(&m_rt->bus_node, &bus->m_rt_list); 112789e59053SSanyog Kale 112889e59053SSanyog Kale m_rt->bus = bus; 112989e59053SSanyog Kale m_rt->stream = stream; 113089e59053SSanyog Kale 113189e59053SSanyog Kale return m_rt; 113289e59053SSanyog Kale } 113389e59053SSanyog Kale 113489e59053SSanyog Kale /** 1135bb10659aSPierre-Louis Bossart * sdw_master_rt_config() - Configure Master runtime handle 1136bb10659aSPierre-Louis Bossart * 1137bb10659aSPierre-Louis Bossart * @m_rt: Master runtime handle 1138bb10659aSPierre-Louis Bossart * @stream_config: Stream configuration 1139bb10659aSPierre-Louis Bossart * 1140bb10659aSPierre-Louis Bossart * This function is to be called with bus_lock held. 1141bb10659aSPierre-Louis Bossart */ 1142bb10659aSPierre-Louis Bossart 1143bb10659aSPierre-Louis Bossart static int sdw_master_rt_config(struct sdw_master_runtime *m_rt, 1144bb10659aSPierre-Louis Bossart struct sdw_stream_config *stream_config) 1145bb10659aSPierre-Louis Bossart { 1146bb10659aSPierre-Louis Bossart m_rt->ch_count = stream_config->ch_count; 1147bb10659aSPierre-Louis Bossart m_rt->direction = stream_config->direction; 1148bb10659aSPierre-Louis Bossart 1149bb10659aSPierre-Louis Bossart return 0; 1150bb10659aSPierre-Louis Bossart } 1151bb10659aSPierre-Louis Bossart 1152bb10659aSPierre-Louis Bossart /** 115300ce0d2aSPierre-Louis Bossart * sdw_master_rt_free() - Free Master runtime handle 115489e59053SSanyog Kale * 115548949722SVinod Koul * @m_rt: Master runtime node 115689e59053SSanyog Kale * @stream: Stream runtime handle. 115789e59053SSanyog Kale * 115889e59053SSanyog Kale * This function is to be called with bus_lock held 115989e59053SSanyog Kale * It frees the Master runtime handle and associated Slave(s) runtime 116000ce0d2aSPierre-Louis Bossart * handle. If this is called first then sdw_slave_rt_free() will have 116189e59053SSanyog Kale * no effect as Slave(s) runtime handle would already be freed up. 116289e59053SSanyog Kale */ 116300ce0d2aSPierre-Louis Bossart static void sdw_master_rt_free(struct sdw_master_runtime *m_rt, 116448949722SVinod Koul struct sdw_stream_runtime *stream) 116589e59053SSanyog Kale { 116689e59053SSanyog Kale struct sdw_slave_runtime *s_rt, *_s_rt; 116789e59053SSanyog Kale 11688d6ccf5cSSanyog Kale list_for_each_entry_safe(s_rt, _s_rt, &m_rt->slave_rt_list, m_rt_node) { 1169c7aa9d77SPierre-Louis Bossart sdw_slave_port_free(s_rt->slave, stream); 117000ce0d2aSPierre-Louis Bossart sdw_slave_rt_free(s_rt->slave, stream); 11718d6ccf5cSSanyog Kale } 117289e59053SSanyog Kale 117348949722SVinod Koul list_del(&m_rt->stream_node); 117489e59053SSanyog Kale list_del(&m_rt->bus_node); 117548949722SVinod Koul kfree(m_rt); 117689e59053SSanyog Kale } 117789e59053SSanyog Kale 117889e59053SSanyog Kale /** 117989e59053SSanyog Kale * sdw_config_stream() - Configure the allocated stream 118089e59053SSanyog Kale * 118189e59053SSanyog Kale * @dev: SDW device 118289e59053SSanyog Kale * @stream: SoundWire stream 118389e59053SSanyog Kale * @stream_config: Stream configuration for audio stream 118489e59053SSanyog Kale * @is_slave: is API called from Slave or Master 118589e59053SSanyog Kale * 118689e59053SSanyog Kale * This function is to be called with bus_lock held. 118789e59053SSanyog Kale */ 118889e59053SSanyog Kale static int sdw_config_stream(struct device *dev, 118989e59053SSanyog Kale struct sdw_stream_runtime *stream, 11901fe74a5eSPierre-Louis Bossart struct sdw_stream_config *stream_config, 11911fe74a5eSPierre-Louis Bossart bool is_slave) 119289e59053SSanyog Kale { 119389e59053SSanyog Kale /* 119489e59053SSanyog Kale * Update the stream rate, channel and bps based on data 119589e59053SSanyog Kale * source. For more than one data source (multilink), 119689e59053SSanyog Kale * match the rate, bps, stream type and increment number of channels. 119789e59053SSanyog Kale * 119889e59053SSanyog Kale * If rate/bps is zero, it means the values are not set, so skip 119989e59053SSanyog Kale * comparison and allow the value to be set and stored in stream 120089e59053SSanyog Kale */ 120189e59053SSanyog Kale if (stream->params.rate && 120289e59053SSanyog Kale stream->params.rate != stream_config->frame_rate) { 120317ed5befSPierre-Louis Bossart dev_err(dev, "rate not matching, stream:%s\n", stream->name); 120489e59053SSanyog Kale return -EINVAL; 120589e59053SSanyog Kale } 120689e59053SSanyog Kale 120789e59053SSanyog Kale if (stream->params.bps && 120889e59053SSanyog Kale stream->params.bps != stream_config->bps) { 120917ed5befSPierre-Louis Bossart dev_err(dev, "bps not matching, stream:%s\n", stream->name); 121089e59053SSanyog Kale return -EINVAL; 121189e59053SSanyog Kale } 121289e59053SSanyog Kale 121389e59053SSanyog Kale stream->type = stream_config->type; 121489e59053SSanyog Kale stream->params.rate = stream_config->frame_rate; 121589e59053SSanyog Kale stream->params.bps = stream_config->bps; 121689e59053SSanyog Kale 121789e59053SSanyog Kale /* TODO: Update this check during Device-device support */ 121889e59053SSanyog Kale if (is_slave) 121989e59053SSanyog Kale stream->params.ch_count += stream_config->ch_count; 122089e59053SSanyog Kale 122189e59053SSanyog Kale return 0; 122289e59053SSanyog Kale } 122389e59053SSanyog Kale 122489e59053SSanyog Kale /** 1225f8101c74SSanyog Kale * sdw_get_slave_dpn_prop() - Get Slave port capabilities 1226f8101c74SSanyog Kale * 1227f8101c74SSanyog Kale * @slave: Slave handle 1228f8101c74SSanyog Kale * @direction: Data direction. 1229f8101c74SSanyog Kale * @port_num: Port number 1230f8101c74SSanyog Kale */ 1231f8101c74SSanyog Kale struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave, 1232f8101c74SSanyog Kale enum sdw_data_direction direction, 1233f8101c74SSanyog Kale unsigned int port_num) 1234f8101c74SSanyog Kale { 1235f8101c74SSanyog Kale struct sdw_dpn_prop *dpn_prop; 1236f8101c74SSanyog Kale u8 num_ports; 1237f8101c74SSanyog Kale int i; 1238f8101c74SSanyog Kale 1239f8101c74SSanyog Kale if (direction == SDW_DATA_DIR_TX) { 1240f8101c74SSanyog Kale num_ports = hweight32(slave->prop.source_ports); 1241f8101c74SSanyog Kale dpn_prop = slave->prop.src_dpn_prop; 1242f8101c74SSanyog Kale } else { 1243f8101c74SSanyog Kale num_ports = hweight32(slave->prop.sink_ports); 1244f8101c74SSanyog Kale dpn_prop = slave->prop.sink_dpn_prop; 1245f8101c74SSanyog Kale } 1246f8101c74SSanyog Kale 1247f8101c74SSanyog Kale for (i = 0; i < num_ports; i++) { 124803ecad90SSrinivas Kandagatla if (dpn_prop[i].num == port_num) 1249f8101c74SSanyog Kale return &dpn_prop[i]; 1250f8101c74SSanyog Kale } 1251f8101c74SSanyog Kale 1252f8101c74SSanyog Kale return NULL; 1253f8101c74SSanyog Kale } 12545c3eb9f7SSanyog Kale 12550c4a1049SSanyog Kale /** 12560c4a1049SSanyog Kale * sdw_acquire_bus_lock: Acquire bus lock for all Master runtime(s) 12570c4a1049SSanyog Kale * 12580c4a1049SSanyog Kale * @stream: SoundWire stream 12590c4a1049SSanyog Kale * 12600c4a1049SSanyog Kale * Acquire bus_lock for each of the master runtime(m_rt) part of this 12610c4a1049SSanyog Kale * stream to reconfigure the bus. 12620c4a1049SSanyog Kale * NOTE: This function is called from SoundWire stream ops and is 12630c4a1049SSanyog Kale * expected that a global lock is held before acquiring bus_lock. 12640c4a1049SSanyog Kale */ 12650c4a1049SSanyog Kale static void sdw_acquire_bus_lock(struct sdw_stream_runtime *stream) 12660c4a1049SSanyog Kale { 12673a0be1a6SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 126853e0a304SPierre-Louis Bossart struct sdw_bus *bus; 12690c4a1049SSanyog Kale 12700c4a1049SSanyog Kale /* Iterate for all Master(s) in Master list */ 12710c4a1049SSanyog Kale list_for_each_entry(m_rt, &stream->master_list, stream_node) { 12720c4a1049SSanyog Kale bus = m_rt->bus; 12730c4a1049SSanyog Kale 12740c4a1049SSanyog Kale mutex_lock(&bus->bus_lock); 12750c4a1049SSanyog Kale } 12760c4a1049SSanyog Kale } 12770c4a1049SSanyog Kale 12780c4a1049SSanyog Kale /** 12790c4a1049SSanyog Kale * sdw_release_bus_lock: Release bus lock for all Master runtime(s) 12800c4a1049SSanyog Kale * 12810c4a1049SSanyog Kale * @stream: SoundWire stream 12820c4a1049SSanyog Kale * 12830c4a1049SSanyog Kale * Release the previously held bus_lock after reconfiguring the bus. 128448949722SVinod Koul * NOTE: This function is called from SoundWire stream ops and is 128548949722SVinod Koul * expected that a global lock is held before releasing bus_lock. 12860c4a1049SSanyog Kale */ 12870c4a1049SSanyog Kale static void sdw_release_bus_lock(struct sdw_stream_runtime *stream) 12880c4a1049SSanyog Kale { 12895920a29dSPierre-Louis Bossart struct sdw_master_runtime *m_rt; 129053e0a304SPierre-Louis Bossart struct sdw_bus *bus; 12910c4a1049SSanyog Kale 12920c4a1049SSanyog Kale /* Iterate for all Master(s) in Master list */ 12930c4a1049SSanyog Kale list_for_each_entry_reverse(m_rt, &stream->master_list, stream_node) { 12940c4a1049SSanyog Kale bus = m_rt->bus; 12950c4a1049SSanyog Kale mutex_unlock(&bus->bus_lock); 12960c4a1049SSanyog Kale } 12970c4a1049SSanyog Kale } 12980c4a1049SSanyog Kale 1299c7a8f049SPierre-Louis Bossart static int _sdw_prepare_stream(struct sdw_stream_runtime *stream, 1300c7a8f049SPierre-Louis Bossart bool update_params) 13015c3eb9f7SSanyog Kale { 13023a0be1a6SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 130348949722SVinod Koul struct sdw_bus *bus = NULL; 13043a0be1a6SPierre-Louis Bossart struct sdw_master_prop *prop; 13055c3eb9f7SSanyog Kale struct sdw_bus_params params; 13065c3eb9f7SSanyog Kale int ret; 13075c3eb9f7SSanyog Kale 130848949722SVinod Koul /* Prepare Master(s) and Slave(s) port(s) associated with stream */ 130948949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 131048949722SVinod Koul bus = m_rt->bus; 13115c3eb9f7SSanyog Kale prop = &bus->prop; 13125c3eb9f7SSanyog Kale memcpy(¶ms, &bus->params, sizeof(params)); 13135c3eb9f7SSanyog Kale 13145c3eb9f7SSanyog Kale /* TODO: Support Asynchronous mode */ 13153424305bSPierre-Louis Bossart if ((prop->max_clk_freq % stream->params.rate) != 0) { 131617ed5befSPierre-Louis Bossart dev_err(bus->dev, "Async mode not supported\n"); 13175c3eb9f7SSanyog Kale return -EINVAL; 13185c3eb9f7SSanyog Kale } 13195c3eb9f7SSanyog Kale 1320c7a8f049SPierre-Louis Bossart if (!update_params) 1321c7a8f049SPierre-Louis Bossart goto program_params; 1322c7a8f049SPierre-Louis Bossart 13235c3eb9f7SSanyog Kale /* Increment cumulative bus bandwidth */ 13245c3eb9f7SSanyog Kale /* TODO: Update this during Device-Device support */ 13255c3eb9f7SSanyog Kale bus->params.bandwidth += m_rt->stream->params.rate * 13265c3eb9f7SSanyog Kale m_rt->ch_count * m_rt->stream->params.bps; 13275c3eb9f7SSanyog Kale 1328c7578c1dSVinod Koul /* Compute params */ 1329c7578c1dSVinod Koul if (bus->compute_params) { 1330c7578c1dSVinod Koul ret = bus->compute_params(bus); 1331c7578c1dSVinod Koul if (ret < 0) { 13326122d3beSPierre-Louis Bossart dev_err(bus->dev, "Compute params failed: %d\n", 1333c7578c1dSVinod Koul ret); 1334c7578c1dSVinod Koul return ret; 1335c7578c1dSVinod Koul } 1336c7578c1dSVinod Koul } 1337c7578c1dSVinod Koul 1338c7a8f049SPierre-Louis Bossart program_params: 13395c3eb9f7SSanyog Kale /* Program params */ 1340bfaa3549SRander Wang ret = sdw_program_params(bus, true); 13415c3eb9f7SSanyog Kale if (ret < 0) { 134217ed5befSPierre-Louis Bossart dev_err(bus->dev, "Program params failed: %d\n", ret); 13435c3eb9f7SSanyog Kale goto restore_params; 13445c3eb9f7SSanyog Kale } 134548949722SVinod Koul } 134648949722SVinod Koul 13473a0be1a6SPierre-Louis Bossart if (!bus) { 13483a0be1a6SPierre-Louis Bossart pr_err("Configuration error in %s\n", __func__); 13493a0be1a6SPierre-Louis Bossart return -EINVAL; 13503a0be1a6SPierre-Louis Bossart } 13513a0be1a6SPierre-Louis Bossart 13525c3eb9f7SSanyog Kale ret = do_bank_switch(stream); 13535c3eb9f7SSanyog Kale if (ret < 0) { 135417ed5befSPierre-Louis Bossart dev_err(bus->dev, "Bank switch failed: %d\n", ret); 13555c3eb9f7SSanyog Kale goto restore_params; 13565c3eb9f7SSanyog Kale } 13575c3eb9f7SSanyog Kale 135848949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 135948949722SVinod Koul bus = m_rt->bus; 136048949722SVinod Koul 13615c3eb9f7SSanyog Kale /* Prepare port(s) on the new clock configuration */ 13625c3eb9f7SSanyog Kale ret = sdw_prep_deprep_ports(m_rt, true); 13635c3eb9f7SSanyog Kale if (ret < 0) { 136417ed5befSPierre-Louis Bossart dev_err(bus->dev, "Prepare port(s) failed ret = %d\n", 13655c3eb9f7SSanyog Kale ret); 13665c3eb9f7SSanyog Kale return ret; 13675c3eb9f7SSanyog Kale } 136848949722SVinod Koul } 13695c3eb9f7SSanyog Kale 13705c3eb9f7SSanyog Kale stream->state = SDW_STREAM_PREPARED; 13715c3eb9f7SSanyog Kale 13725c3eb9f7SSanyog Kale return ret; 13735c3eb9f7SSanyog Kale 13745c3eb9f7SSanyog Kale restore_params: 13755c3eb9f7SSanyog Kale memcpy(&bus->params, ¶ms, sizeof(params)); 13765c3eb9f7SSanyog Kale return ret; 13775c3eb9f7SSanyog Kale } 13785c3eb9f7SSanyog Kale 13795c3eb9f7SSanyog Kale /** 13805c3eb9f7SSanyog Kale * sdw_prepare_stream() - Prepare SoundWire stream 13815c3eb9f7SSanyog Kale * 13825c3eb9f7SSanyog Kale * @stream: Soundwire stream 13835c3eb9f7SSanyog Kale * 138434962fb8SMauro Carvalho Chehab * Documentation/driver-api/soundwire/stream.rst explains this API in detail 13855c3eb9f7SSanyog Kale */ 13865c3eb9f7SSanyog Kale int sdw_prepare_stream(struct sdw_stream_runtime *stream) 13875c3eb9f7SSanyog Kale { 1388c7a8f049SPierre-Louis Bossart bool update_params = true; 1389c32464c9SBard Liao int ret; 13905c3eb9f7SSanyog Kale 13915c3eb9f7SSanyog Kale if (!stream) { 139217ed5befSPierre-Louis Bossart pr_err("SoundWire: Handle not found for stream\n"); 13935c3eb9f7SSanyog Kale return -EINVAL; 13945c3eb9f7SSanyog Kale } 13955c3eb9f7SSanyog Kale 139648949722SVinod Koul sdw_acquire_bus_lock(stream); 13975c3eb9f7SSanyog Kale 1398c32464c9SBard Liao if (stream->state == SDW_STREAM_PREPARED) { 1399c32464c9SBard Liao ret = 0; 1400c32464c9SBard Liao goto state_err; 1401c32464c9SBard Liao } 1402c32464c9SBard Liao 140359528807SPierre-Louis Bossart if (stream->state != SDW_STREAM_CONFIGURED && 140459528807SPierre-Louis Bossart stream->state != SDW_STREAM_DEPREPARED && 140559528807SPierre-Louis Bossart stream->state != SDW_STREAM_DISABLED) { 140659528807SPierre-Louis Bossart pr_err("%s: %s: inconsistent state state %d\n", 140759528807SPierre-Louis Bossart __func__, stream->name, stream->state); 140859528807SPierre-Louis Bossart ret = -EINVAL; 140959528807SPierre-Louis Bossart goto state_err; 141059528807SPierre-Louis Bossart } 141159528807SPierre-Louis Bossart 1412c7a8f049SPierre-Louis Bossart /* 1413c7a8f049SPierre-Louis Bossart * when the stream is DISABLED, this means sdw_prepare_stream() 1414c7a8f049SPierre-Louis Bossart * is called as a result of an underflow or a resume operation. 1415c7a8f049SPierre-Louis Bossart * In this case, the bus parameters shall not be recomputed, but 1416c7a8f049SPierre-Louis Bossart * still need to be re-applied 1417c7a8f049SPierre-Louis Bossart */ 1418c7a8f049SPierre-Louis Bossart if (stream->state == SDW_STREAM_DISABLED) 1419c7a8f049SPierre-Louis Bossart update_params = false; 1420c7a8f049SPierre-Louis Bossart 1421c7a8f049SPierre-Louis Bossart ret = _sdw_prepare_stream(stream, update_params); 14225c3eb9f7SSanyog Kale 142359528807SPierre-Louis Bossart state_err: 142448949722SVinod Koul sdw_release_bus_lock(stream); 14255c3eb9f7SSanyog Kale return ret; 14265c3eb9f7SSanyog Kale } 14275c3eb9f7SSanyog Kale EXPORT_SYMBOL(sdw_prepare_stream); 14285c3eb9f7SSanyog Kale 14295c3eb9f7SSanyog Kale static int _sdw_enable_stream(struct sdw_stream_runtime *stream) 14305c3eb9f7SSanyog Kale { 14313a0be1a6SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 143248949722SVinod Koul struct sdw_bus *bus = NULL; 14335c3eb9f7SSanyog Kale int ret; 14345c3eb9f7SSanyog Kale 143548949722SVinod Koul /* Enable Master(s) and Slave(s) port(s) associated with stream */ 143648949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 143748949722SVinod Koul bus = m_rt->bus; 143848949722SVinod Koul 14395c3eb9f7SSanyog Kale /* Program params */ 1440bfaa3549SRander Wang ret = sdw_program_params(bus, false); 14415c3eb9f7SSanyog Kale if (ret < 0) { 144217ed5befSPierre-Louis Bossart dev_err(bus->dev, "Program params failed: %d\n", ret); 14435c3eb9f7SSanyog Kale return ret; 14445c3eb9f7SSanyog Kale } 14455c3eb9f7SSanyog Kale 14465c3eb9f7SSanyog Kale /* Enable port(s) */ 14475c3eb9f7SSanyog Kale ret = sdw_enable_disable_ports(m_rt, true); 14485c3eb9f7SSanyog Kale if (ret < 0) { 144962f0cec3SVinod Koul dev_err(bus->dev, 145062f0cec3SVinod Koul "Enable port(s) failed ret: %d\n", ret); 14515c3eb9f7SSanyog Kale return ret; 14525c3eb9f7SSanyog Kale } 145348949722SVinod Koul } 14545c3eb9f7SSanyog Kale 14553a0be1a6SPierre-Louis Bossart if (!bus) { 14563a0be1a6SPierre-Louis Bossart pr_err("Configuration error in %s\n", __func__); 14573a0be1a6SPierre-Louis Bossart return -EINVAL; 14583a0be1a6SPierre-Louis Bossart } 14593a0be1a6SPierre-Louis Bossart 14605c3eb9f7SSanyog Kale ret = do_bank_switch(stream); 14615c3eb9f7SSanyog Kale if (ret < 0) { 146217ed5befSPierre-Louis Bossart dev_err(bus->dev, "Bank switch failed: %d\n", ret); 14635c3eb9f7SSanyog Kale return ret; 14645c3eb9f7SSanyog Kale } 14655c3eb9f7SSanyog Kale 14665c3eb9f7SSanyog Kale stream->state = SDW_STREAM_ENABLED; 14675c3eb9f7SSanyog Kale return 0; 14685c3eb9f7SSanyog Kale } 14695c3eb9f7SSanyog Kale 14705c3eb9f7SSanyog Kale /** 14715c3eb9f7SSanyog Kale * sdw_enable_stream() - Enable SoundWire stream 14725c3eb9f7SSanyog Kale * 14735c3eb9f7SSanyog Kale * @stream: Soundwire stream 14745c3eb9f7SSanyog Kale * 147534962fb8SMauro Carvalho Chehab * Documentation/driver-api/soundwire/stream.rst explains this API in detail 14765c3eb9f7SSanyog Kale */ 14775c3eb9f7SSanyog Kale int sdw_enable_stream(struct sdw_stream_runtime *stream) 14785c3eb9f7SSanyog Kale { 14793a0be1a6SPierre-Louis Bossart int ret; 14805c3eb9f7SSanyog Kale 14815c3eb9f7SSanyog Kale if (!stream) { 148217ed5befSPierre-Louis Bossart pr_err("SoundWire: Handle not found for stream\n"); 14835c3eb9f7SSanyog Kale return -EINVAL; 14845c3eb9f7SSanyog Kale } 14855c3eb9f7SSanyog Kale 148648949722SVinod Koul sdw_acquire_bus_lock(stream); 14875c3eb9f7SSanyog Kale 148859528807SPierre-Louis Bossart if (stream->state != SDW_STREAM_PREPARED && 148959528807SPierre-Louis Bossart stream->state != SDW_STREAM_DISABLED) { 149059528807SPierre-Louis Bossart pr_err("%s: %s: inconsistent state state %d\n", 149159528807SPierre-Louis Bossart __func__, stream->name, stream->state); 149259528807SPierre-Louis Bossart ret = -EINVAL; 149359528807SPierre-Louis Bossart goto state_err; 149459528807SPierre-Louis Bossart } 149559528807SPierre-Louis Bossart 14965c3eb9f7SSanyog Kale ret = _sdw_enable_stream(stream); 14975c3eb9f7SSanyog Kale 149859528807SPierre-Louis Bossart state_err: 149948949722SVinod Koul sdw_release_bus_lock(stream); 15005c3eb9f7SSanyog Kale return ret; 15015c3eb9f7SSanyog Kale } 15025c3eb9f7SSanyog Kale EXPORT_SYMBOL(sdw_enable_stream); 15035c3eb9f7SSanyog Kale 15045c3eb9f7SSanyog Kale static int _sdw_disable_stream(struct sdw_stream_runtime *stream) 15055c3eb9f7SSanyog Kale { 15063a0be1a6SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 15075c3eb9f7SSanyog Kale int ret; 15085c3eb9f7SSanyog Kale 150948949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 15103a0be1a6SPierre-Louis Bossart struct sdw_bus *bus = m_rt->bus; 15113a0be1a6SPierre-Louis Bossart 15125c3eb9f7SSanyog Kale /* Disable port(s) */ 15135c3eb9f7SSanyog Kale ret = sdw_enable_disable_ports(m_rt, false); 15145c3eb9f7SSanyog Kale if (ret < 0) { 151517ed5befSPierre-Louis Bossart dev_err(bus->dev, "Disable port(s) failed: %d\n", ret); 15165c3eb9f7SSanyog Kale return ret; 15175c3eb9f7SSanyog Kale } 151848949722SVinod Koul } 15195c3eb9f7SSanyog Kale stream->state = SDW_STREAM_DISABLED; 15205c3eb9f7SSanyog Kale 152148949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 15223a0be1a6SPierre-Louis Bossart struct sdw_bus *bus = m_rt->bus; 15233a0be1a6SPierre-Louis Bossart 15245c3eb9f7SSanyog Kale /* Program params */ 1525bfaa3549SRander Wang ret = sdw_program_params(bus, false); 15265c3eb9f7SSanyog Kale if (ret < 0) { 152717ed5befSPierre-Louis Bossart dev_err(bus->dev, "Program params failed: %d\n", ret); 15285c3eb9f7SSanyog Kale return ret; 15295c3eb9f7SSanyog Kale } 153048949722SVinod Koul } 15315c3eb9f7SSanyog Kale 1532e0279b6bSPierre-Louis Bossart ret = do_bank_switch(stream); 1533e0279b6bSPierre-Louis Bossart if (ret < 0) { 15343a0be1a6SPierre-Louis Bossart pr_err("Bank switch failed: %d\n", ret); 1535e0279b6bSPierre-Louis Bossart return ret; 1536e0279b6bSPierre-Louis Bossart } 1537e0279b6bSPierre-Louis Bossart 1538e0279b6bSPierre-Louis Bossart /* make sure alternate bank (previous current) is also disabled */ 1539e0279b6bSPierre-Louis Bossart list_for_each_entry(m_rt, &stream->master_list, stream_node) { 15403a0be1a6SPierre-Louis Bossart struct sdw_bus *bus = m_rt->bus; 15413a0be1a6SPierre-Louis Bossart 1542e0279b6bSPierre-Louis Bossart /* Disable port(s) */ 1543e0279b6bSPierre-Louis Bossart ret = sdw_enable_disable_ports(m_rt, false); 1544e0279b6bSPierre-Louis Bossart if (ret < 0) { 1545e0279b6bSPierre-Louis Bossart dev_err(bus->dev, "Disable port(s) failed: %d\n", ret); 1546e0279b6bSPierre-Louis Bossart return ret; 1547e0279b6bSPierre-Louis Bossart } 1548e0279b6bSPierre-Louis Bossart } 1549e0279b6bSPierre-Louis Bossart 1550e0279b6bSPierre-Louis Bossart return 0; 15515c3eb9f7SSanyog Kale } 15525c3eb9f7SSanyog Kale 15535c3eb9f7SSanyog Kale /** 15545c3eb9f7SSanyog Kale * sdw_disable_stream() - Disable SoundWire stream 15555c3eb9f7SSanyog Kale * 15565c3eb9f7SSanyog Kale * @stream: Soundwire stream 15575c3eb9f7SSanyog Kale * 155834962fb8SMauro Carvalho Chehab * Documentation/driver-api/soundwire/stream.rst explains this API in detail 15595c3eb9f7SSanyog Kale */ 15605c3eb9f7SSanyog Kale int sdw_disable_stream(struct sdw_stream_runtime *stream) 15615c3eb9f7SSanyog Kale { 15623a0be1a6SPierre-Louis Bossart int ret; 15635c3eb9f7SSanyog Kale 15645c3eb9f7SSanyog Kale if (!stream) { 156517ed5befSPierre-Louis Bossart pr_err("SoundWire: Handle not found for stream\n"); 15665c3eb9f7SSanyog Kale return -EINVAL; 15675c3eb9f7SSanyog Kale } 15685c3eb9f7SSanyog Kale 156948949722SVinod Koul sdw_acquire_bus_lock(stream); 15705c3eb9f7SSanyog Kale 157159528807SPierre-Louis Bossart if (stream->state != SDW_STREAM_ENABLED) { 157259528807SPierre-Louis Bossart pr_err("%s: %s: inconsistent state state %d\n", 157359528807SPierre-Louis Bossart __func__, stream->name, stream->state); 157459528807SPierre-Louis Bossart ret = -EINVAL; 157559528807SPierre-Louis Bossart goto state_err; 157659528807SPierre-Louis Bossart } 157759528807SPierre-Louis Bossart 15785c3eb9f7SSanyog Kale ret = _sdw_disable_stream(stream); 15795c3eb9f7SSanyog Kale 158059528807SPierre-Louis Bossart state_err: 158148949722SVinod Koul sdw_release_bus_lock(stream); 15825c3eb9f7SSanyog Kale return ret; 15835c3eb9f7SSanyog Kale } 15845c3eb9f7SSanyog Kale EXPORT_SYMBOL(sdw_disable_stream); 15855c3eb9f7SSanyog Kale 15865c3eb9f7SSanyog Kale static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream) 15875c3eb9f7SSanyog Kale { 15883a0be1a6SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 15893a0be1a6SPierre-Louis Bossart struct sdw_bus *bus; 15905c3eb9f7SSanyog Kale int ret = 0; 15915c3eb9f7SSanyog Kale 159248949722SVinod Koul list_for_each_entry(m_rt, &stream->master_list, stream_node) { 159348949722SVinod Koul bus = m_rt->bus; 15945c3eb9f7SSanyog Kale /* De-prepare port(s) */ 15955c3eb9f7SSanyog Kale ret = sdw_prep_deprep_ports(m_rt, false); 15965c3eb9f7SSanyog Kale if (ret < 0) { 159762f0cec3SVinod Koul dev_err(bus->dev, 159862f0cec3SVinod Koul "De-prepare port(s) failed: %d\n", ret); 15995c3eb9f7SSanyog Kale return ret; 16005c3eb9f7SSanyog Kale } 16015c3eb9f7SSanyog Kale 16025c3eb9f7SSanyog Kale /* TODO: Update this during Device-Device support */ 16035c3eb9f7SSanyog Kale bus->params.bandwidth -= m_rt->stream->params.rate * 16045c3eb9f7SSanyog Kale m_rt->ch_count * m_rt->stream->params.bps; 16055c3eb9f7SSanyog Kale 16069026118fSBard Liao /* Compute params */ 16079026118fSBard Liao if (bus->compute_params) { 16089026118fSBard Liao ret = bus->compute_params(bus); 16099026118fSBard Liao if (ret < 0) { 16106122d3beSPierre-Louis Bossart dev_err(bus->dev, "Compute params failed: %d\n", 16119026118fSBard Liao ret); 16129026118fSBard Liao return ret; 16139026118fSBard Liao } 16149026118fSBard Liao } 16159026118fSBard Liao 16165c3eb9f7SSanyog Kale /* Program params */ 1617bfaa3549SRander Wang ret = sdw_program_params(bus, false); 16185c3eb9f7SSanyog Kale if (ret < 0) { 161917ed5befSPierre-Louis Bossart dev_err(bus->dev, "Program params failed: %d\n", ret); 16205c3eb9f7SSanyog Kale return ret; 16215c3eb9f7SSanyog Kale } 162248949722SVinod Koul } 162348949722SVinod Koul 162448949722SVinod Koul stream->state = SDW_STREAM_DEPREPARED; 16255c3eb9f7SSanyog Kale return do_bank_switch(stream); 16265c3eb9f7SSanyog Kale } 16275c3eb9f7SSanyog Kale 16285c3eb9f7SSanyog Kale /** 16295c3eb9f7SSanyog Kale * sdw_deprepare_stream() - Deprepare SoundWire stream 16305c3eb9f7SSanyog Kale * 16315c3eb9f7SSanyog Kale * @stream: Soundwire stream 16325c3eb9f7SSanyog Kale * 163334962fb8SMauro Carvalho Chehab * Documentation/driver-api/soundwire/stream.rst explains this API in detail 16345c3eb9f7SSanyog Kale */ 16355c3eb9f7SSanyog Kale int sdw_deprepare_stream(struct sdw_stream_runtime *stream) 16365c3eb9f7SSanyog Kale { 16373a0be1a6SPierre-Louis Bossart int ret; 16385c3eb9f7SSanyog Kale 16395c3eb9f7SSanyog Kale if (!stream) { 164017ed5befSPierre-Louis Bossart pr_err("SoundWire: Handle not found for stream\n"); 16415c3eb9f7SSanyog Kale return -EINVAL; 16425c3eb9f7SSanyog Kale } 16435c3eb9f7SSanyog Kale 164448949722SVinod Koul sdw_acquire_bus_lock(stream); 164559528807SPierre-Louis Bossart 164659528807SPierre-Louis Bossart if (stream->state != SDW_STREAM_PREPARED && 164759528807SPierre-Louis Bossart stream->state != SDW_STREAM_DISABLED) { 164859528807SPierre-Louis Bossart pr_err("%s: %s: inconsistent state state %d\n", 164959528807SPierre-Louis Bossart __func__, stream->name, stream->state); 165059528807SPierre-Louis Bossart ret = -EINVAL; 165159528807SPierre-Louis Bossart goto state_err; 165259528807SPierre-Louis Bossart } 165359528807SPierre-Louis Bossart 16545c3eb9f7SSanyog Kale ret = _sdw_deprepare_stream(stream); 16555c3eb9f7SSanyog Kale 165659528807SPierre-Louis Bossart state_err: 165748949722SVinod Koul sdw_release_bus_lock(stream); 16585c3eb9f7SSanyog Kale return ret; 16595c3eb9f7SSanyog Kale } 16605c3eb9f7SSanyog Kale EXPORT_SYMBOL(sdw_deprepare_stream); 16614550569bSPierre-Louis Bossart 16624550569bSPierre-Louis Bossart static int set_stream(struct snd_pcm_substream *substream, 16634550569bSPierre-Louis Bossart struct sdw_stream_runtime *sdw_stream) 16644550569bSPierre-Louis Bossart { 16654550569bSPierre-Louis Bossart struct snd_soc_pcm_runtime *rtd = substream->private_data; 16664550569bSPierre-Louis Bossart struct snd_soc_dai *dai; 16674550569bSPierre-Louis Bossart int ret = 0; 16684550569bSPierre-Louis Bossart int i; 16694550569bSPierre-Louis Bossart 16704550569bSPierre-Louis Bossart /* Set stream pointer on all DAIs */ 16714550569bSPierre-Louis Bossart for_each_rtd_dais(rtd, i, dai) { 1672e8444560SPierre-Louis Bossart ret = snd_soc_dai_set_stream(dai, sdw_stream, substream->stream); 16734550569bSPierre-Louis Bossart if (ret < 0) { 16746122d3beSPierre-Louis Bossart dev_err(rtd->dev, "failed to set stream pointer on dai %s\n", dai->name); 16754550569bSPierre-Louis Bossart break; 16764550569bSPierre-Louis Bossart } 16774550569bSPierre-Louis Bossart } 16784550569bSPierre-Louis Bossart 16794550569bSPierre-Louis Bossart return ret; 16804550569bSPierre-Louis Bossart } 16814550569bSPierre-Louis Bossart 16824550569bSPierre-Louis Bossart /** 16837a908906SPierre-Louis Bossart * sdw_alloc_stream() - Allocate and return stream runtime 16847a908906SPierre-Louis Bossart * 16857a908906SPierre-Louis Bossart * @stream_name: SoundWire stream name 16867a908906SPierre-Louis Bossart * 16877a908906SPierre-Louis Bossart * Allocates a SoundWire stream runtime instance. 16887a908906SPierre-Louis Bossart * sdw_alloc_stream should be called only once per stream. Typically 16897a908906SPierre-Louis Bossart * invoked from ALSA/ASoC machine/platform driver. 16907a908906SPierre-Louis Bossart */ 16917a908906SPierre-Louis Bossart struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name) 16927a908906SPierre-Louis Bossart { 16937a908906SPierre-Louis Bossart struct sdw_stream_runtime *stream; 16947a908906SPierre-Louis Bossart 16957a908906SPierre-Louis Bossart stream = kzalloc(sizeof(*stream), GFP_KERNEL); 16967a908906SPierre-Louis Bossart if (!stream) 16977a908906SPierre-Louis Bossart return NULL; 16987a908906SPierre-Louis Bossart 16997a908906SPierre-Louis Bossart stream->name = stream_name; 17007a908906SPierre-Louis Bossart INIT_LIST_HEAD(&stream->master_list); 17017a908906SPierre-Louis Bossart stream->state = SDW_STREAM_ALLOCATED; 17027a908906SPierre-Louis Bossart stream->m_rt_count = 0; 17037a908906SPierre-Louis Bossart 17047a908906SPierre-Louis Bossart return stream; 17057a908906SPierre-Louis Bossart } 17067a908906SPierre-Louis Bossart EXPORT_SYMBOL(sdw_alloc_stream); 17077a908906SPierre-Louis Bossart 17087a908906SPierre-Louis Bossart /** 17094550569bSPierre-Louis Bossart * sdw_startup_stream() - Startup SoundWire stream 17104550569bSPierre-Louis Bossart * 17113b71c690SVinod Koul * @sdw_substream: Soundwire stream 17124550569bSPierre-Louis Bossart * 17134550569bSPierre-Louis Bossart * Documentation/driver-api/soundwire/stream.rst explains this API in detail 17144550569bSPierre-Louis Bossart */ 17154550569bSPierre-Louis Bossart int sdw_startup_stream(void *sdw_substream) 17164550569bSPierre-Louis Bossart { 17174550569bSPierre-Louis Bossart struct snd_pcm_substream *substream = sdw_substream; 17184550569bSPierre-Louis Bossart struct snd_soc_pcm_runtime *rtd = substream->private_data; 17194550569bSPierre-Louis Bossart struct sdw_stream_runtime *sdw_stream; 17204550569bSPierre-Louis Bossart char *name; 17214550569bSPierre-Louis Bossart int ret; 17224550569bSPierre-Louis Bossart 17234550569bSPierre-Louis Bossart if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 17244550569bSPierre-Louis Bossart name = kasprintf(GFP_KERNEL, "%s-Playback", substream->name); 17254550569bSPierre-Louis Bossart else 17264550569bSPierre-Louis Bossart name = kasprintf(GFP_KERNEL, "%s-Capture", substream->name); 17274550569bSPierre-Louis Bossart 17284550569bSPierre-Louis Bossart if (!name) 17294550569bSPierre-Louis Bossart return -ENOMEM; 17304550569bSPierre-Louis Bossart 17314550569bSPierre-Louis Bossart sdw_stream = sdw_alloc_stream(name); 17324550569bSPierre-Louis Bossart if (!sdw_stream) { 17336122d3beSPierre-Louis Bossart dev_err(rtd->dev, "alloc stream failed for substream DAI %s\n", substream->name); 17344550569bSPierre-Louis Bossart ret = -ENOMEM; 17354550569bSPierre-Louis Bossart goto error; 17364550569bSPierre-Louis Bossart } 17374550569bSPierre-Louis Bossart 17384550569bSPierre-Louis Bossart ret = set_stream(substream, sdw_stream); 17394550569bSPierre-Louis Bossart if (ret < 0) 17404550569bSPierre-Louis Bossart goto release_stream; 17414550569bSPierre-Louis Bossart return 0; 17424550569bSPierre-Louis Bossart 17434550569bSPierre-Louis Bossart release_stream: 17444550569bSPierre-Louis Bossart sdw_release_stream(sdw_stream); 17454550569bSPierre-Louis Bossart set_stream(substream, NULL); 17464550569bSPierre-Louis Bossart error: 17474550569bSPierre-Louis Bossart kfree(name); 17484550569bSPierre-Louis Bossart return ret; 17494550569bSPierre-Louis Bossart } 17504550569bSPierre-Louis Bossart EXPORT_SYMBOL(sdw_startup_stream); 17514550569bSPierre-Louis Bossart 17524550569bSPierre-Louis Bossart /** 17534550569bSPierre-Louis Bossart * sdw_shutdown_stream() - Shutdown SoundWire stream 17544550569bSPierre-Louis Bossart * 17553b71c690SVinod Koul * @sdw_substream: Soundwire stream 17564550569bSPierre-Louis Bossart * 17574550569bSPierre-Louis Bossart * Documentation/driver-api/soundwire/stream.rst explains this API in detail 17584550569bSPierre-Louis Bossart */ 17594550569bSPierre-Louis Bossart void sdw_shutdown_stream(void *sdw_substream) 17604550569bSPierre-Louis Bossart { 17614550569bSPierre-Louis Bossart struct snd_pcm_substream *substream = sdw_substream; 17624550569bSPierre-Louis Bossart struct snd_soc_pcm_runtime *rtd = substream->private_data; 17634550569bSPierre-Louis Bossart struct sdw_stream_runtime *sdw_stream; 17644550569bSPierre-Louis Bossart struct snd_soc_dai *dai; 17654550569bSPierre-Louis Bossart 17664550569bSPierre-Louis Bossart /* Find stream from first CPU DAI */ 17674550569bSPierre-Louis Bossart dai = asoc_rtd_to_cpu(rtd, 0); 17684550569bSPierre-Louis Bossart 1769e8444560SPierre-Louis Bossart sdw_stream = snd_soc_dai_get_stream(dai, substream->stream); 17704550569bSPierre-Louis Bossart 17713471d2a1SPierre-Louis Bossart if (IS_ERR(sdw_stream)) { 17726122d3beSPierre-Louis Bossart dev_err(rtd->dev, "no stream found for DAI %s\n", dai->name); 17734550569bSPierre-Louis Bossart return; 17744550569bSPierre-Louis Bossart } 17754550569bSPierre-Louis Bossart 17764550569bSPierre-Louis Bossart /* release memory */ 17774550569bSPierre-Louis Bossart kfree(sdw_stream->name); 17784550569bSPierre-Louis Bossart sdw_release_stream(sdw_stream); 17794550569bSPierre-Louis Bossart 17804550569bSPierre-Louis Bossart /* clear DAI data */ 17814550569bSPierre-Louis Bossart set_stream(substream, NULL); 17824550569bSPierre-Louis Bossart } 17834550569bSPierre-Louis Bossart EXPORT_SYMBOL(sdw_shutdown_stream); 17847a908906SPierre-Louis Bossart 17857a908906SPierre-Louis Bossart /** 17867a908906SPierre-Louis Bossart * sdw_release_stream() - Free the assigned stream runtime 17877a908906SPierre-Louis Bossart * 17887a908906SPierre-Louis Bossart * @stream: SoundWire stream runtime 17897a908906SPierre-Louis Bossart * 17907a908906SPierre-Louis Bossart * sdw_release_stream should be called only once per stream 17917a908906SPierre-Louis Bossart */ 17927a908906SPierre-Louis Bossart void sdw_release_stream(struct sdw_stream_runtime *stream) 17937a908906SPierre-Louis Bossart { 17947a908906SPierre-Louis Bossart kfree(stream); 17957a908906SPierre-Louis Bossart } 17967a908906SPierre-Louis Bossart EXPORT_SYMBOL(sdw_release_stream); 17977a908906SPierre-Louis Bossart 17987a908906SPierre-Louis Bossart /** 17997a908906SPierre-Louis Bossart * sdw_stream_add_master() - Allocate and add master runtime to a stream 18007a908906SPierre-Louis Bossart * 18017a908906SPierre-Louis Bossart * @bus: SDW Bus instance 18027a908906SPierre-Louis Bossart * @stream_config: Stream configuration for audio stream 18037a908906SPierre-Louis Bossart * @port_config: Port configuration for audio stream 18047a908906SPierre-Louis Bossart * @num_ports: Number of ports 18057a908906SPierre-Louis Bossart * @stream: SoundWire stream 18067a908906SPierre-Louis Bossart */ 18077a908906SPierre-Louis Bossart int sdw_stream_add_master(struct sdw_bus *bus, 18087a908906SPierre-Louis Bossart struct sdw_stream_config *stream_config, 18097a908906SPierre-Louis Bossart struct sdw_port_config *port_config, 18107a908906SPierre-Louis Bossart unsigned int num_ports, 18117a908906SPierre-Louis Bossart struct sdw_stream_runtime *stream) 18127a908906SPierre-Louis Bossart { 18137a908906SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 18147a908906SPierre-Louis Bossart int ret; 18157a908906SPierre-Louis Bossart 18167a908906SPierre-Louis Bossart mutex_lock(&bus->bus_lock); 18177a908906SPierre-Louis Bossart 18187a908906SPierre-Louis Bossart /* 18197a908906SPierre-Louis Bossart * For multi link streams, add the second master only if 18207a908906SPierre-Louis Bossart * the bus supports it. 18217a908906SPierre-Louis Bossart * Check if bus->multi_link is set 18227a908906SPierre-Louis Bossart */ 18237a908906SPierre-Louis Bossart if (!bus->multi_link && stream->m_rt_count > 0) { 18247a908906SPierre-Louis Bossart dev_err(bus->dev, 18257a908906SPierre-Louis Bossart "Multilink not supported, link %d\n", bus->link_id); 18267a908906SPierre-Louis Bossart ret = -EINVAL; 18277a908906SPierre-Louis Bossart goto unlock; 18287a908906SPierre-Louis Bossart } 18297a908906SPierre-Louis Bossart 18307a908906SPierre-Louis Bossart /* 18317a908906SPierre-Louis Bossart * check if Master is already allocated (e.g. as a result of Slave adding 18327a908906SPierre-Louis Bossart * it first), if so skip allocation and go to configuration 18337a908906SPierre-Louis Bossart */ 18347a908906SPierre-Louis Bossart m_rt = sdw_master_rt_find(bus, stream); 18357a908906SPierre-Louis Bossart if (m_rt) 18367a908906SPierre-Louis Bossart goto skip_alloc_master_rt; 18377a908906SPierre-Louis Bossart 18387a908906SPierre-Louis Bossart m_rt = sdw_master_rt_alloc(bus, stream); 18397a908906SPierre-Louis Bossart if (!m_rt) { 18407a908906SPierre-Louis Bossart dev_err(bus->dev, "Master runtime alloc failed for stream:%s\n", stream->name); 18417a908906SPierre-Louis Bossart ret = -ENOMEM; 18427a908906SPierre-Louis Bossart goto unlock; 18437a908906SPierre-Louis Bossart } 18447a908906SPierre-Louis Bossart 18457a908906SPierre-Louis Bossart ret = sdw_master_rt_config(m_rt, stream_config); 18467a908906SPierre-Louis Bossart if (ret < 0) 18477a908906SPierre-Louis Bossart goto unlock; 18487a908906SPierre-Louis Bossart 18497a908906SPierre-Louis Bossart skip_alloc_master_rt: 18507a908906SPierre-Louis Bossart ret = sdw_config_stream(bus->dev, stream, stream_config, false); 18517a908906SPierre-Louis Bossart if (ret) 18527a908906SPierre-Louis Bossart goto stream_error; 18537a908906SPierre-Louis Bossart 18547a908906SPierre-Louis Bossart ret = sdw_master_port_alloc(m_rt, num_ports); 18557a908906SPierre-Louis Bossart if (ret) 18567a908906SPierre-Louis Bossart goto stream_error; 18577a908906SPierre-Louis Bossart 18587a908906SPierre-Louis Bossart ret = sdw_master_port_config(m_rt, port_config); 18597a908906SPierre-Louis Bossart if (ret) 18607a908906SPierre-Louis Bossart goto stream_error; 18617a908906SPierre-Louis Bossart 18627a908906SPierre-Louis Bossart stream->m_rt_count++; 18637a908906SPierre-Louis Bossart 18647a908906SPierre-Louis Bossart goto unlock; 18657a908906SPierre-Louis Bossart 18667a908906SPierre-Louis Bossart stream_error: 186700ce0d2aSPierre-Louis Bossart sdw_master_rt_free(m_rt, stream); 18687a908906SPierre-Louis Bossart unlock: 18697a908906SPierre-Louis Bossart mutex_unlock(&bus->bus_lock); 18707a908906SPierre-Louis Bossart return ret; 18717a908906SPierre-Louis Bossart } 18727a908906SPierre-Louis Bossart EXPORT_SYMBOL(sdw_stream_add_master); 18737a908906SPierre-Louis Bossart 18747a908906SPierre-Louis Bossart /** 18757a908906SPierre-Louis Bossart * sdw_stream_remove_master() - Remove master from sdw_stream 18767a908906SPierre-Louis Bossart * 18777a908906SPierre-Louis Bossart * @bus: SDW Bus instance 18787a908906SPierre-Louis Bossart * @stream: SoundWire stream 18797a908906SPierre-Louis Bossart * 18807a908906SPierre-Louis Bossart * This removes and frees port_rt and master_rt from a stream 18817a908906SPierre-Louis Bossart */ 18827a908906SPierre-Louis Bossart int sdw_stream_remove_master(struct sdw_bus *bus, 18837a908906SPierre-Louis Bossart struct sdw_stream_runtime *stream) 18847a908906SPierre-Louis Bossart { 18857a908906SPierre-Louis Bossart struct sdw_master_runtime *m_rt, *_m_rt; 18867a908906SPierre-Louis Bossart 18877a908906SPierre-Louis Bossart mutex_lock(&bus->bus_lock); 18887a908906SPierre-Louis Bossart 18897a908906SPierre-Louis Bossart list_for_each_entry_safe(m_rt, _m_rt, 18907a908906SPierre-Louis Bossart &stream->master_list, stream_node) { 18917a908906SPierre-Louis Bossart if (m_rt->bus != bus) 18927a908906SPierre-Louis Bossart continue; 18937a908906SPierre-Louis Bossart 18947a908906SPierre-Louis Bossart sdw_master_port_free(m_rt); 189500ce0d2aSPierre-Louis Bossart sdw_master_rt_free(m_rt, stream); 18967a908906SPierre-Louis Bossart stream->m_rt_count--; 18977a908906SPierre-Louis Bossart } 18987a908906SPierre-Louis Bossart 18997a908906SPierre-Louis Bossart if (list_empty(&stream->master_list)) 19007a908906SPierre-Louis Bossart stream->state = SDW_STREAM_RELEASED; 19017a908906SPierre-Louis Bossart 19027a908906SPierre-Louis Bossart mutex_unlock(&bus->bus_lock); 19037a908906SPierre-Louis Bossart 19047a908906SPierre-Louis Bossart return 0; 19057a908906SPierre-Louis Bossart } 19067a908906SPierre-Louis Bossart EXPORT_SYMBOL(sdw_stream_remove_master); 19077a908906SPierre-Louis Bossart 19087a908906SPierre-Louis Bossart /** 19097a908906SPierre-Louis Bossart * sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream 19107a908906SPierre-Louis Bossart * 19117a908906SPierre-Louis Bossart * @slave: SDW Slave instance 19127a908906SPierre-Louis Bossart * @stream_config: Stream configuration for audio stream 19137a908906SPierre-Louis Bossart * @stream: SoundWire stream 19147a908906SPierre-Louis Bossart * @port_config: Port configuration for audio stream 19157a908906SPierre-Louis Bossart * @num_ports: Number of ports 19167a908906SPierre-Louis Bossart * 19177a908906SPierre-Louis Bossart * It is expected that Slave is added before adding Master 19187a908906SPierre-Louis Bossart * to the Stream. 19197a908906SPierre-Louis Bossart * 19207a908906SPierre-Louis Bossart */ 19217a908906SPierre-Louis Bossart int sdw_stream_add_slave(struct sdw_slave *slave, 19227a908906SPierre-Louis Bossart struct sdw_stream_config *stream_config, 19237a908906SPierre-Louis Bossart struct sdw_port_config *port_config, 19247a908906SPierre-Louis Bossart unsigned int num_ports, 19257a908906SPierre-Louis Bossart struct sdw_stream_runtime *stream) 19267a908906SPierre-Louis Bossart { 19277a908906SPierre-Louis Bossart struct sdw_slave_runtime *s_rt; 19287a908906SPierre-Louis Bossart struct sdw_master_runtime *m_rt; 19297a908906SPierre-Louis Bossart int ret; 19307a908906SPierre-Louis Bossart 19317a908906SPierre-Louis Bossart mutex_lock(&slave->bus->bus_lock); 19327a908906SPierre-Louis Bossart 19337a908906SPierre-Louis Bossart /* 19347a908906SPierre-Louis Bossart * check if Master is already allocated, if so skip allocation 19357a908906SPierre-Louis Bossart * and go to configuration 19367a908906SPierre-Louis Bossart */ 19377a908906SPierre-Louis Bossart m_rt = sdw_master_rt_find(slave->bus, stream); 19387a908906SPierre-Louis Bossart if (m_rt) 19397a908906SPierre-Louis Bossart goto skip_alloc_master_rt; 19407a908906SPierre-Louis Bossart 19417a908906SPierre-Louis Bossart /* 19427a908906SPierre-Louis Bossart * If this API is invoked by Slave first then m_rt is not valid. 19437a908906SPierre-Louis Bossart * So, allocate m_rt and add Slave to it. 19447a908906SPierre-Louis Bossart */ 19457a908906SPierre-Louis Bossart m_rt = sdw_master_rt_alloc(slave->bus, stream); 19467a908906SPierre-Louis Bossart if (!m_rt) { 19477a908906SPierre-Louis Bossart dev_err(&slave->dev, "Master runtime alloc failed for stream:%s\n", stream->name); 19487a908906SPierre-Louis Bossart ret = -ENOMEM; 19497a908906SPierre-Louis Bossart goto error; 19507a908906SPierre-Louis Bossart } 19517a908906SPierre-Louis Bossart ret = sdw_master_rt_config(m_rt, stream_config); 19527a908906SPierre-Louis Bossart if (ret < 0) 19537a908906SPierre-Louis Bossart goto stream_error; 19547a908906SPierre-Louis Bossart 19557a908906SPierre-Louis Bossart skip_alloc_master_rt: 1956*42aad41eSPierre-Louis Bossart s_rt = sdw_slave_rt_alloc(slave, m_rt); 19577a908906SPierre-Louis Bossart if (!s_rt) { 19587a908906SPierre-Louis Bossart dev_err(&slave->dev, "Slave runtime alloc failed for stream:%s\n", stream->name); 19597a908906SPierre-Louis Bossart ret = -ENOMEM; 19607a908906SPierre-Louis Bossart goto stream_error; 19617a908906SPierre-Louis Bossart } 19627a908906SPierre-Louis Bossart 19637a908906SPierre-Louis Bossart ret = sdw_slave_rt_config(s_rt, stream_config); 19647a908906SPierre-Louis Bossart if (ret) 19657a908906SPierre-Louis Bossart goto stream_error; 19667a908906SPierre-Louis Bossart 19677a908906SPierre-Louis Bossart ret = sdw_config_stream(&slave->dev, stream, stream_config, true); 19687a908906SPierre-Louis Bossart if (ret) 19697a908906SPierre-Louis Bossart goto stream_error; 19707a908906SPierre-Louis Bossart 19717a908906SPierre-Louis Bossart ret = sdw_slave_port_alloc(slave, s_rt, num_ports); 19727a908906SPierre-Louis Bossart if (ret) 19737a908906SPierre-Louis Bossart goto stream_error; 19747a908906SPierre-Louis Bossart 19757a908906SPierre-Louis Bossart ret = sdw_slave_port_config(slave, s_rt, port_config); 19767a908906SPierre-Louis Bossart if (ret) 19777a908906SPierre-Louis Bossart goto stream_error; 19787a908906SPierre-Louis Bossart 19797a908906SPierre-Louis Bossart /* 19807a908906SPierre-Louis Bossart * Change stream state to CONFIGURED on first Slave add. 19817a908906SPierre-Louis Bossart * Bus is not aware of number of Slave(s) in a stream at this 19827a908906SPierre-Louis Bossart * point so cannot depend on all Slave(s) to be added in order to 19837a908906SPierre-Louis Bossart * change stream state to CONFIGURED. 19847a908906SPierre-Louis Bossart */ 19857a908906SPierre-Louis Bossart stream->state = SDW_STREAM_CONFIGURED; 19867a908906SPierre-Louis Bossart goto error; 19877a908906SPierre-Louis Bossart 19887a908906SPierre-Louis Bossart stream_error: 19897a908906SPierre-Louis Bossart /* 19907a908906SPierre-Louis Bossart * we hit error so cleanup the stream, release all Slave(s) and 19917a908906SPierre-Louis Bossart * Master runtime 19927a908906SPierre-Louis Bossart */ 199300ce0d2aSPierre-Louis Bossart sdw_master_rt_free(m_rt, stream); 19947a908906SPierre-Louis Bossart error: 19957a908906SPierre-Louis Bossart mutex_unlock(&slave->bus->bus_lock); 19967a908906SPierre-Louis Bossart return ret; 19977a908906SPierre-Louis Bossart } 19987a908906SPierre-Louis Bossart EXPORT_SYMBOL(sdw_stream_add_slave); 19997a908906SPierre-Louis Bossart 20007a908906SPierre-Louis Bossart /** 20017a908906SPierre-Louis Bossart * sdw_stream_remove_slave() - Remove slave from sdw_stream 20027a908906SPierre-Louis Bossart * 20037a908906SPierre-Louis Bossart * @slave: SDW Slave instance 20047a908906SPierre-Louis Bossart * @stream: SoundWire stream 20057a908906SPierre-Louis Bossart * 20067a908906SPierre-Louis Bossart * This removes and frees port_rt and slave_rt from a stream 20077a908906SPierre-Louis Bossart */ 20087a908906SPierre-Louis Bossart int sdw_stream_remove_slave(struct sdw_slave *slave, 20097a908906SPierre-Louis Bossart struct sdw_stream_runtime *stream) 20107a908906SPierre-Louis Bossart { 20117a908906SPierre-Louis Bossart mutex_lock(&slave->bus->bus_lock); 20127a908906SPierre-Louis Bossart 20137a908906SPierre-Louis Bossart sdw_slave_port_free(slave, stream); 201400ce0d2aSPierre-Louis Bossart sdw_slave_rt_free(slave, stream); 20157a908906SPierre-Louis Bossart 20167a908906SPierre-Louis Bossart mutex_unlock(&slave->bus->bus_lock); 20177a908906SPierre-Louis Bossart 20187a908906SPierre-Louis Bossart return 0; 20197a908906SPierre-Louis Bossart } 20207a908906SPierre-Louis Bossart EXPORT_SYMBOL(sdw_stream_remove_slave); 2021