1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/clk.h> 5 #include <linux/completion.h> 6 #include <linux/interrupt.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/debugfs.h> 11 #include <linux/of.h> 12 #include <linux/of_irq.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 #include <linux/slab.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/slimbus.h> 20 #include <linux/soundwire/sdw.h> 21 #include <linux/soundwire/sdw_registers.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include "bus.h" 25 26 #define SWRM_COMP_SW_RESET 0x008 27 #define SWRM_COMP_STATUS 0x014 28 #define SWRM_FRM_GEN_ENABLED BIT(0) 29 #define SWRM_COMP_HW_VERSION 0x00 30 #define SWRM_COMP_CFG_ADDR 0x04 31 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) 32 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0) 33 #define SWRM_COMP_PARAMS 0x100 34 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10) 35 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15) 36 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) 37 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) 38 #define SWRM_COMP_MASTER_ID 0x104 39 #define SWRM_INTERRUPT_STATUS 0x200 40 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) 41 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) 42 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) 43 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2) 44 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3) 45 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4) 46 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5) 47 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6) 48 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7) 49 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) 50 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) 51 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) 52 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) 53 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) 54 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) 55 #define SWRM_INTERRUPT_MAX 17 56 #define SWRM_INTERRUPT_MASK_ADDR 0x204 57 #define SWRM_INTERRUPT_CLEAR 0x208 58 #define SWRM_INTERRUPT_CPU_EN 0x210 59 #define SWRM_CMD_FIFO_WR_CMD 0x300 60 #define SWRM_CMD_FIFO_RD_CMD 0x304 61 #define SWRM_CMD_FIFO_CMD 0x308 62 #define SWRM_CMD_FIFO_FLUSH 0x1 63 #define SWRM_CMD_FIFO_STATUS 0x30C 64 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) 65 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) 66 #define SWRM_CMD_FIFO_CFG_ADDR 0x314 67 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) 68 #define SWRM_RD_WR_CMD_RETRIES 0x7 69 #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318 70 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) 71 #define SWRM_ENUMERATOR_CFG_ADDR 0x500 72 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) 73 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m)) 74 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m)) 75 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0) 76 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3) 77 #define SWRM_MCP_BUS_CTRL 0x1044 78 #define SWRM_MCP_BUS_CLK_START BIT(1) 79 #define SWRM_MCP_CFG_ADDR 0x1048 80 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17) 81 #define SWRM_DEF_CMD_NO_PINGS 0x1f 82 #define SWRM_MCP_STATUS 0x104C 83 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0) 84 #define SWRM_MCP_SLV_STATUS 0x1090 85 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0) 86 #define SWRM_MCP_SLV_STATUS_SZ 2 87 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m) 88 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m) 89 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1)) 90 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) 91 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) 92 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) 93 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) 94 #define SWR_MSTR_MAX_REG_ADDR (0x1740) 95 96 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 97 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 98 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 99 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 100 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 101 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d 102 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91 103 104 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ 105 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) 106 107 #define SWRM_SPECIAL_CMD_ID 0xF 108 #define MAX_FREQ_NUM 1 109 #define TIMEOUT_MS 100 110 #define QCOM_SWRM_MAX_RD_LEN 0x1 111 #define QCOM_SDW_MAX_PORTS 14 112 #define DEFAULT_CLK_FREQ 9600000 113 #define SWRM_MAX_DAIS 0xF 114 #define SWR_INVALID_PARAM 0xFF 115 #define SWR_HSTOP_MAX_VAL 0xF 116 #define SWR_HSTART_MIN_VAL 0x0 117 #define SWR_BROADCAST_CMD_ID 0x0F 118 #define SWR_MAX_CMD_ID 14 119 #define MAX_FIFO_RD_RETRY 3 120 #define SWR_OVERFLOW_RETRY_COUNT 30 121 #define SWRM_LINK_STATUS_RETRY_CNT 100 122 123 enum { 124 MASTER_ID_WSA = 1, 125 MASTER_ID_RX, 126 MASTER_ID_TX 127 }; 128 129 struct qcom_swrm_port_config { 130 u8 si; 131 u8 off1; 132 u8 off2; 133 u8 bp_mode; 134 u8 hstart; 135 u8 hstop; 136 u8 word_length; 137 u8 blk_group_count; 138 u8 lane_control; 139 }; 140 141 struct qcom_swrm_ctrl { 142 struct sdw_bus bus; 143 struct device *dev; 144 struct regmap *regmap; 145 void __iomem *mmio; 146 struct reset_control *audio_cgcr; 147 #ifdef CONFIG_DEBUG_FS 148 struct dentry *debugfs; 149 #endif 150 struct completion broadcast; 151 struct completion enumeration; 152 struct work_struct slave_work; 153 /* Port alloc/free lock */ 154 struct mutex port_lock; 155 struct clk *hclk; 156 u8 wr_cmd_id; 157 u8 rd_cmd_id; 158 int irq; 159 unsigned int version; 160 int wake_irq; 161 int num_din_ports; 162 int num_dout_ports; 163 int cols_index; 164 int rows_index; 165 unsigned long dout_port_mask; 166 unsigned long din_port_mask; 167 u32 intr_mask; 168 u8 rcmd_id; 169 u8 wcmd_id; 170 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS]; 171 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; 172 enum sdw_slave_status status[SDW_MAX_DEVICES + 1]; 173 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); 174 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); 175 u32 slave_status; 176 u32 wr_fifo_depth; 177 u32 rd_fifo_depth; 178 bool clock_stop_not_supported; 179 }; 180 181 struct qcom_swrm_data { 182 u32 default_cols; 183 u32 default_rows; 184 bool sw_clk_gate_required; 185 }; 186 187 static const struct qcom_swrm_data swrm_v1_3_data = { 188 .default_rows = 48, 189 .default_cols = 16, 190 }; 191 192 static const struct qcom_swrm_data swrm_v1_5_data = { 193 .default_rows = 50, 194 .default_cols = 16, 195 }; 196 197 static const struct qcom_swrm_data swrm_v1_6_data = { 198 .default_rows = 50, 199 .default_cols = 16, 200 .sw_clk_gate_required = true, 201 }; 202 203 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) 204 205 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 206 u32 *val) 207 { 208 struct regmap *wcd_regmap = ctrl->regmap; 209 int ret; 210 211 /* pg register + offset */ 212 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0, 213 (u8 *)®, 4); 214 if (ret < 0) 215 return SDW_CMD_FAIL; 216 217 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0, 218 val, 4); 219 if (ret < 0) 220 return SDW_CMD_FAIL; 221 222 return SDW_CMD_OK; 223 } 224 225 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, 226 int reg, int val) 227 { 228 struct regmap *wcd_regmap = ctrl->regmap; 229 int ret; 230 /* pg register + offset */ 231 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0, 232 (u8 *)&val, 4); 233 if (ret) 234 return SDW_CMD_FAIL; 235 236 /* write address register */ 237 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0, 238 (u8 *)®, 4); 239 if (ret) 240 return SDW_CMD_FAIL; 241 242 return SDW_CMD_OK; 243 } 244 245 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 246 u32 *val) 247 { 248 *val = readl(ctrl->mmio + reg); 249 return SDW_CMD_OK; 250 } 251 252 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, 253 int val) 254 { 255 writel(val, ctrl->mmio + reg); 256 return SDW_CMD_OK; 257 } 258 259 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, 260 u8 dev_addr, u16 reg_addr) 261 { 262 u32 val; 263 u8 id = *cmd_id; 264 265 if (id != SWR_BROADCAST_CMD_ID) { 266 if (id < SWR_MAX_CMD_ID) 267 id += 1; 268 else 269 id = 0; 270 *cmd_id = id; 271 } 272 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); 273 274 return val; 275 } 276 277 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) 278 { 279 u32 fifo_outstanding_data, value; 280 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 281 282 do { 283 /* Check for fifo underflow during read */ 284 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 285 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); 286 287 /* Check if read data is available in read fifo */ 288 if (fifo_outstanding_data > 0) 289 return 0; 290 291 usleep_range(500, 510); 292 } while (fifo_retry_count--); 293 294 if (fifo_outstanding_data == 0) { 295 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__); 296 return -EIO; 297 } 298 299 return 0; 300 } 301 302 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm) 303 { 304 u32 fifo_outstanding_cmds, value; 305 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 306 307 do { 308 /* Check for fifo overflow during write */ 309 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 310 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 311 312 /* Check for space in write fifo before writing */ 313 if (fifo_outstanding_cmds < swrm->wr_fifo_depth) 314 return 0; 315 316 usleep_range(500, 510); 317 } while (fifo_retry_count--); 318 319 if (fifo_outstanding_cmds == swrm->wr_fifo_depth) { 320 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__); 321 return -EIO; 322 } 323 324 return 0; 325 } 326 327 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, 328 u8 dev_addr, u16 reg_addr) 329 { 330 331 u32 val; 332 int ret = 0; 333 u8 cmd_id = 0x0; 334 335 if (dev_addr == SDW_BROADCAST_DEV_NUM) { 336 cmd_id = SWR_BROADCAST_CMD_ID; 337 val = swrm_get_packed_reg_val(&cmd_id, cmd_data, 338 dev_addr, reg_addr); 339 } else { 340 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, 341 dev_addr, reg_addr); 342 } 343 344 if (swrm_wait_for_wr_fifo_avail(swrm)) 345 return SDW_CMD_FAIL_OTHER; 346 347 /* Its assumed that write is okay as we do not get any status back */ 348 swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val); 349 350 /* version 1.3 or less */ 351 if (swrm->version <= 0x01030000) 352 usleep_range(150, 155); 353 354 if (cmd_id == SWR_BROADCAST_CMD_ID) { 355 /* 356 * sleep for 10ms for MSM soundwire variant to allow broadcast 357 * command to complete. 358 */ 359 ret = wait_for_completion_timeout(&swrm->broadcast, 360 msecs_to_jiffies(TIMEOUT_MS)); 361 if (!ret) 362 ret = SDW_CMD_IGNORED; 363 else 364 ret = SDW_CMD_OK; 365 366 } else { 367 ret = SDW_CMD_OK; 368 } 369 return ret; 370 } 371 372 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, 373 u8 dev_addr, u16 reg_addr, 374 u32 len, u8 *rval) 375 { 376 u32 cmd_data, cmd_id, val, retry_attempt = 0; 377 378 val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); 379 380 /* wait for FIFO RD to complete to avoid overflow */ 381 usleep_range(100, 105); 382 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); 383 /* wait for FIFO RD CMD complete to avoid overflow */ 384 usleep_range(250, 255); 385 386 if (swrm_wait_for_rd_fifo_avail(swrm)) 387 return SDW_CMD_FAIL_OTHER; 388 389 do { 390 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); 391 rval[0] = cmd_data & 0xFF; 392 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); 393 394 if (cmd_id != swrm->rcmd_id) { 395 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { 396 /* wait 500 us before retry on fifo read failure */ 397 usleep_range(500, 505); 398 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 399 SWRM_CMD_FIFO_FLUSH); 400 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); 401 } 402 retry_attempt++; 403 } else { 404 return SDW_CMD_OK; 405 } 406 407 } while (retry_attempt < MAX_FIFO_RD_RETRY); 408 409 dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ 410 dev_num: 0x%x, cmd_data: 0x%x\n", 411 reg_addr, swrm->rcmd_id, dev_addr, cmd_data); 412 413 return SDW_CMD_IGNORED; 414 } 415 416 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) 417 { 418 u32 val, status; 419 int dev_num; 420 421 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 422 423 for (dev_num = 0; dev_num <= SDW_MAX_DEVICES; dev_num++) { 424 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); 425 426 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { 427 ctrl->status[dev_num] = status; 428 return dev_num; 429 } 430 } 431 432 return -EINVAL; 433 } 434 435 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) 436 { 437 u32 val; 438 int i; 439 440 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 441 ctrl->slave_status = val; 442 443 for (i = 0; i <= SDW_MAX_DEVICES; i++) { 444 u32 s; 445 446 s = (val >> (i * 2)); 447 s &= SWRM_MCP_SLV_STATUS_MASK; 448 ctrl->status[i] = s; 449 } 450 } 451 452 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, 453 struct sdw_slave *slave, int devnum) 454 { 455 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 456 u32 status; 457 458 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); 459 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ)); 460 status &= SWRM_MCP_SLV_STATUS_MASK; 461 462 if (status == SDW_SLAVE_ATTACHED) { 463 if (slave) 464 slave->dev_num = devnum; 465 mutex_lock(&bus->bus_lock); 466 set_bit(devnum, bus->assigned); 467 mutex_unlock(&bus->bus_lock); 468 } 469 } 470 471 static int qcom_swrm_enumerate(struct sdw_bus *bus) 472 { 473 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 474 struct sdw_slave *slave, *_s; 475 struct sdw_slave_id id; 476 u32 val1, val2; 477 bool found; 478 u64 addr; 479 int i; 480 char *buf1 = (char *)&val1, *buf2 = (char *)&val2; 481 482 for (i = 1; i <= SDW_MAX_DEVICES; i++) { 483 /* do not continue if the status is Not Present */ 484 if (!ctrl->status[i]) 485 continue; 486 487 /*SCP_Devid5 - Devid 4*/ 488 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); 489 490 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ 491 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); 492 493 if (!val1 && !val2) 494 break; 495 496 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | 497 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) | 498 ((u64)buf1[0] << 40); 499 500 sdw_extract_slave_id(bus, addr, &id); 501 found = false; 502 /* Now compare with entries */ 503 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { 504 if (sdw_compare_devid(slave, id) == 0) { 505 qcom_swrm_set_slave_dev_num(bus, slave, i); 506 found = true; 507 break; 508 } 509 } 510 511 if (!found) { 512 qcom_swrm_set_slave_dev_num(bus, NULL, i); 513 sdw_slave_add(bus, &id, NULL); 514 } 515 } 516 517 complete(&ctrl->enumeration); 518 return 0; 519 } 520 521 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) 522 { 523 struct qcom_swrm_ctrl *swrm = dev_id; 524 int ret; 525 526 ret = pm_runtime_resume_and_get(swrm->dev); 527 if (ret < 0 && ret != -EACCES) { 528 dev_err_ratelimited(swrm->dev, 529 "pm_runtime_resume_and_get failed in %s, ret %d\n", 530 __func__, ret); 531 return ret; 532 } 533 534 if (swrm->wake_irq > 0) { 535 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) 536 disable_irq_nosync(swrm->wake_irq); 537 } 538 539 pm_runtime_mark_last_busy(swrm->dev); 540 pm_runtime_put_autosuspend(swrm->dev); 541 542 return IRQ_HANDLED; 543 } 544 545 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) 546 { 547 struct qcom_swrm_ctrl *swrm = dev_id; 548 u32 value, intr_sts, intr_sts_masked, slave_status; 549 u32 i; 550 int devnum; 551 int ret = IRQ_HANDLED; 552 clk_prepare_enable(swrm->hclk); 553 554 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); 555 intr_sts_masked = intr_sts & swrm->intr_mask; 556 557 do { 558 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { 559 value = intr_sts_masked & BIT(i); 560 if (!value) 561 continue; 562 563 switch (value) { 564 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: 565 devnum = qcom_swrm_get_alert_slave_dev_num(swrm); 566 if (devnum < 0) { 567 dev_err_ratelimited(swrm->dev, 568 "no slave alert found.spurious interrupt\n"); 569 } else { 570 sdw_handle_slave_status(&swrm->bus, swrm->status); 571 } 572 573 break; 574 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: 575 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: 576 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n", 577 __func__); 578 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); 579 if (swrm->slave_status == slave_status) { 580 dev_err(swrm->dev, "Slave status not changed %x\n", 581 slave_status); 582 } else { 583 qcom_swrm_get_device_status(swrm); 584 qcom_swrm_enumerate(&swrm->bus); 585 sdw_handle_slave_status(&swrm->bus, swrm->status); 586 } 587 break; 588 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: 589 dev_err_ratelimited(swrm->dev, 590 "%s: SWR bus clsh detected\n", 591 __func__); 592 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 593 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 594 break; 595 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: 596 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 597 dev_err_ratelimited(swrm->dev, 598 "%s: SWR read FIFO overflow fifo status 0x%x\n", 599 __func__, value); 600 break; 601 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: 602 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 603 dev_err_ratelimited(swrm->dev, 604 "%s: SWR read FIFO underflow fifo status 0x%x\n", 605 __func__, value); 606 break; 607 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: 608 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 609 dev_err(swrm->dev, 610 "%s: SWR write FIFO overflow fifo status %x\n", 611 __func__, value); 612 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); 613 break; 614 case SWRM_INTERRUPT_STATUS_CMD_ERROR: 615 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 616 dev_err_ratelimited(swrm->dev, 617 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", 618 __func__, value); 619 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); 620 break; 621 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: 622 dev_err_ratelimited(swrm->dev, 623 "%s: SWR Port collision detected\n", 624 __func__); 625 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; 626 swrm->reg_write(swrm, 627 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 628 break; 629 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: 630 dev_err_ratelimited(swrm->dev, 631 "%s: SWR read enable valid mismatch\n", 632 __func__); 633 swrm->intr_mask &= 634 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; 635 swrm->reg_write(swrm, 636 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 637 break; 638 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: 639 complete(&swrm->broadcast); 640 break; 641 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: 642 break; 643 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: 644 break; 645 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: 646 break; 647 default: 648 dev_err_ratelimited(swrm->dev, 649 "%s: SWR unknown interrupt value: %d\n", 650 __func__, value); 651 ret = IRQ_NONE; 652 break; 653 } 654 } 655 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); 656 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); 657 intr_sts_masked = intr_sts & swrm->intr_mask; 658 } while (intr_sts_masked); 659 660 clk_disable_unprepare(swrm->hclk); 661 return ret; 662 } 663 664 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) 665 { 666 u32 val; 667 668 /* Clear Rows and Cols */ 669 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); 670 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); 671 672 reset_control_reset(ctrl->audio_cgcr); 673 674 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); 675 676 /* Enable Auto enumeration */ 677 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); 678 679 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; 680 /* Mask soundwire interrupts */ 681 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, 682 SWRM_INTERRUPT_STATUS_RMSK); 683 684 /* Configure No pings */ 685 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); 686 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); 687 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); 688 689 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 690 /* Configure number of retries of a read/write cmd */ 691 if (ctrl->version > 0x01050001) { 692 /* Only for versions >= 1.5.1 */ 693 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 694 SWRM_RD_WR_CMD_RETRIES | 695 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE); 696 } else { 697 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 698 SWRM_RD_WR_CMD_RETRIES); 699 } 700 701 /* Set IRQ to PULSE */ 702 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 703 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | 704 SWRM_COMP_CFG_ENABLE_MSK); 705 706 /* enable CPU IRQs */ 707 if (ctrl->mmio) { 708 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, 709 SWRM_INTERRUPT_STATUS_RMSK); 710 } 711 ctrl->slave_status = 0; 712 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 713 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); 714 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); 715 716 return 0; 717 } 718 719 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, 720 struct sdw_msg *msg) 721 { 722 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 723 int ret, i, len; 724 725 if (msg->flags == SDW_MSG_FLAG_READ) { 726 for (i = 0; i < msg->len;) { 727 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) 728 len = msg->len - i; 729 else 730 len = QCOM_SWRM_MAX_RD_LEN; 731 732 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, 733 msg->addr + i, len, 734 &msg->buf[i]); 735 if (ret) 736 return ret; 737 738 i = i + len; 739 } 740 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { 741 for (i = 0; i < msg->len; i++) { 742 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], 743 msg->dev_num, 744 msg->addr + i); 745 if (ret) 746 return SDW_CMD_IGNORED; 747 } 748 } 749 750 return SDW_CMD_OK; 751 } 752 753 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) 754 { 755 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); 756 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 757 u32 val; 758 759 ctrl->reg_read(ctrl, reg, &val); 760 761 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); 762 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); 763 764 return ctrl->reg_write(ctrl, reg, val); 765 } 766 767 static int qcom_swrm_port_params(struct sdw_bus *bus, 768 struct sdw_port_params *p_params, 769 unsigned int bank) 770 { 771 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 772 773 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), 774 p_params->bps - 1); 775 776 } 777 778 static int qcom_swrm_transport_params(struct sdw_bus *bus, 779 struct sdw_transport_params *params, 780 enum sdw_reg_bank bank) 781 { 782 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 783 struct qcom_swrm_port_config *pcfg; 784 u32 value; 785 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); 786 int ret; 787 788 pcfg = &ctrl->pconfig[params->port_num]; 789 790 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; 791 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; 792 value |= pcfg->si; 793 794 ret = ctrl->reg_write(ctrl, reg, value); 795 if (ret) 796 goto err; 797 798 if (pcfg->lane_control != SWR_INVALID_PARAM) { 799 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); 800 value = pcfg->lane_control; 801 ret = ctrl->reg_write(ctrl, reg, value); 802 if (ret) 803 goto err; 804 } 805 806 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { 807 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); 808 value = pcfg->blk_group_count; 809 ret = ctrl->reg_write(ctrl, reg, value); 810 if (ret) 811 goto err; 812 } 813 814 if (pcfg->hstart != SWR_INVALID_PARAM 815 && pcfg->hstop != SWR_INVALID_PARAM) { 816 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 817 value = (pcfg->hstop << 4) | pcfg->hstart; 818 ret = ctrl->reg_write(ctrl, reg, value); 819 } else { 820 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 821 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL; 822 ret = ctrl->reg_write(ctrl, reg, value); 823 } 824 825 if (ret) 826 goto err; 827 828 if (pcfg->bp_mode != SWR_INVALID_PARAM) { 829 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); 830 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); 831 } 832 833 err: 834 return ret; 835 } 836 837 static int qcom_swrm_port_enable(struct sdw_bus *bus, 838 struct sdw_enable_ch *enable_ch, 839 unsigned int bank) 840 { 841 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); 842 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 843 u32 val; 844 845 ctrl->reg_read(ctrl, reg, &val); 846 847 if (enable_ch->enable) 848 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 849 else 850 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 851 852 return ctrl->reg_write(ctrl, reg, val); 853 } 854 855 static const struct sdw_master_port_ops qcom_swrm_port_ops = { 856 .dpn_set_port_params = qcom_swrm_port_params, 857 .dpn_set_port_transport_params = qcom_swrm_transport_params, 858 .dpn_port_enable_ch = qcom_swrm_port_enable, 859 }; 860 861 static const struct sdw_master_ops qcom_swrm_ops = { 862 .xfer_msg = qcom_swrm_xfer_msg, 863 .pre_bank_switch = qcom_swrm_pre_bank_switch, 864 }; 865 866 static int qcom_swrm_compute_params(struct sdw_bus *bus) 867 { 868 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 869 struct sdw_master_runtime *m_rt; 870 struct sdw_slave_runtime *s_rt; 871 struct sdw_port_runtime *p_rt; 872 struct qcom_swrm_port_config *pcfg; 873 struct sdw_slave *slave; 874 unsigned int m_port; 875 int i = 1; 876 877 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 878 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 879 pcfg = &ctrl->pconfig[p_rt->num]; 880 p_rt->transport_params.port_num = p_rt->num; 881 if (pcfg->word_length != SWR_INVALID_PARAM) { 882 sdw_fill_port_params(&p_rt->port_params, 883 p_rt->num, pcfg->word_length + 1, 884 SDW_PORT_FLOW_MODE_ISOCH, 885 SDW_PORT_DATA_MODE_NORMAL); 886 } 887 888 } 889 890 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 891 slave = s_rt->slave; 892 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 893 m_port = slave->m_port_map[p_rt->num]; 894 /* port config starts at offset 0 so -1 from actual port number */ 895 if (m_port) 896 pcfg = &ctrl->pconfig[m_port]; 897 else 898 pcfg = &ctrl->pconfig[i]; 899 p_rt->transport_params.port_num = p_rt->num; 900 p_rt->transport_params.sample_interval = 901 pcfg->si + 1; 902 p_rt->transport_params.offset1 = pcfg->off1; 903 p_rt->transport_params.offset2 = pcfg->off2; 904 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; 905 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; 906 907 p_rt->transport_params.hstart = pcfg->hstart; 908 p_rt->transport_params.hstop = pcfg->hstop; 909 p_rt->transport_params.lane_ctrl = pcfg->lane_control; 910 if (pcfg->word_length != SWR_INVALID_PARAM) { 911 sdw_fill_port_params(&p_rt->port_params, 912 p_rt->num, 913 pcfg->word_length + 1, 914 SDW_PORT_FLOW_MODE_ISOCH, 915 SDW_PORT_DATA_MODE_NORMAL); 916 } 917 i++; 918 } 919 } 920 } 921 922 return 0; 923 } 924 925 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = { 926 DEFAULT_CLK_FREQ, 927 }; 928 929 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, 930 struct sdw_stream_runtime *stream) 931 { 932 struct sdw_master_runtime *m_rt; 933 struct sdw_port_runtime *p_rt; 934 unsigned long *port_mask; 935 936 mutex_lock(&ctrl->port_lock); 937 938 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 939 if (m_rt->direction == SDW_DATA_DIR_RX) 940 port_mask = &ctrl->dout_port_mask; 941 else 942 port_mask = &ctrl->din_port_mask; 943 944 list_for_each_entry(p_rt, &m_rt->port_list, port_node) 945 clear_bit(p_rt->num, port_mask); 946 } 947 948 mutex_unlock(&ctrl->port_lock); 949 } 950 951 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, 952 struct sdw_stream_runtime *stream, 953 struct snd_pcm_hw_params *params, 954 int direction) 955 { 956 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS]; 957 struct sdw_stream_config sconfig; 958 struct sdw_master_runtime *m_rt; 959 struct sdw_slave_runtime *s_rt; 960 struct sdw_port_runtime *p_rt; 961 struct sdw_slave *slave; 962 unsigned long *port_mask; 963 int i, maxport, pn, nports = 0, ret = 0; 964 unsigned int m_port; 965 966 mutex_lock(&ctrl->port_lock); 967 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 968 if (m_rt->direction == SDW_DATA_DIR_RX) { 969 maxport = ctrl->num_dout_ports; 970 port_mask = &ctrl->dout_port_mask; 971 } else { 972 maxport = ctrl->num_din_ports; 973 port_mask = &ctrl->din_port_mask; 974 } 975 976 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 977 slave = s_rt->slave; 978 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 979 m_port = slave->m_port_map[p_rt->num]; 980 /* Port numbers start from 1 - 14*/ 981 if (m_port) 982 pn = m_port; 983 else 984 pn = find_first_zero_bit(port_mask, maxport); 985 986 if (pn > maxport) { 987 dev_err(ctrl->dev, "All ports busy\n"); 988 ret = -EBUSY; 989 goto err; 990 } 991 set_bit(pn, port_mask); 992 pconfig[nports].num = pn; 993 pconfig[nports].ch_mask = p_rt->ch_mask; 994 nports++; 995 } 996 } 997 } 998 999 if (direction == SNDRV_PCM_STREAM_CAPTURE) 1000 sconfig.direction = SDW_DATA_DIR_TX; 1001 else 1002 sconfig.direction = SDW_DATA_DIR_RX; 1003 1004 /* hw parameters wil be ignored as we only support PDM */ 1005 sconfig.ch_count = 1; 1006 sconfig.frame_rate = params_rate(params); 1007 sconfig.type = stream->type; 1008 sconfig.bps = 1; 1009 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, 1010 nports, stream); 1011 err: 1012 if (ret) { 1013 for (i = 0; i < nports; i++) 1014 clear_bit(pconfig[i].num, port_mask); 1015 } 1016 1017 mutex_unlock(&ctrl->port_lock); 1018 1019 return ret; 1020 } 1021 1022 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, 1023 struct snd_pcm_hw_params *params, 1024 struct snd_soc_dai *dai) 1025 { 1026 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1027 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1028 int ret; 1029 1030 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, 1031 substream->stream); 1032 if (ret) 1033 qcom_swrm_stream_free_ports(ctrl, sruntime); 1034 1035 return ret; 1036 } 1037 1038 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, 1039 struct snd_soc_dai *dai) 1040 { 1041 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1042 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1043 1044 qcom_swrm_stream_free_ports(ctrl, sruntime); 1045 sdw_stream_remove_master(&ctrl->bus, sruntime); 1046 1047 return 0; 1048 } 1049 1050 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, 1051 void *stream, int direction) 1052 { 1053 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1054 1055 ctrl->sruntime[dai->id] = stream; 1056 1057 return 0; 1058 } 1059 1060 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) 1061 { 1062 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1063 1064 return ctrl->sruntime[dai->id]; 1065 } 1066 1067 static int qcom_swrm_startup(struct snd_pcm_substream *substream, 1068 struct snd_soc_dai *dai) 1069 { 1070 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1071 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1072 struct sdw_stream_runtime *sruntime; 1073 struct snd_soc_dai *codec_dai; 1074 int ret, i; 1075 1076 ret = pm_runtime_resume_and_get(ctrl->dev); 1077 if (ret < 0 && ret != -EACCES) { 1078 dev_err_ratelimited(ctrl->dev, 1079 "pm_runtime_resume_and_get failed in %s, ret %d\n", 1080 __func__, ret); 1081 return ret; 1082 } 1083 1084 sruntime = sdw_alloc_stream(dai->name); 1085 if (!sruntime) 1086 return -ENOMEM; 1087 1088 ctrl->sruntime[dai->id] = sruntime; 1089 1090 for_each_rtd_codec_dais(rtd, i, codec_dai) { 1091 ret = snd_soc_dai_set_stream(codec_dai, sruntime, 1092 substream->stream); 1093 if (ret < 0 && ret != -ENOTSUPP) { 1094 dev_err(dai->dev, "Failed to set sdw stream on %s\n", 1095 codec_dai->name); 1096 sdw_release_stream(sruntime); 1097 return ret; 1098 } 1099 } 1100 1101 return 0; 1102 } 1103 1104 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, 1105 struct snd_soc_dai *dai) 1106 { 1107 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1108 1109 sdw_release_stream(ctrl->sruntime[dai->id]); 1110 ctrl->sruntime[dai->id] = NULL; 1111 pm_runtime_mark_last_busy(ctrl->dev); 1112 pm_runtime_put_autosuspend(ctrl->dev); 1113 1114 } 1115 1116 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { 1117 .hw_params = qcom_swrm_hw_params, 1118 .hw_free = qcom_swrm_hw_free, 1119 .startup = qcom_swrm_startup, 1120 .shutdown = qcom_swrm_shutdown, 1121 .set_stream = qcom_swrm_set_sdw_stream, 1122 .get_stream = qcom_swrm_get_sdw_stream, 1123 }; 1124 1125 static const struct snd_soc_component_driver qcom_swrm_dai_component = { 1126 .name = "soundwire", 1127 }; 1128 1129 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) 1130 { 1131 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; 1132 struct snd_soc_dai_driver *dais; 1133 struct snd_soc_pcm_stream *stream; 1134 struct device *dev = ctrl->dev; 1135 int i; 1136 1137 /* PDM dais are only tested for now */ 1138 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 1139 if (!dais) 1140 return -ENOMEM; 1141 1142 for (i = 0; i < num_dais; i++) { 1143 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i); 1144 if (!dais[i].name) 1145 return -ENOMEM; 1146 1147 if (i < ctrl->num_dout_ports) 1148 stream = &dais[i].playback; 1149 else 1150 stream = &dais[i].capture; 1151 1152 stream->channels_min = 1; 1153 stream->channels_max = 1; 1154 stream->rates = SNDRV_PCM_RATE_48000; 1155 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 1156 1157 dais[i].ops = &qcom_swrm_pdm_dai_ops; 1158 dais[i].id = i; 1159 } 1160 1161 return devm_snd_soc_register_component(ctrl->dev, 1162 &qcom_swrm_dai_component, 1163 dais, num_dais); 1164 } 1165 1166 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) 1167 { 1168 struct device_node *np = ctrl->dev->of_node; 1169 u8 off1[QCOM_SDW_MAX_PORTS]; 1170 u8 off2[QCOM_SDW_MAX_PORTS]; 1171 u8 si[QCOM_SDW_MAX_PORTS]; 1172 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; 1173 u8 hstart[QCOM_SDW_MAX_PORTS]; 1174 u8 hstop[QCOM_SDW_MAX_PORTS]; 1175 u8 word_length[QCOM_SDW_MAX_PORTS]; 1176 u8 blk_group_count[QCOM_SDW_MAX_PORTS]; 1177 u8 lane_control[QCOM_SDW_MAX_PORTS]; 1178 int i, ret, nports, val; 1179 1180 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 1181 1182 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); 1183 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); 1184 1185 ret = of_property_read_u32(np, "qcom,din-ports", &val); 1186 if (ret) 1187 return ret; 1188 1189 if (val > ctrl->num_din_ports) 1190 return -EINVAL; 1191 1192 ctrl->num_din_ports = val; 1193 1194 ret = of_property_read_u32(np, "qcom,dout-ports", &val); 1195 if (ret) 1196 return ret; 1197 1198 if (val > ctrl->num_dout_ports) 1199 return -EINVAL; 1200 1201 ctrl->num_dout_ports = val; 1202 1203 nports = ctrl->num_dout_ports + ctrl->num_din_ports; 1204 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ 1205 set_bit(0, &ctrl->dout_port_mask); 1206 set_bit(0, &ctrl->din_port_mask); 1207 1208 ret = of_property_read_u8_array(np, "qcom,ports-offset1", 1209 off1, nports); 1210 if (ret) 1211 return ret; 1212 1213 ret = of_property_read_u8_array(np, "qcom,ports-offset2", 1214 off2, nports); 1215 if (ret) 1216 return ret; 1217 1218 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", 1219 si, nports); 1220 if (ret) 1221 return ret; 1222 1223 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", 1224 bp_mode, nports); 1225 if (ret) { 1226 if (ctrl->version <= 0x01030000) 1227 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1228 else 1229 return ret; 1230 } 1231 1232 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1233 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); 1234 1235 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1236 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); 1237 1238 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1239 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); 1240 1241 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1242 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); 1243 1244 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1245 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); 1246 1247 for (i = 0; i < nports; i++) { 1248 /* Valid port number range is from 1-14 */ 1249 ctrl->pconfig[i + 1].si = si[i]; 1250 ctrl->pconfig[i + 1].off1 = off1[i]; 1251 ctrl->pconfig[i + 1].off2 = off2[i]; 1252 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; 1253 ctrl->pconfig[i + 1].hstart = hstart[i]; 1254 ctrl->pconfig[i + 1].hstop = hstop[i]; 1255 ctrl->pconfig[i + 1].word_length = word_length[i]; 1256 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; 1257 ctrl->pconfig[i + 1].lane_control = lane_control[i]; 1258 } 1259 1260 return 0; 1261 } 1262 1263 #ifdef CONFIG_DEBUG_FS 1264 static int swrm_reg_show(struct seq_file *s_file, void *data) 1265 { 1266 struct qcom_swrm_ctrl *swrm = s_file->private; 1267 int reg, reg_val, ret; 1268 1269 ret = pm_runtime_resume_and_get(swrm->dev); 1270 if (ret < 0 && ret != -EACCES) { 1271 dev_err_ratelimited(swrm->dev, 1272 "pm_runtime_resume_and_get failed in %s, ret %d\n", 1273 __func__, ret); 1274 return ret; 1275 } 1276 1277 for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) { 1278 swrm->reg_read(swrm, reg, ®_val); 1279 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); 1280 } 1281 pm_runtime_mark_last_busy(swrm->dev); 1282 pm_runtime_put_autosuspend(swrm->dev); 1283 1284 1285 return 0; 1286 } 1287 DEFINE_SHOW_ATTRIBUTE(swrm_reg); 1288 #endif 1289 1290 static int qcom_swrm_probe(struct platform_device *pdev) 1291 { 1292 struct device *dev = &pdev->dev; 1293 struct sdw_master_prop *prop; 1294 struct sdw_bus_params *params; 1295 struct qcom_swrm_ctrl *ctrl; 1296 const struct qcom_swrm_data *data; 1297 int ret; 1298 u32 val; 1299 1300 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1301 if (!ctrl) 1302 return -ENOMEM; 1303 1304 data = of_device_get_match_data(dev); 1305 ctrl->rows_index = sdw_find_row_index(data->default_rows); 1306 ctrl->cols_index = sdw_find_col_index(data->default_cols); 1307 #if IS_REACHABLE(CONFIG_SLIMBUS) 1308 if (dev->parent->bus == &slimbus_bus) { 1309 #else 1310 if (false) { 1311 #endif 1312 ctrl->reg_read = qcom_swrm_ahb_reg_read; 1313 ctrl->reg_write = qcom_swrm_ahb_reg_write; 1314 ctrl->regmap = dev_get_regmap(dev->parent, NULL); 1315 if (!ctrl->regmap) 1316 return -EINVAL; 1317 } else { 1318 ctrl->reg_read = qcom_swrm_cpu_reg_read; 1319 ctrl->reg_write = qcom_swrm_cpu_reg_write; 1320 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0); 1321 if (IS_ERR(ctrl->mmio)) 1322 return PTR_ERR(ctrl->mmio); 1323 } 1324 1325 if (data->sw_clk_gate_required) { 1326 ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr"); 1327 if (IS_ERR_OR_NULL(ctrl->audio_cgcr)) { 1328 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n"); 1329 ret = PTR_ERR(ctrl->audio_cgcr); 1330 goto err_init; 1331 } 1332 } 1333 1334 ctrl->irq = of_irq_get(dev->of_node, 0); 1335 if (ctrl->irq < 0) { 1336 ret = ctrl->irq; 1337 goto err_init; 1338 } 1339 1340 ctrl->hclk = devm_clk_get(dev, "iface"); 1341 if (IS_ERR(ctrl->hclk)) { 1342 ret = PTR_ERR(ctrl->hclk); 1343 goto err_init; 1344 } 1345 1346 clk_prepare_enable(ctrl->hclk); 1347 1348 ctrl->dev = dev; 1349 dev_set_drvdata(&pdev->dev, ctrl); 1350 mutex_init(&ctrl->port_lock); 1351 init_completion(&ctrl->broadcast); 1352 init_completion(&ctrl->enumeration); 1353 1354 ctrl->bus.ops = &qcom_swrm_ops; 1355 ctrl->bus.port_ops = &qcom_swrm_port_ops; 1356 ctrl->bus.compute_params = &qcom_swrm_compute_params; 1357 ctrl->bus.clk_stop_timeout = 300; 1358 1359 ret = qcom_swrm_get_port_config(ctrl); 1360 if (ret) 1361 goto err_clk; 1362 1363 params = &ctrl->bus.params; 1364 params->max_dr_freq = DEFAULT_CLK_FREQ; 1365 params->curr_dr_freq = DEFAULT_CLK_FREQ; 1366 params->col = data->default_cols; 1367 params->row = data->default_rows; 1368 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val); 1369 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK; 1370 params->next_bank = !params->curr_bank; 1371 1372 prop = &ctrl->bus.prop; 1373 prop->max_clk_freq = DEFAULT_CLK_FREQ; 1374 prop->num_clk_gears = 0; 1375 prop->num_clk_freq = MAX_FREQ_NUM; 1376 prop->clk_freq = &qcom_swrm_freq_tbl[0]; 1377 prop->default_col = data->default_cols; 1378 prop->default_row = data->default_rows; 1379 1380 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); 1381 1382 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, 1383 qcom_swrm_irq_handler, 1384 IRQF_TRIGGER_RISING | 1385 IRQF_ONESHOT, 1386 "soundwire", ctrl); 1387 if (ret) { 1388 dev_err(dev, "Failed to request soundwire irq\n"); 1389 goto err_clk; 1390 } 1391 1392 ctrl->wake_irq = of_irq_get(dev->of_node, 1); 1393 if (ctrl->wake_irq > 0) { 1394 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL, 1395 qcom_swrm_wake_irq_handler, 1396 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1397 "swr_wake_irq", ctrl); 1398 if (ret) { 1399 dev_err(dev, "Failed to request soundwire wake irq\n"); 1400 goto err_init; 1401 } 1402 } 1403 1404 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); 1405 if (ret) { 1406 dev_err(dev, "Failed to register Soundwire controller (%d)\n", 1407 ret); 1408 goto err_clk; 1409 } 1410 1411 qcom_swrm_init(ctrl); 1412 wait_for_completion_timeout(&ctrl->enumeration, 1413 msecs_to_jiffies(TIMEOUT_MS)); 1414 ret = qcom_swrm_register_dais(ctrl); 1415 if (ret) 1416 goto err_master_add; 1417 1418 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", 1419 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, 1420 ctrl->version & 0xffff); 1421 1422 pm_runtime_set_autosuspend_delay(dev, 3000); 1423 pm_runtime_use_autosuspend(dev); 1424 pm_runtime_mark_last_busy(dev); 1425 pm_runtime_set_active(dev); 1426 pm_runtime_enable(dev); 1427 1428 /* Clk stop is not supported on WSA Soundwire masters */ 1429 if (ctrl->version <= 0x01030000) { 1430 ctrl->clock_stop_not_supported = true; 1431 } else { 1432 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val); 1433 if (val == MASTER_ID_WSA) 1434 ctrl->clock_stop_not_supported = true; 1435 } 1436 1437 #ifdef CONFIG_DEBUG_FS 1438 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs); 1439 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl, 1440 &swrm_reg_fops); 1441 #endif 1442 1443 return 0; 1444 1445 err_master_add: 1446 sdw_bus_master_delete(&ctrl->bus); 1447 err_clk: 1448 clk_disable_unprepare(ctrl->hclk); 1449 err_init: 1450 return ret; 1451 } 1452 1453 static int qcom_swrm_remove(struct platform_device *pdev) 1454 { 1455 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); 1456 1457 sdw_bus_master_delete(&ctrl->bus); 1458 clk_disable_unprepare(ctrl->hclk); 1459 1460 return 0; 1461 } 1462 1463 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) 1464 { 1465 int retry = SWRM_LINK_STATUS_RETRY_CNT; 1466 int comp_sts; 1467 1468 do { 1469 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts); 1470 1471 if (comp_sts & SWRM_FRM_GEN_ENABLED) 1472 return true; 1473 1474 usleep_range(500, 510); 1475 } while (retry--); 1476 1477 dev_err(swrm->dev, "%s: link status not %s\n", __func__, 1478 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); 1479 1480 return false; 1481 } 1482 1483 static int __maybe_unused swrm_runtime_resume(struct device *dev) 1484 { 1485 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1486 int ret; 1487 1488 if (ctrl->wake_irq > 0) { 1489 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1490 disable_irq_nosync(ctrl->wake_irq); 1491 } 1492 1493 clk_prepare_enable(ctrl->hclk); 1494 1495 if (ctrl->clock_stop_not_supported) { 1496 reinit_completion(&ctrl->enumeration); 1497 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01); 1498 usleep_range(100, 105); 1499 1500 qcom_swrm_init(ctrl); 1501 1502 usleep_range(100, 105); 1503 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1504 dev_err(ctrl->dev, "link failed to connect\n"); 1505 1506 /* wait for hw enumeration to complete */ 1507 wait_for_completion_timeout(&ctrl->enumeration, 1508 msecs_to_jiffies(TIMEOUT_MS)); 1509 qcom_swrm_get_device_status(ctrl); 1510 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 1511 } else { 1512 reset_control_reset(ctrl->audio_cgcr); 1513 1514 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 1515 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, 1516 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); 1517 1518 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1519 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); 1520 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); 1521 1522 usleep_range(100, 105); 1523 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1524 dev_err(ctrl->dev, "link failed to connect\n"); 1525 1526 ret = sdw_bus_exit_clk_stop(&ctrl->bus); 1527 if (ret < 0) 1528 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret); 1529 } 1530 1531 return 0; 1532 } 1533 1534 static int __maybe_unused swrm_runtime_suspend(struct device *dev) 1535 { 1536 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1537 int ret; 1538 1539 if (!ctrl->clock_stop_not_supported) { 1540 /* Mask bus clash interrupt */ 1541 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1542 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); 1543 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); 1544 /* Prepare slaves for clock stop */ 1545 ret = sdw_bus_prep_clk_stop(&ctrl->bus); 1546 if (ret < 0 && ret != -ENODATA) { 1547 dev_err(dev, "prepare clock stop failed %d", ret); 1548 return ret; 1549 } 1550 1551 ret = sdw_bus_clk_stop(&ctrl->bus); 1552 if (ret < 0 && ret != -ENODATA) { 1553 dev_err(dev, "bus clock stop failed %d", ret); 1554 return ret; 1555 } 1556 } 1557 1558 clk_disable_unprepare(ctrl->hclk); 1559 1560 usleep_range(300, 305); 1561 1562 if (ctrl->wake_irq > 0) { 1563 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1564 enable_irq(ctrl->wake_irq); 1565 } 1566 1567 return 0; 1568 } 1569 1570 static const struct dev_pm_ops swrm_dev_pm_ops = { 1571 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL) 1572 }; 1573 1574 static const struct of_device_id qcom_swrm_of_match[] = { 1575 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, 1576 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, 1577 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, 1578 {/* sentinel */}, 1579 }; 1580 1581 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); 1582 1583 static struct platform_driver qcom_swrm_driver = { 1584 .probe = &qcom_swrm_probe, 1585 .remove = &qcom_swrm_remove, 1586 .driver = { 1587 .name = "qcom-soundwire", 1588 .of_match_table = qcom_swrm_of_match, 1589 .pm = &swrm_dev_pm_ops, 1590 } 1591 }; 1592 module_platform_driver(qcom_swrm_driver); 1593 1594 MODULE_DESCRIPTION("Qualcomm soundwire driver"); 1595 MODULE_LICENSE("GPL v2"); 1596