1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/clk.h> 5 #include <linux/completion.h> 6 #include <linux/interrupt.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/debugfs.h> 11 #include <linux/of.h> 12 #include <linux/of_irq.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 #include <linux/slab.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/slimbus.h> 20 #include <linux/soundwire/sdw.h> 21 #include <linux/soundwire/sdw_registers.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include "bus.h" 25 26 #define SWRM_COMP_SW_RESET 0x008 27 #define SWRM_COMP_STATUS 0x014 28 #define SWRM_LINK_MANAGER_EE 0x018 29 #define SWRM_EE_CPU 1 30 #define SWRM_FRM_GEN_ENABLED BIT(0) 31 #define SWRM_VERSION_1_3_0 0x01030000 32 #define SWRM_VERSION_1_5_1 0x01050001 33 #define SWRM_VERSION_1_7_0 0x01070000 34 #define SWRM_VERSION_2_0_0 0x02000000 35 #define SWRM_COMP_HW_VERSION 0x00 36 #define SWRM_COMP_CFG_ADDR 0x04 37 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) 38 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0) 39 #define SWRM_COMP_PARAMS 0x100 40 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10) 41 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15) 42 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) 43 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) 44 #define SWRM_COMP_MASTER_ID 0x104 45 #define SWRM_V1_3_INTERRUPT_STATUS 0x200 46 #define SWRM_V2_0_INTERRUPT_STATUS 0x5000 47 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) 48 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) 49 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) 50 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2) 51 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3) 52 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4) 53 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5) 54 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6) 55 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7) 56 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) 57 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) 58 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) 59 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) 60 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) 61 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) 62 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) 63 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) 64 #define SWRM_INTERRUPT_MAX 17 65 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 66 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 67 #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008 68 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 69 #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004 70 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 71 #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020 72 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 73 #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024 74 #define SWRM_CMD_FIFO_CMD 0x308 75 #define SWRM_CMD_FIFO_FLUSH 0x1 76 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C 77 #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050 78 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) 79 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) 80 #define SWRM_CMD_FIFO_CFG_ADDR 0x314 81 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) 82 #define SWRM_RD_WR_CMD_RETRIES 0x7 83 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 84 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040 85 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) 86 #define SWRM_ENUMERATOR_CFG_ADDR 0x500 87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) 88 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m)) 89 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m)) 90 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0) 91 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3) 92 #define SWRM_MCP_BUS_CTRL 0x1044 93 #define SWRM_MCP_BUS_CLK_START BIT(1) 94 #define SWRM_MCP_CFG_ADDR 0x1048 95 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17) 96 #define SWRM_DEF_CMD_NO_PINGS 0x1f 97 #define SWRM_MCP_STATUS 0x104C 98 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0) 99 #define SWRM_MCP_SLV_STATUS 0x1090 100 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0) 101 #define SWRM_MCP_SLV_STATUS_SZ 2 102 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m) 103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m) 104 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1)) 105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) 106 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) 107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) 108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) 109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) 110 #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740 111 #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac 112 113 #define SWRM_V2_0_CLK_CTRL 0x5060 114 #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) 115 #define SWRM_V2_0_LINK_STATUS 0x5064 116 117 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 118 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 119 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 120 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 121 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 122 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d 123 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91 124 125 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ 126 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) 127 128 #define MAX_FREQ_NUM 1 129 #define TIMEOUT_MS 100 130 #define QCOM_SWRM_MAX_RD_LEN 0x1 131 #define QCOM_SDW_MAX_PORTS 14 132 #define DEFAULT_CLK_FREQ 9600000 133 #define SWRM_MAX_DAIS 0xF 134 #define SWR_INVALID_PARAM 0xFF 135 #define SWR_HSTOP_MAX_VAL 0xF 136 #define SWR_HSTART_MIN_VAL 0x0 137 #define SWR_BROADCAST_CMD_ID 0x0F 138 #define SWR_MAX_CMD_ID 14 139 #define MAX_FIFO_RD_RETRY 3 140 #define SWR_OVERFLOW_RETRY_COUNT 30 141 #define SWRM_LINK_STATUS_RETRY_CNT 100 142 143 enum { 144 MASTER_ID_WSA = 1, 145 MASTER_ID_RX, 146 MASTER_ID_TX 147 }; 148 149 struct qcom_swrm_port_config { 150 u16 si; 151 u8 off1; 152 u8 off2; 153 u8 bp_mode; 154 u8 hstart; 155 u8 hstop; 156 u8 word_length; 157 u8 blk_group_count; 158 u8 lane_control; 159 }; 160 161 /* 162 * Internal IDs for different register layouts. Only few registers differ per 163 * each variant, so the list of IDs below does not include all of registers. 164 */ 165 enum { 166 SWRM_REG_FRAME_GEN_ENABLED, 167 SWRM_REG_INTERRUPT_STATUS, 168 SWRM_REG_INTERRUPT_MASK_ADDR, 169 SWRM_REG_INTERRUPT_CLEAR, 170 SWRM_REG_INTERRUPT_CPU_EN, 171 SWRM_REG_CMD_FIFO_WR_CMD, 172 SWRM_REG_CMD_FIFO_RD_CMD, 173 SWRM_REG_CMD_FIFO_STATUS, 174 SWRM_REG_CMD_FIFO_RD_FIFO_ADDR, 175 }; 176 177 struct qcom_swrm_ctrl { 178 struct sdw_bus bus; 179 struct device *dev; 180 struct regmap *regmap; 181 u32 max_reg; 182 const unsigned int *reg_layout; 183 void __iomem *mmio; 184 struct reset_control *audio_cgcr; 185 #ifdef CONFIG_DEBUG_FS 186 struct dentry *debugfs; 187 #endif 188 struct completion broadcast; 189 struct completion enumeration; 190 /* Port alloc/free lock */ 191 struct mutex port_lock; 192 struct clk *hclk; 193 int irq; 194 unsigned int version; 195 int wake_irq; 196 int num_din_ports; 197 int num_dout_ports; 198 int cols_index; 199 int rows_index; 200 unsigned long dout_port_mask; 201 unsigned long din_port_mask; 202 u32 intr_mask; 203 u8 rcmd_id; 204 u8 wcmd_id; 205 /* Port numbers are 1 - 14 */ 206 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1]; 207 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; 208 enum sdw_slave_status status[SDW_MAX_DEVICES + 1]; 209 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); 210 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); 211 u32 slave_status; 212 u32 wr_fifo_depth; 213 u32 rd_fifo_depth; 214 bool clock_stop_not_supported; 215 }; 216 217 struct qcom_swrm_data { 218 u32 default_cols; 219 u32 default_rows; 220 bool sw_clk_gate_required; 221 u32 max_reg; 222 const unsigned int *reg_layout; 223 }; 224 225 static const unsigned int swrm_v1_3_reg_layout[] = { 226 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS, 227 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS, 228 [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR, 229 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR, 230 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN, 231 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD, 232 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD, 233 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS, 234 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR, 235 }; 236 237 static const struct qcom_swrm_data swrm_v1_3_data = { 238 .default_rows = 48, 239 .default_cols = 16, 240 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 241 .reg_layout = swrm_v1_3_reg_layout, 242 }; 243 244 static const struct qcom_swrm_data swrm_v1_5_data = { 245 .default_rows = 50, 246 .default_cols = 16, 247 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 248 .reg_layout = swrm_v1_3_reg_layout, 249 }; 250 251 static const struct qcom_swrm_data swrm_v1_6_data = { 252 .default_rows = 50, 253 .default_cols = 16, 254 .sw_clk_gate_required = true, 255 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 256 .reg_layout = swrm_v1_3_reg_layout, 257 }; 258 259 static const unsigned int swrm_v2_0_reg_layout[] = { 260 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS, 261 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS, 262 [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */ 263 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR, 264 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN, 265 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD, 266 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD, 267 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS, 268 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR, 269 }; 270 271 static const struct qcom_swrm_data swrm_v2_0_data = { 272 .default_rows = 50, 273 .default_cols = 16, 274 .sw_clk_gate_required = true, 275 .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR, 276 .reg_layout = swrm_v2_0_reg_layout, 277 }; 278 279 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) 280 281 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 282 u32 *val) 283 { 284 struct regmap *wcd_regmap = ctrl->regmap; 285 int ret; 286 287 /* pg register + offset */ 288 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0, 289 (u8 *)®, 4); 290 if (ret < 0) 291 return SDW_CMD_FAIL; 292 293 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0, 294 val, 4); 295 if (ret < 0) 296 return SDW_CMD_FAIL; 297 298 return SDW_CMD_OK; 299 } 300 301 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, 302 int reg, int val) 303 { 304 struct regmap *wcd_regmap = ctrl->regmap; 305 int ret; 306 /* pg register + offset */ 307 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0, 308 (u8 *)&val, 4); 309 if (ret) 310 return SDW_CMD_FAIL; 311 312 /* write address register */ 313 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0, 314 (u8 *)®, 4); 315 if (ret) 316 return SDW_CMD_FAIL; 317 318 return SDW_CMD_OK; 319 } 320 321 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 322 u32 *val) 323 { 324 *val = readl(ctrl->mmio + reg); 325 return SDW_CMD_OK; 326 } 327 328 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, 329 int val) 330 { 331 writel(val, ctrl->mmio + reg); 332 return SDW_CMD_OK; 333 } 334 335 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, 336 u8 dev_addr, u16 reg_addr) 337 { 338 u32 val; 339 u8 id = *cmd_id; 340 341 if (id != SWR_BROADCAST_CMD_ID) { 342 if (id < SWR_MAX_CMD_ID) 343 id += 1; 344 else 345 id = 0; 346 *cmd_id = id; 347 } 348 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); 349 350 return val; 351 } 352 353 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) 354 { 355 u32 fifo_outstanding_data, value; 356 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 357 358 do { 359 /* Check for fifo underflow during read */ 360 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 361 &value); 362 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); 363 364 /* Check if read data is available in read fifo */ 365 if (fifo_outstanding_data > 0) 366 return 0; 367 368 usleep_range(500, 510); 369 } while (fifo_retry_count--); 370 371 if (fifo_outstanding_data == 0) { 372 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); 373 return -EIO; 374 } 375 376 return 0; 377 } 378 379 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) 380 { 381 u32 fifo_outstanding_cmds, value; 382 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 383 384 do { 385 /* Check for fifo overflow during write */ 386 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 387 &value); 388 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 389 390 /* Check for space in write fifo before writing */ 391 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) 392 return 0; 393 394 usleep_range(500, 510); 395 } while (fifo_retry_count--); 396 397 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { 398 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); 399 return -EIO; 400 } 401 402 return 0; 403 } 404 405 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) 406 { 407 u32 fifo_outstanding_cmds, value; 408 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 409 410 /* Check for fifo overflow during write */ 411 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); 412 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 413 414 if (fifo_outstanding_cmds) { 415 while (fifo_retry_count) { 416 usleep_range(500, 510); 417 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); 418 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 419 fifo_retry_count--; 420 if (fifo_outstanding_cmds == 0) 421 return true; 422 } 423 } else { 424 return true; 425 } 426 427 428 return false; 429 } 430 431 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, 432 u8 dev_addr, u16 reg_addr) 433 { 434 435 u32 val; 436 int ret = 0; 437 u8 cmd_id = 0x0; 438 439 if (dev_addr == SDW_BROADCAST_DEV_NUM) { 440 cmd_id = SWR_BROADCAST_CMD_ID; 441 val = swrm_get_packed_reg_val(&cmd_id, cmd_data, 442 dev_addr, reg_addr); 443 } else { 444 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, 445 dev_addr, reg_addr); 446 } 447 448 if (swrm_wait_for_wr_fifo_avail(ctrl)) 449 return SDW_CMD_FAIL_OTHER; 450 451 if (cmd_id == SWR_BROADCAST_CMD_ID) 452 reinit_completion(&ctrl->broadcast); 453 454 /* Its assumed that write is okay as we do not get any status back */ 455 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); 456 457 if (ctrl->version <= SWRM_VERSION_1_3_0) 458 usleep_range(150, 155); 459 460 if (cmd_id == SWR_BROADCAST_CMD_ID) { 461 swrm_wait_for_wr_fifo_done(ctrl); 462 /* 463 * sleep for 10ms for MSM soundwire variant to allow broadcast 464 * command to complete. 465 */ 466 ret = wait_for_completion_timeout(&ctrl->broadcast, 467 msecs_to_jiffies(TIMEOUT_MS)); 468 if (!ret) 469 ret = SDW_CMD_IGNORED; 470 else 471 ret = SDW_CMD_OK; 472 473 } else { 474 ret = SDW_CMD_OK; 475 } 476 return ret; 477 } 478 479 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, 480 u8 dev_addr, u16 reg_addr, 481 u32 len, u8 *rval) 482 { 483 u32 cmd_data, cmd_id, val, retry_attempt = 0; 484 485 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); 486 487 /* 488 * Check for outstanding cmd wrt. write fifo depth to avoid 489 * overflow as read will also increase write fifo cnt. 490 */ 491 swrm_wait_for_wr_fifo_avail(ctrl); 492 493 /* wait for FIFO RD to complete to avoid overflow */ 494 usleep_range(100, 105); 495 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); 496 /* wait for FIFO RD CMD complete to avoid overflow */ 497 usleep_range(250, 255); 498 499 if (swrm_wait_for_rd_fifo_avail(ctrl)) 500 return SDW_CMD_FAIL_OTHER; 501 502 do { 503 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], 504 &cmd_data); 505 rval[0] = cmd_data & 0xFF; 506 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); 507 508 if (cmd_id != ctrl->rcmd_id) { 509 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { 510 /* wait 500 us before retry on fifo read failure */ 511 usleep_range(500, 505); 512 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 513 SWRM_CMD_FIFO_FLUSH); 514 ctrl->reg_write(ctrl, 515 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], 516 val); 517 } 518 retry_attempt++; 519 } else { 520 return SDW_CMD_OK; 521 } 522 523 } while (retry_attempt < MAX_FIFO_RD_RETRY); 524 525 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ 526 dev_num: 0x%x, cmd_data: 0x%x\n", 527 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); 528 529 return SDW_CMD_IGNORED; 530 } 531 532 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) 533 { 534 u32 val, status; 535 int dev_num; 536 537 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 538 539 for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) { 540 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); 541 542 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { 543 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; 544 return dev_num; 545 } 546 } 547 548 return -EINVAL; 549 } 550 551 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) 552 { 553 u32 val; 554 int i; 555 556 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 557 ctrl->slave_status = val; 558 559 for (i = 1; i <= SDW_MAX_DEVICES; i++) { 560 u32 s; 561 562 s = (val >> (i * 2)); 563 s &= SWRM_MCP_SLV_STATUS_MASK; 564 ctrl->status[i] = s; 565 } 566 } 567 568 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, 569 struct sdw_slave *slave, int devnum) 570 { 571 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 572 u32 status; 573 574 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); 575 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ)); 576 status &= SWRM_MCP_SLV_STATUS_MASK; 577 578 if (status == SDW_SLAVE_ATTACHED) { 579 if (slave) 580 slave->dev_num = devnum; 581 mutex_lock(&bus->bus_lock); 582 set_bit(devnum, bus->assigned); 583 mutex_unlock(&bus->bus_lock); 584 } 585 } 586 587 static int qcom_swrm_enumerate(struct sdw_bus *bus) 588 { 589 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 590 struct sdw_slave *slave, *_s; 591 struct sdw_slave_id id; 592 u32 val1, val2; 593 bool found; 594 u64 addr; 595 int i; 596 char *buf1 = (char *)&val1, *buf2 = (char *)&val2; 597 598 for (i = 1; i <= SDW_MAX_DEVICES; i++) { 599 /* do not continue if the status is Not Present */ 600 if (!ctrl->status[i]) 601 continue; 602 603 /*SCP_Devid5 - Devid 4*/ 604 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); 605 606 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ 607 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); 608 609 if (!val1 && !val2) 610 break; 611 612 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | 613 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) | 614 ((u64)buf1[0] << 40); 615 616 sdw_extract_slave_id(bus, addr, &id); 617 found = false; 618 ctrl->clock_stop_not_supported = false; 619 /* Now compare with entries */ 620 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { 621 if (sdw_compare_devid(slave, id) == 0) { 622 qcom_swrm_set_slave_dev_num(bus, slave, i); 623 if (slave->prop.clk_stop_mode1) 624 ctrl->clock_stop_not_supported = true; 625 626 found = true; 627 break; 628 } 629 } 630 631 if (!found) { 632 qcom_swrm_set_slave_dev_num(bus, NULL, i); 633 sdw_slave_add(bus, &id, NULL); 634 } 635 } 636 637 complete(&ctrl->enumeration); 638 return 0; 639 } 640 641 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) 642 { 643 struct qcom_swrm_ctrl *ctrl = dev_id; 644 int ret; 645 646 ret = pm_runtime_get_sync(ctrl->dev); 647 if (ret < 0 && ret != -EACCES) { 648 dev_err_ratelimited(ctrl->dev, 649 "pm_runtime_get_sync failed in %s, ret %d\n", 650 __func__, ret); 651 pm_runtime_put_noidle(ctrl->dev); 652 return ret; 653 } 654 655 if (ctrl->wake_irq > 0) { 656 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 657 disable_irq_nosync(ctrl->wake_irq); 658 } 659 660 pm_runtime_mark_last_busy(ctrl->dev); 661 pm_runtime_put_autosuspend(ctrl->dev); 662 663 return IRQ_HANDLED; 664 } 665 666 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) 667 { 668 struct qcom_swrm_ctrl *ctrl = dev_id; 669 u32 value, intr_sts, intr_sts_masked, slave_status; 670 u32 i; 671 int devnum; 672 int ret = IRQ_HANDLED; 673 clk_prepare_enable(ctrl->hclk); 674 675 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], 676 &intr_sts); 677 intr_sts_masked = intr_sts & ctrl->intr_mask; 678 679 do { 680 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { 681 value = intr_sts_masked & BIT(i); 682 if (!value) 683 continue; 684 685 switch (value) { 686 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: 687 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); 688 if (devnum < 0) { 689 dev_err_ratelimited(ctrl->dev, 690 "no slave alert found.spurious interrupt\n"); 691 } else { 692 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 693 } 694 695 break; 696 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: 697 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: 698 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); 699 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); 700 if (ctrl->slave_status == slave_status) { 701 dev_dbg(ctrl->dev, "Slave status not changed %x\n", 702 slave_status); 703 } else { 704 qcom_swrm_get_device_status(ctrl); 705 qcom_swrm_enumerate(&ctrl->bus); 706 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 707 } 708 break; 709 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: 710 dev_err_ratelimited(ctrl->dev, 711 "%s: SWR bus clsh detected\n", 712 __func__); 713 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 714 ctrl->reg_write(ctrl, 715 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 716 ctrl->intr_mask); 717 break; 718 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: 719 ctrl->reg_read(ctrl, 720 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 721 &value); 722 dev_err_ratelimited(ctrl->dev, 723 "%s: SWR read FIFO overflow fifo status 0x%x\n", 724 __func__, value); 725 break; 726 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: 727 ctrl->reg_read(ctrl, 728 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 729 &value); 730 dev_err_ratelimited(ctrl->dev, 731 "%s: SWR read FIFO underflow fifo status 0x%x\n", 732 __func__, value); 733 break; 734 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: 735 ctrl->reg_read(ctrl, 736 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 737 &value); 738 dev_err(ctrl->dev, 739 "%s: SWR write FIFO overflow fifo status %x\n", 740 __func__, value); 741 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); 742 break; 743 case SWRM_INTERRUPT_STATUS_CMD_ERROR: 744 ctrl->reg_read(ctrl, 745 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 746 &value); 747 dev_err_ratelimited(ctrl->dev, 748 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", 749 __func__, value); 750 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); 751 break; 752 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: 753 dev_err_ratelimited(ctrl->dev, 754 "%s: SWR Port collision detected\n", 755 __func__); 756 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; 757 ctrl->reg_write(ctrl, 758 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 759 ctrl->intr_mask); 760 break; 761 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: 762 dev_err_ratelimited(ctrl->dev, 763 "%s: SWR read enable valid mismatch\n", 764 __func__); 765 ctrl->intr_mask &= 766 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; 767 ctrl->reg_write(ctrl, 768 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 769 ctrl->intr_mask); 770 break; 771 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: 772 complete(&ctrl->broadcast); 773 break; 774 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: 775 break; 776 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: 777 break; 778 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: 779 break; 780 default: 781 dev_err_ratelimited(ctrl->dev, 782 "%s: SWR unknown interrupt value: %d\n", 783 __func__, value); 784 ret = IRQ_NONE; 785 break; 786 } 787 } 788 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 789 intr_sts); 790 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], 791 &intr_sts); 792 intr_sts_masked = intr_sts & ctrl->intr_mask; 793 } while (intr_sts_masked); 794 795 clk_disable_unprepare(ctrl->hclk); 796 return ret; 797 } 798 799 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) 800 { 801 int retry = SWRM_LINK_STATUS_RETRY_CNT; 802 int comp_sts; 803 804 do { 805 ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts); 806 807 if (comp_sts & SWRM_FRM_GEN_ENABLED) 808 return true; 809 810 usleep_range(500, 510); 811 } while (retry--); 812 813 dev_err(ctrl->dev, "%s: link status not %s\n", __func__, 814 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); 815 816 return false; 817 } 818 819 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) 820 { 821 u32 val; 822 823 /* Clear Rows and Cols */ 824 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); 825 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); 826 827 reset_control_reset(ctrl->audio_cgcr); 828 829 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); 830 831 /* Enable Auto enumeration */ 832 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); 833 834 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; 835 /* Mask soundwire interrupts */ 836 if (ctrl->version < SWRM_VERSION_2_0_0) 837 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 838 SWRM_INTERRUPT_STATUS_RMSK); 839 840 /* Configure No pings */ 841 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); 842 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); 843 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); 844 845 if (ctrl->version == SWRM_VERSION_1_7_0) { 846 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 847 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, 848 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); 849 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { 850 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 851 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, 852 SWRM_V2_0_CLK_CTRL_CLK_START); 853 } else { 854 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 855 } 856 857 /* Configure number of retries of a read/write cmd */ 858 if (ctrl->version >= SWRM_VERSION_1_5_1) { 859 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 860 SWRM_RD_WR_CMD_RETRIES | 861 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE); 862 } else { 863 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 864 SWRM_RD_WR_CMD_RETRIES); 865 } 866 867 /* COMP Enable */ 868 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); 869 870 /* Set IRQ to PULSE */ 871 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 872 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK); 873 874 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 875 0xFFFFFFFF); 876 877 /* enable CPU IRQs */ 878 if (ctrl->mmio) { 879 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 880 SWRM_INTERRUPT_STATUS_RMSK); 881 } 882 883 /* Set IRQ to PULSE */ 884 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 885 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | 886 SWRM_COMP_CFG_ENABLE_MSK); 887 888 swrm_wait_for_frame_gen_enabled(ctrl); 889 ctrl->slave_status = 0; 890 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 891 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); 892 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); 893 894 return 0; 895 } 896 897 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, 898 struct sdw_msg *msg) 899 { 900 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 901 int ret, i, len; 902 903 if (msg->flags == SDW_MSG_FLAG_READ) { 904 for (i = 0; i < msg->len;) { 905 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) 906 len = msg->len - i; 907 else 908 len = QCOM_SWRM_MAX_RD_LEN; 909 910 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, 911 msg->addr + i, len, 912 &msg->buf[i]); 913 if (ret) 914 return ret; 915 916 i = i + len; 917 } 918 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { 919 for (i = 0; i < msg->len; i++) { 920 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], 921 msg->dev_num, 922 msg->addr + i); 923 if (ret) 924 return SDW_CMD_IGNORED; 925 } 926 } 927 928 return SDW_CMD_OK; 929 } 930 931 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) 932 { 933 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); 934 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 935 u32 val; 936 937 ctrl->reg_read(ctrl, reg, &val); 938 939 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); 940 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); 941 942 return ctrl->reg_write(ctrl, reg, val); 943 } 944 945 static int qcom_swrm_port_params(struct sdw_bus *bus, 946 struct sdw_port_params *p_params, 947 unsigned int bank) 948 { 949 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 950 951 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), 952 p_params->bps - 1); 953 954 } 955 956 static int qcom_swrm_transport_params(struct sdw_bus *bus, 957 struct sdw_transport_params *params, 958 enum sdw_reg_bank bank) 959 { 960 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 961 struct qcom_swrm_port_config *pcfg; 962 u32 value; 963 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); 964 int ret; 965 966 pcfg = &ctrl->pconfig[params->port_num]; 967 968 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; 969 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; 970 value |= pcfg->si & 0xff; 971 972 ret = ctrl->reg_write(ctrl, reg, value); 973 if (ret) 974 goto err; 975 976 if (pcfg->si > 0xff) { 977 value = (pcfg->si >> 8) & 0xff; 978 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); 979 ret = ctrl->reg_write(ctrl, reg, value); 980 if (ret) 981 goto err; 982 } 983 984 if (pcfg->lane_control != SWR_INVALID_PARAM) { 985 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); 986 value = pcfg->lane_control; 987 ret = ctrl->reg_write(ctrl, reg, value); 988 if (ret) 989 goto err; 990 } 991 992 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { 993 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); 994 value = pcfg->blk_group_count; 995 ret = ctrl->reg_write(ctrl, reg, value); 996 if (ret) 997 goto err; 998 } 999 1000 if (pcfg->hstart != SWR_INVALID_PARAM 1001 && pcfg->hstop != SWR_INVALID_PARAM) { 1002 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 1003 value = (pcfg->hstop << 4) | pcfg->hstart; 1004 ret = ctrl->reg_write(ctrl, reg, value); 1005 } else { 1006 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 1007 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL; 1008 ret = ctrl->reg_write(ctrl, reg, value); 1009 } 1010 1011 if (ret) 1012 goto err; 1013 1014 if (pcfg->bp_mode != SWR_INVALID_PARAM) { 1015 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); 1016 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); 1017 } 1018 1019 err: 1020 return ret; 1021 } 1022 1023 static int qcom_swrm_port_enable(struct sdw_bus *bus, 1024 struct sdw_enable_ch *enable_ch, 1025 unsigned int bank) 1026 { 1027 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); 1028 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 1029 u32 val; 1030 1031 ctrl->reg_read(ctrl, reg, &val); 1032 1033 if (enable_ch->enable) 1034 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 1035 else 1036 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 1037 1038 return ctrl->reg_write(ctrl, reg, val); 1039 } 1040 1041 static const struct sdw_master_port_ops qcom_swrm_port_ops = { 1042 .dpn_set_port_params = qcom_swrm_port_params, 1043 .dpn_set_port_transport_params = qcom_swrm_transport_params, 1044 .dpn_port_enable_ch = qcom_swrm_port_enable, 1045 }; 1046 1047 static const struct sdw_master_ops qcom_swrm_ops = { 1048 .xfer_msg = qcom_swrm_xfer_msg, 1049 .pre_bank_switch = qcom_swrm_pre_bank_switch, 1050 }; 1051 1052 static int qcom_swrm_compute_params(struct sdw_bus *bus) 1053 { 1054 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 1055 struct sdw_master_runtime *m_rt; 1056 struct sdw_slave_runtime *s_rt; 1057 struct sdw_port_runtime *p_rt; 1058 struct qcom_swrm_port_config *pcfg; 1059 struct sdw_slave *slave; 1060 unsigned int m_port; 1061 int i = 1; 1062 1063 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 1064 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 1065 pcfg = &ctrl->pconfig[p_rt->num]; 1066 p_rt->transport_params.port_num = p_rt->num; 1067 if (pcfg->word_length != SWR_INVALID_PARAM) { 1068 sdw_fill_port_params(&p_rt->port_params, 1069 p_rt->num, pcfg->word_length + 1, 1070 SDW_PORT_FLOW_MODE_ISOCH, 1071 SDW_PORT_DATA_MODE_NORMAL); 1072 } 1073 1074 } 1075 1076 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 1077 slave = s_rt->slave; 1078 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 1079 m_port = slave->m_port_map[p_rt->num]; 1080 /* port config starts at offset 0 so -1 from actual port number */ 1081 if (m_port) 1082 pcfg = &ctrl->pconfig[m_port]; 1083 else 1084 pcfg = &ctrl->pconfig[i]; 1085 p_rt->transport_params.port_num = p_rt->num; 1086 p_rt->transport_params.sample_interval = 1087 pcfg->si + 1; 1088 p_rt->transport_params.offset1 = pcfg->off1; 1089 p_rt->transport_params.offset2 = pcfg->off2; 1090 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; 1091 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; 1092 1093 p_rt->transport_params.hstart = pcfg->hstart; 1094 p_rt->transport_params.hstop = pcfg->hstop; 1095 p_rt->transport_params.lane_ctrl = pcfg->lane_control; 1096 if (pcfg->word_length != SWR_INVALID_PARAM) { 1097 sdw_fill_port_params(&p_rt->port_params, 1098 p_rt->num, 1099 pcfg->word_length + 1, 1100 SDW_PORT_FLOW_MODE_ISOCH, 1101 SDW_PORT_DATA_MODE_NORMAL); 1102 } 1103 i++; 1104 } 1105 } 1106 } 1107 1108 return 0; 1109 } 1110 1111 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = { 1112 DEFAULT_CLK_FREQ, 1113 }; 1114 1115 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, 1116 struct sdw_stream_runtime *stream) 1117 { 1118 struct sdw_master_runtime *m_rt; 1119 struct sdw_port_runtime *p_rt; 1120 unsigned long *port_mask; 1121 1122 mutex_lock(&ctrl->port_lock); 1123 1124 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 1125 if (m_rt->direction == SDW_DATA_DIR_RX) 1126 port_mask = &ctrl->dout_port_mask; 1127 else 1128 port_mask = &ctrl->din_port_mask; 1129 1130 list_for_each_entry(p_rt, &m_rt->port_list, port_node) 1131 clear_bit(p_rt->num, port_mask); 1132 } 1133 1134 mutex_unlock(&ctrl->port_lock); 1135 } 1136 1137 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, 1138 struct sdw_stream_runtime *stream, 1139 struct snd_pcm_hw_params *params, 1140 int direction) 1141 { 1142 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS]; 1143 struct sdw_stream_config sconfig; 1144 struct sdw_master_runtime *m_rt; 1145 struct sdw_slave_runtime *s_rt; 1146 struct sdw_port_runtime *p_rt; 1147 struct sdw_slave *slave; 1148 unsigned long *port_mask; 1149 int i, maxport, pn, nports = 0, ret = 0; 1150 unsigned int m_port; 1151 1152 mutex_lock(&ctrl->port_lock); 1153 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 1154 if (m_rt->direction == SDW_DATA_DIR_RX) { 1155 maxport = ctrl->num_dout_ports; 1156 port_mask = &ctrl->dout_port_mask; 1157 } else { 1158 maxport = ctrl->num_din_ports; 1159 port_mask = &ctrl->din_port_mask; 1160 } 1161 1162 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 1163 slave = s_rt->slave; 1164 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 1165 m_port = slave->m_port_map[p_rt->num]; 1166 /* Port numbers start from 1 - 14*/ 1167 if (m_port) 1168 pn = m_port; 1169 else 1170 pn = find_first_zero_bit(port_mask, maxport); 1171 1172 if (pn > maxport) { 1173 dev_err(ctrl->dev, "All ports busy\n"); 1174 ret = -EBUSY; 1175 goto err; 1176 } 1177 set_bit(pn, port_mask); 1178 pconfig[nports].num = pn; 1179 pconfig[nports].ch_mask = p_rt->ch_mask; 1180 nports++; 1181 } 1182 } 1183 } 1184 1185 if (direction == SNDRV_PCM_STREAM_CAPTURE) 1186 sconfig.direction = SDW_DATA_DIR_TX; 1187 else 1188 sconfig.direction = SDW_DATA_DIR_RX; 1189 1190 /* hw parameters wil be ignored as we only support PDM */ 1191 sconfig.ch_count = 1; 1192 sconfig.frame_rate = params_rate(params); 1193 sconfig.type = stream->type; 1194 sconfig.bps = 1; 1195 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, 1196 nports, stream); 1197 err: 1198 if (ret) { 1199 for (i = 0; i < nports; i++) 1200 clear_bit(pconfig[i].num, port_mask); 1201 } 1202 1203 mutex_unlock(&ctrl->port_lock); 1204 1205 return ret; 1206 } 1207 1208 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, 1209 struct snd_pcm_hw_params *params, 1210 struct snd_soc_dai *dai) 1211 { 1212 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1213 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1214 int ret; 1215 1216 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, 1217 substream->stream); 1218 if (ret) 1219 qcom_swrm_stream_free_ports(ctrl, sruntime); 1220 1221 return ret; 1222 } 1223 1224 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, 1225 struct snd_soc_dai *dai) 1226 { 1227 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1228 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1229 1230 qcom_swrm_stream_free_ports(ctrl, sruntime); 1231 sdw_stream_remove_master(&ctrl->bus, sruntime); 1232 1233 return 0; 1234 } 1235 1236 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, 1237 void *stream, int direction) 1238 { 1239 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1240 1241 ctrl->sruntime[dai->id] = stream; 1242 1243 return 0; 1244 } 1245 1246 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) 1247 { 1248 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1249 1250 return ctrl->sruntime[dai->id]; 1251 } 1252 1253 static int qcom_swrm_startup(struct snd_pcm_substream *substream, 1254 struct snd_soc_dai *dai) 1255 { 1256 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1257 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1258 struct sdw_stream_runtime *sruntime; 1259 struct snd_soc_dai *codec_dai; 1260 int ret, i; 1261 1262 ret = pm_runtime_get_sync(ctrl->dev); 1263 if (ret < 0 && ret != -EACCES) { 1264 dev_err_ratelimited(ctrl->dev, 1265 "pm_runtime_get_sync failed in %s, ret %d\n", 1266 __func__, ret); 1267 pm_runtime_put_noidle(ctrl->dev); 1268 return ret; 1269 } 1270 1271 sruntime = sdw_alloc_stream(dai->name); 1272 if (!sruntime) { 1273 ret = -ENOMEM; 1274 goto err_alloc; 1275 } 1276 1277 ctrl->sruntime[dai->id] = sruntime; 1278 1279 for_each_rtd_codec_dais(rtd, i, codec_dai) { 1280 ret = snd_soc_dai_set_stream(codec_dai, sruntime, 1281 substream->stream); 1282 if (ret < 0 && ret != -ENOTSUPP) { 1283 dev_err(dai->dev, "Failed to set sdw stream on %s\n", 1284 codec_dai->name); 1285 goto err_set_stream; 1286 } 1287 } 1288 1289 return 0; 1290 1291 err_set_stream: 1292 sdw_release_stream(sruntime); 1293 err_alloc: 1294 pm_runtime_mark_last_busy(ctrl->dev); 1295 pm_runtime_put_autosuspend(ctrl->dev); 1296 1297 return ret; 1298 } 1299 1300 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, 1301 struct snd_soc_dai *dai) 1302 { 1303 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1304 1305 swrm_wait_for_wr_fifo_done(ctrl); 1306 sdw_release_stream(ctrl->sruntime[dai->id]); 1307 ctrl->sruntime[dai->id] = NULL; 1308 pm_runtime_mark_last_busy(ctrl->dev); 1309 pm_runtime_put_autosuspend(ctrl->dev); 1310 1311 } 1312 1313 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { 1314 .hw_params = qcom_swrm_hw_params, 1315 .hw_free = qcom_swrm_hw_free, 1316 .startup = qcom_swrm_startup, 1317 .shutdown = qcom_swrm_shutdown, 1318 .set_stream = qcom_swrm_set_sdw_stream, 1319 .get_stream = qcom_swrm_get_sdw_stream, 1320 }; 1321 1322 static const struct snd_soc_component_driver qcom_swrm_dai_component = { 1323 .name = "soundwire", 1324 }; 1325 1326 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) 1327 { 1328 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; 1329 struct snd_soc_dai_driver *dais; 1330 struct snd_soc_pcm_stream *stream; 1331 struct device *dev = ctrl->dev; 1332 int i; 1333 1334 /* PDM dais are only tested for now */ 1335 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 1336 if (!dais) 1337 return -ENOMEM; 1338 1339 for (i = 0; i < num_dais; i++) { 1340 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i); 1341 if (!dais[i].name) 1342 return -ENOMEM; 1343 1344 if (i < ctrl->num_dout_ports) 1345 stream = &dais[i].playback; 1346 else 1347 stream = &dais[i].capture; 1348 1349 stream->channels_min = 1; 1350 stream->channels_max = 1; 1351 stream->rates = SNDRV_PCM_RATE_48000; 1352 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 1353 1354 dais[i].ops = &qcom_swrm_pdm_dai_ops; 1355 dais[i].id = i; 1356 } 1357 1358 return devm_snd_soc_register_component(ctrl->dev, 1359 &qcom_swrm_dai_component, 1360 dais, num_dais); 1361 } 1362 1363 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) 1364 { 1365 struct device_node *np = ctrl->dev->of_node; 1366 u8 off1[QCOM_SDW_MAX_PORTS]; 1367 u8 off2[QCOM_SDW_MAX_PORTS]; 1368 u16 si[QCOM_SDW_MAX_PORTS]; 1369 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; 1370 u8 hstart[QCOM_SDW_MAX_PORTS]; 1371 u8 hstop[QCOM_SDW_MAX_PORTS]; 1372 u8 word_length[QCOM_SDW_MAX_PORTS]; 1373 u8 blk_group_count[QCOM_SDW_MAX_PORTS]; 1374 u8 lane_control[QCOM_SDW_MAX_PORTS]; 1375 int i, ret, nports, val; 1376 bool si_16 = false; 1377 1378 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 1379 1380 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); 1381 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); 1382 1383 ret = of_property_read_u32(np, "qcom,din-ports", &val); 1384 if (ret) 1385 return ret; 1386 1387 if (val > ctrl->num_din_ports) 1388 return -EINVAL; 1389 1390 ctrl->num_din_ports = val; 1391 1392 ret = of_property_read_u32(np, "qcom,dout-ports", &val); 1393 if (ret) 1394 return ret; 1395 1396 if (val > ctrl->num_dout_ports) 1397 return -EINVAL; 1398 1399 ctrl->num_dout_ports = val; 1400 1401 nports = ctrl->num_dout_ports + ctrl->num_din_ports; 1402 if (nports > QCOM_SDW_MAX_PORTS) 1403 return -EINVAL; 1404 1405 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ 1406 set_bit(0, &ctrl->dout_port_mask); 1407 set_bit(0, &ctrl->din_port_mask); 1408 1409 ret = of_property_read_u8_array(np, "qcom,ports-offset1", 1410 off1, nports); 1411 if (ret) 1412 return ret; 1413 1414 ret = of_property_read_u8_array(np, "qcom,ports-offset2", 1415 off2, nports); 1416 if (ret) 1417 return ret; 1418 1419 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", 1420 (u8 *)si, nports); 1421 if (ret) { 1422 ret = of_property_read_u16_array(np, "qcom,ports-sinterval", 1423 si, nports); 1424 if (ret) 1425 return ret; 1426 si_16 = true; 1427 } 1428 1429 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", 1430 bp_mode, nports); 1431 if (ret) { 1432 if (ctrl->version <= SWRM_VERSION_1_3_0) 1433 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1434 else 1435 return ret; 1436 } 1437 1438 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1439 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); 1440 1441 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1442 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); 1443 1444 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1445 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); 1446 1447 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1448 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); 1449 1450 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1451 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); 1452 1453 for (i = 0; i < nports; i++) { 1454 /* Valid port number range is from 1-14 */ 1455 if (si_16) 1456 ctrl->pconfig[i + 1].si = si[i]; 1457 else 1458 ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; 1459 ctrl->pconfig[i + 1].off1 = off1[i]; 1460 ctrl->pconfig[i + 1].off2 = off2[i]; 1461 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; 1462 ctrl->pconfig[i + 1].hstart = hstart[i]; 1463 ctrl->pconfig[i + 1].hstop = hstop[i]; 1464 ctrl->pconfig[i + 1].word_length = word_length[i]; 1465 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; 1466 ctrl->pconfig[i + 1].lane_control = lane_control[i]; 1467 } 1468 1469 return 0; 1470 } 1471 1472 #ifdef CONFIG_DEBUG_FS 1473 static int swrm_reg_show(struct seq_file *s_file, void *data) 1474 { 1475 struct qcom_swrm_ctrl *ctrl = s_file->private; 1476 int reg, reg_val, ret; 1477 1478 ret = pm_runtime_get_sync(ctrl->dev); 1479 if (ret < 0 && ret != -EACCES) { 1480 dev_err_ratelimited(ctrl->dev, 1481 "pm_runtime_get_sync failed in %s, ret %d\n", 1482 __func__, ret); 1483 pm_runtime_put_noidle(ctrl->dev); 1484 return ret; 1485 } 1486 1487 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { 1488 ctrl->reg_read(ctrl, reg, ®_val); 1489 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); 1490 } 1491 pm_runtime_mark_last_busy(ctrl->dev); 1492 pm_runtime_put_autosuspend(ctrl->dev); 1493 1494 1495 return 0; 1496 } 1497 DEFINE_SHOW_ATTRIBUTE(swrm_reg); 1498 #endif 1499 1500 static int qcom_swrm_probe(struct platform_device *pdev) 1501 { 1502 struct device *dev = &pdev->dev; 1503 struct sdw_master_prop *prop; 1504 struct sdw_bus_params *params; 1505 struct qcom_swrm_ctrl *ctrl; 1506 const struct qcom_swrm_data *data; 1507 int ret; 1508 u32 val; 1509 1510 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1511 if (!ctrl) 1512 return -ENOMEM; 1513 1514 data = of_device_get_match_data(dev); 1515 ctrl->max_reg = data->max_reg; 1516 ctrl->reg_layout = data->reg_layout; 1517 ctrl->rows_index = sdw_find_row_index(data->default_rows); 1518 ctrl->cols_index = sdw_find_col_index(data->default_cols); 1519 #if IS_REACHABLE(CONFIG_SLIMBUS) 1520 if (dev->parent->bus == &slimbus_bus) { 1521 #else 1522 if (false) { 1523 #endif 1524 ctrl->reg_read = qcom_swrm_ahb_reg_read; 1525 ctrl->reg_write = qcom_swrm_ahb_reg_write; 1526 ctrl->regmap = dev_get_regmap(dev->parent, NULL); 1527 if (!ctrl->regmap) 1528 return -EINVAL; 1529 } else { 1530 ctrl->reg_read = qcom_swrm_cpu_reg_read; 1531 ctrl->reg_write = qcom_swrm_cpu_reg_write; 1532 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0); 1533 if (IS_ERR(ctrl->mmio)) 1534 return PTR_ERR(ctrl->mmio); 1535 } 1536 1537 if (data->sw_clk_gate_required) { 1538 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr"); 1539 if (IS_ERR(ctrl->audio_cgcr)) { 1540 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n"); 1541 ret = PTR_ERR(ctrl->audio_cgcr); 1542 goto err_init; 1543 } 1544 } 1545 1546 ctrl->irq = of_irq_get(dev->of_node, 0); 1547 if (ctrl->irq < 0) { 1548 ret = ctrl->irq; 1549 goto err_init; 1550 } 1551 1552 ctrl->hclk = devm_clk_get(dev, "iface"); 1553 if (IS_ERR(ctrl->hclk)) { 1554 ret = PTR_ERR(ctrl->hclk); 1555 goto err_init; 1556 } 1557 1558 clk_prepare_enable(ctrl->hclk); 1559 1560 ctrl->dev = dev; 1561 dev_set_drvdata(&pdev->dev, ctrl); 1562 mutex_init(&ctrl->port_lock); 1563 init_completion(&ctrl->broadcast); 1564 init_completion(&ctrl->enumeration); 1565 1566 ctrl->bus.ops = &qcom_swrm_ops; 1567 ctrl->bus.port_ops = &qcom_swrm_port_ops; 1568 ctrl->bus.compute_params = &qcom_swrm_compute_params; 1569 ctrl->bus.clk_stop_timeout = 300; 1570 1571 ret = qcom_swrm_get_port_config(ctrl); 1572 if (ret) 1573 goto err_clk; 1574 1575 params = &ctrl->bus.params; 1576 params->max_dr_freq = DEFAULT_CLK_FREQ; 1577 params->curr_dr_freq = DEFAULT_CLK_FREQ; 1578 params->col = data->default_cols; 1579 params->row = data->default_rows; 1580 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val); 1581 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK; 1582 params->next_bank = !params->curr_bank; 1583 1584 prop = &ctrl->bus.prop; 1585 prop->max_clk_freq = DEFAULT_CLK_FREQ; 1586 prop->num_clk_gears = 0; 1587 prop->num_clk_freq = MAX_FREQ_NUM; 1588 prop->clk_freq = &qcom_swrm_freq_tbl[0]; 1589 prop->default_col = data->default_cols; 1590 prop->default_row = data->default_rows; 1591 1592 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); 1593 1594 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, 1595 qcom_swrm_irq_handler, 1596 IRQF_TRIGGER_RISING | 1597 IRQF_ONESHOT, 1598 "soundwire", ctrl); 1599 if (ret) { 1600 dev_err(dev, "Failed to request soundwire irq\n"); 1601 goto err_clk; 1602 } 1603 1604 ctrl->wake_irq = of_irq_get(dev->of_node, 1); 1605 if (ctrl->wake_irq > 0) { 1606 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL, 1607 qcom_swrm_wake_irq_handler, 1608 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1609 "swr_wake_irq", ctrl); 1610 if (ret) { 1611 dev_err(dev, "Failed to request soundwire wake irq\n"); 1612 goto err_init; 1613 } 1614 } 1615 1616 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); 1617 if (ret) { 1618 dev_err(dev, "Failed to register Soundwire controller (%d)\n", 1619 ret); 1620 goto err_clk; 1621 } 1622 1623 qcom_swrm_init(ctrl); 1624 wait_for_completion_timeout(&ctrl->enumeration, 1625 msecs_to_jiffies(TIMEOUT_MS)); 1626 ret = qcom_swrm_register_dais(ctrl); 1627 if (ret) 1628 goto err_master_add; 1629 1630 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", 1631 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, 1632 ctrl->version & 0xffff); 1633 1634 pm_runtime_set_autosuspend_delay(dev, 3000); 1635 pm_runtime_use_autosuspend(dev); 1636 pm_runtime_mark_last_busy(dev); 1637 pm_runtime_set_active(dev); 1638 pm_runtime_enable(dev); 1639 1640 #ifdef CONFIG_DEBUG_FS 1641 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs); 1642 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl, 1643 &swrm_reg_fops); 1644 #endif 1645 1646 return 0; 1647 1648 err_master_add: 1649 sdw_bus_master_delete(&ctrl->bus); 1650 err_clk: 1651 clk_disable_unprepare(ctrl->hclk); 1652 err_init: 1653 return ret; 1654 } 1655 1656 static int qcom_swrm_remove(struct platform_device *pdev) 1657 { 1658 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); 1659 1660 sdw_bus_master_delete(&ctrl->bus); 1661 clk_disable_unprepare(ctrl->hclk); 1662 1663 return 0; 1664 } 1665 1666 static int __maybe_unused swrm_runtime_resume(struct device *dev) 1667 { 1668 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1669 int ret; 1670 1671 if (ctrl->wake_irq > 0) { 1672 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1673 disable_irq_nosync(ctrl->wake_irq); 1674 } 1675 1676 clk_prepare_enable(ctrl->hclk); 1677 1678 if (ctrl->clock_stop_not_supported) { 1679 reinit_completion(&ctrl->enumeration); 1680 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01); 1681 usleep_range(100, 105); 1682 1683 qcom_swrm_init(ctrl); 1684 1685 usleep_range(100, 105); 1686 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1687 dev_err(ctrl->dev, "link failed to connect\n"); 1688 1689 /* wait for hw enumeration to complete */ 1690 wait_for_completion_timeout(&ctrl->enumeration, 1691 msecs_to_jiffies(TIMEOUT_MS)); 1692 qcom_swrm_get_device_status(ctrl); 1693 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 1694 } else { 1695 reset_control_reset(ctrl->audio_cgcr); 1696 1697 if (ctrl->version == SWRM_VERSION_1_7_0) { 1698 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 1699 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, 1700 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); 1701 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { 1702 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 1703 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, 1704 SWRM_V2_0_CLK_CTRL_CLK_START); 1705 } else { 1706 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 1707 } 1708 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 1709 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); 1710 1711 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1712 if (ctrl->version < SWRM_VERSION_2_0_0) 1713 ctrl->reg_write(ctrl, 1714 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 1715 ctrl->intr_mask); 1716 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 1717 ctrl->intr_mask); 1718 1719 usleep_range(100, 105); 1720 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1721 dev_err(ctrl->dev, "link failed to connect\n"); 1722 1723 ret = sdw_bus_exit_clk_stop(&ctrl->bus); 1724 if (ret < 0) 1725 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret); 1726 } 1727 1728 return 0; 1729 } 1730 1731 static int __maybe_unused swrm_runtime_suspend(struct device *dev) 1732 { 1733 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1734 int ret; 1735 1736 swrm_wait_for_wr_fifo_done(ctrl); 1737 if (!ctrl->clock_stop_not_supported) { 1738 /* Mask bus clash interrupt */ 1739 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1740 if (ctrl->version < SWRM_VERSION_2_0_0) 1741 ctrl->reg_write(ctrl, 1742 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 1743 ctrl->intr_mask); 1744 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 1745 ctrl->intr_mask); 1746 /* Prepare slaves for clock stop */ 1747 ret = sdw_bus_prep_clk_stop(&ctrl->bus); 1748 if (ret < 0 && ret != -ENODATA) { 1749 dev_err(dev, "prepare clock stop failed %d", ret); 1750 return ret; 1751 } 1752 1753 ret = sdw_bus_clk_stop(&ctrl->bus); 1754 if (ret < 0 && ret != -ENODATA) { 1755 dev_err(dev, "bus clock stop failed %d", ret); 1756 return ret; 1757 } 1758 } 1759 1760 clk_disable_unprepare(ctrl->hclk); 1761 1762 usleep_range(300, 305); 1763 1764 if (ctrl->wake_irq > 0) { 1765 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1766 enable_irq(ctrl->wake_irq); 1767 } 1768 1769 return 0; 1770 } 1771 1772 static const struct dev_pm_ops swrm_dev_pm_ops = { 1773 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL) 1774 }; 1775 1776 static const struct of_device_id qcom_swrm_of_match[] = { 1777 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, 1778 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, 1779 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, 1780 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data }, 1781 { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data }, 1782 {/* sentinel */}, 1783 }; 1784 1785 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); 1786 1787 static struct platform_driver qcom_swrm_driver = { 1788 .probe = &qcom_swrm_probe, 1789 .remove = &qcom_swrm_remove, 1790 .driver = { 1791 .name = "qcom-soundwire", 1792 .of_match_table = qcom_swrm_of_match, 1793 .pm = &swrm_dev_pm_ops, 1794 } 1795 }; 1796 module_platform_driver(qcom_swrm_driver); 1797 1798 MODULE_DESCRIPTION("Qualcomm soundwire driver"); 1799 MODULE_LICENSE("GPL v2"); 1800