1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/clk.h> 5 #include <linux/completion.h> 6 #include <linux/interrupt.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/debugfs.h> 11 #include <linux/of.h> 12 #include <linux/of_irq.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 #include <linux/slab.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/slimbus.h> 19 #include <linux/soundwire/sdw.h> 20 #include <linux/soundwire/sdw_registers.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include "bus.h" 24 25 #define SWRM_COMP_SW_RESET 0x008 26 #define SWRM_COMP_STATUS 0x014 27 #define SWRM_LINK_MANAGER_EE 0x018 28 #define SWRM_EE_CPU 1 29 #define SWRM_FRM_GEN_ENABLED BIT(0) 30 #define SWRM_VERSION_1_3_0 0x01030000 31 #define SWRM_VERSION_1_5_1 0x01050001 32 #define SWRM_VERSION_1_7_0 0x01070000 33 #define SWRM_VERSION_2_0_0 0x02000000 34 #define SWRM_COMP_HW_VERSION 0x00 35 #define SWRM_COMP_CFG_ADDR 0x04 36 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) 37 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0) 38 #define SWRM_COMP_PARAMS 0x100 39 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10) 40 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15) 41 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) 42 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) 43 #define SWRM_COMP_MASTER_ID 0x104 44 #define SWRM_V1_3_INTERRUPT_STATUS 0x200 45 #define SWRM_V2_0_INTERRUPT_STATUS 0x5000 46 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) 47 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) 48 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) 49 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2) 50 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3) 51 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4) 52 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5) 53 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6) 54 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7) 55 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) 56 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) 57 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) 58 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11) 59 #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12) 60 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) 61 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) 62 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) 63 #define SWRM_INTERRUPT_MAX 17 64 #define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204 65 #define SWRM_V1_3_INTERRUPT_CLEAR 0x208 66 #define SWRM_V2_0_INTERRUPT_CLEAR 0x5008 67 #define SWRM_V1_3_INTERRUPT_CPU_EN 0x210 68 #define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004 69 #define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300 70 #define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020 71 #define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304 72 #define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024 73 #define SWRM_CMD_FIFO_CMD 0x308 74 #define SWRM_CMD_FIFO_FLUSH 0x1 75 #define SWRM_V1_3_CMD_FIFO_STATUS 0x30C 76 #define SWRM_V2_0_CMD_FIFO_STATUS 0x5050 77 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) 78 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) 79 #define SWRM_CMD_FIFO_CFG_ADDR 0x314 80 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) 81 #define SWRM_RD_WR_CMD_RETRIES 0x7 82 #define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318 83 #define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040 84 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) 85 #define SWRM_ENUMERATOR_CFG_ADDR 0x500 86 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) 87 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m)) 88 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m)) 89 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0) 90 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3) 91 #define SWRM_MCP_BUS_CTRL 0x1044 92 #define SWRM_MCP_BUS_CLK_START BIT(1) 93 #define SWRM_MCP_CFG_ADDR 0x1048 94 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17) 95 #define SWRM_DEF_CMD_NO_PINGS 0x1f 96 #define SWRM_MCP_STATUS 0x104C 97 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0) 98 #define SWRM_MCP_SLV_STATUS 0x1090 99 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0) 100 #define SWRM_MCP_SLV_STATUS_SZ 2 101 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m) 102 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m) 103 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1)) 104 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) 105 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) 106 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) 107 #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m) 108 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) 109 #define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740 110 #define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac 111 112 #define SWRM_V2_0_CLK_CTRL 0x5060 113 #define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0) 114 #define SWRM_V2_0_LINK_STATUS 0x5064 115 116 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 117 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 118 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 119 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 120 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 121 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d 122 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91 123 124 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ 125 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) 126 127 #define MAX_FREQ_NUM 1 128 #define TIMEOUT_MS 100 129 #define QCOM_SWRM_MAX_RD_LEN 0x1 130 #define QCOM_SDW_MAX_PORTS 14 131 #define DEFAULT_CLK_FREQ 9600000 132 #define SWRM_MAX_DAIS 0xF 133 #define SWR_INVALID_PARAM 0xFF 134 #define SWR_HSTOP_MAX_VAL 0xF 135 #define SWR_HSTART_MIN_VAL 0x0 136 #define SWR_BROADCAST_CMD_ID 0x0F 137 #define SWR_MAX_CMD_ID 14 138 #define MAX_FIFO_RD_RETRY 3 139 #define SWR_OVERFLOW_RETRY_COUNT 30 140 #define SWRM_LINK_STATUS_RETRY_CNT 100 141 142 enum { 143 MASTER_ID_WSA = 1, 144 MASTER_ID_RX, 145 MASTER_ID_TX 146 }; 147 148 struct qcom_swrm_port_config { 149 u16 si; 150 u8 off1; 151 u8 off2; 152 u8 bp_mode; 153 u8 hstart; 154 u8 hstop; 155 u8 word_length; 156 u8 blk_group_count; 157 u8 lane_control; 158 }; 159 160 /* 161 * Internal IDs for different register layouts. Only few registers differ per 162 * each variant, so the list of IDs below does not include all of registers. 163 */ 164 enum { 165 SWRM_REG_FRAME_GEN_ENABLED, 166 SWRM_REG_INTERRUPT_STATUS, 167 SWRM_REG_INTERRUPT_MASK_ADDR, 168 SWRM_REG_INTERRUPT_CLEAR, 169 SWRM_REG_INTERRUPT_CPU_EN, 170 SWRM_REG_CMD_FIFO_WR_CMD, 171 SWRM_REG_CMD_FIFO_RD_CMD, 172 SWRM_REG_CMD_FIFO_STATUS, 173 SWRM_REG_CMD_FIFO_RD_FIFO_ADDR, 174 }; 175 176 struct qcom_swrm_ctrl { 177 struct sdw_bus bus; 178 struct device *dev; 179 struct regmap *regmap; 180 u32 max_reg; 181 const unsigned int *reg_layout; 182 void __iomem *mmio; 183 struct reset_control *audio_cgcr; 184 #ifdef CONFIG_DEBUG_FS 185 struct dentry *debugfs; 186 #endif 187 struct completion broadcast; 188 struct completion enumeration; 189 /* Port alloc/free lock */ 190 struct mutex port_lock; 191 struct clk *hclk; 192 int irq; 193 unsigned int version; 194 int wake_irq; 195 int num_din_ports; 196 int num_dout_ports; 197 int cols_index; 198 int rows_index; 199 unsigned long dout_port_mask; 200 unsigned long din_port_mask; 201 u32 intr_mask; 202 u8 rcmd_id; 203 u8 wcmd_id; 204 /* Port numbers are 1 - 14 */ 205 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS + 1]; 206 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; 207 enum sdw_slave_status status[SDW_MAX_DEVICES + 1]; 208 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); 209 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); 210 u32 slave_status; 211 u32 wr_fifo_depth; 212 u32 rd_fifo_depth; 213 bool clock_stop_not_supported; 214 }; 215 216 struct qcom_swrm_data { 217 u32 default_cols; 218 u32 default_rows; 219 bool sw_clk_gate_required; 220 u32 max_reg; 221 const unsigned int *reg_layout; 222 }; 223 224 static const unsigned int swrm_v1_3_reg_layout[] = { 225 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS, 226 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS, 227 [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR, 228 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR, 229 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN, 230 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD, 231 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD, 232 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS, 233 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR, 234 }; 235 236 static const struct qcom_swrm_data swrm_v1_3_data = { 237 .default_rows = 48, 238 .default_cols = 16, 239 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 240 .reg_layout = swrm_v1_3_reg_layout, 241 }; 242 243 static const struct qcom_swrm_data swrm_v1_5_data = { 244 .default_rows = 50, 245 .default_cols = 16, 246 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 247 .reg_layout = swrm_v1_3_reg_layout, 248 }; 249 250 static const struct qcom_swrm_data swrm_v1_6_data = { 251 .default_rows = 50, 252 .default_cols = 16, 253 .sw_clk_gate_required = true, 254 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR, 255 .reg_layout = swrm_v1_3_reg_layout, 256 }; 257 258 static const unsigned int swrm_v2_0_reg_layout[] = { 259 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS, 260 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS, 261 [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */ 262 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR, 263 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN, 264 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD, 265 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD, 266 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS, 267 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR, 268 }; 269 270 static const struct qcom_swrm_data swrm_v2_0_data = { 271 .default_rows = 50, 272 .default_cols = 16, 273 .sw_clk_gate_required = true, 274 .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR, 275 .reg_layout = swrm_v2_0_reg_layout, 276 }; 277 278 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) 279 280 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 281 u32 *val) 282 { 283 struct regmap *wcd_regmap = ctrl->regmap; 284 int ret; 285 286 /* pg register + offset */ 287 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0, 288 (u8 *)®, 4); 289 if (ret < 0) 290 return SDW_CMD_FAIL; 291 292 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0, 293 val, 4); 294 if (ret < 0) 295 return SDW_CMD_FAIL; 296 297 return SDW_CMD_OK; 298 } 299 300 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, 301 int reg, int val) 302 { 303 struct regmap *wcd_regmap = ctrl->regmap; 304 int ret; 305 /* pg register + offset */ 306 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0, 307 (u8 *)&val, 4); 308 if (ret) 309 return SDW_CMD_FAIL; 310 311 /* write address register */ 312 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0, 313 (u8 *)®, 4); 314 if (ret) 315 return SDW_CMD_FAIL; 316 317 return SDW_CMD_OK; 318 } 319 320 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 321 u32 *val) 322 { 323 *val = readl(ctrl->mmio + reg); 324 return SDW_CMD_OK; 325 } 326 327 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, 328 int val) 329 { 330 writel(val, ctrl->mmio + reg); 331 return SDW_CMD_OK; 332 } 333 334 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, 335 u8 dev_addr, u16 reg_addr) 336 { 337 u32 val; 338 u8 id = *cmd_id; 339 340 if (id != SWR_BROADCAST_CMD_ID) { 341 if (id < SWR_MAX_CMD_ID) 342 id += 1; 343 else 344 id = 0; 345 *cmd_id = id; 346 } 347 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); 348 349 return val; 350 } 351 352 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl) 353 { 354 u32 fifo_outstanding_data, value; 355 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 356 357 do { 358 /* Check for fifo underflow during read */ 359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 360 &value); 361 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); 362 363 /* Check if read data is available in read fifo */ 364 if (fifo_outstanding_data > 0) 365 return 0; 366 367 usleep_range(500, 510); 368 } while (fifo_retry_count--); 369 370 if (fifo_outstanding_data == 0) { 371 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); 372 return -EIO; 373 } 374 375 return 0; 376 } 377 378 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl) 379 { 380 u32 fifo_outstanding_cmds, value; 381 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 382 383 do { 384 /* Check for fifo overflow during write */ 385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 386 &value); 387 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 388 389 /* Check for space in write fifo before writing */ 390 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) 391 return 0; 392 393 usleep_range(500, 510); 394 } while (fifo_retry_count--); 395 396 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { 397 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); 398 return -EIO; 399 } 400 401 return 0; 402 } 403 404 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl) 405 { 406 u32 fifo_outstanding_cmds, value; 407 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 408 409 /* Check for fifo overflow during write */ 410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); 411 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 412 413 if (fifo_outstanding_cmds) { 414 while (fifo_retry_count) { 415 usleep_range(500, 510); 416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); 417 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 418 fifo_retry_count--; 419 if (fifo_outstanding_cmds == 0) 420 return true; 421 } 422 } else { 423 return true; 424 } 425 426 427 return false; 428 } 429 430 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data, 431 u8 dev_addr, u16 reg_addr) 432 { 433 434 u32 val; 435 int ret = 0; 436 u8 cmd_id = 0x0; 437 438 if (dev_addr == SDW_BROADCAST_DEV_NUM) { 439 cmd_id = SWR_BROADCAST_CMD_ID; 440 val = swrm_get_packed_reg_val(&cmd_id, cmd_data, 441 dev_addr, reg_addr); 442 } else { 443 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, 444 dev_addr, reg_addr); 445 } 446 447 if (swrm_wait_for_wr_fifo_avail(ctrl)) 448 return SDW_CMD_FAIL_OTHER; 449 450 if (cmd_id == SWR_BROADCAST_CMD_ID) 451 reinit_completion(&ctrl->broadcast); 452 453 /* Its assumed that write is okay as we do not get any status back */ 454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); 455 456 if (ctrl->version <= SWRM_VERSION_1_3_0) 457 usleep_range(150, 155); 458 459 if (cmd_id == SWR_BROADCAST_CMD_ID) { 460 swrm_wait_for_wr_fifo_done(ctrl); 461 /* 462 * sleep for 10ms for MSM soundwire variant to allow broadcast 463 * command to complete. 464 */ 465 ret = wait_for_completion_timeout(&ctrl->broadcast, 466 msecs_to_jiffies(TIMEOUT_MS)); 467 if (!ret) 468 ret = SDW_CMD_IGNORED; 469 else 470 ret = SDW_CMD_OK; 471 472 } else { 473 ret = SDW_CMD_OK; 474 } 475 return ret; 476 } 477 478 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl, 479 u8 dev_addr, u16 reg_addr, 480 u32 len, u8 *rval) 481 { 482 u32 cmd_data, cmd_id, val, retry_attempt = 0; 483 484 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); 485 486 /* 487 * Check for outstanding cmd wrt. write fifo depth to avoid 488 * overflow as read will also increase write fifo cnt. 489 */ 490 swrm_wait_for_wr_fifo_avail(ctrl); 491 492 /* wait for FIFO RD to complete to avoid overflow */ 493 usleep_range(100, 105); 494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); 495 /* wait for FIFO RD CMD complete to avoid overflow */ 496 usleep_range(250, 255); 497 498 if (swrm_wait_for_rd_fifo_avail(ctrl)) 499 return SDW_CMD_FAIL_OTHER; 500 501 do { 502 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], 503 &cmd_data); 504 rval[0] = cmd_data & 0xFF; 505 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); 506 507 if (cmd_id != ctrl->rcmd_id) { 508 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { 509 /* wait 500 us before retry on fifo read failure */ 510 usleep_range(500, 505); 511 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 512 SWRM_CMD_FIFO_FLUSH); 513 ctrl->reg_write(ctrl, 514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], 515 val); 516 } 517 retry_attempt++; 518 } else { 519 return SDW_CMD_OK; 520 } 521 522 } while (retry_attempt < MAX_FIFO_RD_RETRY); 523 524 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ 525 dev_num: 0x%x, cmd_data: 0x%x\n", 526 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); 527 528 return SDW_CMD_IGNORED; 529 } 530 531 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) 532 { 533 u32 val, status; 534 int dev_num; 535 536 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 537 538 for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) { 539 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); 540 541 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { 542 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; 543 return dev_num; 544 } 545 } 546 547 return -EINVAL; 548 } 549 550 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) 551 { 552 u32 val; 553 int i; 554 555 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 556 ctrl->slave_status = val; 557 558 for (i = 1; i <= SDW_MAX_DEVICES; i++) { 559 u32 s; 560 561 s = (val >> (i * 2)); 562 s &= SWRM_MCP_SLV_STATUS_MASK; 563 ctrl->status[i] = s; 564 } 565 } 566 567 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, 568 struct sdw_slave *slave, int devnum) 569 { 570 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 571 u32 status; 572 573 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); 574 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ)); 575 status &= SWRM_MCP_SLV_STATUS_MASK; 576 577 if (status == SDW_SLAVE_ATTACHED) { 578 if (slave) 579 slave->dev_num = devnum; 580 mutex_lock(&bus->bus_lock); 581 set_bit(devnum, bus->assigned); 582 mutex_unlock(&bus->bus_lock); 583 } 584 } 585 586 static int qcom_swrm_enumerate(struct sdw_bus *bus) 587 { 588 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 589 struct sdw_slave *slave, *_s; 590 struct sdw_slave_id id; 591 u32 val1, val2; 592 bool found; 593 u64 addr; 594 int i; 595 char *buf1 = (char *)&val1, *buf2 = (char *)&val2; 596 597 for (i = 1; i <= SDW_MAX_DEVICES; i++) { 598 /* do not continue if the status is Not Present */ 599 if (!ctrl->status[i]) 600 continue; 601 602 /*SCP_Devid5 - Devid 4*/ 603 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); 604 605 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ 606 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); 607 608 if (!val1 && !val2) 609 break; 610 611 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | 612 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) | 613 ((u64)buf1[0] << 40); 614 615 sdw_extract_slave_id(bus, addr, &id); 616 found = false; 617 ctrl->clock_stop_not_supported = false; 618 /* Now compare with entries */ 619 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { 620 if (sdw_compare_devid(slave, id) == 0) { 621 qcom_swrm_set_slave_dev_num(bus, slave, i); 622 if (slave->prop.clk_stop_mode1) 623 ctrl->clock_stop_not_supported = true; 624 625 found = true; 626 break; 627 } 628 } 629 630 if (!found) { 631 qcom_swrm_set_slave_dev_num(bus, NULL, i); 632 sdw_slave_add(bus, &id, NULL); 633 } 634 } 635 636 complete(&ctrl->enumeration); 637 return 0; 638 } 639 640 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) 641 { 642 struct qcom_swrm_ctrl *ctrl = dev_id; 643 int ret; 644 645 ret = pm_runtime_get_sync(ctrl->dev); 646 if (ret < 0 && ret != -EACCES) { 647 dev_err_ratelimited(ctrl->dev, 648 "pm_runtime_get_sync failed in %s, ret %d\n", 649 __func__, ret); 650 pm_runtime_put_noidle(ctrl->dev); 651 return ret; 652 } 653 654 if (ctrl->wake_irq > 0) { 655 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 656 disable_irq_nosync(ctrl->wake_irq); 657 } 658 659 pm_runtime_mark_last_busy(ctrl->dev); 660 pm_runtime_put_autosuspend(ctrl->dev); 661 662 return IRQ_HANDLED; 663 } 664 665 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) 666 { 667 struct qcom_swrm_ctrl *ctrl = dev_id; 668 u32 value, intr_sts, intr_sts_masked, slave_status; 669 u32 i; 670 int devnum; 671 int ret = IRQ_HANDLED; 672 clk_prepare_enable(ctrl->hclk); 673 674 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], 675 &intr_sts); 676 intr_sts_masked = intr_sts & ctrl->intr_mask; 677 678 do { 679 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { 680 value = intr_sts_masked & BIT(i); 681 if (!value) 682 continue; 683 684 switch (value) { 685 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: 686 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl); 687 if (devnum < 0) { 688 dev_err_ratelimited(ctrl->dev, 689 "no slave alert found.spurious interrupt\n"); 690 } else { 691 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 692 } 693 694 break; 695 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: 696 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: 697 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); 698 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); 699 if (ctrl->slave_status == slave_status) { 700 dev_dbg(ctrl->dev, "Slave status not changed %x\n", 701 slave_status); 702 } else { 703 qcom_swrm_get_device_status(ctrl); 704 qcom_swrm_enumerate(&ctrl->bus); 705 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 706 } 707 break; 708 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: 709 dev_err_ratelimited(ctrl->dev, 710 "%s: SWR bus clsh detected\n", 711 __func__); 712 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 713 ctrl->reg_write(ctrl, 714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 715 ctrl->intr_mask); 716 break; 717 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: 718 ctrl->reg_read(ctrl, 719 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 720 &value); 721 dev_err_ratelimited(ctrl->dev, 722 "%s: SWR read FIFO overflow fifo status 0x%x\n", 723 __func__, value); 724 break; 725 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: 726 ctrl->reg_read(ctrl, 727 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 728 &value); 729 dev_err_ratelimited(ctrl->dev, 730 "%s: SWR read FIFO underflow fifo status 0x%x\n", 731 __func__, value); 732 break; 733 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: 734 ctrl->reg_read(ctrl, 735 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 736 &value); 737 dev_err(ctrl->dev, 738 "%s: SWR write FIFO overflow fifo status %x\n", 739 __func__, value); 740 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); 741 break; 742 case SWRM_INTERRUPT_STATUS_CMD_ERROR: 743 ctrl->reg_read(ctrl, 744 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], 745 &value); 746 dev_err_ratelimited(ctrl->dev, 747 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", 748 __func__, value); 749 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); 750 break; 751 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: 752 dev_err_ratelimited(ctrl->dev, 753 "%s: SWR Port collision detected\n", 754 __func__); 755 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; 756 ctrl->reg_write(ctrl, 757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 758 ctrl->intr_mask); 759 break; 760 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: 761 dev_err_ratelimited(ctrl->dev, 762 "%s: SWR read enable valid mismatch\n", 763 __func__); 764 ctrl->intr_mask &= 765 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; 766 ctrl->reg_write(ctrl, 767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 768 ctrl->intr_mask); 769 break; 770 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: 771 complete(&ctrl->broadcast); 772 break; 773 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: 774 break; 775 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: 776 break; 777 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: 778 break; 779 default: 780 dev_err_ratelimited(ctrl->dev, 781 "%s: SWR unknown interrupt value: %d\n", 782 __func__, value); 783 ret = IRQ_NONE; 784 break; 785 } 786 } 787 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 788 intr_sts); 789 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], 790 &intr_sts); 791 intr_sts_masked = intr_sts & ctrl->intr_mask; 792 } while (intr_sts_masked); 793 794 clk_disable_unprepare(ctrl->hclk); 795 return ret; 796 } 797 798 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl) 799 { 800 int retry = SWRM_LINK_STATUS_RETRY_CNT; 801 int comp_sts; 802 803 do { 804 ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts); 805 806 if (comp_sts & SWRM_FRM_GEN_ENABLED) 807 return true; 808 809 usleep_range(500, 510); 810 } while (retry--); 811 812 dev_err(ctrl->dev, "%s: link status not %s\n", __func__, 813 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); 814 815 return false; 816 } 817 818 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) 819 { 820 u32 val; 821 822 /* Clear Rows and Cols */ 823 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); 824 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); 825 826 reset_control_reset(ctrl->audio_cgcr); 827 828 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); 829 830 /* Enable Auto enumeration */ 831 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); 832 833 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; 834 /* Mask soundwire interrupts */ 835 if (ctrl->version < SWRM_VERSION_2_0_0) 836 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 837 SWRM_INTERRUPT_STATUS_RMSK); 838 839 /* Configure No pings */ 840 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); 841 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); 842 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); 843 844 if (ctrl->version == SWRM_VERSION_1_7_0) { 845 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 846 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, 847 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); 848 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { 849 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 850 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, 851 SWRM_V2_0_CLK_CTRL_CLK_START); 852 } else { 853 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 854 } 855 856 /* Configure number of retries of a read/write cmd */ 857 if (ctrl->version >= SWRM_VERSION_1_5_1) { 858 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 859 SWRM_RD_WR_CMD_RETRIES | 860 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE); 861 } else { 862 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 863 SWRM_RD_WR_CMD_RETRIES); 864 } 865 866 /* COMP Enable */ 867 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); 868 869 /* Set IRQ to PULSE */ 870 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 871 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK); 872 873 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 874 0xFFFFFFFF); 875 876 /* enable CPU IRQs */ 877 if (ctrl->mmio) { 878 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 879 SWRM_INTERRUPT_STATUS_RMSK); 880 } 881 882 /* Set IRQ to PULSE */ 883 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 884 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | 885 SWRM_COMP_CFG_ENABLE_MSK); 886 887 swrm_wait_for_frame_gen_enabled(ctrl); 888 ctrl->slave_status = 0; 889 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 890 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); 891 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); 892 893 return 0; 894 } 895 896 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, 897 struct sdw_msg *msg) 898 { 899 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 900 int ret, i, len; 901 902 if (msg->flags == SDW_MSG_FLAG_READ) { 903 for (i = 0; i < msg->len;) { 904 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) 905 len = msg->len - i; 906 else 907 len = QCOM_SWRM_MAX_RD_LEN; 908 909 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, 910 msg->addr + i, len, 911 &msg->buf[i]); 912 if (ret) 913 return ret; 914 915 i = i + len; 916 } 917 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { 918 for (i = 0; i < msg->len; i++) { 919 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], 920 msg->dev_num, 921 msg->addr + i); 922 if (ret) 923 return SDW_CMD_IGNORED; 924 } 925 } 926 927 return SDW_CMD_OK; 928 } 929 930 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) 931 { 932 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); 933 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 934 u32 val; 935 936 ctrl->reg_read(ctrl, reg, &val); 937 938 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); 939 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); 940 941 return ctrl->reg_write(ctrl, reg, val); 942 } 943 944 static int qcom_swrm_port_params(struct sdw_bus *bus, 945 struct sdw_port_params *p_params, 946 unsigned int bank) 947 { 948 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 949 950 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), 951 p_params->bps - 1); 952 953 } 954 955 static int qcom_swrm_transport_params(struct sdw_bus *bus, 956 struct sdw_transport_params *params, 957 enum sdw_reg_bank bank) 958 { 959 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 960 struct qcom_swrm_port_config *pcfg; 961 u32 value; 962 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); 963 int ret; 964 965 pcfg = &ctrl->pconfig[params->port_num]; 966 967 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; 968 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; 969 value |= pcfg->si & 0xff; 970 971 ret = ctrl->reg_write(ctrl, reg, value); 972 if (ret) 973 goto err; 974 975 if (pcfg->si > 0xff) { 976 value = (pcfg->si >> 8) & 0xff; 977 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); 978 ret = ctrl->reg_write(ctrl, reg, value); 979 if (ret) 980 goto err; 981 } 982 983 if (pcfg->lane_control != SWR_INVALID_PARAM) { 984 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); 985 value = pcfg->lane_control; 986 ret = ctrl->reg_write(ctrl, reg, value); 987 if (ret) 988 goto err; 989 } 990 991 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { 992 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); 993 value = pcfg->blk_group_count; 994 ret = ctrl->reg_write(ctrl, reg, value); 995 if (ret) 996 goto err; 997 } 998 999 if (pcfg->hstart != SWR_INVALID_PARAM 1000 && pcfg->hstop != SWR_INVALID_PARAM) { 1001 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 1002 value = (pcfg->hstop << 4) | pcfg->hstart; 1003 ret = ctrl->reg_write(ctrl, reg, value); 1004 } else { 1005 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 1006 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL; 1007 ret = ctrl->reg_write(ctrl, reg, value); 1008 } 1009 1010 if (ret) 1011 goto err; 1012 1013 if (pcfg->bp_mode != SWR_INVALID_PARAM) { 1014 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); 1015 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); 1016 } 1017 1018 err: 1019 return ret; 1020 } 1021 1022 static int qcom_swrm_port_enable(struct sdw_bus *bus, 1023 struct sdw_enable_ch *enable_ch, 1024 unsigned int bank) 1025 { 1026 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); 1027 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 1028 u32 val; 1029 1030 ctrl->reg_read(ctrl, reg, &val); 1031 1032 if (enable_ch->enable) 1033 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 1034 else 1035 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 1036 1037 return ctrl->reg_write(ctrl, reg, val); 1038 } 1039 1040 static const struct sdw_master_port_ops qcom_swrm_port_ops = { 1041 .dpn_set_port_params = qcom_swrm_port_params, 1042 .dpn_set_port_transport_params = qcom_swrm_transport_params, 1043 .dpn_port_enable_ch = qcom_swrm_port_enable, 1044 }; 1045 1046 static const struct sdw_master_ops qcom_swrm_ops = { 1047 .xfer_msg = qcom_swrm_xfer_msg, 1048 .pre_bank_switch = qcom_swrm_pre_bank_switch, 1049 }; 1050 1051 static int qcom_swrm_compute_params(struct sdw_bus *bus) 1052 { 1053 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 1054 struct sdw_master_runtime *m_rt; 1055 struct sdw_slave_runtime *s_rt; 1056 struct sdw_port_runtime *p_rt; 1057 struct qcom_swrm_port_config *pcfg; 1058 struct sdw_slave *slave; 1059 unsigned int m_port; 1060 int i = 1; 1061 1062 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 1063 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 1064 pcfg = &ctrl->pconfig[p_rt->num]; 1065 p_rt->transport_params.port_num = p_rt->num; 1066 if (pcfg->word_length != SWR_INVALID_PARAM) { 1067 sdw_fill_port_params(&p_rt->port_params, 1068 p_rt->num, pcfg->word_length + 1, 1069 SDW_PORT_FLOW_MODE_ISOCH, 1070 SDW_PORT_DATA_MODE_NORMAL); 1071 } 1072 1073 } 1074 1075 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 1076 slave = s_rt->slave; 1077 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 1078 m_port = slave->m_port_map[p_rt->num]; 1079 /* port config starts at offset 0 so -1 from actual port number */ 1080 if (m_port) 1081 pcfg = &ctrl->pconfig[m_port]; 1082 else 1083 pcfg = &ctrl->pconfig[i]; 1084 p_rt->transport_params.port_num = p_rt->num; 1085 p_rt->transport_params.sample_interval = 1086 pcfg->si + 1; 1087 p_rt->transport_params.offset1 = pcfg->off1; 1088 p_rt->transport_params.offset2 = pcfg->off2; 1089 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; 1090 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; 1091 1092 p_rt->transport_params.hstart = pcfg->hstart; 1093 p_rt->transport_params.hstop = pcfg->hstop; 1094 p_rt->transport_params.lane_ctrl = pcfg->lane_control; 1095 if (pcfg->word_length != SWR_INVALID_PARAM) { 1096 sdw_fill_port_params(&p_rt->port_params, 1097 p_rt->num, 1098 pcfg->word_length + 1, 1099 SDW_PORT_FLOW_MODE_ISOCH, 1100 SDW_PORT_DATA_MODE_NORMAL); 1101 } 1102 i++; 1103 } 1104 } 1105 } 1106 1107 return 0; 1108 } 1109 1110 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = { 1111 DEFAULT_CLK_FREQ, 1112 }; 1113 1114 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, 1115 struct sdw_stream_runtime *stream) 1116 { 1117 struct sdw_master_runtime *m_rt; 1118 struct sdw_port_runtime *p_rt; 1119 unsigned long *port_mask; 1120 1121 mutex_lock(&ctrl->port_lock); 1122 1123 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 1124 if (m_rt->direction == SDW_DATA_DIR_RX) 1125 port_mask = &ctrl->dout_port_mask; 1126 else 1127 port_mask = &ctrl->din_port_mask; 1128 1129 list_for_each_entry(p_rt, &m_rt->port_list, port_node) 1130 clear_bit(p_rt->num, port_mask); 1131 } 1132 1133 mutex_unlock(&ctrl->port_lock); 1134 } 1135 1136 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, 1137 struct sdw_stream_runtime *stream, 1138 struct snd_pcm_hw_params *params, 1139 int direction) 1140 { 1141 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS]; 1142 struct sdw_stream_config sconfig; 1143 struct sdw_master_runtime *m_rt; 1144 struct sdw_slave_runtime *s_rt; 1145 struct sdw_port_runtime *p_rt; 1146 struct sdw_slave *slave; 1147 unsigned long *port_mask; 1148 int i, maxport, pn, nports = 0, ret = 0; 1149 unsigned int m_port; 1150 1151 mutex_lock(&ctrl->port_lock); 1152 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 1153 if (m_rt->direction == SDW_DATA_DIR_RX) { 1154 maxport = ctrl->num_dout_ports; 1155 port_mask = &ctrl->dout_port_mask; 1156 } else { 1157 maxport = ctrl->num_din_ports; 1158 port_mask = &ctrl->din_port_mask; 1159 } 1160 1161 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 1162 slave = s_rt->slave; 1163 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 1164 m_port = slave->m_port_map[p_rt->num]; 1165 /* Port numbers start from 1 - 14*/ 1166 if (m_port) 1167 pn = m_port; 1168 else 1169 pn = find_first_zero_bit(port_mask, maxport); 1170 1171 if (pn > maxport) { 1172 dev_err(ctrl->dev, "All ports busy\n"); 1173 ret = -EBUSY; 1174 goto err; 1175 } 1176 set_bit(pn, port_mask); 1177 pconfig[nports].num = pn; 1178 pconfig[nports].ch_mask = p_rt->ch_mask; 1179 nports++; 1180 } 1181 } 1182 } 1183 1184 if (direction == SNDRV_PCM_STREAM_CAPTURE) 1185 sconfig.direction = SDW_DATA_DIR_TX; 1186 else 1187 sconfig.direction = SDW_DATA_DIR_RX; 1188 1189 /* hw parameters wil be ignored as we only support PDM */ 1190 sconfig.ch_count = 1; 1191 sconfig.frame_rate = params_rate(params); 1192 sconfig.type = stream->type; 1193 sconfig.bps = 1; 1194 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, 1195 nports, stream); 1196 err: 1197 if (ret) { 1198 for (i = 0; i < nports; i++) 1199 clear_bit(pconfig[i].num, port_mask); 1200 } 1201 1202 mutex_unlock(&ctrl->port_lock); 1203 1204 return ret; 1205 } 1206 1207 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, 1208 struct snd_pcm_hw_params *params, 1209 struct snd_soc_dai *dai) 1210 { 1211 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1212 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1213 int ret; 1214 1215 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, 1216 substream->stream); 1217 if (ret) 1218 qcom_swrm_stream_free_ports(ctrl, sruntime); 1219 1220 return ret; 1221 } 1222 1223 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, 1224 struct snd_soc_dai *dai) 1225 { 1226 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1227 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1228 1229 qcom_swrm_stream_free_ports(ctrl, sruntime); 1230 sdw_stream_remove_master(&ctrl->bus, sruntime); 1231 1232 return 0; 1233 } 1234 1235 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, 1236 void *stream, int direction) 1237 { 1238 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1239 1240 ctrl->sruntime[dai->id] = stream; 1241 1242 return 0; 1243 } 1244 1245 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) 1246 { 1247 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1248 1249 return ctrl->sruntime[dai->id]; 1250 } 1251 1252 static int qcom_swrm_startup(struct snd_pcm_substream *substream, 1253 struct snd_soc_dai *dai) 1254 { 1255 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1256 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1257 struct sdw_stream_runtime *sruntime; 1258 struct snd_soc_dai *codec_dai; 1259 int ret, i; 1260 1261 ret = pm_runtime_get_sync(ctrl->dev); 1262 if (ret < 0 && ret != -EACCES) { 1263 dev_err_ratelimited(ctrl->dev, 1264 "pm_runtime_get_sync failed in %s, ret %d\n", 1265 __func__, ret); 1266 pm_runtime_put_noidle(ctrl->dev); 1267 return ret; 1268 } 1269 1270 sruntime = sdw_alloc_stream(dai->name); 1271 if (!sruntime) { 1272 ret = -ENOMEM; 1273 goto err_alloc; 1274 } 1275 1276 ctrl->sruntime[dai->id] = sruntime; 1277 1278 for_each_rtd_codec_dais(rtd, i, codec_dai) { 1279 ret = snd_soc_dai_set_stream(codec_dai, sruntime, 1280 substream->stream); 1281 if (ret < 0 && ret != -ENOTSUPP) { 1282 dev_err(dai->dev, "Failed to set sdw stream on %s\n", 1283 codec_dai->name); 1284 goto err_set_stream; 1285 } 1286 } 1287 1288 return 0; 1289 1290 err_set_stream: 1291 sdw_release_stream(sruntime); 1292 err_alloc: 1293 pm_runtime_mark_last_busy(ctrl->dev); 1294 pm_runtime_put_autosuspend(ctrl->dev); 1295 1296 return ret; 1297 } 1298 1299 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, 1300 struct snd_soc_dai *dai) 1301 { 1302 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1303 1304 swrm_wait_for_wr_fifo_done(ctrl); 1305 sdw_release_stream(ctrl->sruntime[dai->id]); 1306 ctrl->sruntime[dai->id] = NULL; 1307 pm_runtime_mark_last_busy(ctrl->dev); 1308 pm_runtime_put_autosuspend(ctrl->dev); 1309 1310 } 1311 1312 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { 1313 .hw_params = qcom_swrm_hw_params, 1314 .hw_free = qcom_swrm_hw_free, 1315 .startup = qcom_swrm_startup, 1316 .shutdown = qcom_swrm_shutdown, 1317 .set_stream = qcom_swrm_set_sdw_stream, 1318 .get_stream = qcom_swrm_get_sdw_stream, 1319 }; 1320 1321 static const struct snd_soc_component_driver qcom_swrm_dai_component = { 1322 .name = "soundwire", 1323 }; 1324 1325 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) 1326 { 1327 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; 1328 struct snd_soc_dai_driver *dais; 1329 struct snd_soc_pcm_stream *stream; 1330 struct device *dev = ctrl->dev; 1331 int i; 1332 1333 /* PDM dais are only tested for now */ 1334 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 1335 if (!dais) 1336 return -ENOMEM; 1337 1338 for (i = 0; i < num_dais; i++) { 1339 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i); 1340 if (!dais[i].name) 1341 return -ENOMEM; 1342 1343 if (i < ctrl->num_dout_ports) 1344 stream = &dais[i].playback; 1345 else 1346 stream = &dais[i].capture; 1347 1348 stream->channels_min = 1; 1349 stream->channels_max = 1; 1350 stream->rates = SNDRV_PCM_RATE_48000; 1351 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 1352 1353 dais[i].ops = &qcom_swrm_pdm_dai_ops; 1354 dais[i].id = i; 1355 } 1356 1357 return devm_snd_soc_register_component(ctrl->dev, 1358 &qcom_swrm_dai_component, 1359 dais, num_dais); 1360 } 1361 1362 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) 1363 { 1364 struct device_node *np = ctrl->dev->of_node; 1365 u8 off1[QCOM_SDW_MAX_PORTS]; 1366 u8 off2[QCOM_SDW_MAX_PORTS]; 1367 u16 si[QCOM_SDW_MAX_PORTS]; 1368 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; 1369 u8 hstart[QCOM_SDW_MAX_PORTS]; 1370 u8 hstop[QCOM_SDW_MAX_PORTS]; 1371 u8 word_length[QCOM_SDW_MAX_PORTS]; 1372 u8 blk_group_count[QCOM_SDW_MAX_PORTS]; 1373 u8 lane_control[QCOM_SDW_MAX_PORTS]; 1374 int i, ret, nports, val; 1375 bool si_16 = false; 1376 1377 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 1378 1379 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); 1380 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); 1381 1382 ret = of_property_read_u32(np, "qcom,din-ports", &val); 1383 if (ret) 1384 return ret; 1385 1386 if (val > ctrl->num_din_ports) 1387 return -EINVAL; 1388 1389 ctrl->num_din_ports = val; 1390 1391 ret = of_property_read_u32(np, "qcom,dout-ports", &val); 1392 if (ret) 1393 return ret; 1394 1395 if (val > ctrl->num_dout_ports) 1396 return -EINVAL; 1397 1398 ctrl->num_dout_ports = val; 1399 1400 nports = ctrl->num_dout_ports + ctrl->num_din_ports; 1401 if (nports > QCOM_SDW_MAX_PORTS) 1402 return -EINVAL; 1403 1404 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ 1405 set_bit(0, &ctrl->dout_port_mask); 1406 set_bit(0, &ctrl->din_port_mask); 1407 1408 ret = of_property_read_u8_array(np, "qcom,ports-offset1", 1409 off1, nports); 1410 if (ret) 1411 return ret; 1412 1413 ret = of_property_read_u8_array(np, "qcom,ports-offset2", 1414 off2, nports); 1415 if (ret) 1416 return ret; 1417 1418 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", 1419 (u8 *)si, nports); 1420 if (ret) { 1421 ret = of_property_read_u16_array(np, "qcom,ports-sinterval", 1422 si, nports); 1423 if (ret) 1424 return ret; 1425 si_16 = true; 1426 } 1427 1428 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", 1429 bp_mode, nports); 1430 if (ret) { 1431 if (ctrl->version <= SWRM_VERSION_1_3_0) 1432 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1433 else 1434 return ret; 1435 } 1436 1437 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1438 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); 1439 1440 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1441 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); 1442 1443 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1444 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); 1445 1446 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1447 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); 1448 1449 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1450 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); 1451 1452 for (i = 0; i < nports; i++) { 1453 /* Valid port number range is from 1-14 */ 1454 if (si_16) 1455 ctrl->pconfig[i + 1].si = si[i]; 1456 else 1457 ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; 1458 ctrl->pconfig[i + 1].off1 = off1[i]; 1459 ctrl->pconfig[i + 1].off2 = off2[i]; 1460 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; 1461 ctrl->pconfig[i + 1].hstart = hstart[i]; 1462 ctrl->pconfig[i + 1].hstop = hstop[i]; 1463 ctrl->pconfig[i + 1].word_length = word_length[i]; 1464 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; 1465 ctrl->pconfig[i + 1].lane_control = lane_control[i]; 1466 } 1467 1468 return 0; 1469 } 1470 1471 #ifdef CONFIG_DEBUG_FS 1472 static int swrm_reg_show(struct seq_file *s_file, void *data) 1473 { 1474 struct qcom_swrm_ctrl *ctrl = s_file->private; 1475 int reg, reg_val, ret; 1476 1477 ret = pm_runtime_get_sync(ctrl->dev); 1478 if (ret < 0 && ret != -EACCES) { 1479 dev_err_ratelimited(ctrl->dev, 1480 "pm_runtime_get_sync failed in %s, ret %d\n", 1481 __func__, ret); 1482 pm_runtime_put_noidle(ctrl->dev); 1483 return ret; 1484 } 1485 1486 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { 1487 ctrl->reg_read(ctrl, reg, ®_val); 1488 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); 1489 } 1490 pm_runtime_mark_last_busy(ctrl->dev); 1491 pm_runtime_put_autosuspend(ctrl->dev); 1492 1493 1494 return 0; 1495 } 1496 DEFINE_SHOW_ATTRIBUTE(swrm_reg); 1497 #endif 1498 1499 static int qcom_swrm_probe(struct platform_device *pdev) 1500 { 1501 struct device *dev = &pdev->dev; 1502 struct sdw_master_prop *prop; 1503 struct sdw_bus_params *params; 1504 struct qcom_swrm_ctrl *ctrl; 1505 const struct qcom_swrm_data *data; 1506 int ret; 1507 u32 val; 1508 1509 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1510 if (!ctrl) 1511 return -ENOMEM; 1512 1513 data = of_device_get_match_data(dev); 1514 ctrl->max_reg = data->max_reg; 1515 ctrl->reg_layout = data->reg_layout; 1516 ctrl->rows_index = sdw_find_row_index(data->default_rows); 1517 ctrl->cols_index = sdw_find_col_index(data->default_cols); 1518 #if IS_REACHABLE(CONFIG_SLIMBUS) 1519 if (dev->parent->bus == &slimbus_bus) { 1520 #else 1521 if (false) { 1522 #endif 1523 ctrl->reg_read = qcom_swrm_ahb_reg_read; 1524 ctrl->reg_write = qcom_swrm_ahb_reg_write; 1525 ctrl->regmap = dev_get_regmap(dev->parent, NULL); 1526 if (!ctrl->regmap) 1527 return -EINVAL; 1528 } else { 1529 ctrl->reg_read = qcom_swrm_cpu_reg_read; 1530 ctrl->reg_write = qcom_swrm_cpu_reg_write; 1531 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0); 1532 if (IS_ERR(ctrl->mmio)) 1533 return PTR_ERR(ctrl->mmio); 1534 } 1535 1536 if (data->sw_clk_gate_required) { 1537 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr"); 1538 if (IS_ERR(ctrl->audio_cgcr)) { 1539 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n"); 1540 ret = PTR_ERR(ctrl->audio_cgcr); 1541 goto err_init; 1542 } 1543 } 1544 1545 ctrl->irq = of_irq_get(dev->of_node, 0); 1546 if (ctrl->irq < 0) { 1547 ret = ctrl->irq; 1548 goto err_init; 1549 } 1550 1551 ctrl->hclk = devm_clk_get(dev, "iface"); 1552 if (IS_ERR(ctrl->hclk)) { 1553 ret = PTR_ERR(ctrl->hclk); 1554 goto err_init; 1555 } 1556 1557 clk_prepare_enable(ctrl->hclk); 1558 1559 ctrl->dev = dev; 1560 dev_set_drvdata(&pdev->dev, ctrl); 1561 mutex_init(&ctrl->port_lock); 1562 init_completion(&ctrl->broadcast); 1563 init_completion(&ctrl->enumeration); 1564 1565 ctrl->bus.ops = &qcom_swrm_ops; 1566 ctrl->bus.port_ops = &qcom_swrm_port_ops; 1567 ctrl->bus.compute_params = &qcom_swrm_compute_params; 1568 ctrl->bus.clk_stop_timeout = 300; 1569 1570 ret = qcom_swrm_get_port_config(ctrl); 1571 if (ret) 1572 goto err_clk; 1573 1574 params = &ctrl->bus.params; 1575 params->max_dr_freq = DEFAULT_CLK_FREQ; 1576 params->curr_dr_freq = DEFAULT_CLK_FREQ; 1577 params->col = data->default_cols; 1578 params->row = data->default_rows; 1579 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val); 1580 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK; 1581 params->next_bank = !params->curr_bank; 1582 1583 prop = &ctrl->bus.prop; 1584 prop->max_clk_freq = DEFAULT_CLK_FREQ; 1585 prop->num_clk_gears = 0; 1586 prop->num_clk_freq = MAX_FREQ_NUM; 1587 prop->clk_freq = &qcom_swrm_freq_tbl[0]; 1588 prop->default_col = data->default_cols; 1589 prop->default_row = data->default_rows; 1590 1591 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); 1592 1593 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, 1594 qcom_swrm_irq_handler, 1595 IRQF_TRIGGER_RISING | 1596 IRQF_ONESHOT, 1597 "soundwire", ctrl); 1598 if (ret) { 1599 dev_err(dev, "Failed to request soundwire irq\n"); 1600 goto err_clk; 1601 } 1602 1603 ctrl->wake_irq = of_irq_get(dev->of_node, 1); 1604 if (ctrl->wake_irq > 0) { 1605 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL, 1606 qcom_swrm_wake_irq_handler, 1607 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1608 "swr_wake_irq", ctrl); 1609 if (ret) { 1610 dev_err(dev, "Failed to request soundwire wake irq\n"); 1611 goto err_init; 1612 } 1613 } 1614 1615 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); 1616 if (ret) { 1617 dev_err(dev, "Failed to register Soundwire controller (%d)\n", 1618 ret); 1619 goto err_clk; 1620 } 1621 1622 qcom_swrm_init(ctrl); 1623 wait_for_completion_timeout(&ctrl->enumeration, 1624 msecs_to_jiffies(TIMEOUT_MS)); 1625 ret = qcom_swrm_register_dais(ctrl); 1626 if (ret) 1627 goto err_master_add; 1628 1629 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", 1630 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, 1631 ctrl->version & 0xffff); 1632 1633 pm_runtime_set_autosuspend_delay(dev, 3000); 1634 pm_runtime_use_autosuspend(dev); 1635 pm_runtime_mark_last_busy(dev); 1636 pm_runtime_set_active(dev); 1637 pm_runtime_enable(dev); 1638 1639 #ifdef CONFIG_DEBUG_FS 1640 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs); 1641 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl, 1642 &swrm_reg_fops); 1643 #endif 1644 1645 return 0; 1646 1647 err_master_add: 1648 sdw_bus_master_delete(&ctrl->bus); 1649 err_clk: 1650 clk_disable_unprepare(ctrl->hclk); 1651 err_init: 1652 return ret; 1653 } 1654 1655 static int qcom_swrm_remove(struct platform_device *pdev) 1656 { 1657 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); 1658 1659 sdw_bus_master_delete(&ctrl->bus); 1660 clk_disable_unprepare(ctrl->hclk); 1661 1662 return 0; 1663 } 1664 1665 static int __maybe_unused swrm_runtime_resume(struct device *dev) 1666 { 1667 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1668 int ret; 1669 1670 if (ctrl->wake_irq > 0) { 1671 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1672 disable_irq_nosync(ctrl->wake_irq); 1673 } 1674 1675 clk_prepare_enable(ctrl->hclk); 1676 1677 if (ctrl->clock_stop_not_supported) { 1678 reinit_completion(&ctrl->enumeration); 1679 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01); 1680 usleep_range(100, 105); 1681 1682 qcom_swrm_init(ctrl); 1683 1684 usleep_range(100, 105); 1685 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1686 dev_err(ctrl->dev, "link failed to connect\n"); 1687 1688 /* wait for hw enumeration to complete */ 1689 wait_for_completion_timeout(&ctrl->enumeration, 1690 msecs_to_jiffies(TIMEOUT_MS)); 1691 qcom_swrm_get_device_status(ctrl); 1692 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 1693 } else { 1694 reset_control_reset(ctrl->audio_cgcr); 1695 1696 if (ctrl->version == SWRM_VERSION_1_7_0) { 1697 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 1698 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, 1699 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU); 1700 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { 1701 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); 1702 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, 1703 SWRM_V2_0_CLK_CTRL_CLK_START); 1704 } else { 1705 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 1706 } 1707 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], 1708 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); 1709 1710 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1711 if (ctrl->version < SWRM_VERSION_2_0_0) 1712 ctrl->reg_write(ctrl, 1713 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 1714 ctrl->intr_mask); 1715 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 1716 ctrl->intr_mask); 1717 1718 usleep_range(100, 105); 1719 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1720 dev_err(ctrl->dev, "link failed to connect\n"); 1721 1722 ret = sdw_bus_exit_clk_stop(&ctrl->bus); 1723 if (ret < 0) 1724 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret); 1725 } 1726 1727 return 0; 1728 } 1729 1730 static int __maybe_unused swrm_runtime_suspend(struct device *dev) 1731 { 1732 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1733 int ret; 1734 1735 swrm_wait_for_wr_fifo_done(ctrl); 1736 if (!ctrl->clock_stop_not_supported) { 1737 /* Mask bus clash interrupt */ 1738 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1739 if (ctrl->version < SWRM_VERSION_2_0_0) 1740 ctrl->reg_write(ctrl, 1741 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], 1742 ctrl->intr_mask); 1743 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], 1744 ctrl->intr_mask); 1745 /* Prepare slaves for clock stop */ 1746 ret = sdw_bus_prep_clk_stop(&ctrl->bus); 1747 if (ret < 0 && ret != -ENODATA) { 1748 dev_err(dev, "prepare clock stop failed %d", ret); 1749 return ret; 1750 } 1751 1752 ret = sdw_bus_clk_stop(&ctrl->bus); 1753 if (ret < 0 && ret != -ENODATA) { 1754 dev_err(dev, "bus clock stop failed %d", ret); 1755 return ret; 1756 } 1757 } 1758 1759 clk_disable_unprepare(ctrl->hclk); 1760 1761 usleep_range(300, 305); 1762 1763 if (ctrl->wake_irq > 0) { 1764 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1765 enable_irq(ctrl->wake_irq); 1766 } 1767 1768 return 0; 1769 } 1770 1771 static const struct dev_pm_ops swrm_dev_pm_ops = { 1772 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL) 1773 }; 1774 1775 static const struct of_device_id qcom_swrm_of_match[] = { 1776 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, 1777 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, 1778 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data }, 1779 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data }, 1780 { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data }, 1781 {/* sentinel */}, 1782 }; 1783 1784 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); 1785 1786 static struct platform_driver qcom_swrm_driver = { 1787 .probe = &qcom_swrm_probe, 1788 .remove = &qcom_swrm_remove, 1789 .driver = { 1790 .name = "qcom-soundwire", 1791 .of_match_table = qcom_swrm_of_match, 1792 .pm = &swrm_dev_pm_ops, 1793 } 1794 }; 1795 module_platform_driver(qcom_swrm_driver); 1796 1797 MODULE_DESCRIPTION("Qualcomm soundwire driver"); 1798 MODULE_LICENSE("GPL v2"); 1799