1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/clk.h> 5 #include <linux/completion.h> 6 #include <linux/interrupt.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/debugfs.h> 11 #include <linux/of.h> 12 #include <linux/of_irq.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 #include <linux/slab.h> 18 #include <linux/pm_wakeirq.h> 19 #include <linux/slimbus.h> 20 #include <linux/soundwire/sdw.h> 21 #include <linux/soundwire/sdw_registers.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include "bus.h" 25 26 #define SWRM_COMP_SW_RESET 0x008 27 #define SWRM_COMP_STATUS 0x014 28 #define SWRM_FRM_GEN_ENABLED BIT(0) 29 #define SWRM_COMP_HW_VERSION 0x00 30 #define SWRM_COMP_CFG_ADDR 0x04 31 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) 32 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0) 33 #define SWRM_COMP_PARAMS 0x100 34 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10) 35 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15) 36 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) 37 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) 38 #define SWRM_COMP_MASTER_ID 0x104 39 #define SWRM_INTERRUPT_STATUS 0x200 40 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) 41 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) 42 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) 43 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2) 44 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3) 45 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4) 46 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5) 47 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6) 48 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7) 49 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) 50 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) 51 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) 52 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) 53 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) 54 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) 55 #define SWRM_INTERRUPT_MAX 17 56 #define SWRM_INTERRUPT_MASK_ADDR 0x204 57 #define SWRM_INTERRUPT_CLEAR 0x208 58 #define SWRM_INTERRUPT_CPU_EN 0x210 59 #define SWRM_CMD_FIFO_WR_CMD 0x300 60 #define SWRM_CMD_FIFO_RD_CMD 0x304 61 #define SWRM_CMD_FIFO_CMD 0x308 62 #define SWRM_CMD_FIFO_FLUSH 0x1 63 #define SWRM_CMD_FIFO_STATUS 0x30C 64 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) 65 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) 66 #define SWRM_CMD_FIFO_CFG_ADDR 0x314 67 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) 68 #define SWRM_RD_WR_CMD_RETRIES 0x7 69 #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318 70 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) 71 #define SWRM_ENUMERATOR_CFG_ADDR 0x500 72 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) 73 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m)) 74 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m)) 75 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0) 76 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3) 77 #define SWRM_MCP_BUS_CTRL 0x1044 78 #define SWRM_MCP_BUS_CLK_START BIT(1) 79 #define SWRM_MCP_CFG_ADDR 0x1048 80 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17) 81 #define SWRM_DEF_CMD_NO_PINGS 0x1f 82 #define SWRM_MCP_STATUS 0x104C 83 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0) 84 #define SWRM_MCP_SLV_STATUS 0x1090 85 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0) 86 #define SWRM_MCP_SLV_STATUS_SZ 2 87 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m) 88 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m) 89 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1)) 90 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) 91 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) 92 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) 93 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) 94 #define SWR_MSTR_MAX_REG_ADDR (0x1740) 95 96 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 97 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 98 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 99 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 100 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 101 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d 102 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91 103 104 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ 105 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) 106 107 #define SWRM_SPECIAL_CMD_ID 0xF 108 #define MAX_FREQ_NUM 1 109 #define TIMEOUT_MS 100 110 #define QCOM_SWRM_MAX_RD_LEN 0x1 111 #define QCOM_SDW_MAX_PORTS 14 112 #define DEFAULT_CLK_FREQ 9600000 113 #define SWRM_MAX_DAIS 0xF 114 #define SWR_INVALID_PARAM 0xFF 115 #define SWR_HSTOP_MAX_VAL 0xF 116 #define SWR_HSTART_MIN_VAL 0x0 117 #define SWR_BROADCAST_CMD_ID 0x0F 118 #define SWR_MAX_CMD_ID 14 119 #define MAX_FIFO_RD_RETRY 3 120 #define SWR_OVERFLOW_RETRY_COUNT 30 121 #define SWRM_LINK_STATUS_RETRY_CNT 100 122 123 enum { 124 MASTER_ID_WSA = 1, 125 MASTER_ID_RX, 126 MASTER_ID_TX 127 }; 128 129 struct qcom_swrm_port_config { 130 u8 si; 131 u8 off1; 132 u8 off2; 133 u8 bp_mode; 134 u8 hstart; 135 u8 hstop; 136 u8 word_length; 137 u8 blk_group_count; 138 u8 lane_control; 139 }; 140 141 struct qcom_swrm_ctrl { 142 struct sdw_bus bus; 143 struct device *dev; 144 struct regmap *regmap; 145 void __iomem *mmio; 146 struct reset_control *audio_cgcr; 147 #ifdef CONFIG_DEBUG_FS 148 struct dentry *debugfs; 149 #endif 150 struct completion broadcast; 151 struct completion enumeration; 152 struct work_struct slave_work; 153 /* Port alloc/free lock */ 154 struct mutex port_lock; 155 struct clk *hclk; 156 u8 wr_cmd_id; 157 u8 rd_cmd_id; 158 int irq; 159 unsigned int version; 160 int wake_irq; 161 int num_din_ports; 162 int num_dout_ports; 163 int cols_index; 164 int rows_index; 165 unsigned long dout_port_mask; 166 unsigned long din_port_mask; 167 u32 intr_mask; 168 u8 rcmd_id; 169 u8 wcmd_id; 170 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS]; 171 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; 172 enum sdw_slave_status status[SDW_MAX_DEVICES]; 173 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); 174 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); 175 u32 slave_status; 176 u32 wr_fifo_depth; 177 u32 rd_fifo_depth; 178 bool clock_stop_not_supported; 179 }; 180 181 struct qcom_swrm_data { 182 u32 default_cols; 183 u32 default_rows; 184 }; 185 186 static const struct qcom_swrm_data swrm_v1_3_data = { 187 .default_rows = 48, 188 .default_cols = 16, 189 }; 190 191 static const struct qcom_swrm_data swrm_v1_5_data = { 192 .default_rows = 50, 193 .default_cols = 16, 194 }; 195 196 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) 197 198 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 199 u32 *val) 200 { 201 struct regmap *wcd_regmap = ctrl->regmap; 202 int ret; 203 204 /* pg register + offset */ 205 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0, 206 (u8 *)®, 4); 207 if (ret < 0) 208 return SDW_CMD_FAIL; 209 210 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0, 211 val, 4); 212 if (ret < 0) 213 return SDW_CMD_FAIL; 214 215 return SDW_CMD_OK; 216 } 217 218 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, 219 int reg, int val) 220 { 221 struct regmap *wcd_regmap = ctrl->regmap; 222 int ret; 223 /* pg register + offset */ 224 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0, 225 (u8 *)&val, 4); 226 if (ret) 227 return SDW_CMD_FAIL; 228 229 /* write address register */ 230 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0, 231 (u8 *)®, 4); 232 if (ret) 233 return SDW_CMD_FAIL; 234 235 return SDW_CMD_OK; 236 } 237 238 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 239 u32 *val) 240 { 241 *val = readl(ctrl->mmio + reg); 242 return SDW_CMD_OK; 243 } 244 245 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, 246 int val) 247 { 248 writel(val, ctrl->mmio + reg); 249 return SDW_CMD_OK; 250 } 251 252 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, 253 u8 dev_addr, u16 reg_addr) 254 { 255 u32 val; 256 u8 id = *cmd_id; 257 258 if (id != SWR_BROADCAST_CMD_ID) { 259 if (id < SWR_MAX_CMD_ID) 260 id += 1; 261 else 262 id = 0; 263 *cmd_id = id; 264 } 265 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); 266 267 return val; 268 } 269 270 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) 271 { 272 u32 fifo_outstanding_data, value; 273 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 274 275 do { 276 /* Check for fifo underflow during read */ 277 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 278 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); 279 280 /* Check if read data is available in read fifo */ 281 if (fifo_outstanding_data > 0) 282 return 0; 283 284 usleep_range(500, 510); 285 } while (fifo_retry_count--); 286 287 if (fifo_outstanding_data == 0) { 288 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__); 289 return -EIO; 290 } 291 292 return 0; 293 } 294 295 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm) 296 { 297 u32 fifo_outstanding_cmds, value; 298 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 299 300 do { 301 /* Check for fifo overflow during write */ 302 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 303 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 304 305 /* Check for space in write fifo before writing */ 306 if (fifo_outstanding_cmds < swrm->wr_fifo_depth) 307 return 0; 308 309 usleep_range(500, 510); 310 } while (fifo_retry_count--); 311 312 if (fifo_outstanding_cmds == swrm->wr_fifo_depth) { 313 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__); 314 return -EIO; 315 } 316 317 return 0; 318 } 319 320 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, 321 u8 dev_addr, u16 reg_addr) 322 { 323 324 u32 val; 325 int ret = 0; 326 u8 cmd_id = 0x0; 327 328 if (dev_addr == SDW_BROADCAST_DEV_NUM) { 329 cmd_id = SWR_BROADCAST_CMD_ID; 330 val = swrm_get_packed_reg_val(&cmd_id, cmd_data, 331 dev_addr, reg_addr); 332 } else { 333 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, 334 dev_addr, reg_addr); 335 } 336 337 if (swrm_wait_for_wr_fifo_avail(swrm)) 338 return SDW_CMD_FAIL_OTHER; 339 340 /* Its assumed that write is okay as we do not get any status back */ 341 swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val); 342 343 /* version 1.3 or less */ 344 if (swrm->version <= 0x01030000) 345 usleep_range(150, 155); 346 347 if (cmd_id == SWR_BROADCAST_CMD_ID) { 348 /* 349 * sleep for 10ms for MSM soundwire variant to allow broadcast 350 * command to complete. 351 */ 352 ret = wait_for_completion_timeout(&swrm->broadcast, 353 msecs_to_jiffies(TIMEOUT_MS)); 354 if (!ret) 355 ret = SDW_CMD_IGNORED; 356 else 357 ret = SDW_CMD_OK; 358 359 } else { 360 ret = SDW_CMD_OK; 361 } 362 return ret; 363 } 364 365 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, 366 u8 dev_addr, u16 reg_addr, 367 u32 len, u8 *rval) 368 { 369 u32 cmd_data, cmd_id, val, retry_attempt = 0; 370 371 val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); 372 373 /* wait for FIFO RD to complete to avoid overflow */ 374 usleep_range(100, 105); 375 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); 376 /* wait for FIFO RD CMD complete to avoid overflow */ 377 usleep_range(250, 255); 378 379 if (swrm_wait_for_rd_fifo_avail(swrm)) 380 return SDW_CMD_FAIL_OTHER; 381 382 do { 383 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); 384 rval[0] = cmd_data & 0xFF; 385 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); 386 387 if (cmd_id != swrm->rcmd_id) { 388 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { 389 /* wait 500 us before retry on fifo read failure */ 390 usleep_range(500, 505); 391 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 392 SWRM_CMD_FIFO_FLUSH); 393 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); 394 } 395 retry_attempt++; 396 } else { 397 return SDW_CMD_OK; 398 } 399 400 } while (retry_attempt < MAX_FIFO_RD_RETRY); 401 402 dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ 403 dev_num: 0x%x, cmd_data: 0x%x\n", 404 reg_addr, swrm->rcmd_id, dev_addr, cmd_data); 405 406 return SDW_CMD_IGNORED; 407 } 408 409 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) 410 { 411 u32 val, status; 412 int dev_num; 413 414 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 415 416 for (dev_num = 0; dev_num < SDW_MAX_DEVICES; dev_num++) { 417 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); 418 419 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { 420 ctrl->status[dev_num] = status; 421 return dev_num; 422 } 423 } 424 425 return -EINVAL; 426 } 427 428 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) 429 { 430 u32 val; 431 int i; 432 433 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 434 ctrl->slave_status = val; 435 436 for (i = 0; i < SDW_MAX_DEVICES; i++) { 437 u32 s; 438 439 s = (val >> (i * 2)); 440 s &= SWRM_MCP_SLV_STATUS_MASK; 441 ctrl->status[i] = s; 442 } 443 } 444 445 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, 446 struct sdw_slave *slave, int devnum) 447 { 448 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 449 u32 status; 450 451 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); 452 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ)); 453 status &= SWRM_MCP_SLV_STATUS_MASK; 454 455 if (status == SDW_SLAVE_ATTACHED) { 456 if (slave) 457 slave->dev_num = devnum; 458 mutex_lock(&bus->bus_lock); 459 set_bit(devnum, bus->assigned); 460 mutex_unlock(&bus->bus_lock); 461 } 462 } 463 464 static int qcom_swrm_enumerate(struct sdw_bus *bus) 465 { 466 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 467 struct sdw_slave *slave, *_s; 468 struct sdw_slave_id id; 469 u32 val1, val2; 470 bool found; 471 u64 addr; 472 int i; 473 char *buf1 = (char *)&val1, *buf2 = (char *)&val2; 474 475 for (i = 1; i <= SDW_MAX_DEVICES; i++) { 476 /*SCP_Devid5 - Devid 4*/ 477 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); 478 479 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ 480 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); 481 482 if (!val1 && !val2) 483 break; 484 485 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | 486 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) | 487 ((u64)buf1[0] << 40); 488 489 sdw_extract_slave_id(bus, addr, &id); 490 found = false; 491 /* Now compare with entries */ 492 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { 493 if (sdw_compare_devid(slave, id) == 0) { 494 qcom_swrm_set_slave_dev_num(bus, slave, i); 495 found = true; 496 break; 497 } 498 } 499 500 if (!found) { 501 qcom_swrm_set_slave_dev_num(bus, NULL, i); 502 sdw_slave_add(bus, &id, NULL); 503 } 504 } 505 506 complete(&ctrl->enumeration); 507 return 0; 508 } 509 510 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) 511 { 512 struct qcom_swrm_ctrl *swrm = dev_id; 513 int ret; 514 515 ret = pm_runtime_resume_and_get(swrm->dev); 516 if (ret < 0 && ret != -EACCES) { 517 dev_err_ratelimited(swrm->dev, 518 "pm_runtime_resume_and_get failed in %s, ret %d\n", 519 __func__, ret); 520 return ret; 521 } 522 523 if (swrm->wake_irq > 0) { 524 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) 525 disable_irq_nosync(swrm->wake_irq); 526 } 527 528 pm_runtime_mark_last_busy(swrm->dev); 529 pm_runtime_put_autosuspend(swrm->dev); 530 531 return IRQ_HANDLED; 532 } 533 534 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) 535 { 536 struct qcom_swrm_ctrl *swrm = dev_id; 537 u32 value, intr_sts, intr_sts_masked, slave_status; 538 u32 i; 539 int devnum; 540 int ret = IRQ_HANDLED; 541 clk_prepare_enable(swrm->hclk); 542 543 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); 544 intr_sts_masked = intr_sts & swrm->intr_mask; 545 546 do { 547 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { 548 value = intr_sts_masked & BIT(i); 549 if (!value) 550 continue; 551 552 switch (value) { 553 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: 554 devnum = qcom_swrm_get_alert_slave_dev_num(swrm); 555 if (devnum < 0) { 556 dev_err_ratelimited(swrm->dev, 557 "no slave alert found.spurious interrupt\n"); 558 } else { 559 sdw_handle_slave_status(&swrm->bus, swrm->status); 560 } 561 562 break; 563 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: 564 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: 565 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n", 566 __func__); 567 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); 568 if (swrm->slave_status == slave_status) { 569 dev_err(swrm->dev, "Slave status not changed %x\n", 570 slave_status); 571 } else { 572 qcom_swrm_get_device_status(swrm); 573 qcom_swrm_enumerate(&swrm->bus); 574 sdw_handle_slave_status(&swrm->bus, swrm->status); 575 } 576 break; 577 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: 578 dev_err_ratelimited(swrm->dev, 579 "%s: SWR bus clsh detected\n", 580 __func__); 581 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 582 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 583 break; 584 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: 585 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 586 dev_err_ratelimited(swrm->dev, 587 "%s: SWR read FIFO overflow fifo status 0x%x\n", 588 __func__, value); 589 break; 590 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: 591 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 592 dev_err_ratelimited(swrm->dev, 593 "%s: SWR read FIFO underflow fifo status 0x%x\n", 594 __func__, value); 595 break; 596 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: 597 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 598 dev_err(swrm->dev, 599 "%s: SWR write FIFO overflow fifo status %x\n", 600 __func__, value); 601 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); 602 break; 603 case SWRM_INTERRUPT_STATUS_CMD_ERROR: 604 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 605 dev_err_ratelimited(swrm->dev, 606 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", 607 __func__, value); 608 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); 609 break; 610 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: 611 dev_err_ratelimited(swrm->dev, 612 "%s: SWR Port collision detected\n", 613 __func__); 614 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; 615 swrm->reg_write(swrm, 616 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 617 break; 618 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: 619 dev_err_ratelimited(swrm->dev, 620 "%s: SWR read enable valid mismatch\n", 621 __func__); 622 swrm->intr_mask &= 623 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; 624 swrm->reg_write(swrm, 625 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 626 break; 627 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: 628 complete(&swrm->broadcast); 629 break; 630 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: 631 break; 632 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: 633 break; 634 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: 635 break; 636 default: 637 dev_err_ratelimited(swrm->dev, 638 "%s: SWR unknown interrupt value: %d\n", 639 __func__, value); 640 ret = IRQ_NONE; 641 break; 642 } 643 } 644 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); 645 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); 646 intr_sts_masked = intr_sts & swrm->intr_mask; 647 } while (intr_sts_masked); 648 649 clk_disable_unprepare(swrm->hclk); 650 return ret; 651 } 652 653 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) 654 { 655 u32 val; 656 657 /* Clear Rows and Cols */ 658 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); 659 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); 660 661 reset_control_reset(ctrl->audio_cgcr); 662 663 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); 664 665 /* Enable Auto enumeration */ 666 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); 667 668 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; 669 /* Mask soundwire interrupts */ 670 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, 671 SWRM_INTERRUPT_STATUS_RMSK); 672 673 /* Configure No pings */ 674 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); 675 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); 676 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); 677 678 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 679 /* Configure number of retries of a read/write cmd */ 680 if (ctrl->version > 0x01050001) { 681 /* Only for versions >= 1.5.1 */ 682 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 683 SWRM_RD_WR_CMD_RETRIES | 684 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE); 685 } else { 686 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 687 SWRM_RD_WR_CMD_RETRIES); 688 } 689 690 /* Set IRQ to PULSE */ 691 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 692 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | 693 SWRM_COMP_CFG_ENABLE_MSK); 694 695 /* enable CPU IRQs */ 696 if (ctrl->mmio) { 697 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, 698 SWRM_INTERRUPT_STATUS_RMSK); 699 } 700 ctrl->slave_status = 0; 701 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 702 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); 703 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); 704 705 return 0; 706 } 707 708 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, 709 struct sdw_msg *msg) 710 { 711 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 712 int ret, i, len; 713 714 if (msg->flags == SDW_MSG_FLAG_READ) { 715 for (i = 0; i < msg->len;) { 716 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) 717 len = msg->len - i; 718 else 719 len = QCOM_SWRM_MAX_RD_LEN; 720 721 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, 722 msg->addr + i, len, 723 &msg->buf[i]); 724 if (ret) 725 return ret; 726 727 i = i + len; 728 } 729 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { 730 for (i = 0; i < msg->len; i++) { 731 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], 732 msg->dev_num, 733 msg->addr + i); 734 if (ret) 735 return SDW_CMD_IGNORED; 736 } 737 } 738 739 return SDW_CMD_OK; 740 } 741 742 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) 743 { 744 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); 745 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 746 u32 val; 747 748 ctrl->reg_read(ctrl, reg, &val); 749 750 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); 751 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); 752 753 return ctrl->reg_write(ctrl, reg, val); 754 } 755 756 static int qcom_swrm_port_params(struct sdw_bus *bus, 757 struct sdw_port_params *p_params, 758 unsigned int bank) 759 { 760 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 761 762 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), 763 p_params->bps - 1); 764 765 } 766 767 static int qcom_swrm_transport_params(struct sdw_bus *bus, 768 struct sdw_transport_params *params, 769 enum sdw_reg_bank bank) 770 { 771 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 772 struct qcom_swrm_port_config *pcfg; 773 u32 value; 774 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); 775 int ret; 776 777 pcfg = &ctrl->pconfig[params->port_num]; 778 779 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; 780 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; 781 value |= pcfg->si; 782 783 ret = ctrl->reg_write(ctrl, reg, value); 784 if (ret) 785 goto err; 786 787 if (pcfg->lane_control != SWR_INVALID_PARAM) { 788 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); 789 value = pcfg->lane_control; 790 ret = ctrl->reg_write(ctrl, reg, value); 791 if (ret) 792 goto err; 793 } 794 795 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { 796 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); 797 value = pcfg->blk_group_count; 798 ret = ctrl->reg_write(ctrl, reg, value); 799 if (ret) 800 goto err; 801 } 802 803 if (pcfg->hstart != SWR_INVALID_PARAM 804 && pcfg->hstop != SWR_INVALID_PARAM) { 805 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 806 value = (pcfg->hstop << 4) | pcfg->hstart; 807 ret = ctrl->reg_write(ctrl, reg, value); 808 } else { 809 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 810 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL; 811 ret = ctrl->reg_write(ctrl, reg, value); 812 } 813 814 if (ret) 815 goto err; 816 817 if (pcfg->bp_mode != SWR_INVALID_PARAM) { 818 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); 819 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); 820 } 821 822 err: 823 return ret; 824 } 825 826 static int qcom_swrm_port_enable(struct sdw_bus *bus, 827 struct sdw_enable_ch *enable_ch, 828 unsigned int bank) 829 { 830 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); 831 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 832 u32 val; 833 834 ctrl->reg_read(ctrl, reg, &val); 835 836 if (enable_ch->enable) 837 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 838 else 839 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 840 841 return ctrl->reg_write(ctrl, reg, val); 842 } 843 844 static const struct sdw_master_port_ops qcom_swrm_port_ops = { 845 .dpn_set_port_params = qcom_swrm_port_params, 846 .dpn_set_port_transport_params = qcom_swrm_transport_params, 847 .dpn_port_enable_ch = qcom_swrm_port_enable, 848 }; 849 850 static const struct sdw_master_ops qcom_swrm_ops = { 851 .xfer_msg = qcom_swrm_xfer_msg, 852 .pre_bank_switch = qcom_swrm_pre_bank_switch, 853 }; 854 855 static int qcom_swrm_compute_params(struct sdw_bus *bus) 856 { 857 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 858 struct sdw_master_runtime *m_rt; 859 struct sdw_slave_runtime *s_rt; 860 struct sdw_port_runtime *p_rt; 861 struct qcom_swrm_port_config *pcfg; 862 struct sdw_slave *slave; 863 unsigned int m_port; 864 int i = 1; 865 866 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 867 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 868 pcfg = &ctrl->pconfig[p_rt->num]; 869 p_rt->transport_params.port_num = p_rt->num; 870 if (pcfg->word_length != SWR_INVALID_PARAM) { 871 sdw_fill_port_params(&p_rt->port_params, 872 p_rt->num, pcfg->word_length + 1, 873 SDW_PORT_FLOW_MODE_ISOCH, 874 SDW_PORT_DATA_MODE_NORMAL); 875 } 876 877 } 878 879 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 880 slave = s_rt->slave; 881 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 882 m_port = slave->m_port_map[p_rt->num]; 883 /* port config starts at offset 0 so -1 from actual port number */ 884 if (m_port) 885 pcfg = &ctrl->pconfig[m_port]; 886 else 887 pcfg = &ctrl->pconfig[i]; 888 p_rt->transport_params.port_num = p_rt->num; 889 p_rt->transport_params.sample_interval = 890 pcfg->si + 1; 891 p_rt->transport_params.offset1 = pcfg->off1; 892 p_rt->transport_params.offset2 = pcfg->off2; 893 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; 894 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; 895 896 p_rt->transport_params.hstart = pcfg->hstart; 897 p_rt->transport_params.hstop = pcfg->hstop; 898 p_rt->transport_params.lane_ctrl = pcfg->lane_control; 899 if (pcfg->word_length != SWR_INVALID_PARAM) { 900 sdw_fill_port_params(&p_rt->port_params, 901 p_rt->num, 902 pcfg->word_length + 1, 903 SDW_PORT_FLOW_MODE_ISOCH, 904 SDW_PORT_DATA_MODE_NORMAL); 905 } 906 i++; 907 } 908 } 909 } 910 911 return 0; 912 } 913 914 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = { 915 DEFAULT_CLK_FREQ, 916 }; 917 918 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, 919 struct sdw_stream_runtime *stream) 920 { 921 struct sdw_master_runtime *m_rt; 922 struct sdw_port_runtime *p_rt; 923 unsigned long *port_mask; 924 925 mutex_lock(&ctrl->port_lock); 926 927 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 928 if (m_rt->direction == SDW_DATA_DIR_RX) 929 port_mask = &ctrl->dout_port_mask; 930 else 931 port_mask = &ctrl->din_port_mask; 932 933 list_for_each_entry(p_rt, &m_rt->port_list, port_node) 934 clear_bit(p_rt->num, port_mask); 935 } 936 937 mutex_unlock(&ctrl->port_lock); 938 } 939 940 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, 941 struct sdw_stream_runtime *stream, 942 struct snd_pcm_hw_params *params, 943 int direction) 944 { 945 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS]; 946 struct sdw_stream_config sconfig; 947 struct sdw_master_runtime *m_rt; 948 struct sdw_slave_runtime *s_rt; 949 struct sdw_port_runtime *p_rt; 950 struct sdw_slave *slave; 951 unsigned long *port_mask; 952 int i, maxport, pn, nports = 0, ret = 0; 953 unsigned int m_port; 954 955 mutex_lock(&ctrl->port_lock); 956 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 957 if (m_rt->direction == SDW_DATA_DIR_RX) { 958 maxport = ctrl->num_dout_ports; 959 port_mask = &ctrl->dout_port_mask; 960 } else { 961 maxport = ctrl->num_din_ports; 962 port_mask = &ctrl->din_port_mask; 963 } 964 965 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 966 slave = s_rt->slave; 967 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 968 m_port = slave->m_port_map[p_rt->num]; 969 /* Port numbers start from 1 - 14*/ 970 if (m_port) 971 pn = m_port; 972 else 973 pn = find_first_zero_bit(port_mask, maxport); 974 975 if (pn > maxport) { 976 dev_err(ctrl->dev, "All ports busy\n"); 977 ret = -EBUSY; 978 goto err; 979 } 980 set_bit(pn, port_mask); 981 pconfig[nports].num = pn; 982 pconfig[nports].ch_mask = p_rt->ch_mask; 983 nports++; 984 } 985 } 986 } 987 988 if (direction == SNDRV_PCM_STREAM_CAPTURE) 989 sconfig.direction = SDW_DATA_DIR_TX; 990 else 991 sconfig.direction = SDW_DATA_DIR_RX; 992 993 /* hw parameters wil be ignored as we only support PDM */ 994 sconfig.ch_count = 1; 995 sconfig.frame_rate = params_rate(params); 996 sconfig.type = stream->type; 997 sconfig.bps = 1; 998 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, 999 nports, stream); 1000 err: 1001 if (ret) { 1002 for (i = 0; i < nports; i++) 1003 clear_bit(pconfig[i].num, port_mask); 1004 } 1005 1006 mutex_unlock(&ctrl->port_lock); 1007 1008 return ret; 1009 } 1010 1011 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, 1012 struct snd_pcm_hw_params *params, 1013 struct snd_soc_dai *dai) 1014 { 1015 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1016 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1017 int ret; 1018 1019 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, 1020 substream->stream); 1021 if (ret) 1022 qcom_swrm_stream_free_ports(ctrl, sruntime); 1023 1024 return ret; 1025 } 1026 1027 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, 1028 struct snd_soc_dai *dai) 1029 { 1030 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1031 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1032 1033 qcom_swrm_stream_free_ports(ctrl, sruntime); 1034 sdw_stream_remove_master(&ctrl->bus, sruntime); 1035 1036 return 0; 1037 } 1038 1039 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, 1040 void *stream, int direction) 1041 { 1042 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1043 1044 ctrl->sruntime[dai->id] = stream; 1045 1046 return 0; 1047 } 1048 1049 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) 1050 { 1051 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1052 1053 return ctrl->sruntime[dai->id]; 1054 } 1055 1056 static int qcom_swrm_startup(struct snd_pcm_substream *substream, 1057 struct snd_soc_dai *dai) 1058 { 1059 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1060 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1061 struct sdw_stream_runtime *sruntime; 1062 struct snd_soc_dai *codec_dai; 1063 int ret, i; 1064 1065 ret = pm_runtime_resume_and_get(ctrl->dev); 1066 if (ret < 0 && ret != -EACCES) { 1067 dev_err_ratelimited(ctrl->dev, 1068 "pm_runtime_resume_and_get failed in %s, ret %d\n", 1069 __func__, ret); 1070 return ret; 1071 } 1072 1073 sruntime = sdw_alloc_stream(dai->name); 1074 if (!sruntime) 1075 return -ENOMEM; 1076 1077 ctrl->sruntime[dai->id] = sruntime; 1078 1079 for_each_rtd_codec_dais(rtd, i, codec_dai) { 1080 ret = snd_soc_dai_set_stream(codec_dai, sruntime, 1081 substream->stream); 1082 if (ret < 0 && ret != -ENOTSUPP) { 1083 dev_err(dai->dev, "Failed to set sdw stream on %s\n", 1084 codec_dai->name); 1085 sdw_release_stream(sruntime); 1086 return ret; 1087 } 1088 } 1089 1090 return 0; 1091 } 1092 1093 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, 1094 struct snd_soc_dai *dai) 1095 { 1096 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1097 1098 sdw_release_stream(ctrl->sruntime[dai->id]); 1099 ctrl->sruntime[dai->id] = NULL; 1100 pm_runtime_mark_last_busy(ctrl->dev); 1101 pm_runtime_put_autosuspend(ctrl->dev); 1102 1103 } 1104 1105 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { 1106 .hw_params = qcom_swrm_hw_params, 1107 .hw_free = qcom_swrm_hw_free, 1108 .startup = qcom_swrm_startup, 1109 .shutdown = qcom_swrm_shutdown, 1110 .set_stream = qcom_swrm_set_sdw_stream, 1111 .get_stream = qcom_swrm_get_sdw_stream, 1112 }; 1113 1114 static const struct snd_soc_component_driver qcom_swrm_dai_component = { 1115 .name = "soundwire", 1116 }; 1117 1118 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) 1119 { 1120 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; 1121 struct snd_soc_dai_driver *dais; 1122 struct snd_soc_pcm_stream *stream; 1123 struct device *dev = ctrl->dev; 1124 int i; 1125 1126 /* PDM dais are only tested for now */ 1127 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 1128 if (!dais) 1129 return -ENOMEM; 1130 1131 for (i = 0; i < num_dais; i++) { 1132 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i); 1133 if (!dais[i].name) 1134 return -ENOMEM; 1135 1136 if (i < ctrl->num_dout_ports) 1137 stream = &dais[i].playback; 1138 else 1139 stream = &dais[i].capture; 1140 1141 stream->channels_min = 1; 1142 stream->channels_max = 1; 1143 stream->rates = SNDRV_PCM_RATE_48000; 1144 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 1145 1146 dais[i].ops = &qcom_swrm_pdm_dai_ops; 1147 dais[i].id = i; 1148 } 1149 1150 return devm_snd_soc_register_component(ctrl->dev, 1151 &qcom_swrm_dai_component, 1152 dais, num_dais); 1153 } 1154 1155 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) 1156 { 1157 struct device_node *np = ctrl->dev->of_node; 1158 u8 off1[QCOM_SDW_MAX_PORTS]; 1159 u8 off2[QCOM_SDW_MAX_PORTS]; 1160 u8 si[QCOM_SDW_MAX_PORTS]; 1161 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; 1162 u8 hstart[QCOM_SDW_MAX_PORTS]; 1163 u8 hstop[QCOM_SDW_MAX_PORTS]; 1164 u8 word_length[QCOM_SDW_MAX_PORTS]; 1165 u8 blk_group_count[QCOM_SDW_MAX_PORTS]; 1166 u8 lane_control[QCOM_SDW_MAX_PORTS]; 1167 int i, ret, nports, val; 1168 1169 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 1170 1171 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); 1172 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); 1173 1174 ret = of_property_read_u32(np, "qcom,din-ports", &val); 1175 if (ret) 1176 return ret; 1177 1178 if (val > ctrl->num_din_ports) 1179 return -EINVAL; 1180 1181 ctrl->num_din_ports = val; 1182 1183 ret = of_property_read_u32(np, "qcom,dout-ports", &val); 1184 if (ret) 1185 return ret; 1186 1187 if (val > ctrl->num_dout_ports) 1188 return -EINVAL; 1189 1190 ctrl->num_dout_ports = val; 1191 1192 nports = ctrl->num_dout_ports + ctrl->num_din_ports; 1193 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ 1194 set_bit(0, &ctrl->dout_port_mask); 1195 set_bit(0, &ctrl->din_port_mask); 1196 1197 ret = of_property_read_u8_array(np, "qcom,ports-offset1", 1198 off1, nports); 1199 if (ret) 1200 return ret; 1201 1202 ret = of_property_read_u8_array(np, "qcom,ports-offset2", 1203 off2, nports); 1204 if (ret) 1205 return ret; 1206 1207 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", 1208 si, nports); 1209 if (ret) 1210 return ret; 1211 1212 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", 1213 bp_mode, nports); 1214 if (ret) { 1215 if (ctrl->version <= 0x01030000) 1216 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1217 else 1218 return ret; 1219 } 1220 1221 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1222 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); 1223 1224 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1225 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); 1226 1227 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1228 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); 1229 1230 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1231 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); 1232 1233 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1234 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); 1235 1236 for (i = 0; i < nports; i++) { 1237 /* Valid port number range is from 1-14 */ 1238 ctrl->pconfig[i + 1].si = si[i]; 1239 ctrl->pconfig[i + 1].off1 = off1[i]; 1240 ctrl->pconfig[i + 1].off2 = off2[i]; 1241 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; 1242 ctrl->pconfig[i + 1].hstart = hstart[i]; 1243 ctrl->pconfig[i + 1].hstop = hstop[i]; 1244 ctrl->pconfig[i + 1].word_length = word_length[i]; 1245 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; 1246 ctrl->pconfig[i + 1].lane_control = lane_control[i]; 1247 } 1248 1249 return 0; 1250 } 1251 1252 #ifdef CONFIG_DEBUG_FS 1253 static int swrm_reg_show(struct seq_file *s_file, void *data) 1254 { 1255 struct qcom_swrm_ctrl *swrm = s_file->private; 1256 int reg, reg_val, ret; 1257 1258 ret = pm_runtime_resume_and_get(swrm->dev); 1259 if (ret < 0 && ret != -EACCES) { 1260 dev_err_ratelimited(swrm->dev, 1261 "pm_runtime_resume_and_get failed in %s, ret %d\n", 1262 __func__, ret); 1263 return ret; 1264 } 1265 1266 for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) { 1267 swrm->reg_read(swrm, reg, ®_val); 1268 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); 1269 } 1270 pm_runtime_mark_last_busy(swrm->dev); 1271 pm_runtime_put_autosuspend(swrm->dev); 1272 1273 1274 return 0; 1275 } 1276 DEFINE_SHOW_ATTRIBUTE(swrm_reg); 1277 #endif 1278 1279 static int qcom_swrm_probe(struct platform_device *pdev) 1280 { 1281 struct device *dev = &pdev->dev; 1282 struct sdw_master_prop *prop; 1283 struct sdw_bus_params *params; 1284 struct qcom_swrm_ctrl *ctrl; 1285 const struct qcom_swrm_data *data; 1286 int ret; 1287 u32 val; 1288 1289 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1290 if (!ctrl) 1291 return -ENOMEM; 1292 1293 data = of_device_get_match_data(dev); 1294 ctrl->rows_index = sdw_find_row_index(data->default_rows); 1295 ctrl->cols_index = sdw_find_col_index(data->default_cols); 1296 #if IS_REACHABLE(CONFIG_SLIMBUS) 1297 if (dev->parent->bus == &slimbus_bus) { 1298 #else 1299 if (false) { 1300 #endif 1301 ctrl->reg_read = qcom_swrm_ahb_reg_read; 1302 ctrl->reg_write = qcom_swrm_ahb_reg_write; 1303 ctrl->regmap = dev_get_regmap(dev->parent, NULL); 1304 if (!ctrl->regmap) 1305 return -EINVAL; 1306 } else { 1307 ctrl->reg_read = qcom_swrm_cpu_reg_read; 1308 ctrl->reg_write = qcom_swrm_cpu_reg_write; 1309 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0); 1310 if (IS_ERR(ctrl->mmio)) 1311 return PTR_ERR(ctrl->mmio); 1312 } 1313 1314 ctrl->irq = of_irq_get(dev->of_node, 0); 1315 if (ctrl->irq < 0) { 1316 ret = ctrl->irq; 1317 goto err_init; 1318 } 1319 1320 ctrl->hclk = devm_clk_get(dev, "iface"); 1321 if (IS_ERR(ctrl->hclk)) { 1322 ret = PTR_ERR(ctrl->hclk); 1323 goto err_init; 1324 } 1325 1326 clk_prepare_enable(ctrl->hclk); 1327 1328 ctrl->dev = dev; 1329 dev_set_drvdata(&pdev->dev, ctrl); 1330 mutex_init(&ctrl->port_lock); 1331 init_completion(&ctrl->broadcast); 1332 init_completion(&ctrl->enumeration); 1333 1334 ctrl->bus.ops = &qcom_swrm_ops; 1335 ctrl->bus.port_ops = &qcom_swrm_port_ops; 1336 ctrl->bus.compute_params = &qcom_swrm_compute_params; 1337 ctrl->bus.clk_stop_timeout = 300; 1338 1339 ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr"); 1340 if (IS_ERR(ctrl->audio_cgcr)) 1341 dev_err(dev, "Failed to get audio_cgcr reset required for soundwire-v1.6.0\n"); 1342 1343 ret = qcom_swrm_get_port_config(ctrl); 1344 if (ret) 1345 goto err_clk; 1346 1347 params = &ctrl->bus.params; 1348 params->max_dr_freq = DEFAULT_CLK_FREQ; 1349 params->curr_dr_freq = DEFAULT_CLK_FREQ; 1350 params->col = data->default_cols; 1351 params->row = data->default_rows; 1352 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val); 1353 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK; 1354 params->next_bank = !params->curr_bank; 1355 1356 prop = &ctrl->bus.prop; 1357 prop->max_clk_freq = DEFAULT_CLK_FREQ; 1358 prop->num_clk_gears = 0; 1359 prop->num_clk_freq = MAX_FREQ_NUM; 1360 prop->clk_freq = &qcom_swrm_freq_tbl[0]; 1361 prop->default_col = data->default_cols; 1362 prop->default_row = data->default_rows; 1363 1364 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); 1365 1366 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, 1367 qcom_swrm_irq_handler, 1368 IRQF_TRIGGER_RISING | 1369 IRQF_ONESHOT, 1370 "soundwire", ctrl); 1371 if (ret) { 1372 dev_err(dev, "Failed to request soundwire irq\n"); 1373 goto err_clk; 1374 } 1375 1376 ctrl->wake_irq = of_irq_get(dev->of_node, 1); 1377 if (ctrl->wake_irq > 0) { 1378 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL, 1379 qcom_swrm_wake_irq_handler, 1380 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1381 "swr_wake_irq", ctrl); 1382 if (ret) { 1383 dev_err(dev, "Failed to request soundwire wake irq\n"); 1384 goto err_init; 1385 } 1386 } 1387 1388 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); 1389 if (ret) { 1390 dev_err(dev, "Failed to register Soundwire controller (%d)\n", 1391 ret); 1392 goto err_clk; 1393 } 1394 1395 qcom_swrm_init(ctrl); 1396 wait_for_completion_timeout(&ctrl->enumeration, 1397 msecs_to_jiffies(TIMEOUT_MS)); 1398 ret = qcom_swrm_register_dais(ctrl); 1399 if (ret) 1400 goto err_master_add; 1401 1402 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", 1403 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, 1404 ctrl->version & 0xffff); 1405 1406 pm_runtime_set_autosuspend_delay(dev, 3000); 1407 pm_runtime_use_autosuspend(dev); 1408 pm_runtime_mark_last_busy(dev); 1409 pm_runtime_set_active(dev); 1410 pm_runtime_enable(dev); 1411 1412 /* Clk stop is not supported on WSA Soundwire masters */ 1413 if (ctrl->version <= 0x01030000) { 1414 ctrl->clock_stop_not_supported = true; 1415 } else { 1416 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val); 1417 if (val == MASTER_ID_WSA) 1418 ctrl->clock_stop_not_supported = true; 1419 } 1420 1421 #ifdef CONFIG_DEBUG_FS 1422 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs); 1423 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl, 1424 &swrm_reg_fops); 1425 #endif 1426 1427 return 0; 1428 1429 err_master_add: 1430 sdw_bus_master_delete(&ctrl->bus); 1431 err_clk: 1432 clk_disable_unprepare(ctrl->hclk); 1433 err_init: 1434 return ret; 1435 } 1436 1437 static int qcom_swrm_remove(struct platform_device *pdev) 1438 { 1439 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); 1440 1441 sdw_bus_master_delete(&ctrl->bus); 1442 clk_disable_unprepare(ctrl->hclk); 1443 1444 return 0; 1445 } 1446 1447 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) 1448 { 1449 int retry = SWRM_LINK_STATUS_RETRY_CNT; 1450 int comp_sts; 1451 1452 do { 1453 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts); 1454 1455 if (comp_sts & SWRM_FRM_GEN_ENABLED) 1456 return true; 1457 1458 usleep_range(500, 510); 1459 } while (retry--); 1460 1461 dev_err(swrm->dev, "%s: link status not %s\n", __func__, 1462 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); 1463 1464 return false; 1465 } 1466 1467 static int __maybe_unused swrm_runtime_resume(struct device *dev) 1468 { 1469 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1470 int ret; 1471 1472 if (ctrl->wake_irq > 0) { 1473 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1474 disable_irq_nosync(ctrl->wake_irq); 1475 } 1476 1477 clk_prepare_enable(ctrl->hclk); 1478 1479 if (ctrl->clock_stop_not_supported) { 1480 reinit_completion(&ctrl->enumeration); 1481 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01); 1482 usleep_range(100, 105); 1483 1484 qcom_swrm_init(ctrl); 1485 1486 usleep_range(100, 105); 1487 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1488 dev_err(ctrl->dev, "link failed to connect\n"); 1489 1490 /* wait for hw enumeration to complete */ 1491 wait_for_completion_timeout(&ctrl->enumeration, 1492 msecs_to_jiffies(TIMEOUT_MS)); 1493 qcom_swrm_get_device_status(ctrl); 1494 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 1495 } else { 1496 reset_control_reset(ctrl->audio_cgcr); 1497 1498 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 1499 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, 1500 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); 1501 1502 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1503 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); 1504 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); 1505 1506 usleep_range(100, 105); 1507 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1508 dev_err(ctrl->dev, "link failed to connect\n"); 1509 1510 ret = sdw_bus_exit_clk_stop(&ctrl->bus); 1511 if (ret < 0) 1512 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret); 1513 } 1514 1515 return 0; 1516 } 1517 1518 static int __maybe_unused swrm_runtime_suspend(struct device *dev) 1519 { 1520 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1521 int ret; 1522 1523 if (!ctrl->clock_stop_not_supported) { 1524 /* Mask bus clash interrupt */ 1525 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1526 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); 1527 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); 1528 /* Prepare slaves for clock stop */ 1529 ret = sdw_bus_prep_clk_stop(&ctrl->bus); 1530 if (ret < 0 && ret != -ENODATA) { 1531 dev_err(dev, "prepare clock stop failed %d", ret); 1532 return ret; 1533 } 1534 1535 ret = sdw_bus_clk_stop(&ctrl->bus); 1536 if (ret < 0 && ret != -ENODATA) { 1537 dev_err(dev, "bus clock stop failed %d", ret); 1538 return ret; 1539 } 1540 } 1541 1542 clk_disable_unprepare(ctrl->hclk); 1543 1544 usleep_range(300, 305); 1545 1546 if (ctrl->wake_irq > 0) { 1547 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1548 enable_irq(ctrl->wake_irq); 1549 } 1550 1551 return 0; 1552 } 1553 1554 static const struct dev_pm_ops swrm_dev_pm_ops = { 1555 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL) 1556 }; 1557 1558 static const struct of_device_id qcom_swrm_of_match[] = { 1559 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, 1560 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, 1561 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_5_data }, 1562 {/* sentinel */}, 1563 }; 1564 1565 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); 1566 1567 static struct platform_driver qcom_swrm_driver = { 1568 .probe = &qcom_swrm_probe, 1569 .remove = &qcom_swrm_remove, 1570 .driver = { 1571 .name = "qcom-soundwire", 1572 .of_match_table = qcom_swrm_of_match, 1573 .pm = &swrm_dev_pm_ops, 1574 } 1575 }; 1576 module_platform_driver(qcom_swrm_driver); 1577 1578 MODULE_DESCRIPTION("Qualcomm soundwire driver"); 1579 MODULE_LICENSE("GPL v2"); 1580