1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2019, Linaro Limited 3 4 #include <linux/clk.h> 5 #include <linux/completion.h> 6 #include <linux/interrupt.h> 7 #include <linux/io.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/debugfs.h> 11 #include <linux/of.h> 12 #include <linux/of_irq.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 #include <linux/pm_wakeirq.h> 18 #include <linux/slimbus.h> 19 #include <linux/soundwire/sdw.h> 20 #include <linux/soundwire/sdw_registers.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include "bus.h" 24 25 #define SWRM_COMP_SW_RESET 0x008 26 #define SWRM_COMP_STATUS 0x014 27 #define SWRM_FRM_GEN_ENABLED BIT(0) 28 #define SWRM_COMP_HW_VERSION 0x00 29 #define SWRM_COMP_CFG_ADDR 0x04 30 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1) 31 #define SWRM_COMP_CFG_ENABLE_MSK BIT(0) 32 #define SWRM_COMP_PARAMS 0x100 33 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10) 34 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15) 35 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0) 36 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5) 37 #define SWRM_COMP_MASTER_ID 0x104 38 #define SWRM_INTERRUPT_STATUS 0x200 39 #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0) 40 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0) 41 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1) 42 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2) 43 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3) 44 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4) 45 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5) 46 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6) 47 #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7) 48 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8) 49 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9) 50 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10) 51 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13) 52 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14) 53 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16) 54 #define SWRM_INTERRUPT_MAX 17 55 #define SWRM_INTERRUPT_MASK_ADDR 0x204 56 #define SWRM_INTERRUPT_CLEAR 0x208 57 #define SWRM_INTERRUPT_CPU_EN 0x210 58 #define SWRM_CMD_FIFO_WR_CMD 0x300 59 #define SWRM_CMD_FIFO_RD_CMD 0x304 60 #define SWRM_CMD_FIFO_CMD 0x308 61 #define SWRM_CMD_FIFO_FLUSH 0x1 62 #define SWRM_CMD_FIFO_STATUS 0x30C 63 #define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16) 64 #define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8) 65 #define SWRM_CMD_FIFO_CFG_ADDR 0x314 66 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31) 67 #define SWRM_RD_WR_CMD_RETRIES 0x7 68 #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318 69 #define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8) 70 #define SWRM_ENUMERATOR_CFG_ADDR 0x500 71 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m)) 72 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m)) 73 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m)) 74 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0) 75 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3) 76 #define SWRM_MCP_BUS_CTRL 0x1044 77 #define SWRM_MCP_BUS_CLK_START BIT(1) 78 #define SWRM_MCP_CFG_ADDR 0x1048 79 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17) 80 #define SWRM_DEF_CMD_NO_PINGS 0x1f 81 #define SWRM_MCP_STATUS 0x104C 82 #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0) 83 #define SWRM_MCP_SLV_STATUS 0x1090 84 #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0) 85 #define SWRM_MCP_SLV_STATUS_SZ 2 86 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m) 87 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m) 88 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1)) 89 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m) 90 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m) 91 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m) 92 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1)) 93 #define SWR_MSTR_MAX_REG_ADDR (0x1740) 94 95 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 96 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 97 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 98 #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85 99 #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89 100 #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d 101 #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91 102 103 #define SWRM_REG_VAL_PACK(data, dev, id, reg) \ 104 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24)) 105 106 #define SWRM_SPECIAL_CMD_ID 0xF 107 #define MAX_FREQ_NUM 1 108 #define TIMEOUT_MS 100 109 #define QCOM_SWRM_MAX_RD_LEN 0x1 110 #define QCOM_SDW_MAX_PORTS 14 111 #define DEFAULT_CLK_FREQ 9600000 112 #define SWRM_MAX_DAIS 0xF 113 #define SWR_INVALID_PARAM 0xFF 114 #define SWR_HSTOP_MAX_VAL 0xF 115 #define SWR_HSTART_MIN_VAL 0x0 116 #define SWR_BROADCAST_CMD_ID 0x0F 117 #define SWR_MAX_CMD_ID 14 118 #define MAX_FIFO_RD_RETRY 3 119 #define SWR_OVERFLOW_RETRY_COUNT 30 120 #define SWRM_LINK_STATUS_RETRY_CNT 100 121 122 enum { 123 MASTER_ID_WSA = 1, 124 MASTER_ID_RX, 125 MASTER_ID_TX 126 }; 127 128 struct qcom_swrm_port_config { 129 u8 si; 130 u8 off1; 131 u8 off2; 132 u8 bp_mode; 133 u8 hstart; 134 u8 hstop; 135 u8 word_length; 136 u8 blk_group_count; 137 u8 lane_control; 138 }; 139 140 struct qcom_swrm_ctrl { 141 struct sdw_bus bus; 142 struct device *dev; 143 struct regmap *regmap; 144 void __iomem *mmio; 145 #ifdef CONFIG_DEBUG_FS 146 struct dentry *debugfs; 147 #endif 148 struct completion broadcast; 149 struct completion enumeration; 150 struct work_struct slave_work; 151 /* Port alloc/free lock */ 152 struct mutex port_lock; 153 struct clk *hclk; 154 u8 wr_cmd_id; 155 u8 rd_cmd_id; 156 int irq; 157 unsigned int version; 158 int wake_irq; 159 int num_din_ports; 160 int num_dout_ports; 161 int cols_index; 162 int rows_index; 163 unsigned long dout_port_mask; 164 unsigned long din_port_mask; 165 u32 intr_mask; 166 u8 rcmd_id; 167 u8 wcmd_id; 168 struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS]; 169 struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS]; 170 enum sdw_slave_status status[SDW_MAX_DEVICES]; 171 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val); 172 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); 173 u32 slave_status; 174 u32 wr_fifo_depth; 175 u32 rd_fifo_depth; 176 bool clock_stop_not_supported; 177 }; 178 179 struct qcom_swrm_data { 180 u32 default_cols; 181 u32 default_rows; 182 }; 183 184 static const struct qcom_swrm_data swrm_v1_3_data = { 185 .default_rows = 48, 186 .default_cols = 16, 187 }; 188 189 static const struct qcom_swrm_data swrm_v1_5_data = { 190 .default_rows = 50, 191 .default_cols = 16, 192 }; 193 194 #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) 195 196 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 197 u32 *val) 198 { 199 struct regmap *wcd_regmap = ctrl->regmap; 200 int ret; 201 202 /* pg register + offset */ 203 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0, 204 (u8 *)®, 4); 205 if (ret < 0) 206 return SDW_CMD_FAIL; 207 208 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0, 209 val, 4); 210 if (ret < 0) 211 return SDW_CMD_FAIL; 212 213 return SDW_CMD_OK; 214 } 215 216 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, 217 int reg, int val) 218 { 219 struct regmap *wcd_regmap = ctrl->regmap; 220 int ret; 221 /* pg register + offset */ 222 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0, 223 (u8 *)&val, 4); 224 if (ret) 225 return SDW_CMD_FAIL; 226 227 /* write address register */ 228 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0, 229 (u8 *)®, 4); 230 if (ret) 231 return SDW_CMD_FAIL; 232 233 return SDW_CMD_OK; 234 } 235 236 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, 237 u32 *val) 238 { 239 *val = readl(ctrl->mmio + reg); 240 return SDW_CMD_OK; 241 } 242 243 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, 244 int val) 245 { 246 writel(val, ctrl->mmio + reg); 247 return SDW_CMD_OK; 248 } 249 250 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data, 251 u8 dev_addr, u16 reg_addr) 252 { 253 u32 val; 254 u8 id = *cmd_id; 255 256 if (id != SWR_BROADCAST_CMD_ID) { 257 if (id < SWR_MAX_CMD_ID) 258 id += 1; 259 else 260 id = 0; 261 *cmd_id = id; 262 } 263 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr); 264 265 return val; 266 } 267 268 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm) 269 { 270 u32 fifo_outstanding_data, value; 271 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 272 273 do { 274 /* Check for fifo underflow during read */ 275 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 276 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value); 277 278 /* Check if read data is available in read fifo */ 279 if (fifo_outstanding_data > 0) 280 return 0; 281 282 usleep_range(500, 510); 283 } while (fifo_retry_count--); 284 285 if (fifo_outstanding_data == 0) { 286 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__); 287 return -EIO; 288 } 289 290 return 0; 291 } 292 293 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm) 294 { 295 u32 fifo_outstanding_cmds, value; 296 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT; 297 298 do { 299 /* Check for fifo overflow during write */ 300 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 301 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value); 302 303 /* Check for space in write fifo before writing */ 304 if (fifo_outstanding_cmds < swrm->wr_fifo_depth) 305 return 0; 306 307 usleep_range(500, 510); 308 } while (fifo_retry_count--); 309 310 if (fifo_outstanding_cmds == swrm->wr_fifo_depth) { 311 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__); 312 return -EIO; 313 } 314 315 return 0; 316 } 317 318 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data, 319 u8 dev_addr, u16 reg_addr) 320 { 321 322 u32 val; 323 int ret = 0; 324 u8 cmd_id = 0x0; 325 326 if (dev_addr == SDW_BROADCAST_DEV_NUM) { 327 cmd_id = SWR_BROADCAST_CMD_ID; 328 val = swrm_get_packed_reg_val(&cmd_id, cmd_data, 329 dev_addr, reg_addr); 330 } else { 331 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, 332 dev_addr, reg_addr); 333 } 334 335 if (swrm_wait_for_wr_fifo_avail(swrm)) 336 return SDW_CMD_FAIL_OTHER; 337 338 /* Its assumed that write is okay as we do not get any status back */ 339 swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val); 340 341 /* version 1.3 or less */ 342 if (swrm->version <= 0x01030000) 343 usleep_range(150, 155); 344 345 if (cmd_id == SWR_BROADCAST_CMD_ID) { 346 /* 347 * sleep for 10ms for MSM soundwire variant to allow broadcast 348 * command to complete. 349 */ 350 ret = wait_for_completion_timeout(&swrm->broadcast, 351 msecs_to_jiffies(TIMEOUT_MS)); 352 if (!ret) 353 ret = SDW_CMD_IGNORED; 354 else 355 ret = SDW_CMD_OK; 356 357 } else { 358 ret = SDW_CMD_OK; 359 } 360 return ret; 361 } 362 363 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm, 364 u8 dev_addr, u16 reg_addr, 365 u32 len, u8 *rval) 366 { 367 u32 cmd_data, cmd_id, val, retry_attempt = 0; 368 369 val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); 370 371 /* wait for FIFO RD to complete to avoid overflow */ 372 usleep_range(100, 105); 373 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); 374 /* wait for FIFO RD CMD complete to avoid overflow */ 375 usleep_range(250, 255); 376 377 if (swrm_wait_for_rd_fifo_avail(swrm)) 378 return SDW_CMD_FAIL_OTHER; 379 380 do { 381 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); 382 rval[0] = cmd_data & 0xFF; 383 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data); 384 385 if (cmd_id != swrm->rcmd_id) { 386 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { 387 /* wait 500 us before retry on fifo read failure */ 388 usleep_range(500, 505); 389 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 390 SWRM_CMD_FIFO_FLUSH); 391 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); 392 } 393 retry_attempt++; 394 } else { 395 return SDW_CMD_OK; 396 } 397 398 } while (retry_attempt < MAX_FIFO_RD_RETRY); 399 400 dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ 401 dev_num: 0x%x, cmd_data: 0x%x\n", 402 reg_addr, swrm->rcmd_id, dev_addr, cmd_data); 403 404 return SDW_CMD_IGNORED; 405 } 406 407 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl) 408 { 409 u32 val, status; 410 int dev_num; 411 412 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 413 414 for (dev_num = 0; dev_num < SDW_MAX_DEVICES; dev_num++) { 415 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ)); 416 417 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) { 418 ctrl->status[dev_num] = status; 419 return dev_num; 420 } 421 } 422 423 return -EINVAL; 424 } 425 426 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl) 427 { 428 u32 val; 429 int i; 430 431 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); 432 ctrl->slave_status = val; 433 434 for (i = 0; i < SDW_MAX_DEVICES; i++) { 435 u32 s; 436 437 s = (val >> (i * 2)); 438 s &= SWRM_MCP_SLV_STATUS_MASK; 439 ctrl->status[i] = s; 440 } 441 } 442 443 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus, 444 struct sdw_slave *slave, int devnum) 445 { 446 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 447 u32 status; 448 449 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); 450 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ)); 451 status &= SWRM_MCP_SLV_STATUS_MASK; 452 453 if (status == SDW_SLAVE_ATTACHED) { 454 if (slave) 455 slave->dev_num = devnum; 456 mutex_lock(&bus->bus_lock); 457 set_bit(devnum, bus->assigned); 458 mutex_unlock(&bus->bus_lock); 459 } 460 } 461 462 static int qcom_swrm_enumerate(struct sdw_bus *bus) 463 { 464 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 465 struct sdw_slave *slave, *_s; 466 struct sdw_slave_id id; 467 u32 val1, val2; 468 bool found; 469 u64 addr; 470 int i; 471 char *buf1 = (char *)&val1, *buf2 = (char *)&val2; 472 473 for (i = 1; i <= SDW_MAX_DEVICES; i++) { 474 /*SCP_Devid5 - Devid 4*/ 475 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); 476 477 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ 478 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); 479 480 if (!val1 && !val2) 481 break; 482 483 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) | 484 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) | 485 ((u64)buf1[0] << 40); 486 487 sdw_extract_slave_id(bus, addr, &id); 488 found = false; 489 /* Now compare with entries */ 490 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { 491 if (sdw_compare_devid(slave, id) == 0) { 492 qcom_swrm_set_slave_dev_num(bus, slave, i); 493 found = true; 494 break; 495 } 496 } 497 498 if (!found) { 499 qcom_swrm_set_slave_dev_num(bus, NULL, i); 500 sdw_slave_add(bus, &id, NULL); 501 } 502 } 503 504 complete(&ctrl->enumeration); 505 return 0; 506 } 507 508 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id) 509 { 510 struct qcom_swrm_ctrl *swrm = dev_id; 511 int ret; 512 513 ret = pm_runtime_resume_and_get(swrm->dev); 514 if (ret < 0 && ret != -EACCES) { 515 dev_err_ratelimited(swrm->dev, 516 "pm_runtime_resume_and_get failed in %s, ret %d\n", 517 __func__, ret); 518 return ret; 519 } 520 521 if (swrm->wake_irq > 0) { 522 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) 523 disable_irq_nosync(swrm->wake_irq); 524 } 525 526 pm_runtime_mark_last_busy(swrm->dev); 527 pm_runtime_put_autosuspend(swrm->dev); 528 529 return IRQ_HANDLED; 530 } 531 532 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id) 533 { 534 struct qcom_swrm_ctrl *swrm = dev_id; 535 u32 value, intr_sts, intr_sts_masked, slave_status; 536 u32 i; 537 int devnum; 538 int ret = IRQ_HANDLED; 539 clk_prepare_enable(swrm->hclk); 540 541 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); 542 intr_sts_masked = intr_sts & swrm->intr_mask; 543 544 do { 545 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) { 546 value = intr_sts_masked & BIT(i); 547 if (!value) 548 continue; 549 550 switch (value) { 551 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ: 552 devnum = qcom_swrm_get_alert_slave_dev_num(swrm); 553 if (devnum < 0) { 554 dev_err_ratelimited(swrm->dev, 555 "no slave alert found.spurious interrupt\n"); 556 } else { 557 sdw_handle_slave_status(&swrm->bus, swrm->status); 558 } 559 560 break; 561 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED: 562 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS: 563 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n", 564 __func__); 565 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); 566 if (swrm->slave_status == slave_status) { 567 dev_err(swrm->dev, "Slave status not changed %x\n", 568 slave_status); 569 } else { 570 qcom_swrm_get_device_status(swrm); 571 qcom_swrm_enumerate(&swrm->bus); 572 sdw_handle_slave_status(&swrm->bus, swrm->status); 573 } 574 break; 575 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET: 576 dev_err_ratelimited(swrm->dev, 577 "%s: SWR bus clsh detected\n", 578 __func__); 579 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 580 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 581 break; 582 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW: 583 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 584 dev_err_ratelimited(swrm->dev, 585 "%s: SWR read FIFO overflow fifo status 0x%x\n", 586 __func__, value); 587 break; 588 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW: 589 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 590 dev_err_ratelimited(swrm->dev, 591 "%s: SWR read FIFO underflow fifo status 0x%x\n", 592 __func__, value); 593 break; 594 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW: 595 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 596 dev_err(swrm->dev, 597 "%s: SWR write FIFO overflow fifo status %x\n", 598 __func__, value); 599 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); 600 break; 601 case SWRM_INTERRUPT_STATUS_CMD_ERROR: 602 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); 603 dev_err_ratelimited(swrm->dev, 604 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n", 605 __func__, value); 606 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); 607 break; 608 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION: 609 dev_err_ratelimited(swrm->dev, 610 "%s: SWR Port collision detected\n", 611 __func__); 612 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; 613 swrm->reg_write(swrm, 614 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 615 break; 616 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: 617 dev_err_ratelimited(swrm->dev, 618 "%s: SWR read enable valid mismatch\n", 619 __func__); 620 swrm->intr_mask &= 621 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; 622 swrm->reg_write(swrm, 623 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); 624 break; 625 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: 626 complete(&swrm->broadcast); 627 break; 628 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2: 629 break; 630 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: 631 break; 632 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: 633 break; 634 default: 635 dev_err_ratelimited(swrm->dev, 636 "%s: SWR unknown interrupt value: %d\n", 637 __func__, value); 638 ret = IRQ_NONE; 639 break; 640 } 641 } 642 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); 643 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); 644 intr_sts_masked = intr_sts & swrm->intr_mask; 645 } while (intr_sts_masked); 646 647 clk_disable_unprepare(swrm->hclk); 648 return ret; 649 } 650 651 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) 652 { 653 u32 val; 654 655 /* Clear Rows and Cols */ 656 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); 657 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); 658 659 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); 660 661 /* Enable Auto enumeration */ 662 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); 663 664 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; 665 /* Mask soundwire interrupts */ 666 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, 667 SWRM_INTERRUPT_STATUS_RMSK); 668 669 /* Configure No pings */ 670 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); 671 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK); 672 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); 673 674 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 675 /* Configure number of retries of a read/write cmd */ 676 if (ctrl->version > 0x01050001) { 677 /* Only for versions >= 1.5.1 */ 678 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 679 SWRM_RD_WR_CMD_RETRIES | 680 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE); 681 } else { 682 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, 683 SWRM_RD_WR_CMD_RETRIES); 684 } 685 686 /* Set IRQ to PULSE */ 687 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, 688 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK | 689 SWRM_COMP_CFG_ENABLE_MSK); 690 691 /* enable CPU IRQs */ 692 if (ctrl->mmio) { 693 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, 694 SWRM_INTERRUPT_STATUS_RMSK); 695 } 696 ctrl->slave_status = 0; 697 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 698 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); 699 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); 700 701 return 0; 702 } 703 704 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus, 705 struct sdw_msg *msg) 706 { 707 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 708 int ret, i, len; 709 710 if (msg->flags == SDW_MSG_FLAG_READ) { 711 for (i = 0; i < msg->len;) { 712 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) 713 len = msg->len - i; 714 else 715 len = QCOM_SWRM_MAX_RD_LEN; 716 717 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, 718 msg->addr + i, len, 719 &msg->buf[i]); 720 if (ret) 721 return ret; 722 723 i = i + len; 724 } 725 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { 726 for (i = 0; i < msg->len; i++) { 727 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], 728 msg->dev_num, 729 msg->addr + i); 730 if (ret) 731 return SDW_CMD_IGNORED; 732 } 733 } 734 735 return SDW_CMD_OK; 736 } 737 738 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus) 739 { 740 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); 741 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 742 u32 val; 743 744 ctrl->reg_read(ctrl, reg, &val); 745 746 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); 747 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); 748 749 return ctrl->reg_write(ctrl, reg, val); 750 } 751 752 static int qcom_swrm_port_params(struct sdw_bus *bus, 753 struct sdw_port_params *p_params, 754 unsigned int bank) 755 { 756 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 757 758 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), 759 p_params->bps - 1); 760 761 } 762 763 static int qcom_swrm_transport_params(struct sdw_bus *bus, 764 struct sdw_transport_params *params, 765 enum sdw_reg_bank bank) 766 { 767 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 768 struct qcom_swrm_port_config *pcfg; 769 u32 value; 770 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); 771 int ret; 772 773 pcfg = &ctrl->pconfig[params->port_num]; 774 775 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; 776 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; 777 value |= pcfg->si; 778 779 ret = ctrl->reg_write(ctrl, reg, value); 780 if (ret) 781 goto err; 782 783 if (pcfg->lane_control != SWR_INVALID_PARAM) { 784 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); 785 value = pcfg->lane_control; 786 ret = ctrl->reg_write(ctrl, reg, value); 787 if (ret) 788 goto err; 789 } 790 791 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { 792 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); 793 value = pcfg->blk_group_count; 794 ret = ctrl->reg_write(ctrl, reg, value); 795 if (ret) 796 goto err; 797 } 798 799 if (pcfg->hstart != SWR_INVALID_PARAM 800 && pcfg->hstop != SWR_INVALID_PARAM) { 801 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 802 value = (pcfg->hstop << 4) | pcfg->hstart; 803 ret = ctrl->reg_write(ctrl, reg, value); 804 } else { 805 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); 806 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL; 807 ret = ctrl->reg_write(ctrl, reg, value); 808 } 809 810 if (ret) 811 goto err; 812 813 if (pcfg->bp_mode != SWR_INVALID_PARAM) { 814 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); 815 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); 816 } 817 818 err: 819 return ret; 820 } 821 822 static int qcom_swrm_port_enable(struct sdw_bus *bus, 823 struct sdw_enable_ch *enable_ch, 824 unsigned int bank) 825 { 826 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); 827 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 828 u32 val; 829 830 ctrl->reg_read(ctrl, reg, &val); 831 832 if (enable_ch->enable) 833 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 834 else 835 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); 836 837 return ctrl->reg_write(ctrl, reg, val); 838 } 839 840 static const struct sdw_master_port_ops qcom_swrm_port_ops = { 841 .dpn_set_port_params = qcom_swrm_port_params, 842 .dpn_set_port_transport_params = qcom_swrm_transport_params, 843 .dpn_port_enable_ch = qcom_swrm_port_enable, 844 }; 845 846 static const struct sdw_master_ops qcom_swrm_ops = { 847 .xfer_msg = qcom_swrm_xfer_msg, 848 .pre_bank_switch = qcom_swrm_pre_bank_switch, 849 }; 850 851 static int qcom_swrm_compute_params(struct sdw_bus *bus) 852 { 853 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus); 854 struct sdw_master_runtime *m_rt; 855 struct sdw_slave_runtime *s_rt; 856 struct sdw_port_runtime *p_rt; 857 struct qcom_swrm_port_config *pcfg; 858 struct sdw_slave *slave; 859 unsigned int m_port; 860 int i = 1; 861 862 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { 863 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { 864 pcfg = &ctrl->pconfig[p_rt->num]; 865 p_rt->transport_params.port_num = p_rt->num; 866 if (pcfg->word_length != SWR_INVALID_PARAM) { 867 sdw_fill_port_params(&p_rt->port_params, 868 p_rt->num, pcfg->word_length + 1, 869 SDW_PORT_FLOW_MODE_ISOCH, 870 SDW_PORT_DATA_MODE_NORMAL); 871 } 872 873 } 874 875 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 876 slave = s_rt->slave; 877 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 878 m_port = slave->m_port_map[p_rt->num]; 879 /* port config starts at offset 0 so -1 from actual port number */ 880 if (m_port) 881 pcfg = &ctrl->pconfig[m_port]; 882 else 883 pcfg = &ctrl->pconfig[i]; 884 p_rt->transport_params.port_num = p_rt->num; 885 p_rt->transport_params.sample_interval = 886 pcfg->si + 1; 887 p_rt->transport_params.offset1 = pcfg->off1; 888 p_rt->transport_params.offset2 = pcfg->off2; 889 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; 890 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; 891 892 p_rt->transport_params.hstart = pcfg->hstart; 893 p_rt->transport_params.hstop = pcfg->hstop; 894 p_rt->transport_params.lane_ctrl = pcfg->lane_control; 895 if (pcfg->word_length != SWR_INVALID_PARAM) { 896 sdw_fill_port_params(&p_rt->port_params, 897 p_rt->num, 898 pcfg->word_length + 1, 899 SDW_PORT_FLOW_MODE_ISOCH, 900 SDW_PORT_DATA_MODE_NORMAL); 901 } 902 i++; 903 } 904 } 905 } 906 907 return 0; 908 } 909 910 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = { 911 DEFAULT_CLK_FREQ, 912 }; 913 914 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl, 915 struct sdw_stream_runtime *stream) 916 { 917 struct sdw_master_runtime *m_rt; 918 struct sdw_port_runtime *p_rt; 919 unsigned long *port_mask; 920 921 mutex_lock(&ctrl->port_lock); 922 923 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 924 if (m_rt->direction == SDW_DATA_DIR_RX) 925 port_mask = &ctrl->dout_port_mask; 926 else 927 port_mask = &ctrl->din_port_mask; 928 929 list_for_each_entry(p_rt, &m_rt->port_list, port_node) 930 clear_bit(p_rt->num, port_mask); 931 } 932 933 mutex_unlock(&ctrl->port_lock); 934 } 935 936 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl, 937 struct sdw_stream_runtime *stream, 938 struct snd_pcm_hw_params *params, 939 int direction) 940 { 941 struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS]; 942 struct sdw_stream_config sconfig; 943 struct sdw_master_runtime *m_rt; 944 struct sdw_slave_runtime *s_rt; 945 struct sdw_port_runtime *p_rt; 946 struct sdw_slave *slave; 947 unsigned long *port_mask; 948 int i, maxport, pn, nports = 0, ret = 0; 949 unsigned int m_port; 950 951 mutex_lock(&ctrl->port_lock); 952 list_for_each_entry(m_rt, &stream->master_list, stream_node) { 953 if (m_rt->direction == SDW_DATA_DIR_RX) { 954 maxport = ctrl->num_dout_ports; 955 port_mask = &ctrl->dout_port_mask; 956 } else { 957 maxport = ctrl->num_din_ports; 958 port_mask = &ctrl->din_port_mask; 959 } 960 961 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { 962 slave = s_rt->slave; 963 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { 964 m_port = slave->m_port_map[p_rt->num]; 965 /* Port numbers start from 1 - 14*/ 966 if (m_port) 967 pn = m_port; 968 else 969 pn = find_first_zero_bit(port_mask, maxport); 970 971 if (pn > maxport) { 972 dev_err(ctrl->dev, "All ports busy\n"); 973 ret = -EBUSY; 974 goto err; 975 } 976 set_bit(pn, port_mask); 977 pconfig[nports].num = pn; 978 pconfig[nports].ch_mask = p_rt->ch_mask; 979 nports++; 980 } 981 } 982 } 983 984 if (direction == SNDRV_PCM_STREAM_CAPTURE) 985 sconfig.direction = SDW_DATA_DIR_TX; 986 else 987 sconfig.direction = SDW_DATA_DIR_RX; 988 989 /* hw parameters wil be ignored as we only support PDM */ 990 sconfig.ch_count = 1; 991 sconfig.frame_rate = params_rate(params); 992 sconfig.type = stream->type; 993 sconfig.bps = 1; 994 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, 995 nports, stream); 996 err: 997 if (ret) { 998 for (i = 0; i < nports; i++) 999 clear_bit(pconfig[i].num, port_mask); 1000 } 1001 1002 mutex_unlock(&ctrl->port_lock); 1003 1004 return ret; 1005 } 1006 1007 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream, 1008 struct snd_pcm_hw_params *params, 1009 struct snd_soc_dai *dai) 1010 { 1011 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1012 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1013 int ret; 1014 1015 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params, 1016 substream->stream); 1017 if (ret) 1018 qcom_swrm_stream_free_ports(ctrl, sruntime); 1019 1020 return ret; 1021 } 1022 1023 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream, 1024 struct snd_soc_dai *dai) 1025 { 1026 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1027 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; 1028 1029 qcom_swrm_stream_free_ports(ctrl, sruntime); 1030 sdw_stream_remove_master(&ctrl->bus, sruntime); 1031 1032 return 0; 1033 } 1034 1035 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai, 1036 void *stream, int direction) 1037 { 1038 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1039 1040 ctrl->sruntime[dai->id] = stream; 1041 1042 return 0; 1043 } 1044 1045 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction) 1046 { 1047 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1048 1049 return ctrl->sruntime[dai->id]; 1050 } 1051 1052 static int qcom_swrm_startup(struct snd_pcm_substream *substream, 1053 struct snd_soc_dai *dai) 1054 { 1055 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1056 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1057 struct sdw_stream_runtime *sruntime; 1058 struct snd_soc_dai *codec_dai; 1059 int ret, i; 1060 1061 ret = pm_runtime_resume_and_get(ctrl->dev); 1062 if (ret < 0 && ret != -EACCES) { 1063 dev_err_ratelimited(ctrl->dev, 1064 "pm_runtime_resume_and_get failed in %s, ret %d\n", 1065 __func__, ret); 1066 return ret; 1067 } 1068 1069 sruntime = sdw_alloc_stream(dai->name); 1070 if (!sruntime) 1071 return -ENOMEM; 1072 1073 ctrl->sruntime[dai->id] = sruntime; 1074 1075 for_each_rtd_codec_dais(rtd, i, codec_dai) { 1076 ret = snd_soc_dai_set_stream(codec_dai, sruntime, 1077 substream->stream); 1078 if (ret < 0 && ret != -ENOTSUPP) { 1079 dev_err(dai->dev, "Failed to set sdw stream on %s\n", 1080 codec_dai->name); 1081 sdw_release_stream(sruntime); 1082 return ret; 1083 } 1084 } 1085 1086 return 0; 1087 } 1088 1089 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream, 1090 struct snd_soc_dai *dai) 1091 { 1092 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); 1093 1094 sdw_release_stream(ctrl->sruntime[dai->id]); 1095 ctrl->sruntime[dai->id] = NULL; 1096 pm_runtime_mark_last_busy(ctrl->dev); 1097 pm_runtime_put_autosuspend(ctrl->dev); 1098 1099 } 1100 1101 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = { 1102 .hw_params = qcom_swrm_hw_params, 1103 .hw_free = qcom_swrm_hw_free, 1104 .startup = qcom_swrm_startup, 1105 .shutdown = qcom_swrm_shutdown, 1106 .set_stream = qcom_swrm_set_sdw_stream, 1107 .get_stream = qcom_swrm_get_sdw_stream, 1108 }; 1109 1110 static const struct snd_soc_component_driver qcom_swrm_dai_component = { 1111 .name = "soundwire", 1112 }; 1113 1114 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl) 1115 { 1116 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; 1117 struct snd_soc_dai_driver *dais; 1118 struct snd_soc_pcm_stream *stream; 1119 struct device *dev = ctrl->dev; 1120 int i; 1121 1122 /* PDM dais are only tested for now */ 1123 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL); 1124 if (!dais) 1125 return -ENOMEM; 1126 1127 for (i = 0; i < num_dais; i++) { 1128 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i); 1129 if (!dais[i].name) 1130 return -ENOMEM; 1131 1132 if (i < ctrl->num_dout_ports) 1133 stream = &dais[i].playback; 1134 else 1135 stream = &dais[i].capture; 1136 1137 stream->channels_min = 1; 1138 stream->channels_max = 1; 1139 stream->rates = SNDRV_PCM_RATE_48000; 1140 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; 1141 1142 dais[i].ops = &qcom_swrm_pdm_dai_ops; 1143 dais[i].id = i; 1144 } 1145 1146 return devm_snd_soc_register_component(ctrl->dev, 1147 &qcom_swrm_dai_component, 1148 dais, num_dais); 1149 } 1150 1151 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl) 1152 { 1153 struct device_node *np = ctrl->dev->of_node; 1154 u8 off1[QCOM_SDW_MAX_PORTS]; 1155 u8 off2[QCOM_SDW_MAX_PORTS]; 1156 u8 si[QCOM_SDW_MAX_PORTS]; 1157 u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, }; 1158 u8 hstart[QCOM_SDW_MAX_PORTS]; 1159 u8 hstop[QCOM_SDW_MAX_PORTS]; 1160 u8 word_length[QCOM_SDW_MAX_PORTS]; 1161 u8 blk_group_count[QCOM_SDW_MAX_PORTS]; 1162 u8 lane_control[QCOM_SDW_MAX_PORTS]; 1163 int i, ret, nports, val; 1164 1165 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); 1166 1167 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); 1168 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); 1169 1170 ret = of_property_read_u32(np, "qcom,din-ports", &val); 1171 if (ret) 1172 return ret; 1173 1174 if (val > ctrl->num_din_ports) 1175 return -EINVAL; 1176 1177 ctrl->num_din_ports = val; 1178 1179 ret = of_property_read_u32(np, "qcom,dout-ports", &val); 1180 if (ret) 1181 return ret; 1182 1183 if (val > ctrl->num_dout_ports) 1184 return -EINVAL; 1185 1186 ctrl->num_dout_ports = val; 1187 1188 nports = ctrl->num_dout_ports + ctrl->num_din_ports; 1189 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ 1190 set_bit(0, &ctrl->dout_port_mask); 1191 set_bit(0, &ctrl->din_port_mask); 1192 1193 ret = of_property_read_u8_array(np, "qcom,ports-offset1", 1194 off1, nports); 1195 if (ret) 1196 return ret; 1197 1198 ret = of_property_read_u8_array(np, "qcom,ports-offset2", 1199 off2, nports); 1200 if (ret) 1201 return ret; 1202 1203 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", 1204 si, nports); 1205 if (ret) 1206 return ret; 1207 1208 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", 1209 bp_mode, nports); 1210 if (ret) { 1211 if (ctrl->version <= 0x01030000) 1212 memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1213 else 1214 return ret; 1215 } 1216 1217 memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1218 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); 1219 1220 memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1221 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); 1222 1223 memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1224 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); 1225 1226 memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1227 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); 1228 1229 memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS); 1230 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); 1231 1232 for (i = 0; i < nports; i++) { 1233 /* Valid port number range is from 1-14 */ 1234 ctrl->pconfig[i + 1].si = si[i]; 1235 ctrl->pconfig[i + 1].off1 = off1[i]; 1236 ctrl->pconfig[i + 1].off2 = off2[i]; 1237 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; 1238 ctrl->pconfig[i + 1].hstart = hstart[i]; 1239 ctrl->pconfig[i + 1].hstop = hstop[i]; 1240 ctrl->pconfig[i + 1].word_length = word_length[i]; 1241 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; 1242 ctrl->pconfig[i + 1].lane_control = lane_control[i]; 1243 } 1244 1245 return 0; 1246 } 1247 1248 #ifdef CONFIG_DEBUG_FS 1249 static int swrm_reg_show(struct seq_file *s_file, void *data) 1250 { 1251 struct qcom_swrm_ctrl *swrm = s_file->private; 1252 int reg, reg_val, ret; 1253 1254 ret = pm_runtime_resume_and_get(swrm->dev); 1255 if (ret < 0 && ret != -EACCES) { 1256 dev_err_ratelimited(swrm->dev, 1257 "pm_runtime_resume_and_get failed in %s, ret %d\n", 1258 __func__, ret); 1259 return ret; 1260 } 1261 1262 for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) { 1263 swrm->reg_read(swrm, reg, ®_val); 1264 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val); 1265 } 1266 pm_runtime_mark_last_busy(swrm->dev); 1267 pm_runtime_put_autosuspend(swrm->dev); 1268 1269 1270 return 0; 1271 } 1272 DEFINE_SHOW_ATTRIBUTE(swrm_reg); 1273 #endif 1274 1275 static int qcom_swrm_probe(struct platform_device *pdev) 1276 { 1277 struct device *dev = &pdev->dev; 1278 struct sdw_master_prop *prop; 1279 struct sdw_bus_params *params; 1280 struct qcom_swrm_ctrl *ctrl; 1281 const struct qcom_swrm_data *data; 1282 int ret; 1283 u32 val; 1284 1285 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 1286 if (!ctrl) 1287 return -ENOMEM; 1288 1289 data = of_device_get_match_data(dev); 1290 ctrl->rows_index = sdw_find_row_index(data->default_rows); 1291 ctrl->cols_index = sdw_find_col_index(data->default_cols); 1292 #if IS_REACHABLE(CONFIG_SLIMBUS) 1293 if (dev->parent->bus == &slimbus_bus) { 1294 #else 1295 if (false) { 1296 #endif 1297 ctrl->reg_read = qcom_swrm_ahb_reg_read; 1298 ctrl->reg_write = qcom_swrm_ahb_reg_write; 1299 ctrl->regmap = dev_get_regmap(dev->parent, NULL); 1300 if (!ctrl->regmap) 1301 return -EINVAL; 1302 } else { 1303 ctrl->reg_read = qcom_swrm_cpu_reg_read; 1304 ctrl->reg_write = qcom_swrm_cpu_reg_write; 1305 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0); 1306 if (IS_ERR(ctrl->mmio)) 1307 return PTR_ERR(ctrl->mmio); 1308 } 1309 1310 ctrl->irq = of_irq_get(dev->of_node, 0); 1311 if (ctrl->irq < 0) { 1312 ret = ctrl->irq; 1313 goto err_init; 1314 } 1315 1316 ctrl->hclk = devm_clk_get(dev, "iface"); 1317 if (IS_ERR(ctrl->hclk)) { 1318 ret = PTR_ERR(ctrl->hclk); 1319 goto err_init; 1320 } 1321 1322 clk_prepare_enable(ctrl->hclk); 1323 1324 ctrl->dev = dev; 1325 dev_set_drvdata(&pdev->dev, ctrl); 1326 mutex_init(&ctrl->port_lock); 1327 init_completion(&ctrl->broadcast); 1328 init_completion(&ctrl->enumeration); 1329 1330 ctrl->bus.ops = &qcom_swrm_ops; 1331 ctrl->bus.port_ops = &qcom_swrm_port_ops; 1332 ctrl->bus.compute_params = &qcom_swrm_compute_params; 1333 ctrl->bus.clk_stop_timeout = 300; 1334 1335 ret = qcom_swrm_get_port_config(ctrl); 1336 if (ret) 1337 goto err_clk; 1338 1339 params = &ctrl->bus.params; 1340 params->max_dr_freq = DEFAULT_CLK_FREQ; 1341 params->curr_dr_freq = DEFAULT_CLK_FREQ; 1342 params->col = data->default_cols; 1343 params->row = data->default_rows; 1344 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val); 1345 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK; 1346 params->next_bank = !params->curr_bank; 1347 1348 prop = &ctrl->bus.prop; 1349 prop->max_clk_freq = DEFAULT_CLK_FREQ; 1350 prop->num_clk_gears = 0; 1351 prop->num_clk_freq = MAX_FREQ_NUM; 1352 prop->clk_freq = &qcom_swrm_freq_tbl[0]; 1353 prop->default_col = data->default_cols; 1354 prop->default_row = data->default_rows; 1355 1356 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version); 1357 1358 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL, 1359 qcom_swrm_irq_handler, 1360 IRQF_TRIGGER_RISING | 1361 IRQF_ONESHOT, 1362 "soundwire", ctrl); 1363 if (ret) { 1364 dev_err(dev, "Failed to request soundwire irq\n"); 1365 goto err_clk; 1366 } 1367 1368 ctrl->wake_irq = of_irq_get(dev->of_node, 1); 1369 if (ctrl->wake_irq > 0) { 1370 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL, 1371 qcom_swrm_wake_irq_handler, 1372 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1373 "swr_wake_irq", ctrl); 1374 if (ret) { 1375 dev_err(dev, "Failed to request soundwire wake irq\n"); 1376 goto err_init; 1377 } 1378 } 1379 1380 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode); 1381 if (ret) { 1382 dev_err(dev, "Failed to register Soundwire controller (%d)\n", 1383 ret); 1384 goto err_clk; 1385 } 1386 1387 qcom_swrm_init(ctrl); 1388 wait_for_completion_timeout(&ctrl->enumeration, 1389 msecs_to_jiffies(TIMEOUT_MS)); 1390 ret = qcom_swrm_register_dais(ctrl); 1391 if (ret) 1392 goto err_master_add; 1393 1394 dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n", 1395 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff, 1396 ctrl->version & 0xffff); 1397 1398 pm_runtime_set_autosuspend_delay(dev, 3000); 1399 pm_runtime_use_autosuspend(dev); 1400 pm_runtime_mark_last_busy(dev); 1401 pm_runtime_set_active(dev); 1402 pm_runtime_enable(dev); 1403 1404 /* Clk stop is not supported on WSA Soundwire masters */ 1405 if (ctrl->version <= 0x01030000) { 1406 ctrl->clock_stop_not_supported = true; 1407 } else { 1408 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val); 1409 if (val == MASTER_ID_WSA) 1410 ctrl->clock_stop_not_supported = true; 1411 } 1412 1413 #ifdef CONFIG_DEBUG_FS 1414 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs); 1415 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl, 1416 &swrm_reg_fops); 1417 #endif 1418 1419 return 0; 1420 1421 err_master_add: 1422 sdw_bus_master_delete(&ctrl->bus); 1423 err_clk: 1424 clk_disable_unprepare(ctrl->hclk); 1425 err_init: 1426 return ret; 1427 } 1428 1429 static int qcom_swrm_remove(struct platform_device *pdev) 1430 { 1431 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev); 1432 1433 sdw_bus_master_delete(&ctrl->bus); 1434 clk_disable_unprepare(ctrl->hclk); 1435 1436 return 0; 1437 } 1438 1439 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm) 1440 { 1441 int retry = SWRM_LINK_STATUS_RETRY_CNT; 1442 int comp_sts; 1443 1444 do { 1445 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts); 1446 1447 if (comp_sts & SWRM_FRM_GEN_ENABLED) 1448 return true; 1449 1450 usleep_range(500, 510); 1451 } while (retry--); 1452 1453 dev_err(swrm->dev, "%s: link status not %s\n", __func__, 1454 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected"); 1455 1456 return false; 1457 } 1458 1459 static int __maybe_unused swrm_runtime_resume(struct device *dev) 1460 { 1461 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1462 int ret; 1463 1464 if (ctrl->wake_irq > 0) { 1465 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1466 disable_irq_nosync(ctrl->wake_irq); 1467 } 1468 1469 clk_prepare_enable(ctrl->hclk); 1470 1471 if (ctrl->clock_stop_not_supported) { 1472 reinit_completion(&ctrl->enumeration); 1473 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01); 1474 usleep_range(100, 105); 1475 1476 qcom_swrm_init(ctrl); 1477 1478 usleep_range(100, 105); 1479 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1480 dev_err(ctrl->dev, "link failed to connect\n"); 1481 1482 /* wait for hw enumeration to complete */ 1483 wait_for_completion_timeout(&ctrl->enumeration, 1484 msecs_to_jiffies(TIMEOUT_MS)); 1485 qcom_swrm_get_device_status(ctrl); 1486 sdw_handle_slave_status(&ctrl->bus, ctrl->status); 1487 } else { 1488 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); 1489 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, 1490 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET); 1491 1492 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1493 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); 1494 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); 1495 1496 usleep_range(100, 105); 1497 if (!swrm_wait_for_frame_gen_enabled(ctrl)) 1498 dev_err(ctrl->dev, "link failed to connect\n"); 1499 1500 ret = sdw_bus_exit_clk_stop(&ctrl->bus); 1501 if (ret < 0) 1502 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret); 1503 } 1504 1505 return 0; 1506 } 1507 1508 static int __maybe_unused swrm_runtime_suspend(struct device *dev) 1509 { 1510 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); 1511 int ret; 1512 1513 if (!ctrl->clock_stop_not_supported) { 1514 /* Mask bus clash interrupt */ 1515 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; 1516 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask); 1517 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask); 1518 /* Prepare slaves for clock stop */ 1519 ret = sdw_bus_prep_clk_stop(&ctrl->bus); 1520 if (ret < 0 && ret != -ENODATA) { 1521 dev_err(dev, "prepare clock stop failed %d", ret); 1522 return ret; 1523 } 1524 1525 ret = sdw_bus_clk_stop(&ctrl->bus); 1526 if (ret < 0 && ret != -ENODATA) { 1527 dev_err(dev, "bus clock stop failed %d", ret); 1528 return ret; 1529 } 1530 } 1531 1532 clk_disable_unprepare(ctrl->hclk); 1533 1534 usleep_range(300, 305); 1535 1536 if (ctrl->wake_irq > 0) { 1537 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) 1538 enable_irq(ctrl->wake_irq); 1539 } 1540 1541 return 0; 1542 } 1543 1544 static const struct dev_pm_ops swrm_dev_pm_ops = { 1545 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL) 1546 }; 1547 1548 static const struct of_device_id qcom_swrm_of_match[] = { 1549 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data }, 1550 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data }, 1551 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_5_data }, 1552 {/* sentinel */}, 1553 }; 1554 1555 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match); 1556 1557 static struct platform_driver qcom_swrm_driver = { 1558 .probe = &qcom_swrm_probe, 1559 .remove = &qcom_swrm_remove, 1560 .driver = { 1561 .name = "qcom-soundwire", 1562 .of_match_table = qcom_swrm_of_match, 1563 .pm = &swrm_dev_pm_ops, 1564 } 1565 }; 1566 module_platform_driver(qcom_swrm_driver); 1567 1568 MODULE_DESCRIPTION("Qualcomm soundwire driver"); 1569 MODULE_LICENSE("GPL v2"); 1570