1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* Copyright(c) 2015-17 Intel Corporation. */ 3 4 #ifndef __SDW_INTEL_LOCAL_H 5 #define __SDW_INTEL_LOCAL_H 6 7 struct hdac_bus; 8 9 /** 10 * struct sdw_intel_link_res - Soundwire Intel link resource structure, 11 * typically populated by the controller driver. 12 * @hw_ops: platform-specific ops 13 * @mmio_base: mmio base of SoundWire registers 14 * @registers: Link IO registers base 15 * @ip_offset: offset for MCP_IP registers 16 * @shim: Audio shim pointer 17 * @shim_vs: Audio vendor-specific shim pointer 18 * @alh: ALH (Audio Link Hub) pointer 19 * @irq: Interrupt line 20 * @ops: Shim callback ops 21 * @dev: device implementing hw_params and free callbacks 22 * @shim_lock: mutex to handle access to shared SHIM registers 23 * @shim_mask: global pointer to check SHIM register initialization 24 * @clock_stop_quirks: mask defining requested behavior on pm_suspend 25 * @link_mask: global mask needed for power-up/down sequences 26 * @cdns: Cadence master descriptor 27 * @list: used to walk-through all masters exposed by the same controller 28 * @hbus: hdac_bus pointer, needed for power management 29 */ 30 struct sdw_intel_link_res { 31 const struct sdw_intel_hw_ops *hw_ops; 32 33 void __iomem *mmio_base; /* not strictly needed, useful for debug */ 34 void __iomem *registers; 35 u32 ip_offset; 36 void __iomem *shim; 37 void __iomem *shim_vs; 38 void __iomem *alh; 39 int irq; 40 const struct sdw_intel_ops *ops; 41 struct device *dev; 42 struct mutex *shim_lock; /* protect shared registers */ 43 u32 *shim_mask; 44 u32 clock_stop_quirks; 45 u32 link_mask; 46 struct sdw_cdns *cdns; 47 struct list_head list; 48 struct hdac_bus *hbus; 49 }; 50 51 struct sdw_intel { 52 struct sdw_cdns cdns; 53 int instance; 54 struct sdw_intel_link_res *link_res; 55 bool startup_done; 56 #ifdef CONFIG_DEBUG_FS 57 struct dentry *debugfs; 58 #endif 59 }; 60 61 enum intel_pdi_type { 62 INTEL_PDI_IN = 0, 63 INTEL_PDI_OUT = 1, 64 INTEL_PDI_BD = 2, 65 }; 66 67 /* 68 * Read, write helpers for HW registers 69 */ 70 static inline int intel_readl(void __iomem *base, int offset) 71 { 72 return readl(base + offset); 73 } 74 75 static inline void intel_writel(void __iomem *base, int offset, int value) 76 { 77 writel(value, base + offset); 78 } 79 80 static inline u16 intel_readw(void __iomem *base, int offset) 81 { 82 return readw(base + offset); 83 } 84 85 static inline void intel_writew(void __iomem *base, int offset, u16 value) 86 { 87 writew(value, base + offset); 88 } 89 90 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) 91 92 #define INTEL_MASTER_RESET_ITERATIONS 10 93 94 #define SDW_INTEL_DELAYED_ENUMERATION_MS 100 95 96 #define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \ 97 (sdw)->link_res->hw_ops->cb) 98 #define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb) 99 100 #ifdef CONFIG_DEBUG_FS 101 void intel_ace2x_debugfs_init(struct sdw_intel *sdw); 102 void intel_ace2x_debugfs_exit(struct sdw_intel *sdw); 103 #else 104 static inline void intel_ace2x_debugfs_init(struct sdw_intel *sdw) {} 105 static inline void intel_ace2x_debugfs_exit(struct sdw_intel *sdw) {} 106 #endif 107 108 static inline void sdw_intel_debugfs_init(struct sdw_intel *sdw) 109 { 110 if (SDW_INTEL_CHECK_OPS(sdw, debugfs_init)) 111 SDW_INTEL_OPS(sdw, debugfs_init)(sdw); 112 } 113 114 static inline void sdw_intel_debugfs_exit(struct sdw_intel *sdw) 115 { 116 if (SDW_INTEL_CHECK_OPS(sdw, debugfs_exit)) 117 SDW_INTEL_OPS(sdw, debugfs_exit)(sdw); 118 } 119 120 static inline int sdw_intel_register_dai(struct sdw_intel *sdw) 121 { 122 if (SDW_INTEL_CHECK_OPS(sdw, register_dai)) 123 return SDW_INTEL_OPS(sdw, register_dai)(sdw); 124 return -ENOTSUPP; 125 } 126 127 static inline void sdw_intel_check_clock_stop(struct sdw_intel *sdw) 128 { 129 if (SDW_INTEL_CHECK_OPS(sdw, check_clock_stop)) 130 SDW_INTEL_OPS(sdw, check_clock_stop)(sdw); 131 } 132 133 static inline int sdw_intel_start_bus(struct sdw_intel *sdw) 134 { 135 if (SDW_INTEL_CHECK_OPS(sdw, start_bus)) 136 return SDW_INTEL_OPS(sdw, start_bus)(sdw); 137 return -ENOTSUPP; 138 } 139 140 static inline int sdw_intel_start_bus_after_reset(struct sdw_intel *sdw) 141 { 142 if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_reset)) 143 return SDW_INTEL_OPS(sdw, start_bus_after_reset)(sdw); 144 return -ENOTSUPP; 145 } 146 147 static inline int sdw_intel_start_bus_after_clock_stop(struct sdw_intel *sdw) 148 { 149 if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_clock_stop)) 150 return SDW_INTEL_OPS(sdw, start_bus_after_clock_stop)(sdw); 151 return -ENOTSUPP; 152 } 153 154 static inline int sdw_intel_stop_bus(struct sdw_intel *sdw, bool clock_stop) 155 { 156 if (SDW_INTEL_CHECK_OPS(sdw, stop_bus)) 157 return SDW_INTEL_OPS(sdw, stop_bus)(sdw, clock_stop); 158 return -ENOTSUPP; 159 } 160 161 static inline int sdw_intel_link_power_up(struct sdw_intel *sdw) 162 { 163 if (SDW_INTEL_CHECK_OPS(sdw, link_power_up)) 164 return SDW_INTEL_OPS(sdw, link_power_up)(sdw); 165 return -ENOTSUPP; 166 } 167 168 static inline int sdw_intel_link_power_down(struct sdw_intel *sdw) 169 { 170 if (SDW_INTEL_CHECK_OPS(sdw, link_power_down)) 171 return SDW_INTEL_OPS(sdw, link_power_down)(sdw); 172 return -ENOTSUPP; 173 } 174 175 static inline int sdw_intel_shim_check_wake(struct sdw_intel *sdw) 176 { 177 if (SDW_INTEL_CHECK_OPS(sdw, shim_check_wake)) 178 return SDW_INTEL_OPS(sdw, shim_check_wake)(sdw); 179 return -ENOTSUPP; 180 } 181 182 static inline void sdw_intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 183 { 184 if (SDW_INTEL_CHECK_OPS(sdw, shim_wake)) 185 SDW_INTEL_OPS(sdw, shim_wake)(sdw, wake_enable); 186 } 187 188 static inline void sdw_intel_sync_arm(struct sdw_intel *sdw) 189 { 190 if (SDW_INTEL_CHECK_OPS(sdw, sync_arm)) 191 SDW_INTEL_OPS(sdw, sync_arm)(sdw); 192 } 193 194 static inline int sdw_intel_sync_go_unlocked(struct sdw_intel *sdw) 195 { 196 if (SDW_INTEL_CHECK_OPS(sdw, sync_go_unlocked)) 197 return SDW_INTEL_OPS(sdw, sync_go_unlocked)(sdw); 198 return -ENOTSUPP; 199 } 200 201 static inline int sdw_intel_sync_go(struct sdw_intel *sdw) 202 { 203 if (SDW_INTEL_CHECK_OPS(sdw, sync_go)) 204 return SDW_INTEL_OPS(sdw, sync_go)(sdw); 205 return -ENOTSUPP; 206 } 207 208 static inline bool sdw_intel_sync_check_cmdsync_unlocked(struct sdw_intel *sdw) 209 { 210 if (SDW_INTEL_CHECK_OPS(sdw, sync_check_cmdsync_unlocked)) 211 return SDW_INTEL_OPS(sdw, sync_check_cmdsync_unlocked)(sdw); 212 return false; 213 } 214 215 /* common bus management */ 216 int intel_start_bus(struct sdw_intel *sdw); 217 int intel_start_bus_after_reset(struct sdw_intel *sdw); 218 void intel_check_clock_stop(struct sdw_intel *sdw); 219 int intel_start_bus_after_clock_stop(struct sdw_intel *sdw); 220 int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop); 221 222 /* common bank switch routines */ 223 int intel_pre_bank_switch(struct sdw_intel *sdw); 224 int intel_post_bank_switch(struct sdw_intel *sdw); 225 226 #endif /* __SDW_INTEL_LOCAL_H */ 227