123859465SPierre-Louis Bossart /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 223859465SPierre-Louis Bossart /* Copyright(c) 2015-17 Intel Corporation. */ 371bb8a1bSVinod Koul 471bb8a1bSVinod Koul #ifndef __SDW_INTEL_LOCAL_H 571bb8a1bSVinod Koul #define __SDW_INTEL_LOCAL_H 671bb8a1bSVinod Koul 771bb8a1bSVinod Koul /** 8f98f690fSPierre-Louis Bossart * struct sdw_intel_link_res - Soundwire Intel link resource structure, 9f98f690fSPierre-Louis Bossart * typically populated by the controller driver. 10b3ad31f3SPierre-Louis Bossart * @hw_ops: platform-specific ops 11f98f690fSPierre-Louis Bossart * @mmio_base: mmio base of SoundWire registers 1271bb8a1bSVinod Koul * @registers: Link IO registers base 1371bb8a1bSVinod Koul * @shim: Audio shim pointer 1471bb8a1bSVinod Koul * @alh: ALH (Audio Link Hub) pointer 1571bb8a1bSVinod Koul * @irq: Interrupt line 16c46302ecSVinod Koul * @ops: Shim callback ops 174b206d34SRander Wang * @dev: device implementing hw_params and free callbacks 184a17c441SPierre-Louis Bossart * @shim_lock: mutex to handle access to shared SHIM registers 194a17c441SPierre-Louis Bossart * @shim_mask: global pointer to check SHIM register initialization 20a320f41eSPierre-Louis Bossart * @clock_stop_quirks: mask defining requested behavior on pm_suspend 21de763fa8SPierre-Louis Bossart * @link_mask: global mask needed for power-up/down sequences 224a98a6b2SBard Liao * @cdns: Cadence master descriptor 234a98a6b2SBard Liao * @list: used to walk-through all masters exposed by the same controller 2471bb8a1bSVinod Koul */ 2571bb8a1bSVinod Koul struct sdw_intel_link_res { 26b3ad31f3SPierre-Louis Bossart const struct sdw_intel_hw_ops *hw_ops; 27b3ad31f3SPierre-Louis Bossart 28f98f690fSPierre-Louis Bossart void __iomem *mmio_base; /* not strictly needed, useful for debug */ 2971bb8a1bSVinod Koul void __iomem *registers; 3071bb8a1bSVinod Koul void __iomem *shim; 3171bb8a1bSVinod Koul void __iomem *alh; 3271bb8a1bSVinod Koul int irq; 33c46302ecSVinod Koul const struct sdw_intel_ops *ops; 344b206d34SRander Wang struct device *dev; 354a17c441SPierre-Louis Bossart struct mutex *shim_lock; /* protect shared registers */ 364a17c441SPierre-Louis Bossart u32 *shim_mask; 37a320f41eSPierre-Louis Bossart u32 clock_stop_quirks; 38de763fa8SPierre-Louis Bossart u32 link_mask; 394a98a6b2SBard Liao struct sdw_cdns *cdns; 404a98a6b2SBard Liao struct list_head list; 4171bb8a1bSVinod Koul }; 4271bb8a1bSVinod Koul 43b6109dd6SPierre-Louis Bossart struct sdw_intel { 44b6109dd6SPierre-Louis Bossart struct sdw_cdns cdns; 45b6109dd6SPierre-Louis Bossart int instance; 46b6109dd6SPierre-Louis Bossart struct sdw_intel_link_res *link_res; 47e4401abbSPierre-Louis Bossart bool startup_done; 48b6109dd6SPierre-Louis Bossart #ifdef CONFIG_DEBUG_FS 49b6109dd6SPierre-Louis Bossart struct dentry *debugfs; 50b6109dd6SPierre-Louis Bossart #endif 51b6109dd6SPierre-Louis Bossart }; 52b6109dd6SPierre-Louis Bossart 534dd50affSPierre-Louis Bossart enum intel_pdi_type { 544dd50affSPierre-Louis Bossart INTEL_PDI_IN = 0, 554dd50affSPierre-Louis Bossart INTEL_PDI_OUT = 1, 564dd50affSPierre-Louis Bossart INTEL_PDI_BD = 2, 574dd50affSPierre-Louis Bossart }; 584dd50affSPierre-Louis Bossart 594dd50affSPierre-Louis Bossart /* 604dd50affSPierre-Louis Bossart * Read, write helpers for HW registers 614dd50affSPierre-Louis Bossart */ 624dd50affSPierre-Louis Bossart static inline int intel_readl(void __iomem *base, int offset) 634dd50affSPierre-Louis Bossart { 644dd50affSPierre-Louis Bossart return readl(base + offset); 654dd50affSPierre-Louis Bossart } 664dd50affSPierre-Louis Bossart 674dd50affSPierre-Louis Bossart static inline void intel_writel(void __iomem *base, int offset, int value) 684dd50affSPierre-Louis Bossart { 694dd50affSPierre-Louis Bossart writel(value, base + offset); 704dd50affSPierre-Louis Bossart } 714dd50affSPierre-Louis Bossart 724dd50affSPierre-Louis Bossart static inline u16 intel_readw(void __iomem *base, int offset) 734dd50affSPierre-Louis Bossart { 744dd50affSPierre-Louis Bossart return readw(base + offset); 754dd50affSPierre-Louis Bossart } 764dd50affSPierre-Louis Bossart 774dd50affSPierre-Louis Bossart static inline void intel_writew(void __iomem *base, int offset, u16 value) 784dd50affSPierre-Louis Bossart { 794dd50affSPierre-Louis Bossart writew(value, base + offset); 804dd50affSPierre-Louis Bossart } 814dd50affSPierre-Louis Bossart 827cbf00bdSPierre-Louis Bossart #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) 8329a269c6SPierre-Louis Bossart 847cbf00bdSPierre-Louis Bossart #define INTEL_MASTER_RESET_ITERATIONS 10 856d2c6669SPierre-Louis Bossart 86fb2dc6a0SPierre-Louis Bossart #define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \ 87fb2dc6a0SPierre-Louis Bossart (sdw)->link_res->hw_ops->cb) 88fb2dc6a0SPierre-Louis Bossart #define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb) 89fb2dc6a0SPierre-Louis Bossart 90fb2dc6a0SPierre-Louis Bossart static inline void sdw_intel_debugfs_init(struct sdw_intel *sdw) 91fb2dc6a0SPierre-Louis Bossart { 92fb2dc6a0SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, debugfs_init)) 93fb2dc6a0SPierre-Louis Bossart SDW_INTEL_OPS(sdw, debugfs_init)(sdw); 94fb2dc6a0SPierre-Louis Bossart } 95fb2dc6a0SPierre-Louis Bossart 96fb2dc6a0SPierre-Louis Bossart static inline void sdw_intel_debugfs_exit(struct sdw_intel *sdw) 97fb2dc6a0SPierre-Louis Bossart { 98fb2dc6a0SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, debugfs_exit)) 99fb2dc6a0SPierre-Louis Bossart SDW_INTEL_OPS(sdw, debugfs_exit)(sdw); 100fb2dc6a0SPierre-Louis Bossart } 101fb2dc6a0SPierre-Louis Bossart 102b6234bccSPierre-Louis Bossart static inline int sdw_intel_register_dai(struct sdw_intel *sdw) 103b6234bccSPierre-Louis Bossart { 104b6234bccSPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, register_dai)) 105b6234bccSPierre-Louis Bossart return SDW_INTEL_OPS(sdw, register_dai)(sdw); 106b6234bccSPierre-Louis Bossart return -ENOTSUPP; 107b6234bccSPierre-Louis Bossart } 108b6234bccSPierre-Louis Bossart 1093db0c5a6SPierre-Louis Bossart static inline void sdw_intel_check_clock_stop(struct sdw_intel *sdw) 1103db0c5a6SPierre-Louis Bossart { 1113db0c5a6SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, check_clock_stop)) 1123db0c5a6SPierre-Louis Bossart SDW_INTEL_OPS(sdw, check_clock_stop)(sdw); 1133db0c5a6SPierre-Louis Bossart } 1143db0c5a6SPierre-Louis Bossart 1153db0c5a6SPierre-Louis Bossart static inline int sdw_intel_start_bus(struct sdw_intel *sdw) 1163db0c5a6SPierre-Louis Bossart { 1173db0c5a6SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, start_bus)) 1183db0c5a6SPierre-Louis Bossart return SDW_INTEL_OPS(sdw, start_bus)(sdw); 1193db0c5a6SPierre-Louis Bossart return -ENOTSUPP; 1203db0c5a6SPierre-Louis Bossart } 1213db0c5a6SPierre-Louis Bossart 1223db0c5a6SPierre-Louis Bossart static inline int sdw_intel_start_bus_after_reset(struct sdw_intel *sdw) 1233db0c5a6SPierre-Louis Bossart { 1243db0c5a6SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_reset)) 1253db0c5a6SPierre-Louis Bossart return SDW_INTEL_OPS(sdw, start_bus_after_reset)(sdw); 1263db0c5a6SPierre-Louis Bossart return -ENOTSUPP; 1273db0c5a6SPierre-Louis Bossart } 1283db0c5a6SPierre-Louis Bossart 1293db0c5a6SPierre-Louis Bossart static inline int sdw_intel_start_bus_after_clock_stop(struct sdw_intel *sdw) 1303db0c5a6SPierre-Louis Bossart { 1313db0c5a6SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_clock_stop)) 1323db0c5a6SPierre-Louis Bossart return SDW_INTEL_OPS(sdw, start_bus_after_clock_stop)(sdw); 1333db0c5a6SPierre-Louis Bossart return -ENOTSUPP; 1343db0c5a6SPierre-Louis Bossart } 1353db0c5a6SPierre-Louis Bossart 1363db0c5a6SPierre-Louis Bossart static inline int sdw_intel_stop_bus(struct sdw_intel *sdw, bool clock_stop) 1373db0c5a6SPierre-Louis Bossart { 1383db0c5a6SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, stop_bus)) 1393db0c5a6SPierre-Louis Bossart return SDW_INTEL_OPS(sdw, stop_bus)(sdw, clock_stop); 1403db0c5a6SPierre-Louis Bossart return -ENOTSUPP; 1413db0c5a6SPierre-Louis Bossart } 1423db0c5a6SPierre-Louis Bossart 14349c9ff45SPierre-Louis Bossart static inline int sdw_intel_link_power_up(struct sdw_intel *sdw) 14449c9ff45SPierre-Louis Bossart { 14549c9ff45SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, link_power_up)) 14649c9ff45SPierre-Louis Bossart return SDW_INTEL_OPS(sdw, link_power_up)(sdw); 14749c9ff45SPierre-Louis Bossart return -ENOTSUPP; 14849c9ff45SPierre-Louis Bossart } 14949c9ff45SPierre-Louis Bossart 15049c9ff45SPierre-Louis Bossart static inline int sdw_intel_link_power_down(struct sdw_intel *sdw) 15149c9ff45SPierre-Louis Bossart { 15249c9ff45SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, link_power_down)) 15349c9ff45SPierre-Louis Bossart return SDW_INTEL_OPS(sdw, link_power_down)(sdw); 15449c9ff45SPierre-Louis Bossart return -ENOTSUPP; 15549c9ff45SPierre-Louis Bossart } 15649c9ff45SPierre-Louis Bossart 15736e3b385SPierre-Louis Bossart static inline int sdw_intel_shim_check_wake(struct sdw_intel *sdw) 15836e3b385SPierre-Louis Bossart { 15936e3b385SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, shim_check_wake)) 16036e3b385SPierre-Louis Bossart return SDW_INTEL_OPS(sdw, shim_check_wake)(sdw); 16136e3b385SPierre-Louis Bossart return -ENOTSUPP; 16236e3b385SPierre-Louis Bossart } 16336e3b385SPierre-Louis Bossart 16436e3b385SPierre-Louis Bossart static inline void sdw_intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 16536e3b385SPierre-Louis Bossart { 16636e3b385SPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, shim_wake)) 16736e3b385SPierre-Louis Bossart SDW_INTEL_OPS(sdw, shim_wake)(sdw, wake_enable); 16836e3b385SPierre-Louis Bossart } 16936e3b385SPierre-Louis Bossart 17084706e9aSPierre-Louis Bossart static inline void sdw_intel_sync_arm(struct sdw_intel *sdw) 17184706e9aSPierre-Louis Bossart { 17284706e9aSPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, sync_arm)) 17384706e9aSPierre-Louis Bossart SDW_INTEL_OPS(sdw, sync_arm)(sdw); 17484706e9aSPierre-Louis Bossart } 17584706e9aSPierre-Louis Bossart 17684706e9aSPierre-Louis Bossart static inline int sdw_intel_sync_go_unlocked(struct sdw_intel *sdw) 17784706e9aSPierre-Louis Bossart { 17884706e9aSPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, sync_go_unlocked)) 17984706e9aSPierre-Louis Bossart return SDW_INTEL_OPS(sdw, sync_go_unlocked)(sdw); 18084706e9aSPierre-Louis Bossart return -ENOTSUPP; 18184706e9aSPierre-Louis Bossart } 18284706e9aSPierre-Louis Bossart 18384706e9aSPierre-Louis Bossart static inline int sdw_intel_sync_go(struct sdw_intel *sdw) 18484706e9aSPierre-Louis Bossart { 18584706e9aSPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, sync_go)) 18684706e9aSPierre-Louis Bossart return SDW_INTEL_OPS(sdw, sync_go)(sdw); 18784706e9aSPierre-Louis Bossart return -ENOTSUPP; 18884706e9aSPierre-Louis Bossart } 18984706e9aSPierre-Louis Bossart 1901e76de2eSPierre-Louis Bossart static inline bool sdw_intel_sync_check_cmdsync_unlocked(struct sdw_intel *sdw) 1911e76de2eSPierre-Louis Bossart { 1921e76de2eSPierre-Louis Bossart if (SDW_INTEL_CHECK_OPS(sdw, sync_check_cmdsync_unlocked)) 1931e76de2eSPierre-Louis Bossart return SDW_INTEL_OPS(sdw, sync_check_cmdsync_unlocked)(sdw); 1941e76de2eSPierre-Louis Bossart return false; 1951e76de2eSPierre-Louis Bossart } 1961e76de2eSPierre-Louis Bossart 1971a1a6a69SPierre-Louis Bossart /* common bus management */ 1981a1a6a69SPierre-Louis Bossart int intel_start_bus(struct sdw_intel *sdw); 1991a1a6a69SPierre-Louis Bossart int intel_start_bus_after_reset(struct sdw_intel *sdw); 2001a1a6a69SPierre-Louis Bossart void intel_check_clock_stop(struct sdw_intel *sdw); 2011a1a6a69SPierre-Louis Bossart int intel_start_bus_after_clock_stop(struct sdw_intel *sdw); 2021a1a6a69SPierre-Louis Bossart int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop); 2031a1a6a69SPierre-Louis Bossart 204*fb43d62eSPierre-Louis Bossart /* common bank switch routines */ 205*fb43d62eSPierre-Louis Bossart int intel_pre_bank_switch(struct sdw_intel *sdw); 206*fb43d62eSPierre-Louis Bossart int intel_post_bank_switch(struct sdw_intel *sdw); 207*fb43d62eSPierre-Louis Bossart 20871bb8a1bSVinod Koul #endif /* __SDW_INTEL_LOCAL_H */ 209