1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // Copyright(c) 2015-17 Intel Corporation. 3 4 /* 5 * Soundwire Intel Master Driver 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/platform_device.h> 15 #include <sound/pcm_params.h> 16 #include <linux/pm_runtime.h> 17 #include <sound/soc.h> 18 #include <linux/soundwire/sdw_registers.h> 19 #include <linux/soundwire/sdw.h> 20 #include <linux/soundwire/sdw_intel.h> 21 #include "cadence_master.h" 22 #include "bus.h" 23 #include "intel.h" 24 25 /* Intel SHIM Registers Definition */ 26 #define SDW_SHIM_LCAP 0x0 27 #define SDW_SHIM_LCTL 0x4 28 #define SDW_SHIM_IPPTR 0x8 29 #define SDW_SHIM_SYNC 0xC 30 31 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 32 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 33 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 34 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 35 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 36 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 37 38 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 39 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 40 #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) 41 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 42 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 43 44 #define SDW_SHIM_WAKEEN 0x190 45 #define SDW_SHIM_WAKESTS 0x192 46 47 #define SDW_SHIM_LCTL_SPA BIT(0) 48 #define SDW_SHIM_LCTL_CPA BIT(8) 49 50 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1) 51 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1) 52 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) 53 #define SDW_SHIM_SYNC_SYNCCPU BIT(15) 54 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) 55 #define SDW_SHIM_SYNC_CMDSYNC BIT(16) 56 #define SDW_SHIM_SYNC_SYNCGO BIT(24) 57 58 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) 59 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) 60 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) 61 62 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) 63 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) 64 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) 65 #define SDW_SHIM_PCMSYCM_DIR BIT(15) 66 67 #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) 68 #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) 69 #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) 70 #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) 71 72 #define SDW_SHIM_IOCTL_MIF BIT(0) 73 #define SDW_SHIM_IOCTL_CO BIT(1) 74 #define SDW_SHIM_IOCTL_COE BIT(2) 75 #define SDW_SHIM_IOCTL_DO BIT(3) 76 #define SDW_SHIM_IOCTL_DOE BIT(4) 77 #define SDW_SHIM_IOCTL_BKE BIT(5) 78 #define SDW_SHIM_IOCTL_WPDD BIT(6) 79 #define SDW_SHIM_IOCTL_CIBD BIT(8) 80 #define SDW_SHIM_IOCTL_DIBD BIT(9) 81 82 #define SDW_SHIM_CTMCTL_DACTQE BIT(0) 83 #define SDW_SHIM_CTMCTL_DODS BIT(1) 84 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) 85 86 #define SDW_SHIM_WAKEEN_ENABLE BIT(0) 87 #define SDW_SHIM_WAKESTS_STATUS BIT(0) 88 89 /* Intel ALH Register definitions */ 90 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) 91 #define SDW_ALH_NUM_STREAMS 64 92 93 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 94 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) 95 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) 96 97 enum intel_pdi_type { 98 INTEL_PDI_IN = 0, 99 INTEL_PDI_OUT = 1, 100 INTEL_PDI_BD = 2, 101 }; 102 103 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) 104 105 /* 106 * Read, write helpers for HW registers 107 */ 108 static inline int intel_readl(void __iomem *base, int offset) 109 { 110 return readl(base + offset); 111 } 112 113 static inline void intel_writel(void __iomem *base, int offset, int value) 114 { 115 writel(value, base + offset); 116 } 117 118 static inline u16 intel_readw(void __iomem *base, int offset) 119 { 120 return readw(base + offset); 121 } 122 123 static inline void intel_writew(void __iomem *base, int offset, u16 value) 124 { 125 writew(value, base + offset); 126 } 127 128 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target) 129 { 130 int timeout = 10; 131 u32 reg_read; 132 133 do { 134 reg_read = readl(base + offset); 135 if ((reg_read & mask) == target) 136 return 0; 137 138 timeout--; 139 usleep_range(50, 100); 140 } while (timeout != 0); 141 142 return -EAGAIN; 143 } 144 145 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) 146 { 147 writel(value, base + offset); 148 return intel_wait_bit(base, offset, mask, 0); 149 } 150 151 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) 152 { 153 writel(value, base + offset); 154 return intel_wait_bit(base, offset, mask, mask); 155 } 156 157 /* 158 * debugfs 159 */ 160 #ifdef CONFIG_DEBUG_FS 161 162 #define RD_BUF (2 * PAGE_SIZE) 163 164 static ssize_t intel_sprintf(void __iomem *mem, bool l, 165 char *buf, size_t pos, unsigned int reg) 166 { 167 int value; 168 169 if (l) 170 value = intel_readl(mem, reg); 171 else 172 value = intel_readw(mem, reg); 173 174 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); 175 } 176 177 static int intel_reg_show(struct seq_file *s_file, void *data) 178 { 179 struct sdw_intel *sdw = s_file->private; 180 void __iomem *s = sdw->link_res->shim; 181 void __iomem *a = sdw->link_res->alh; 182 char *buf; 183 ssize_t ret; 184 int i, j; 185 unsigned int links, reg; 186 187 buf = kzalloc(RD_BUF, GFP_KERNEL); 188 if (!buf) 189 return -ENOMEM; 190 191 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0); 192 193 ret = scnprintf(buf, RD_BUF, "Register Value\n"); 194 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); 195 196 for (i = 0; i < links; i++) { 197 reg = SDW_SHIM_LCAP + i * 4; 198 ret += intel_sprintf(s, true, buf, ret, reg); 199 } 200 201 for (i = 0; i < links; i++) { 202 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i); 203 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i)); 204 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i)); 205 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i)); 206 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i)); 207 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i)); 208 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i)); 209 210 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n"); 211 212 /* 213 * the value 10 is the number of PDIs. We will need a 214 * cleanup to remove hard-coded Intel configurations 215 * from cadence_master.c 216 */ 217 for (j = 0; j < 10; j++) { 218 ret += intel_sprintf(s, false, buf, ret, 219 SDW_SHIM_PCMSYCHM(i, j)); 220 ret += intel_sprintf(s, false, buf, ret, 221 SDW_SHIM_PCMSYCHC(i, j)); 222 } 223 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n"); 224 225 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i)); 226 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i)); 227 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i)); 228 } 229 230 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n"); 231 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN); 232 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS); 233 234 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n"); 235 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++) 236 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i)); 237 238 seq_printf(s_file, "%s", buf); 239 kfree(buf); 240 241 return 0; 242 } 243 DEFINE_SHOW_ATTRIBUTE(intel_reg); 244 245 static void intel_debugfs_init(struct sdw_intel *sdw) 246 { 247 struct dentry *root = sdw->cdns.bus.debugfs; 248 249 if (!root) 250 return; 251 252 sdw->debugfs = debugfs_create_dir("intel-sdw", root); 253 254 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw, 255 &intel_reg_fops); 256 257 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); 258 } 259 260 static void intel_debugfs_exit(struct sdw_intel *sdw) 261 { 262 debugfs_remove_recursive(sdw->debugfs); 263 } 264 #else 265 static void intel_debugfs_init(struct sdw_intel *sdw) {} 266 static void intel_debugfs_exit(struct sdw_intel *sdw) {} 267 #endif /* CONFIG_DEBUG_FS */ 268 269 /* 270 * shim ops 271 */ 272 273 static int intel_link_power_up(struct sdw_intel *sdw) 274 { 275 unsigned int link_id = sdw->instance; 276 void __iomem *shim = sdw->link_res->shim; 277 u32 *shim_mask = sdw->link_res->shim_mask; 278 struct sdw_bus *bus = &sdw->cdns.bus; 279 struct sdw_master_prop *prop = &bus->prop; 280 int spa_mask, cpa_mask; 281 int link_control; 282 int ret = 0; 283 u32 syncprd; 284 u32 sync_reg; 285 286 mutex_lock(sdw->link_res->shim_lock); 287 288 /* 289 * The hardware relies on an internal counter, typically 4kHz, 290 * to generate the SoundWire SSP - which defines a 'safe' 291 * synchronization point between commands and audio transport 292 * and allows for multi link synchronization. The SYNCPRD value 293 * is only dependent on the oscillator clock provided to 294 * the IP, so adjust based on _DSD properties reported in DSDT 295 * tables. The values reported are based on either 24MHz 296 * (CNL/CML) or 38.4 MHz (ICL/TGL+). 297 */ 298 if (prop->mclk_freq % 6000000) 299 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; 300 else 301 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24; 302 303 if (!*shim_mask) { 304 /* we first need to program the SyncPRD/CPU registers */ 305 dev_dbg(sdw->cdns.dev, 306 "%s: first link up, programming SYNCPRD\n", __func__); 307 308 /* set SyncPRD period */ 309 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 310 sync_reg |= (syncprd << 311 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD)); 312 313 /* Set SyncCPU bit */ 314 sync_reg |= SDW_SHIM_SYNC_SYNCCPU; 315 intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 316 } 317 318 /* Link power up sequence */ 319 link_control = intel_readl(shim, SDW_SHIM_LCTL); 320 spa_mask = (SDW_SHIM_LCTL_SPA << link_id); 321 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id); 322 link_control |= spa_mask; 323 324 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 325 if (ret < 0) { 326 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret); 327 goto out; 328 } 329 330 if (!*shim_mask) { 331 /* SyncCPU will change once link is active */ 332 ret = intel_wait_bit(shim, SDW_SHIM_SYNC, 333 SDW_SHIM_SYNC_SYNCCPU, 0); 334 if (ret < 0) { 335 dev_err(sdw->cdns.dev, 336 "Failed to set SHIM_SYNC: %d\n", ret); 337 goto out; 338 } 339 } 340 341 *shim_mask |= BIT(link_id); 342 343 sdw->cdns.link_up = true; 344 out: 345 mutex_unlock(sdw->link_res->shim_lock); 346 347 return ret; 348 } 349 350 /* this needs to be called with shim_lock */ 351 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw) 352 { 353 void __iomem *shim = sdw->link_res->shim; 354 unsigned int link_id = sdw->instance; 355 u16 ioctl; 356 357 /* Switch to MIP from Glue logic */ 358 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); 359 360 ioctl &= ~(SDW_SHIM_IOCTL_DOE); 361 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 362 usleep_range(10, 15); 363 364 ioctl &= ~(SDW_SHIM_IOCTL_DO); 365 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 366 usleep_range(10, 15); 367 368 ioctl |= (SDW_SHIM_IOCTL_MIF); 369 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 370 usleep_range(10, 15); 371 372 ioctl &= ~(SDW_SHIM_IOCTL_BKE); 373 ioctl &= ~(SDW_SHIM_IOCTL_COE); 374 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 375 usleep_range(10, 15); 376 377 /* at this point Master IP has full control of the I/Os */ 378 } 379 380 /* this needs to be called with shim_lock */ 381 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw) 382 { 383 unsigned int link_id = sdw->instance; 384 void __iomem *shim = sdw->link_res->shim; 385 u16 ioctl; 386 387 /* Glue logic */ 388 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); 389 ioctl |= SDW_SHIM_IOCTL_BKE; 390 ioctl |= SDW_SHIM_IOCTL_COE; 391 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 392 usleep_range(10, 15); 393 394 ioctl &= ~(SDW_SHIM_IOCTL_MIF); 395 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 396 usleep_range(10, 15); 397 398 /* at this point Integration Glue has full control of the I/Os */ 399 } 400 401 static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop) 402 { 403 void __iomem *shim = sdw->link_res->shim; 404 unsigned int link_id = sdw->instance; 405 int ret = 0; 406 u16 ioctl = 0, act = 0; 407 408 mutex_lock(sdw->link_res->shim_lock); 409 410 /* Initialize Shim */ 411 ioctl |= SDW_SHIM_IOCTL_BKE; 412 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 413 usleep_range(10, 15); 414 415 ioctl |= SDW_SHIM_IOCTL_WPDD; 416 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 417 usleep_range(10, 15); 418 419 ioctl |= SDW_SHIM_IOCTL_DO; 420 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 421 usleep_range(10, 15); 422 423 ioctl |= SDW_SHIM_IOCTL_DOE; 424 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 425 usleep_range(10, 15); 426 427 intel_shim_glue_to_master_ip(sdw); 428 429 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS); 430 act |= SDW_SHIM_CTMCTL_DACTQE; 431 act |= SDW_SHIM_CTMCTL_DODS; 432 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); 433 usleep_range(10, 15); 434 435 mutex_unlock(sdw->link_res->shim_lock); 436 437 return ret; 438 } 439 440 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 441 { 442 void __iomem *shim = sdw->link_res->shim; 443 unsigned int link_id = sdw->instance; 444 u16 wake_en, wake_sts; 445 446 mutex_lock(sdw->link_res->shim_lock); 447 wake_en = intel_readw(shim, SDW_SHIM_WAKEEN); 448 449 if (wake_enable) { 450 /* Enable the wakeup */ 451 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id); 452 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en); 453 } else { 454 /* Disable the wake up interrupt */ 455 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id); 456 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en); 457 458 /* Clear wake status */ 459 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); 460 wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id); 461 intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts); 462 } 463 mutex_unlock(sdw->link_res->shim_lock); 464 } 465 466 static int __maybe_unused intel_link_power_down(struct sdw_intel *sdw) 467 { 468 int link_control, spa_mask, cpa_mask; 469 unsigned int link_id = sdw->instance; 470 void __iomem *shim = sdw->link_res->shim; 471 u32 *shim_mask = sdw->link_res->shim_mask; 472 int ret = 0; 473 474 mutex_lock(sdw->link_res->shim_lock); 475 476 intel_shim_master_ip_to_glue(sdw); 477 478 /* Link power down sequence */ 479 link_control = intel_readl(shim, SDW_SHIM_LCTL); 480 spa_mask = ~(SDW_SHIM_LCTL_SPA << link_id); 481 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id); 482 link_control &= spa_mask; 483 484 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 485 486 if (!(*shim_mask & BIT(link_id))) 487 dev_err(sdw->cdns.dev, 488 "%s: Unbalanced power-up/down calls\n", __func__); 489 490 *shim_mask &= ~BIT(link_id); 491 492 mutex_unlock(sdw->link_res->shim_lock); 493 494 if (ret < 0) 495 return ret; 496 497 sdw->cdns.link_up = false; 498 return 0; 499 } 500 501 static void intel_shim_sync_arm(struct sdw_intel *sdw) 502 { 503 void __iomem *shim = sdw->link_res->shim; 504 u32 sync_reg; 505 506 mutex_lock(sdw->link_res->shim_lock); 507 508 /* update SYNC register */ 509 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 510 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance); 511 intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 512 513 mutex_unlock(sdw->link_res->shim_lock); 514 } 515 516 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw) 517 { 518 void __iomem *shim = sdw->link_res->shim; 519 u32 sync_reg; 520 int ret; 521 522 /* Read SYNC register */ 523 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 524 525 /* 526 * Set SyncGO bit to synchronously trigger a bank switch for 527 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all 528 * the Masters. 529 */ 530 sync_reg |= SDW_SHIM_SYNC_SYNCGO; 531 532 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, 533 SDW_SHIM_SYNC_SYNCGO); 534 535 if (ret < 0) 536 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret); 537 538 return ret; 539 } 540 541 /* 542 * PDI routines 543 */ 544 static void intel_pdi_init(struct sdw_intel *sdw, 545 struct sdw_cdns_stream_config *config) 546 { 547 void __iomem *shim = sdw->link_res->shim; 548 unsigned int link_id = sdw->instance; 549 int pcm_cap, pdm_cap; 550 551 /* PCM Stream Capability */ 552 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); 553 554 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >> 555 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS); 556 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >> 557 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS); 558 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >> 559 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS); 560 561 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", 562 config->pcm_bd, config->pcm_in, config->pcm_out); 563 564 /* PDM Stream Capability */ 565 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 566 567 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >> 568 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS); 569 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >> 570 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS); 571 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >> 572 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS); 573 574 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n", 575 config->pdm_bd, config->pdm_in, config->pdm_out); 576 } 577 578 static int 579 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm) 580 { 581 void __iomem *shim = sdw->link_res->shim; 582 unsigned int link_id = sdw->instance; 583 int count; 584 585 if (pcm) { 586 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); 587 588 /* 589 * WORKAROUND: on all existing Intel controllers, pdi 590 * number 2 reports channel count as 1 even though it 591 * supports 8 channels. Performing hardcoding for pdi 592 * number 2. 593 */ 594 if (pdi_num == 2) 595 count = 7; 596 597 } else { 598 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 599 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >> 600 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS)); 601 } 602 603 /* zero based values for channel count in register */ 604 count++; 605 606 return count; 607 } 608 609 static int intel_pdi_get_ch_update(struct sdw_intel *sdw, 610 struct sdw_cdns_pdi *pdi, 611 unsigned int num_pdi, 612 unsigned int *num_ch, bool pcm) 613 { 614 int i, ch_count = 0; 615 616 for (i = 0; i < num_pdi; i++) { 617 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); 618 ch_count += pdi->ch_count; 619 pdi++; 620 } 621 622 *num_ch = ch_count; 623 return 0; 624 } 625 626 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw, 627 struct sdw_cdns_streams *stream, bool pcm) 628 { 629 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, 630 &stream->num_ch_bd, pcm); 631 632 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, 633 &stream->num_ch_in, pcm); 634 635 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, 636 &stream->num_ch_out, pcm); 637 638 return 0; 639 } 640 641 static int intel_pdi_ch_update(struct sdw_intel *sdw) 642 { 643 /* First update PCM streams followed by PDM streams */ 644 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); 645 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); 646 647 return 0; 648 } 649 650 static void 651 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 652 { 653 void __iomem *shim = sdw->link_res->shim; 654 unsigned int link_id = sdw->instance; 655 int pdi_conf = 0; 656 657 /* the Bulk and PCM streams are not contiguous */ 658 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; 659 if (pdi->num >= 2) 660 pdi->intel_alh_id += 2; 661 662 /* 663 * Program stream parameters to stream SHIM register 664 * This is applicable for PCM stream only. 665 */ 666 if (pdi->type != SDW_STREAM_PCM) 667 return; 668 669 if (pdi->dir == SDW_DATA_DIR_RX) 670 pdi_conf |= SDW_SHIM_PCMSYCM_DIR; 671 else 672 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR); 673 674 pdi_conf |= (pdi->intel_alh_id << 675 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM)); 676 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN)); 677 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN)); 678 679 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); 680 } 681 682 static void 683 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 684 { 685 void __iomem *alh = sdw->link_res->alh; 686 unsigned int link_id = sdw->instance; 687 unsigned int conf; 688 689 /* the Bulk and PCM streams are not contiguous */ 690 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; 691 if (pdi->num >= 2) 692 pdi->intel_alh_id += 2; 693 694 /* Program Stream config ALH register */ 695 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); 696 697 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL << 698 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT)); 699 700 conf |= ((pdi->ch_count - 1) << 701 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN)); 702 703 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); 704 } 705 706 static int intel_params_stream(struct sdw_intel *sdw, 707 struct snd_pcm_substream *substream, 708 struct snd_soc_dai *dai, 709 struct snd_pcm_hw_params *hw_params, 710 int link_id, int alh_stream_id) 711 { 712 struct sdw_intel_link_res *res = sdw->link_res; 713 struct sdw_intel_stream_params_data params_data; 714 715 params_data.substream = substream; 716 params_data.dai = dai; 717 params_data.hw_params = hw_params; 718 params_data.link_id = link_id; 719 params_data.alh_stream_id = alh_stream_id; 720 721 if (res->ops && res->ops->params_stream && res->dev) 722 return res->ops->params_stream(res->dev, 723 ¶ms_data); 724 return -EIO; 725 } 726 727 static int intel_free_stream(struct sdw_intel *sdw, 728 struct snd_pcm_substream *substream, 729 struct snd_soc_dai *dai, 730 int link_id) 731 { 732 struct sdw_intel_link_res *res = sdw->link_res; 733 struct sdw_intel_stream_free_data free_data; 734 735 free_data.substream = substream; 736 free_data.dai = dai; 737 free_data.link_id = link_id; 738 739 if (res->ops && res->ops->free_stream && res->dev) 740 return res->ops->free_stream(res->dev, 741 &free_data); 742 743 return 0; 744 } 745 746 /* 747 * bank switch routines 748 */ 749 750 static int intel_pre_bank_switch(struct sdw_bus *bus) 751 { 752 struct sdw_cdns *cdns = bus_to_cdns(bus); 753 struct sdw_intel *sdw = cdns_to_intel(cdns); 754 755 /* Write to register only for multi-link */ 756 if (!bus->multi_link) 757 return 0; 758 759 intel_shim_sync_arm(sdw); 760 761 return 0; 762 } 763 764 static int intel_post_bank_switch(struct sdw_bus *bus) 765 { 766 struct sdw_cdns *cdns = bus_to_cdns(bus); 767 struct sdw_intel *sdw = cdns_to_intel(cdns); 768 void __iomem *shim = sdw->link_res->shim; 769 int sync_reg, ret; 770 771 /* Write to register only for multi-link */ 772 if (!bus->multi_link) 773 return 0; 774 775 mutex_lock(sdw->link_res->shim_lock); 776 777 /* Read SYNC register */ 778 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 779 780 /* 781 * post_bank_switch() ops is called from the bus in loop for 782 * all the Masters in the steam with the expectation that 783 * we trigger the bankswitch for the only first Master in the list 784 * and do nothing for the other Masters 785 * 786 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master. 787 */ 788 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) { 789 ret = 0; 790 goto unlock; 791 } 792 793 ret = intel_shim_sync_go_unlocked(sdw); 794 unlock: 795 mutex_unlock(sdw->link_res->shim_lock); 796 797 if (ret < 0) 798 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret); 799 800 return ret; 801 } 802 803 /* 804 * DAI routines 805 */ 806 807 static int intel_startup(struct snd_pcm_substream *substream, 808 struct snd_soc_dai *dai) 809 { 810 /* 811 * TODO: add pm_runtime support here, the startup callback 812 * will make sure the IP is 'active' 813 */ 814 return 0; 815 } 816 817 static int intel_hw_params(struct snd_pcm_substream *substream, 818 struct snd_pcm_hw_params *params, 819 struct snd_soc_dai *dai) 820 { 821 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 822 struct sdw_intel *sdw = cdns_to_intel(cdns); 823 struct sdw_cdns_dma_data *dma; 824 struct sdw_cdns_pdi *pdi; 825 struct sdw_stream_config sconfig; 826 struct sdw_port_config *pconfig; 827 int ch, dir; 828 int ret; 829 bool pcm = true; 830 831 dma = snd_soc_dai_get_dma_data(dai, substream); 832 if (!dma) 833 return -EIO; 834 835 ch = params_channels(params); 836 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 837 dir = SDW_DATA_DIR_RX; 838 else 839 dir = SDW_DATA_DIR_TX; 840 841 if (dma->stream_type == SDW_STREAM_PDM) 842 pcm = false; 843 844 if (pcm) 845 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); 846 else 847 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id); 848 849 if (!pdi) { 850 ret = -EINVAL; 851 goto error; 852 } 853 854 /* do run-time configurations for SHIM, ALH and PDI/PORT */ 855 intel_pdi_shim_configure(sdw, pdi); 856 intel_pdi_alh_configure(sdw, pdi); 857 sdw_cdns_config_stream(cdns, ch, dir, pdi); 858 859 860 /* Inform DSP about PDI stream number */ 861 ret = intel_params_stream(sdw, substream, dai, params, 862 sdw->instance, 863 pdi->intel_alh_id); 864 if (ret) 865 goto error; 866 867 sconfig.direction = dir; 868 sconfig.ch_count = ch; 869 sconfig.frame_rate = params_rate(params); 870 sconfig.type = dma->stream_type; 871 872 if (dma->stream_type == SDW_STREAM_PDM) { 873 sconfig.frame_rate *= 50; 874 sconfig.bps = 1; 875 } else { 876 sconfig.bps = snd_pcm_format_width(params_format(params)); 877 } 878 879 /* Port configuration */ 880 pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL); 881 if (!pconfig) { 882 ret = -ENOMEM; 883 goto error; 884 } 885 886 pconfig->num = pdi->num; 887 pconfig->ch_mask = (1 << ch) - 1; 888 889 ret = sdw_stream_add_master(&cdns->bus, &sconfig, 890 pconfig, 1, dma->stream); 891 if (ret) 892 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 893 894 kfree(pconfig); 895 error: 896 return ret; 897 } 898 899 static int intel_prepare(struct snd_pcm_substream *substream, 900 struct snd_soc_dai *dai) 901 { 902 struct sdw_cdns_dma_data *dma; 903 904 dma = snd_soc_dai_get_dma_data(dai, substream); 905 if (!dma) { 906 dev_err(dai->dev, "failed to get dma data in %s", 907 __func__); 908 return -EIO; 909 } 910 911 return sdw_prepare_stream(dma->stream); 912 } 913 914 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, 915 struct snd_soc_dai *dai) 916 { 917 struct sdw_cdns_dma_data *dma; 918 int ret; 919 920 dma = snd_soc_dai_get_dma_data(dai, substream); 921 if (!dma) { 922 dev_err(dai->dev, "failed to get dma data in %s", __func__); 923 return -EIO; 924 } 925 926 switch (cmd) { 927 case SNDRV_PCM_TRIGGER_START: 928 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 929 case SNDRV_PCM_TRIGGER_RESUME: 930 ret = sdw_enable_stream(dma->stream); 931 break; 932 933 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 934 case SNDRV_PCM_TRIGGER_SUSPEND: 935 case SNDRV_PCM_TRIGGER_STOP: 936 ret = sdw_disable_stream(dma->stream); 937 break; 938 939 default: 940 ret = -EINVAL; 941 break; 942 } 943 944 if (ret) 945 dev_err(dai->dev, 946 "%s trigger %d failed: %d", 947 __func__, cmd, ret); 948 return ret; 949 } 950 951 static int 952 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 953 { 954 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 955 struct sdw_intel *sdw = cdns_to_intel(cdns); 956 struct sdw_cdns_dma_data *dma; 957 int ret; 958 959 dma = snd_soc_dai_get_dma_data(dai, substream); 960 if (!dma) 961 return -EIO; 962 963 ret = sdw_deprepare_stream(dma->stream); 964 if (ret) { 965 dev_err(dai->dev, "sdw_deprepare_stream: failed %d", ret); 966 return ret; 967 } 968 969 ret = sdw_stream_remove_master(&cdns->bus, dma->stream); 970 if (ret < 0) { 971 dev_err(dai->dev, "remove master from stream %s failed: %d\n", 972 dma->stream->name, ret); 973 return ret; 974 } 975 976 ret = intel_free_stream(sdw, substream, dai, sdw->instance); 977 if (ret < 0) { 978 dev_err(dai->dev, "intel_free_stream: failed %d", ret); 979 return ret; 980 } 981 982 return 0; 983 } 984 985 static void intel_shutdown(struct snd_pcm_substream *substream, 986 struct snd_soc_dai *dai) 987 { 988 989 } 990 991 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, 992 void *stream, int direction) 993 { 994 return cdns_set_sdw_stream(dai, stream, true, direction); 995 } 996 997 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai, 998 void *stream, int direction) 999 { 1000 return cdns_set_sdw_stream(dai, stream, false, direction); 1001 } 1002 1003 static void *intel_get_sdw_stream(struct snd_soc_dai *dai, 1004 int direction) 1005 { 1006 struct sdw_cdns_dma_data *dma; 1007 1008 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 1009 dma = dai->playback_dma_data; 1010 else 1011 dma = dai->capture_dma_data; 1012 1013 if (!dma) 1014 return NULL; 1015 1016 return dma->stream; 1017 } 1018 1019 static const struct snd_soc_dai_ops intel_pcm_dai_ops = { 1020 .startup = intel_startup, 1021 .hw_params = intel_hw_params, 1022 .prepare = intel_prepare, 1023 .trigger = intel_trigger, 1024 .hw_free = intel_hw_free, 1025 .shutdown = intel_shutdown, 1026 .set_sdw_stream = intel_pcm_set_sdw_stream, 1027 .get_sdw_stream = intel_get_sdw_stream, 1028 }; 1029 1030 static const struct snd_soc_dai_ops intel_pdm_dai_ops = { 1031 .startup = intel_startup, 1032 .hw_params = intel_hw_params, 1033 .prepare = intel_prepare, 1034 .trigger = intel_trigger, 1035 .hw_free = intel_hw_free, 1036 .shutdown = intel_shutdown, 1037 .set_sdw_stream = intel_pdm_set_sdw_stream, 1038 .get_sdw_stream = intel_get_sdw_stream, 1039 }; 1040 1041 static const struct snd_soc_component_driver dai_component = { 1042 .name = "soundwire", 1043 }; 1044 1045 static int intel_create_dai(struct sdw_cdns *cdns, 1046 struct snd_soc_dai_driver *dais, 1047 enum intel_pdi_type type, 1048 u32 num, u32 off, u32 max_ch, bool pcm) 1049 { 1050 int i; 1051 1052 if (num == 0) 1053 return 0; 1054 1055 /* TODO: Read supported rates/formats from hardware */ 1056 for (i = off; i < (off + num); i++) { 1057 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, 1058 "SDW%d Pin%d", 1059 cdns->instance, i); 1060 if (!dais[i].name) 1061 return -ENOMEM; 1062 1063 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { 1064 dais[i].playback.channels_min = 1; 1065 dais[i].playback.channels_max = max_ch; 1066 dais[i].playback.rates = SNDRV_PCM_RATE_48000; 1067 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 1068 } 1069 1070 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { 1071 dais[i].capture.channels_min = 1; 1072 dais[i].capture.channels_max = max_ch; 1073 dais[i].capture.rates = SNDRV_PCM_RATE_48000; 1074 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 1075 } 1076 1077 if (pcm) 1078 dais[i].ops = &intel_pcm_dai_ops; 1079 else 1080 dais[i].ops = &intel_pdm_dai_ops; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int intel_register_dai(struct sdw_intel *sdw) 1087 { 1088 struct sdw_cdns *cdns = &sdw->cdns; 1089 struct sdw_cdns_streams *stream; 1090 struct snd_soc_dai_driver *dais; 1091 int num_dai, ret, off = 0; 1092 1093 /* DAIs are created based on total number of PDIs supported */ 1094 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; 1095 1096 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); 1097 if (!dais) 1098 return -ENOMEM; 1099 1100 /* Create PCM DAIs */ 1101 stream = &cdns->pcm; 1102 1103 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, 1104 off, stream->num_ch_in, true); 1105 if (ret) 1106 return ret; 1107 1108 off += cdns->pcm.num_in; 1109 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, 1110 off, stream->num_ch_out, true); 1111 if (ret) 1112 return ret; 1113 1114 off += cdns->pcm.num_out; 1115 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, 1116 off, stream->num_ch_bd, true); 1117 if (ret) 1118 return ret; 1119 1120 /* Create PDM DAIs */ 1121 stream = &cdns->pdm; 1122 off += cdns->pcm.num_bd; 1123 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in, 1124 off, stream->num_ch_in, false); 1125 if (ret) 1126 return ret; 1127 1128 off += cdns->pdm.num_in; 1129 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out, 1130 off, stream->num_ch_out, false); 1131 if (ret) 1132 return ret; 1133 1134 off += cdns->pdm.num_out; 1135 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd, 1136 off, stream->num_ch_bd, false); 1137 if (ret) 1138 return ret; 1139 1140 return snd_soc_register_component(cdns->dev, &dai_component, 1141 dais, num_dai); 1142 } 1143 1144 static int sdw_master_read_intel_prop(struct sdw_bus *bus) 1145 { 1146 struct sdw_master_prop *prop = &bus->prop; 1147 struct fwnode_handle *link; 1148 char name[32]; 1149 u32 quirk_mask; 1150 1151 /* Find master handle */ 1152 snprintf(name, sizeof(name), 1153 "mipi-sdw-link-%d-subproperties", bus->link_id); 1154 1155 link = device_get_named_child_node(bus->dev, name); 1156 if (!link) { 1157 dev_err(bus->dev, "Master node %s not found\n", name); 1158 return -EIO; 1159 } 1160 1161 fwnode_property_read_u32(link, 1162 "intel-sdw-ip-clock", 1163 &prop->mclk_freq); 1164 1165 /* the values reported by BIOS are the 2x clock, not the bus clock */ 1166 prop->mclk_freq /= 2; 1167 1168 fwnode_property_read_u32(link, 1169 "intel-quirk-mask", 1170 &quirk_mask); 1171 1172 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE) 1173 prop->hw_disabled = true; 1174 1175 return 0; 1176 } 1177 1178 static int intel_prop_read(struct sdw_bus *bus) 1179 { 1180 /* Initialize with default handler to read all DisCo properties */ 1181 sdw_master_read_prop(bus); 1182 1183 /* read Intel-specific properties */ 1184 sdw_master_read_intel_prop(bus); 1185 1186 return 0; 1187 } 1188 1189 static struct sdw_master_ops sdw_intel_ops = { 1190 .read_prop = sdw_master_read_prop, 1191 .xfer_msg = cdns_xfer_msg, 1192 .xfer_msg_defer = cdns_xfer_msg_defer, 1193 .reset_page_addr = cdns_reset_page_addr, 1194 .set_bus_conf = cdns_bus_conf, 1195 .pre_bank_switch = intel_pre_bank_switch, 1196 .post_bank_switch = intel_post_bank_switch, 1197 }; 1198 1199 static int intel_init(struct sdw_intel *sdw) 1200 { 1201 bool clock_stop; 1202 1203 /* Initialize shim and controller */ 1204 intel_link_power_up(sdw); 1205 1206 clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns); 1207 1208 intel_shim_init(sdw, clock_stop); 1209 1210 if (clock_stop) 1211 return 0; 1212 1213 return sdw_cdns_init(&sdw->cdns); 1214 } 1215 1216 /* 1217 * probe and init 1218 */ 1219 static int intel_master_probe(struct platform_device *pdev) 1220 { 1221 struct device *dev = &pdev->dev; 1222 struct sdw_intel *sdw; 1223 struct sdw_cdns *cdns; 1224 struct sdw_bus *bus; 1225 int ret; 1226 1227 sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL); 1228 if (!sdw) 1229 return -ENOMEM; 1230 1231 cdns = &sdw->cdns; 1232 bus = &cdns->bus; 1233 1234 sdw->instance = pdev->id; 1235 sdw->link_res = dev_get_platdata(dev); 1236 cdns->dev = dev; 1237 cdns->registers = sdw->link_res->registers; 1238 cdns->instance = sdw->instance; 1239 cdns->msg_count = 0; 1240 1241 bus->link_id = pdev->id; 1242 1243 sdw_cdns_probe(cdns); 1244 1245 /* Set property read ops */ 1246 sdw_intel_ops.read_prop = intel_prop_read; 1247 bus->ops = &sdw_intel_ops; 1248 1249 /* set driver data, accessed by snd_soc_dai_get_drvdata() */ 1250 dev_set_drvdata(dev, cdns); 1251 1252 ret = sdw_bus_master_add(bus, dev, dev->fwnode); 1253 if (ret) { 1254 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret); 1255 return ret; 1256 } 1257 1258 if (bus->prop.hw_disabled) 1259 dev_info(dev, 1260 "SoundWire master %d is disabled, will be ignored\n", 1261 bus->link_id); 1262 1263 return 0; 1264 } 1265 1266 int intel_master_startup(struct platform_device *pdev) 1267 { 1268 struct sdw_cdns_stream_config config; 1269 struct device *dev = &pdev->dev; 1270 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1271 struct sdw_intel *sdw = cdns_to_intel(cdns); 1272 struct sdw_bus *bus = &cdns->bus; 1273 int ret; 1274 1275 if (bus->prop.hw_disabled) { 1276 dev_info(dev, 1277 "SoundWire master %d is disabled, ignoring\n", 1278 sdw->instance); 1279 return 0; 1280 } 1281 1282 /* Initialize shim, controller and Cadence IP */ 1283 ret = intel_init(sdw); 1284 if (ret) 1285 goto err_init; 1286 1287 /* Read the PDI config and initialize cadence PDI */ 1288 intel_pdi_init(sdw, &config); 1289 ret = sdw_cdns_pdi_init(cdns, config); 1290 if (ret) 1291 goto err_init; 1292 1293 intel_pdi_ch_update(sdw); 1294 1295 ret = sdw_cdns_enable_interrupt(cdns, true); 1296 if (ret < 0) { 1297 dev_err(dev, "cannot enable interrupts\n"); 1298 goto err_init; 1299 } 1300 1301 ret = sdw_cdns_exit_reset(cdns); 1302 if (ret < 0) { 1303 dev_err(dev, "unable to exit bus reset sequence\n"); 1304 goto err_interrupt; 1305 } 1306 1307 /* Register DAIs */ 1308 ret = intel_register_dai(sdw); 1309 if (ret) { 1310 dev_err(dev, "DAI registration failed: %d\n", ret); 1311 snd_soc_unregister_component(dev); 1312 goto err_interrupt; 1313 } 1314 1315 intel_debugfs_init(sdw); 1316 1317 return 0; 1318 1319 err_interrupt: 1320 sdw_cdns_enable_interrupt(cdns, false); 1321 err_init: 1322 return ret; 1323 } 1324 1325 static int intel_master_remove(struct platform_device *pdev) 1326 { 1327 struct device *dev = &pdev->dev; 1328 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1329 struct sdw_intel *sdw = cdns_to_intel(cdns); 1330 struct sdw_bus *bus = &cdns->bus; 1331 1332 if (!bus->prop.hw_disabled) { 1333 intel_debugfs_exit(sdw); 1334 sdw_cdns_enable_interrupt(cdns, false); 1335 snd_soc_unregister_component(dev); 1336 } 1337 sdw_bus_master_delete(bus); 1338 1339 return 0; 1340 } 1341 1342 int intel_master_process_wakeen_event(struct platform_device *pdev) 1343 { 1344 struct device *dev = &pdev->dev; 1345 struct sdw_intel *sdw; 1346 struct sdw_bus *bus; 1347 void __iomem *shim; 1348 u16 wake_sts; 1349 1350 sdw = platform_get_drvdata(pdev); 1351 bus = &sdw->cdns.bus; 1352 1353 if (bus->prop.hw_disabled) { 1354 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id); 1355 return 0; 1356 } 1357 1358 shim = sdw->link_res->shim; 1359 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); 1360 1361 if (!(wake_sts & BIT(sdw->instance))) 1362 return 0; 1363 1364 /* disable WAKEEN interrupt ASAP to prevent interrupt flood */ 1365 intel_shim_wake(sdw, false); 1366 1367 /* 1368 * resume the Master, which will generate a bus reset and result in 1369 * Slaves re-attaching and be re-enumerated. The SoundWire physical 1370 * device which generated the wake will trigger an interrupt, which 1371 * will in turn cause the corresponding Linux Slave device to be 1372 * resumed and the Slave codec driver to check the status. 1373 */ 1374 pm_request_resume(dev); 1375 1376 return 0; 1377 } 1378 1379 static struct platform_driver sdw_intel_drv = { 1380 .probe = intel_master_probe, 1381 .remove = intel_master_remove, 1382 .driver = { 1383 .name = "intel-sdw", 1384 }, 1385 }; 1386 1387 module_platform_driver(sdw_intel_drv); 1388 1389 MODULE_LICENSE("Dual BSD/GPL"); 1390 MODULE_ALIAS("platform:intel-sdw"); 1391 MODULE_DESCRIPTION("Intel Soundwire Master Driver"); 1392