1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // Copyright(c) 2015-17 Intel Corporation. 3 4 /* 5 * Soundwire Intel Master Driver 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/platform_device.h> 15 #include <sound/pcm_params.h> 16 #include <sound/soc.h> 17 #include <linux/soundwire/sdw_registers.h> 18 #include <linux/soundwire/sdw.h> 19 #include <linux/soundwire/sdw_intel.h> 20 #include "cadence_master.h" 21 #include "bus.h" 22 #include "intel.h" 23 24 /* Intel SHIM Registers Definition */ 25 #define SDW_SHIM_LCAP 0x0 26 #define SDW_SHIM_LCTL 0x4 27 #define SDW_SHIM_IPPTR 0x8 28 #define SDW_SHIM_SYNC 0xC 29 30 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 31 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 32 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 33 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 34 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 35 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 36 37 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 38 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 39 #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) 40 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 41 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 42 43 #define SDW_SHIM_WAKEEN 0x190 44 #define SDW_SHIM_WAKESTS 0x192 45 46 #define SDW_SHIM_LCTL_SPA BIT(0) 47 #define SDW_SHIM_LCTL_CPA BIT(8) 48 49 #define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F 50 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) 51 #define SDW_SHIM_SYNC_SYNCCPU BIT(15) 52 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) 53 #define SDW_SHIM_SYNC_CMDSYNC BIT(16) 54 #define SDW_SHIM_SYNC_SYNCGO BIT(24) 55 56 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) 57 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) 58 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) 59 60 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) 61 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) 62 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) 63 #define SDW_SHIM_PCMSYCM_DIR BIT(15) 64 65 #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) 66 #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) 67 #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) 68 #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) 69 70 #define SDW_SHIM_IOCTL_MIF BIT(0) 71 #define SDW_SHIM_IOCTL_CO BIT(1) 72 #define SDW_SHIM_IOCTL_COE BIT(2) 73 #define SDW_SHIM_IOCTL_DO BIT(3) 74 #define SDW_SHIM_IOCTL_DOE BIT(4) 75 #define SDW_SHIM_IOCTL_BKE BIT(5) 76 #define SDW_SHIM_IOCTL_WPDD BIT(6) 77 #define SDW_SHIM_IOCTL_CIBD BIT(8) 78 #define SDW_SHIM_IOCTL_DIBD BIT(9) 79 80 #define SDW_SHIM_CTMCTL_DACTQE BIT(0) 81 #define SDW_SHIM_CTMCTL_DODS BIT(1) 82 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) 83 84 #define SDW_SHIM_WAKEEN_ENABLE BIT(0) 85 #define SDW_SHIM_WAKESTS_STATUS BIT(0) 86 87 /* Intel ALH Register definitions */ 88 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) 89 #define SDW_ALH_NUM_STREAMS 64 90 91 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 92 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) 93 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) 94 95 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1) 96 97 enum intel_pdi_type { 98 INTEL_PDI_IN = 0, 99 INTEL_PDI_OUT = 1, 100 INTEL_PDI_BD = 2, 101 }; 102 103 struct sdw_intel { 104 struct sdw_cdns cdns; 105 int instance; 106 struct sdw_intel_link_res *link_res; 107 #ifdef CONFIG_DEBUG_FS 108 struct dentry *debugfs; 109 #endif 110 }; 111 112 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) 113 114 /* 115 * Read, write helpers for HW registers 116 */ 117 static inline int intel_readl(void __iomem *base, int offset) 118 { 119 return readl(base + offset); 120 } 121 122 static inline void intel_writel(void __iomem *base, int offset, int value) 123 { 124 writel(value, base + offset); 125 } 126 127 static inline u16 intel_readw(void __iomem *base, int offset) 128 { 129 return readw(base + offset); 130 } 131 132 static inline void intel_writew(void __iomem *base, int offset, u16 value) 133 { 134 writew(value, base + offset); 135 } 136 137 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) 138 { 139 int timeout = 10; 140 u32 reg_read; 141 142 writel(value, base + offset); 143 do { 144 reg_read = readl(base + offset); 145 if (!(reg_read & mask)) 146 return 0; 147 148 timeout--; 149 udelay(50); 150 } while (timeout != 0); 151 152 return -EAGAIN; 153 } 154 155 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) 156 { 157 int timeout = 10; 158 u32 reg_read; 159 160 writel(value, base + offset); 161 do { 162 reg_read = readl(base + offset); 163 if (reg_read & mask) 164 return 0; 165 166 timeout--; 167 udelay(50); 168 } while (timeout != 0); 169 170 return -EAGAIN; 171 } 172 173 /* 174 * debugfs 175 */ 176 #ifdef CONFIG_DEBUG_FS 177 178 #define RD_BUF (2 * PAGE_SIZE) 179 180 static ssize_t intel_sprintf(void __iomem *mem, bool l, 181 char *buf, size_t pos, unsigned int reg) 182 { 183 int value; 184 185 if (l) 186 value = intel_readl(mem, reg); 187 else 188 value = intel_readw(mem, reg); 189 190 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); 191 } 192 193 static int intel_reg_show(struct seq_file *s_file, void *data) 194 { 195 struct sdw_intel *sdw = s_file->private; 196 void __iomem *s = sdw->link_res->shim; 197 void __iomem *a = sdw->link_res->alh; 198 char *buf; 199 ssize_t ret; 200 int i, j; 201 unsigned int links, reg; 202 203 buf = kzalloc(RD_BUF, GFP_KERNEL); 204 if (!buf) 205 return -ENOMEM; 206 207 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0); 208 209 ret = scnprintf(buf, RD_BUF, "Register Value\n"); 210 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); 211 212 for (i = 0; i < links; i++) { 213 reg = SDW_SHIM_LCAP + i * 4; 214 ret += intel_sprintf(s, true, buf, ret, reg); 215 } 216 217 for (i = 0; i < links; i++) { 218 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i); 219 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i)); 220 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i)); 221 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i)); 222 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i)); 223 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i)); 224 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i)); 225 226 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n"); 227 228 /* 229 * the value 10 is the number of PDIs. We will need a 230 * cleanup to remove hard-coded Intel configurations 231 * from cadence_master.c 232 */ 233 for (j = 0; j < 10; j++) { 234 ret += intel_sprintf(s, false, buf, ret, 235 SDW_SHIM_PCMSYCHM(i, j)); 236 ret += intel_sprintf(s, false, buf, ret, 237 SDW_SHIM_PCMSYCHC(i, j)); 238 } 239 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n"); 240 241 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i)); 242 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i)); 243 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i)); 244 } 245 246 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n"); 247 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN); 248 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS); 249 250 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n"); 251 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++) 252 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i)); 253 254 seq_printf(s_file, "%s", buf); 255 kfree(buf); 256 257 return 0; 258 } 259 DEFINE_SHOW_ATTRIBUTE(intel_reg); 260 261 static void intel_debugfs_init(struct sdw_intel *sdw) 262 { 263 struct dentry *root = sdw->cdns.bus.debugfs; 264 265 if (!root) 266 return; 267 268 sdw->debugfs = debugfs_create_dir("intel-sdw", root); 269 270 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw, 271 &intel_reg_fops); 272 273 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); 274 } 275 276 static void intel_debugfs_exit(struct sdw_intel *sdw) 277 { 278 debugfs_remove_recursive(sdw->debugfs); 279 } 280 #else 281 static void intel_debugfs_init(struct sdw_intel *sdw) {} 282 static void intel_debugfs_exit(struct sdw_intel *sdw) {} 283 #endif /* CONFIG_DEBUG_FS */ 284 285 /* 286 * shim ops 287 */ 288 289 static int intel_link_power_up(struct sdw_intel *sdw) 290 { 291 unsigned int link_id = sdw->instance; 292 void __iomem *shim = sdw->link_res->shim; 293 int spa_mask, cpa_mask; 294 int link_control, ret; 295 296 /* Link power up sequence */ 297 link_control = intel_readl(shim, SDW_SHIM_LCTL); 298 spa_mask = (SDW_SHIM_LCTL_SPA << link_id); 299 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id); 300 link_control |= spa_mask; 301 302 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 303 if (ret < 0) 304 return ret; 305 306 sdw->cdns.link_up = true; 307 return 0; 308 } 309 310 static int intel_shim_init(struct sdw_intel *sdw) 311 { 312 void __iomem *shim = sdw->link_res->shim; 313 unsigned int link_id = sdw->instance; 314 int sync_reg, ret; 315 u16 ioctl = 0, act = 0; 316 317 /* Initialize Shim */ 318 ioctl |= SDW_SHIM_IOCTL_BKE; 319 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 320 321 ioctl |= SDW_SHIM_IOCTL_WPDD; 322 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 323 324 ioctl |= SDW_SHIM_IOCTL_DO; 325 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 326 327 ioctl |= SDW_SHIM_IOCTL_DOE; 328 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 329 330 /* Switch to MIP from Glue logic */ 331 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); 332 333 ioctl &= ~(SDW_SHIM_IOCTL_DOE); 334 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 335 336 ioctl &= ~(SDW_SHIM_IOCTL_DO); 337 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 338 339 ioctl |= (SDW_SHIM_IOCTL_MIF); 340 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 341 342 ioctl &= ~(SDW_SHIM_IOCTL_BKE); 343 ioctl &= ~(SDW_SHIM_IOCTL_COE); 344 345 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 346 347 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS); 348 act |= SDW_SHIM_CTMCTL_DACTQE; 349 act |= SDW_SHIM_CTMCTL_DODS; 350 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); 351 352 /* Now set SyncPRD period */ 353 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 354 sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL << 355 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD)); 356 357 /* Set SyncCPU bit */ 358 sync_reg |= SDW_SHIM_SYNC_SYNCCPU; 359 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, 360 SDW_SHIM_SYNC_SYNCCPU); 361 if (ret < 0) 362 dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret); 363 364 return ret; 365 } 366 367 /* 368 * PDI routines 369 */ 370 static void intel_pdi_init(struct sdw_intel *sdw, 371 struct sdw_cdns_stream_config *config) 372 { 373 void __iomem *shim = sdw->link_res->shim; 374 unsigned int link_id = sdw->instance; 375 int pcm_cap, pdm_cap; 376 377 /* PCM Stream Capability */ 378 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); 379 380 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >> 381 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS); 382 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >> 383 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS); 384 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >> 385 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS); 386 387 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", 388 config->pcm_bd, config->pcm_in, config->pcm_out); 389 390 /* PDM Stream Capability */ 391 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 392 393 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >> 394 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS); 395 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >> 396 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS); 397 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >> 398 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS); 399 400 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n", 401 config->pdm_bd, config->pdm_in, config->pdm_out); 402 } 403 404 static int 405 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm) 406 { 407 void __iomem *shim = sdw->link_res->shim; 408 unsigned int link_id = sdw->instance; 409 int count; 410 411 if (pcm) { 412 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); 413 414 /* 415 * WORKAROUND: on all existing Intel controllers, pdi 416 * number 2 reports channel count as 1 even though it 417 * supports 8 channels. Performing hardcoding for pdi 418 * number 2. 419 */ 420 if (pdi_num == 2) 421 count = 7; 422 423 } else { 424 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 425 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >> 426 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS)); 427 } 428 429 /* zero based values for channel count in register */ 430 count++; 431 432 return count; 433 } 434 435 static int intel_pdi_get_ch_update(struct sdw_intel *sdw, 436 struct sdw_cdns_pdi *pdi, 437 unsigned int num_pdi, 438 unsigned int *num_ch, bool pcm) 439 { 440 int i, ch_count = 0; 441 442 for (i = 0; i < num_pdi; i++) { 443 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); 444 ch_count += pdi->ch_count; 445 pdi++; 446 } 447 448 *num_ch = ch_count; 449 return 0; 450 } 451 452 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw, 453 struct sdw_cdns_streams *stream, bool pcm) 454 { 455 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, 456 &stream->num_ch_bd, pcm); 457 458 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, 459 &stream->num_ch_in, pcm); 460 461 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, 462 &stream->num_ch_out, pcm); 463 464 return 0; 465 } 466 467 static int intel_pdi_ch_update(struct sdw_intel *sdw) 468 { 469 /* First update PCM streams followed by PDM streams */ 470 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); 471 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); 472 473 return 0; 474 } 475 476 static void 477 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 478 { 479 void __iomem *shim = sdw->link_res->shim; 480 unsigned int link_id = sdw->instance; 481 int pdi_conf = 0; 482 483 /* the Bulk and PCM streams are not contiguous */ 484 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; 485 if (pdi->num >= 2) 486 pdi->intel_alh_id += 2; 487 488 /* 489 * Program stream parameters to stream SHIM register 490 * This is applicable for PCM stream only. 491 */ 492 if (pdi->type != SDW_STREAM_PCM) 493 return; 494 495 if (pdi->dir == SDW_DATA_DIR_RX) 496 pdi_conf |= SDW_SHIM_PCMSYCM_DIR; 497 else 498 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR); 499 500 pdi_conf |= (pdi->intel_alh_id << 501 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM)); 502 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN)); 503 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN)); 504 505 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); 506 } 507 508 static void 509 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 510 { 511 void __iomem *alh = sdw->link_res->alh; 512 unsigned int link_id = sdw->instance; 513 unsigned int conf; 514 515 /* the Bulk and PCM streams are not contiguous */ 516 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; 517 if (pdi->num >= 2) 518 pdi->intel_alh_id += 2; 519 520 /* Program Stream config ALH register */ 521 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); 522 523 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL << 524 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT)); 525 526 conf |= ((pdi->ch_count - 1) << 527 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN)); 528 529 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); 530 } 531 532 static int intel_params_stream(struct sdw_intel *sdw, 533 struct snd_pcm_substream *substream, 534 struct snd_soc_dai *dai, 535 struct snd_pcm_hw_params *hw_params, 536 int link_id, int alh_stream_id) 537 { 538 struct sdw_intel_link_res *res = sdw->link_res; 539 struct sdw_intel_stream_params_data params_data; 540 541 params_data.substream = substream; 542 params_data.dai = dai; 543 params_data.hw_params = hw_params; 544 params_data.link_id = link_id; 545 params_data.alh_stream_id = alh_stream_id; 546 547 if (res->ops && res->ops->params_stream && res->dev) 548 return res->ops->params_stream(res->dev, 549 ¶ms_data); 550 return -EIO; 551 } 552 553 static int intel_free_stream(struct sdw_intel *sdw, 554 struct snd_pcm_substream *substream, 555 struct snd_soc_dai *dai, 556 int link_id) 557 { 558 struct sdw_intel_link_res *res = sdw->link_res; 559 struct sdw_intel_stream_free_data free_data; 560 561 free_data.substream = substream; 562 free_data.dai = dai; 563 free_data.link_id = link_id; 564 565 if (res->ops && res->ops->free_stream && res->dev) 566 return res->ops->free_stream(res->dev, 567 &free_data); 568 569 return 0; 570 } 571 572 /* 573 * bank switch routines 574 */ 575 576 static int intel_pre_bank_switch(struct sdw_bus *bus) 577 { 578 struct sdw_cdns *cdns = bus_to_cdns(bus); 579 struct sdw_intel *sdw = cdns_to_intel(cdns); 580 void __iomem *shim = sdw->link_res->shim; 581 int sync_reg; 582 583 /* Write to register only for multi-link */ 584 if (!bus->multi_link) 585 return 0; 586 587 /* Read SYNC register */ 588 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 589 sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance; 590 intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 591 592 return 0; 593 } 594 595 static int intel_post_bank_switch(struct sdw_bus *bus) 596 { 597 struct sdw_cdns *cdns = bus_to_cdns(bus); 598 struct sdw_intel *sdw = cdns_to_intel(cdns); 599 void __iomem *shim = sdw->link_res->shim; 600 int sync_reg, ret; 601 602 /* Write to register only for multi-link */ 603 if (!bus->multi_link) 604 return 0; 605 606 /* Read SYNC register */ 607 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 608 609 /* 610 * post_bank_switch() ops is called from the bus in loop for 611 * all the Masters in the steam with the expectation that 612 * we trigger the bankswitch for the only first Master in the list 613 * and do nothing for the other Masters 614 * 615 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master. 616 */ 617 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) 618 return 0; 619 620 /* 621 * Set SyncGO bit to synchronously trigger a bank switch for 622 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all 623 * the Masters. 624 */ 625 sync_reg |= SDW_SHIM_SYNC_SYNCGO; 626 627 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, 628 SDW_SHIM_SYNC_SYNCGO); 629 if (ret < 0) 630 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret); 631 632 return ret; 633 } 634 635 /* 636 * DAI routines 637 */ 638 639 static int sdw_stream_setup(struct snd_pcm_substream *substream, 640 struct snd_soc_dai *dai) 641 { 642 struct snd_soc_pcm_runtime *rtd = substream->private_data; 643 struct sdw_stream_runtime *sdw_stream = NULL; 644 char *name; 645 int i, ret; 646 647 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 648 name = kasprintf(GFP_KERNEL, "%s-Playback", dai->name); 649 else 650 name = kasprintf(GFP_KERNEL, "%s-Capture", dai->name); 651 652 if (!name) 653 return -ENOMEM; 654 655 sdw_stream = sdw_alloc_stream(name); 656 if (!sdw_stream) { 657 dev_err(dai->dev, "alloc stream failed for DAI %s", dai->name); 658 ret = -ENOMEM; 659 goto error; 660 } 661 662 /* Set stream pointer on CPU DAI */ 663 ret = snd_soc_dai_set_sdw_stream(dai, sdw_stream, substream->stream); 664 if (ret < 0) { 665 dev_err(dai->dev, "failed to set stream pointer on cpu dai %s", 666 dai->name); 667 goto release_stream; 668 } 669 670 /* Set stream pointer on all CODEC DAIs */ 671 for (i = 0; i < rtd->num_codecs; i++) { 672 ret = snd_soc_dai_set_sdw_stream(asoc_rtd_to_codec(rtd, i), sdw_stream, 673 substream->stream); 674 if (ret < 0) { 675 dev_err(dai->dev, "failed to set stream pointer on codec dai %s", 676 asoc_rtd_to_codec(rtd, i)->name); 677 goto release_stream; 678 } 679 } 680 681 return 0; 682 683 release_stream: 684 sdw_release_stream(sdw_stream); 685 error: 686 kfree(name); 687 return ret; 688 } 689 690 static int intel_startup(struct snd_pcm_substream *substream, 691 struct snd_soc_dai *dai) 692 { 693 /* 694 * TODO: add pm_runtime support here, the startup callback 695 * will make sure the IP is 'active' 696 */ 697 698 return sdw_stream_setup(substream, dai); 699 } 700 701 static int intel_hw_params(struct snd_pcm_substream *substream, 702 struct snd_pcm_hw_params *params, 703 struct snd_soc_dai *dai) 704 { 705 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 706 struct sdw_intel *sdw = cdns_to_intel(cdns); 707 struct sdw_cdns_dma_data *dma; 708 struct sdw_cdns_pdi *pdi; 709 struct sdw_stream_config sconfig; 710 struct sdw_port_config *pconfig; 711 int ch, dir; 712 int ret; 713 bool pcm = true; 714 715 dma = snd_soc_dai_get_dma_data(dai, substream); 716 if (!dma) 717 return -EIO; 718 719 ch = params_channels(params); 720 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 721 dir = SDW_DATA_DIR_RX; 722 else 723 dir = SDW_DATA_DIR_TX; 724 725 if (dma->stream_type == SDW_STREAM_PDM) 726 pcm = false; 727 728 if (pcm) 729 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); 730 else 731 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id); 732 733 if (!pdi) { 734 ret = -EINVAL; 735 goto error; 736 } 737 738 /* do run-time configurations for SHIM, ALH and PDI/PORT */ 739 intel_pdi_shim_configure(sdw, pdi); 740 intel_pdi_alh_configure(sdw, pdi); 741 sdw_cdns_config_stream(cdns, ch, dir, pdi); 742 743 744 /* Inform DSP about PDI stream number */ 745 ret = intel_params_stream(sdw, substream, dai, params, 746 sdw->instance, 747 pdi->intel_alh_id); 748 if (ret) 749 goto error; 750 751 sconfig.direction = dir; 752 sconfig.ch_count = ch; 753 sconfig.frame_rate = params_rate(params); 754 sconfig.type = dma->stream_type; 755 756 if (dma->stream_type == SDW_STREAM_PDM) { 757 sconfig.frame_rate *= 50; 758 sconfig.bps = 1; 759 } else { 760 sconfig.bps = snd_pcm_format_width(params_format(params)); 761 } 762 763 /* Port configuration */ 764 pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL); 765 if (!pconfig) { 766 ret = -ENOMEM; 767 goto error; 768 } 769 770 pconfig->num = pdi->num; 771 pconfig->ch_mask = (1 << ch) - 1; 772 773 ret = sdw_stream_add_master(&cdns->bus, &sconfig, 774 pconfig, 1, dma->stream); 775 if (ret) 776 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 777 778 kfree(pconfig); 779 error: 780 return ret; 781 } 782 783 static int intel_prepare(struct snd_pcm_substream *substream, 784 struct snd_soc_dai *dai) 785 { 786 struct sdw_cdns_dma_data *dma; 787 788 dma = snd_soc_dai_get_dma_data(dai, substream); 789 if (!dma) { 790 dev_err(dai->dev, "failed to get dma data in %s", 791 __func__); 792 return -EIO; 793 } 794 795 return sdw_prepare_stream(dma->stream); 796 } 797 798 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, 799 struct snd_soc_dai *dai) 800 { 801 struct sdw_cdns_dma_data *dma; 802 int ret; 803 804 dma = snd_soc_dai_get_dma_data(dai, substream); 805 if (!dma) { 806 dev_err(dai->dev, "failed to get dma data in %s", __func__); 807 return -EIO; 808 } 809 810 switch (cmd) { 811 case SNDRV_PCM_TRIGGER_START: 812 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 813 case SNDRV_PCM_TRIGGER_RESUME: 814 ret = sdw_enable_stream(dma->stream); 815 break; 816 817 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 818 case SNDRV_PCM_TRIGGER_SUSPEND: 819 case SNDRV_PCM_TRIGGER_STOP: 820 ret = sdw_disable_stream(dma->stream); 821 break; 822 823 default: 824 ret = -EINVAL; 825 break; 826 } 827 828 if (ret) 829 dev_err(dai->dev, 830 "%s trigger %d failed: %d", 831 __func__, cmd, ret); 832 return ret; 833 } 834 835 static int 836 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 837 { 838 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 839 struct sdw_intel *sdw = cdns_to_intel(cdns); 840 struct sdw_cdns_dma_data *dma; 841 int ret; 842 843 dma = snd_soc_dai_get_dma_data(dai, substream); 844 if (!dma) 845 return -EIO; 846 847 ret = sdw_deprepare_stream(dma->stream); 848 if (ret) { 849 dev_err(dai->dev, "sdw_deprepare_stream: failed %d", ret); 850 return ret; 851 } 852 853 ret = sdw_stream_remove_master(&cdns->bus, dma->stream); 854 if (ret < 0) { 855 dev_err(dai->dev, "remove master from stream %s failed: %d\n", 856 dma->stream->name, ret); 857 return ret; 858 } 859 860 ret = intel_free_stream(sdw, substream, dai, sdw->instance); 861 if (ret < 0) { 862 dev_err(dai->dev, "intel_free_stream: failed %d", ret); 863 return ret; 864 } 865 866 kfree(dma->stream->name); 867 sdw_release_stream(dma->stream); 868 869 return 0; 870 } 871 872 static void intel_shutdown(struct snd_pcm_substream *substream, 873 struct snd_soc_dai *dai) 874 { 875 struct sdw_cdns_dma_data *dma; 876 877 dma = snd_soc_dai_get_dma_data(dai, substream); 878 if (!dma) 879 return; 880 881 snd_soc_dai_set_dma_data(dai, substream, NULL); 882 kfree(dma); 883 } 884 885 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, 886 void *stream, int direction) 887 { 888 return cdns_set_sdw_stream(dai, stream, true, direction); 889 } 890 891 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai, 892 void *stream, int direction) 893 { 894 return cdns_set_sdw_stream(dai, stream, false, direction); 895 } 896 897 static const struct snd_soc_dai_ops intel_pcm_dai_ops = { 898 .startup = intel_startup, 899 .hw_params = intel_hw_params, 900 .prepare = intel_prepare, 901 .trigger = intel_trigger, 902 .hw_free = intel_hw_free, 903 .shutdown = intel_shutdown, 904 .set_sdw_stream = intel_pcm_set_sdw_stream, 905 }; 906 907 static const struct snd_soc_dai_ops intel_pdm_dai_ops = { 908 .startup = intel_startup, 909 .hw_params = intel_hw_params, 910 .prepare = intel_prepare, 911 .trigger = intel_trigger, 912 .hw_free = intel_hw_free, 913 .shutdown = intel_shutdown, 914 .set_sdw_stream = intel_pdm_set_sdw_stream, 915 }; 916 917 static const struct snd_soc_component_driver dai_component = { 918 .name = "soundwire", 919 }; 920 921 static int intel_create_dai(struct sdw_cdns *cdns, 922 struct snd_soc_dai_driver *dais, 923 enum intel_pdi_type type, 924 u32 num, u32 off, u32 max_ch, bool pcm) 925 { 926 int i; 927 928 if (num == 0) 929 return 0; 930 931 /* TODO: Read supported rates/formats from hardware */ 932 for (i = off; i < (off + num); i++) { 933 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, 934 "SDW%d Pin%d", 935 cdns->instance, i); 936 if (!dais[i].name) 937 return -ENOMEM; 938 939 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { 940 dais[i].playback.channels_min = 1; 941 dais[i].playback.channels_max = max_ch; 942 dais[i].playback.rates = SNDRV_PCM_RATE_48000; 943 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 944 } 945 946 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { 947 dais[i].capture.channels_min = 1; 948 dais[i].capture.channels_max = max_ch; 949 dais[i].capture.rates = SNDRV_PCM_RATE_48000; 950 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 951 } 952 953 if (pcm) 954 dais[i].ops = &intel_pcm_dai_ops; 955 else 956 dais[i].ops = &intel_pdm_dai_ops; 957 } 958 959 return 0; 960 } 961 962 static int intel_register_dai(struct sdw_intel *sdw) 963 { 964 struct sdw_cdns *cdns = &sdw->cdns; 965 struct sdw_cdns_streams *stream; 966 struct snd_soc_dai_driver *dais; 967 int num_dai, ret, off = 0; 968 969 /* DAIs are created based on total number of PDIs supported */ 970 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; 971 972 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); 973 if (!dais) 974 return -ENOMEM; 975 976 /* Create PCM DAIs */ 977 stream = &cdns->pcm; 978 979 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, 980 off, stream->num_ch_in, true); 981 if (ret) 982 return ret; 983 984 off += cdns->pcm.num_in; 985 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, 986 off, stream->num_ch_out, true); 987 if (ret) 988 return ret; 989 990 off += cdns->pcm.num_out; 991 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, 992 off, stream->num_ch_bd, true); 993 if (ret) 994 return ret; 995 996 /* Create PDM DAIs */ 997 stream = &cdns->pdm; 998 off += cdns->pcm.num_bd; 999 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in, 1000 off, stream->num_ch_in, false); 1001 if (ret) 1002 return ret; 1003 1004 off += cdns->pdm.num_in; 1005 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out, 1006 off, stream->num_ch_out, false); 1007 if (ret) 1008 return ret; 1009 1010 off += cdns->pdm.num_out; 1011 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd, 1012 off, stream->num_ch_bd, false); 1013 if (ret) 1014 return ret; 1015 1016 return snd_soc_register_component(cdns->dev, &dai_component, 1017 dais, num_dai); 1018 } 1019 1020 static int sdw_master_read_intel_prop(struct sdw_bus *bus) 1021 { 1022 struct sdw_master_prop *prop = &bus->prop; 1023 struct fwnode_handle *link; 1024 char name[32]; 1025 u32 quirk_mask; 1026 1027 /* Find master handle */ 1028 snprintf(name, sizeof(name), 1029 "mipi-sdw-link-%d-subproperties", bus->link_id); 1030 1031 link = device_get_named_child_node(bus->dev, name); 1032 if (!link) { 1033 dev_err(bus->dev, "Master node %s not found\n", name); 1034 return -EIO; 1035 } 1036 1037 fwnode_property_read_u32(link, 1038 "intel-sdw-ip-clock", 1039 &prop->mclk_freq); 1040 1041 /* the values reported by BIOS are the 2x clock, not the bus clock */ 1042 prop->mclk_freq /= 2; 1043 1044 fwnode_property_read_u32(link, 1045 "intel-quirk-mask", 1046 &quirk_mask); 1047 1048 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE) 1049 prop->hw_disabled = true; 1050 1051 return 0; 1052 } 1053 1054 static int intel_prop_read(struct sdw_bus *bus) 1055 { 1056 /* Initialize with default handler to read all DisCo properties */ 1057 sdw_master_read_prop(bus); 1058 1059 /* read Intel-specific properties */ 1060 sdw_master_read_intel_prop(bus); 1061 1062 return 0; 1063 } 1064 1065 static struct sdw_master_ops sdw_intel_ops = { 1066 .read_prop = sdw_master_read_prop, 1067 .xfer_msg = cdns_xfer_msg, 1068 .xfer_msg_defer = cdns_xfer_msg_defer, 1069 .reset_page_addr = cdns_reset_page_addr, 1070 .set_bus_conf = cdns_bus_conf, 1071 .pre_bank_switch = intel_pre_bank_switch, 1072 .post_bank_switch = intel_post_bank_switch, 1073 }; 1074 1075 static int intel_init(struct sdw_intel *sdw) 1076 { 1077 /* Initialize shim and controller */ 1078 intel_link_power_up(sdw); 1079 intel_shim_init(sdw); 1080 1081 return sdw_cdns_init(&sdw->cdns); 1082 } 1083 1084 /* 1085 * probe and init 1086 */ 1087 static int intel_probe(struct platform_device *pdev) 1088 { 1089 struct sdw_cdns_stream_config config; 1090 struct sdw_intel *sdw; 1091 int ret; 1092 1093 sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL); 1094 if (!sdw) 1095 return -ENOMEM; 1096 1097 sdw->instance = pdev->id; 1098 sdw->link_res = dev_get_platdata(&pdev->dev); 1099 sdw->cdns.dev = &pdev->dev; 1100 sdw->cdns.registers = sdw->link_res->registers; 1101 sdw->cdns.instance = sdw->instance; 1102 sdw->cdns.msg_count = 0; 1103 sdw->cdns.bus.link_id = pdev->id; 1104 1105 sdw_cdns_probe(&sdw->cdns); 1106 1107 /* Set property read ops */ 1108 sdw_intel_ops.read_prop = intel_prop_read; 1109 sdw->cdns.bus.ops = &sdw_intel_ops; 1110 1111 platform_set_drvdata(pdev, sdw); 1112 1113 ret = sdw_bus_master_add(&sdw->cdns.bus, &pdev->dev, pdev->dev.fwnode); 1114 if (ret) { 1115 dev_err(&pdev->dev, "sdw_bus_master_add fail: %d\n", ret); 1116 return ret; 1117 } 1118 1119 if (sdw->cdns.bus.prop.hw_disabled) { 1120 dev_info(&pdev->dev, "SoundWire master %d is disabled, ignoring\n", 1121 sdw->cdns.bus.link_id); 1122 return 0; 1123 } 1124 1125 /* Initialize shim, controller and Cadence IP */ 1126 ret = intel_init(sdw); 1127 if (ret) 1128 goto err_init; 1129 1130 /* Read the PDI config and initialize cadence PDI */ 1131 intel_pdi_init(sdw, &config); 1132 ret = sdw_cdns_pdi_init(&sdw->cdns, config); 1133 if (ret) 1134 goto err_init; 1135 1136 intel_pdi_ch_update(sdw); 1137 1138 /* Acquire IRQ */ 1139 ret = request_threaded_irq(sdw->link_res->irq, 1140 sdw_cdns_irq, sdw_cdns_thread, 1141 IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns); 1142 if (ret < 0) { 1143 dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n", 1144 sdw->link_res->irq); 1145 goto err_init; 1146 } 1147 1148 ret = sdw_cdns_enable_interrupt(&sdw->cdns, true); 1149 if (ret < 0) { 1150 dev_err(sdw->cdns.dev, "cannot enable interrupts\n"); 1151 goto err_init; 1152 } 1153 1154 ret = sdw_cdns_exit_reset(&sdw->cdns); 1155 if (ret < 0) { 1156 dev_err(sdw->cdns.dev, "unable to exit bus reset sequence\n"); 1157 goto err_interrupt; 1158 } 1159 1160 /* Register DAIs */ 1161 ret = intel_register_dai(sdw); 1162 if (ret) { 1163 dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret); 1164 snd_soc_unregister_component(sdw->cdns.dev); 1165 goto err_interrupt; 1166 } 1167 1168 intel_debugfs_init(sdw); 1169 1170 return 0; 1171 1172 err_interrupt: 1173 sdw_cdns_enable_interrupt(&sdw->cdns, false); 1174 free_irq(sdw->link_res->irq, sdw); 1175 err_init: 1176 sdw_bus_master_delete(&sdw->cdns.bus); 1177 return ret; 1178 } 1179 1180 static int intel_remove(struct platform_device *pdev) 1181 { 1182 struct sdw_intel *sdw; 1183 1184 sdw = platform_get_drvdata(pdev); 1185 1186 if (!sdw->cdns.bus.prop.hw_disabled) { 1187 intel_debugfs_exit(sdw); 1188 sdw_cdns_enable_interrupt(&sdw->cdns, false); 1189 free_irq(sdw->link_res->irq, sdw); 1190 snd_soc_unregister_component(sdw->cdns.dev); 1191 } 1192 sdw_bus_master_delete(&sdw->cdns.bus); 1193 1194 return 0; 1195 } 1196 1197 static struct platform_driver sdw_intel_drv = { 1198 .probe = intel_probe, 1199 .remove = intel_remove, 1200 .driver = { 1201 .name = "int-sdw", 1202 1203 }, 1204 }; 1205 1206 module_platform_driver(sdw_intel_drv); 1207 1208 MODULE_LICENSE("Dual BSD/GPL"); 1209 MODULE_ALIAS("platform:int-sdw"); 1210 MODULE_DESCRIPTION("Intel Soundwire Master Driver"); 1211