1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // Copyright(c) 2015-17 Intel Corporation. 3 4 /* 5 * Soundwire Intel Master Driver 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/auxiliary_bus.h> 15 #include <sound/pcm_params.h> 16 #include <linux/pm_runtime.h> 17 #include <sound/soc.h> 18 #include <linux/soundwire/sdw_registers.h> 19 #include <linux/soundwire/sdw.h> 20 #include <linux/soundwire/sdw_intel.h> 21 #include "cadence_master.h" 22 #include "bus.h" 23 #include "intel.h" 24 25 #define INTEL_MASTER_SUSPEND_DELAY_MS 3000 26 27 /* 28 * debug/config flags for the Intel SoundWire Master. 29 * 30 * Since we may have multiple masters active, we can have up to 8 31 * flags reused in each byte, with master0 using the ls-byte, etc. 32 */ 33 34 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME BIT(0) 35 #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP BIT(1) 36 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE BIT(2) 37 #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK BIT(3) 38 39 static int md_flags; 40 module_param_named(sdw_md_flags, md_flags, int, 0444); 41 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)"); 42 43 /* Intel SHIM Registers Definition */ 44 #define SDW_SHIM_LCAP 0x0 45 #define SDW_SHIM_LCTL 0x4 46 #define SDW_SHIM_IPPTR 0x8 47 #define SDW_SHIM_SYNC 0xC 48 49 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 50 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 51 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 52 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 53 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 54 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 55 56 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 57 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 58 #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) 59 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 60 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 61 62 #define SDW_SHIM_WAKEEN 0x190 63 #define SDW_SHIM_WAKESTS 0x192 64 65 #define SDW_SHIM_LCTL_SPA BIT(0) 66 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0) 67 #define SDW_SHIM_LCTL_CPA BIT(8) 68 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8) 69 70 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1) 71 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1) 72 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) 73 #define SDW_SHIM_SYNC_SYNCCPU BIT(15) 74 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) 75 #define SDW_SHIM_SYNC_CMDSYNC BIT(16) 76 #define SDW_SHIM_SYNC_SYNCGO BIT(24) 77 78 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) 79 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) 80 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) 81 82 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) 83 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) 84 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) 85 #define SDW_SHIM_PCMSYCM_DIR BIT(15) 86 87 #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) 88 #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) 89 #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) 90 #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) 91 92 #define SDW_SHIM_IOCTL_MIF BIT(0) 93 #define SDW_SHIM_IOCTL_CO BIT(1) 94 #define SDW_SHIM_IOCTL_COE BIT(2) 95 #define SDW_SHIM_IOCTL_DO BIT(3) 96 #define SDW_SHIM_IOCTL_DOE BIT(4) 97 #define SDW_SHIM_IOCTL_BKE BIT(5) 98 #define SDW_SHIM_IOCTL_WPDD BIT(6) 99 #define SDW_SHIM_IOCTL_CIBD BIT(8) 100 #define SDW_SHIM_IOCTL_DIBD BIT(9) 101 102 #define SDW_SHIM_CTMCTL_DACTQE BIT(0) 103 #define SDW_SHIM_CTMCTL_DODS BIT(1) 104 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) 105 106 #define SDW_SHIM_WAKEEN_ENABLE BIT(0) 107 #define SDW_SHIM_WAKESTS_STATUS BIT(0) 108 109 /* Intel ALH Register definitions */ 110 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) 111 #define SDW_ALH_NUM_STREAMS 64 112 113 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 114 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) 115 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) 116 117 enum intel_pdi_type { 118 INTEL_PDI_IN = 0, 119 INTEL_PDI_OUT = 1, 120 INTEL_PDI_BD = 2, 121 }; 122 123 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) 124 125 /* 126 * Read, write helpers for HW registers 127 */ 128 static inline int intel_readl(void __iomem *base, int offset) 129 { 130 return readl(base + offset); 131 } 132 133 static inline void intel_writel(void __iomem *base, int offset, int value) 134 { 135 writel(value, base + offset); 136 } 137 138 static inline u16 intel_readw(void __iomem *base, int offset) 139 { 140 return readw(base + offset); 141 } 142 143 static inline void intel_writew(void __iomem *base, int offset, u16 value) 144 { 145 writew(value, base + offset); 146 } 147 148 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target) 149 { 150 int timeout = 10; 151 u32 reg_read; 152 153 do { 154 reg_read = readl(base + offset); 155 if ((reg_read & mask) == target) 156 return 0; 157 158 timeout--; 159 usleep_range(50, 100); 160 } while (timeout != 0); 161 162 return -EAGAIN; 163 } 164 165 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) 166 { 167 writel(value, base + offset); 168 return intel_wait_bit(base, offset, mask, 0); 169 } 170 171 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) 172 { 173 writel(value, base + offset); 174 return intel_wait_bit(base, offset, mask, mask); 175 } 176 177 /* 178 * debugfs 179 */ 180 #ifdef CONFIG_DEBUG_FS 181 182 #define RD_BUF (2 * PAGE_SIZE) 183 184 static ssize_t intel_sprintf(void __iomem *mem, bool l, 185 char *buf, size_t pos, unsigned int reg) 186 { 187 int value; 188 189 if (l) 190 value = intel_readl(mem, reg); 191 else 192 value = intel_readw(mem, reg); 193 194 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value); 195 } 196 197 static int intel_reg_show(struct seq_file *s_file, void *data) 198 { 199 struct sdw_intel *sdw = s_file->private; 200 void __iomem *s = sdw->link_res->shim; 201 void __iomem *a = sdw->link_res->alh; 202 char *buf; 203 ssize_t ret; 204 int i, j; 205 unsigned int links, reg; 206 207 buf = kzalloc(RD_BUF, GFP_KERNEL); 208 if (!buf) 209 return -ENOMEM; 210 211 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0); 212 213 ret = scnprintf(buf, RD_BUF, "Register Value\n"); 214 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n"); 215 216 for (i = 0; i < links; i++) { 217 reg = SDW_SHIM_LCAP + i * 4; 218 ret += intel_sprintf(s, true, buf, ret, reg); 219 } 220 221 for (i = 0; i < links; i++) { 222 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i); 223 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i)); 224 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i)); 225 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i)); 226 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i)); 227 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i)); 228 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i)); 229 230 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n"); 231 232 /* 233 * the value 10 is the number of PDIs. We will need a 234 * cleanup to remove hard-coded Intel configurations 235 * from cadence_master.c 236 */ 237 for (j = 0; j < 10; j++) { 238 ret += intel_sprintf(s, false, buf, ret, 239 SDW_SHIM_PCMSYCHM(i, j)); 240 ret += intel_sprintf(s, false, buf, ret, 241 SDW_SHIM_PCMSYCHC(i, j)); 242 } 243 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n"); 244 245 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i)); 246 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i)); 247 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i)); 248 } 249 250 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n"); 251 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN); 252 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS); 253 254 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n"); 255 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++) 256 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i)); 257 258 seq_printf(s_file, "%s", buf); 259 kfree(buf); 260 261 return 0; 262 } 263 DEFINE_SHOW_ATTRIBUTE(intel_reg); 264 265 static int intel_set_m_datamode(void *data, u64 value) 266 { 267 struct sdw_intel *sdw = data; 268 struct sdw_bus *bus = &sdw->cdns.bus; 269 270 if (value > SDW_PORT_DATA_MODE_STATIC_1) 271 return -EINVAL; 272 273 /* Userspace changed the hardware state behind the kernel's back */ 274 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 275 276 bus->params.m_data_mode = value; 277 278 return 0; 279 } 280 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL, 281 intel_set_m_datamode, "%llu\n"); 282 283 static int intel_set_s_datamode(void *data, u64 value) 284 { 285 struct sdw_intel *sdw = data; 286 struct sdw_bus *bus = &sdw->cdns.bus; 287 288 if (value > SDW_PORT_DATA_MODE_STATIC_1) 289 return -EINVAL; 290 291 /* Userspace changed the hardware state behind the kernel's back */ 292 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 293 294 bus->params.s_data_mode = value; 295 296 return 0; 297 } 298 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL, 299 intel_set_s_datamode, "%llu\n"); 300 301 static void intel_debugfs_init(struct sdw_intel *sdw) 302 { 303 struct dentry *root = sdw->cdns.bus.debugfs; 304 305 if (!root) 306 return; 307 308 sdw->debugfs = debugfs_create_dir("intel-sdw", root); 309 310 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw, 311 &intel_reg_fops); 312 313 debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw, 314 &intel_set_m_datamode_fops); 315 316 debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw, 317 &intel_set_s_datamode_fops); 318 319 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs); 320 } 321 322 static void intel_debugfs_exit(struct sdw_intel *sdw) 323 { 324 debugfs_remove_recursive(sdw->debugfs); 325 } 326 #else 327 static void intel_debugfs_init(struct sdw_intel *sdw) {} 328 static void intel_debugfs_exit(struct sdw_intel *sdw) {} 329 #endif /* CONFIG_DEBUG_FS */ 330 331 /* 332 * shim ops 333 */ 334 335 static int intel_link_power_up(struct sdw_intel *sdw) 336 { 337 unsigned int link_id = sdw->instance; 338 void __iomem *shim = sdw->link_res->shim; 339 u32 *shim_mask = sdw->link_res->shim_mask; 340 struct sdw_bus *bus = &sdw->cdns.bus; 341 struct sdw_master_prop *prop = &bus->prop; 342 u32 spa_mask, cpa_mask; 343 u32 link_control; 344 int ret = 0; 345 u32 syncprd; 346 u32 sync_reg; 347 348 mutex_lock(sdw->link_res->shim_lock); 349 350 /* 351 * The hardware relies on an internal counter, typically 4kHz, 352 * to generate the SoundWire SSP - which defines a 'safe' 353 * synchronization point between commands and audio transport 354 * and allows for multi link synchronization. The SYNCPRD value 355 * is only dependent on the oscillator clock provided to 356 * the IP, so adjust based on _DSD properties reported in DSDT 357 * tables. The values reported are based on either 24MHz 358 * (CNL/CML) or 38.4 MHz (ICL/TGL+). 359 */ 360 if (prop->mclk_freq % 6000000) 361 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; 362 else 363 syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24; 364 365 if (!*shim_mask) { 366 dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__); 367 368 /* we first need to program the SyncPRD/CPU registers */ 369 dev_dbg(sdw->cdns.dev, 370 "%s: first link up, programming SYNCPRD\n", __func__); 371 372 /* set SyncPRD period */ 373 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 374 u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD); 375 376 /* Set SyncCPU bit */ 377 sync_reg |= SDW_SHIM_SYNC_SYNCCPU; 378 intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 379 380 /* Link power up sequence */ 381 link_control = intel_readl(shim, SDW_SHIM_LCTL); 382 383 /* only power-up enabled links */ 384 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask); 385 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); 386 387 link_control |= spa_mask; 388 389 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 390 if (ret < 0) { 391 dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret); 392 goto out; 393 } 394 395 /* SyncCPU will change once link is active */ 396 ret = intel_wait_bit(shim, SDW_SHIM_SYNC, 397 SDW_SHIM_SYNC_SYNCCPU, 0); 398 if (ret < 0) { 399 dev_err(sdw->cdns.dev, 400 "Failed to set SHIM_SYNC: %d\n", ret); 401 goto out; 402 } 403 } 404 405 *shim_mask |= BIT(link_id); 406 407 sdw->cdns.link_up = true; 408 out: 409 mutex_unlock(sdw->link_res->shim_lock); 410 411 return ret; 412 } 413 414 /* this needs to be called with shim_lock */ 415 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw) 416 { 417 void __iomem *shim = sdw->link_res->shim; 418 unsigned int link_id = sdw->instance; 419 u16 ioctl; 420 421 /* Switch to MIP from Glue logic */ 422 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); 423 424 ioctl &= ~(SDW_SHIM_IOCTL_DOE); 425 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 426 usleep_range(10, 15); 427 428 ioctl &= ~(SDW_SHIM_IOCTL_DO); 429 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 430 usleep_range(10, 15); 431 432 ioctl |= (SDW_SHIM_IOCTL_MIF); 433 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 434 usleep_range(10, 15); 435 436 ioctl &= ~(SDW_SHIM_IOCTL_BKE); 437 ioctl &= ~(SDW_SHIM_IOCTL_COE); 438 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 439 usleep_range(10, 15); 440 441 /* at this point Master IP has full control of the I/Os */ 442 } 443 444 /* this needs to be called with shim_lock */ 445 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw) 446 { 447 unsigned int link_id = sdw->instance; 448 void __iomem *shim = sdw->link_res->shim; 449 u16 ioctl; 450 451 /* Glue logic */ 452 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); 453 ioctl |= SDW_SHIM_IOCTL_BKE; 454 ioctl |= SDW_SHIM_IOCTL_COE; 455 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 456 usleep_range(10, 15); 457 458 ioctl &= ~(SDW_SHIM_IOCTL_MIF); 459 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 460 usleep_range(10, 15); 461 462 /* at this point Integration Glue has full control of the I/Os */ 463 } 464 465 static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop) 466 { 467 void __iomem *shim = sdw->link_res->shim; 468 unsigned int link_id = sdw->instance; 469 int ret = 0; 470 u16 ioctl = 0, act = 0; 471 472 mutex_lock(sdw->link_res->shim_lock); 473 474 /* Initialize Shim */ 475 ioctl |= SDW_SHIM_IOCTL_BKE; 476 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 477 usleep_range(10, 15); 478 479 ioctl |= SDW_SHIM_IOCTL_WPDD; 480 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 481 usleep_range(10, 15); 482 483 ioctl |= SDW_SHIM_IOCTL_DO; 484 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 485 usleep_range(10, 15); 486 487 ioctl |= SDW_SHIM_IOCTL_DOE; 488 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 489 usleep_range(10, 15); 490 491 intel_shim_glue_to_master_ip(sdw); 492 493 u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS); 494 act |= SDW_SHIM_CTMCTL_DACTQE; 495 act |= SDW_SHIM_CTMCTL_DODS; 496 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); 497 usleep_range(10, 15); 498 499 mutex_unlock(sdw->link_res->shim_lock); 500 501 return ret; 502 } 503 504 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 505 { 506 void __iomem *shim = sdw->link_res->shim; 507 unsigned int link_id = sdw->instance; 508 u16 wake_en, wake_sts; 509 510 mutex_lock(sdw->link_res->shim_lock); 511 wake_en = intel_readw(shim, SDW_SHIM_WAKEEN); 512 513 if (wake_enable) { 514 /* Enable the wakeup */ 515 wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id); 516 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en); 517 } else { 518 /* Disable the wake up interrupt */ 519 wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id); 520 intel_writew(shim, SDW_SHIM_WAKEEN, wake_en); 521 522 /* Clear wake status */ 523 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); 524 wake_sts |= (SDW_SHIM_WAKEEN_ENABLE << link_id); 525 intel_writew(shim, SDW_SHIM_WAKESTS_STATUS, wake_sts); 526 } 527 mutex_unlock(sdw->link_res->shim_lock); 528 } 529 530 static int intel_link_power_down(struct sdw_intel *sdw) 531 { 532 u32 link_control, spa_mask, cpa_mask; 533 unsigned int link_id = sdw->instance; 534 void __iomem *shim = sdw->link_res->shim; 535 u32 *shim_mask = sdw->link_res->shim_mask; 536 int ret = 0; 537 538 mutex_lock(sdw->link_res->shim_lock); 539 540 intel_shim_master_ip_to_glue(sdw); 541 542 if (!(*shim_mask & BIT(link_id))) 543 dev_err(sdw->cdns.dev, 544 "%s: Unbalanced power-up/down calls\n", __func__); 545 546 *shim_mask &= ~BIT(link_id); 547 548 if (!*shim_mask) { 549 550 dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__); 551 552 /* Link power down sequence */ 553 link_control = intel_readl(shim, SDW_SHIM_LCTL); 554 555 /* only power-down enabled links */ 556 spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask); 557 cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask); 558 559 link_control &= spa_mask; 560 561 ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 562 } 563 564 mutex_unlock(sdw->link_res->shim_lock); 565 566 if (ret < 0) { 567 dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__); 568 569 return ret; 570 } 571 572 sdw->cdns.link_up = false; 573 return 0; 574 } 575 576 static void intel_shim_sync_arm(struct sdw_intel *sdw) 577 { 578 void __iomem *shim = sdw->link_res->shim; 579 u32 sync_reg; 580 581 mutex_lock(sdw->link_res->shim_lock); 582 583 /* update SYNC register */ 584 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 585 sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance); 586 intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 587 588 mutex_unlock(sdw->link_res->shim_lock); 589 } 590 591 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw) 592 { 593 void __iomem *shim = sdw->link_res->shim; 594 u32 sync_reg; 595 int ret; 596 597 /* Read SYNC register */ 598 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 599 600 /* 601 * Set SyncGO bit to synchronously trigger a bank switch for 602 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all 603 * the Masters. 604 */ 605 sync_reg |= SDW_SHIM_SYNC_SYNCGO; 606 607 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, 608 SDW_SHIM_SYNC_SYNCGO); 609 610 if (ret < 0) 611 dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret); 612 613 return ret; 614 } 615 616 static int intel_shim_sync_go(struct sdw_intel *sdw) 617 { 618 int ret; 619 620 mutex_lock(sdw->link_res->shim_lock); 621 622 ret = intel_shim_sync_go_unlocked(sdw); 623 624 mutex_unlock(sdw->link_res->shim_lock); 625 626 return ret; 627 } 628 629 /* 630 * PDI routines 631 */ 632 static void intel_pdi_init(struct sdw_intel *sdw, 633 struct sdw_cdns_stream_config *config) 634 { 635 void __iomem *shim = sdw->link_res->shim; 636 unsigned int link_id = sdw->instance; 637 int pcm_cap, pdm_cap; 638 639 /* PCM Stream Capability */ 640 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); 641 642 config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap); 643 config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap); 644 config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap); 645 646 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", 647 config->pcm_bd, config->pcm_in, config->pcm_out); 648 649 /* PDM Stream Capability */ 650 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 651 652 config->pdm_bd = FIELD_GET(SDW_SHIM_PDMSCAP_BSS, pdm_cap); 653 config->pdm_in = FIELD_GET(SDW_SHIM_PDMSCAP_ISS, pdm_cap); 654 config->pdm_out = FIELD_GET(SDW_SHIM_PDMSCAP_OSS, pdm_cap); 655 656 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n", 657 config->pdm_bd, config->pdm_in, config->pdm_out); 658 } 659 660 static int 661 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm) 662 { 663 void __iomem *shim = sdw->link_res->shim; 664 unsigned int link_id = sdw->instance; 665 int count; 666 667 if (pcm) { 668 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); 669 670 /* 671 * WORKAROUND: on all existing Intel controllers, pdi 672 * number 2 reports channel count as 1 even though it 673 * supports 8 channels. Performing hardcoding for pdi 674 * number 2. 675 */ 676 if (pdi_num == 2) 677 count = 7; 678 679 } else { 680 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 681 count = FIELD_GET(SDW_SHIM_PDMSCAP_CPSS, count); 682 } 683 684 /* zero based values for channel count in register */ 685 count++; 686 687 return count; 688 } 689 690 static int intel_pdi_get_ch_update(struct sdw_intel *sdw, 691 struct sdw_cdns_pdi *pdi, 692 unsigned int num_pdi, 693 unsigned int *num_ch, bool pcm) 694 { 695 int i, ch_count = 0; 696 697 for (i = 0; i < num_pdi; i++) { 698 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); 699 ch_count += pdi->ch_count; 700 pdi++; 701 } 702 703 *num_ch = ch_count; 704 return 0; 705 } 706 707 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw, 708 struct sdw_cdns_streams *stream, bool pcm) 709 { 710 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, 711 &stream->num_ch_bd, pcm); 712 713 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, 714 &stream->num_ch_in, pcm); 715 716 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, 717 &stream->num_ch_out, pcm); 718 719 return 0; 720 } 721 722 static int intel_pdi_ch_update(struct sdw_intel *sdw) 723 { 724 /* First update PCM streams followed by PDM streams */ 725 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); 726 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); 727 728 return 0; 729 } 730 731 static void 732 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 733 { 734 void __iomem *shim = sdw->link_res->shim; 735 unsigned int link_id = sdw->instance; 736 int pdi_conf = 0; 737 738 /* the Bulk and PCM streams are not contiguous */ 739 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; 740 if (pdi->num >= 2) 741 pdi->intel_alh_id += 2; 742 743 /* 744 * Program stream parameters to stream SHIM register 745 * This is applicable for PCM stream only. 746 */ 747 if (pdi->type != SDW_STREAM_PCM) 748 return; 749 750 if (pdi->dir == SDW_DATA_DIR_RX) 751 pdi_conf |= SDW_SHIM_PCMSYCM_DIR; 752 else 753 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR); 754 755 u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM); 756 u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN); 757 u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN); 758 759 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); 760 } 761 762 static void 763 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 764 { 765 void __iomem *alh = sdw->link_res->alh; 766 unsigned int link_id = sdw->instance; 767 unsigned int conf; 768 769 /* the Bulk and PCM streams are not contiguous */ 770 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3; 771 if (pdi->num >= 2) 772 pdi->intel_alh_id += 2; 773 774 /* Program Stream config ALH register */ 775 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); 776 777 u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT); 778 u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN); 779 780 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); 781 } 782 783 static int intel_params_stream(struct sdw_intel *sdw, 784 struct snd_pcm_substream *substream, 785 struct snd_soc_dai *dai, 786 struct snd_pcm_hw_params *hw_params, 787 int link_id, int alh_stream_id) 788 { 789 struct sdw_intel_link_res *res = sdw->link_res; 790 struct sdw_intel_stream_params_data params_data; 791 792 params_data.substream = substream; 793 params_data.dai = dai; 794 params_data.hw_params = hw_params; 795 params_data.link_id = link_id; 796 params_data.alh_stream_id = alh_stream_id; 797 798 if (res->ops && res->ops->params_stream && res->dev) 799 return res->ops->params_stream(res->dev, 800 ¶ms_data); 801 return -EIO; 802 } 803 804 static int intel_free_stream(struct sdw_intel *sdw, 805 struct snd_pcm_substream *substream, 806 struct snd_soc_dai *dai, 807 int link_id) 808 { 809 struct sdw_intel_link_res *res = sdw->link_res; 810 struct sdw_intel_stream_free_data free_data; 811 812 free_data.substream = substream; 813 free_data.dai = dai; 814 free_data.link_id = link_id; 815 816 if (res->ops && res->ops->free_stream && res->dev) 817 return res->ops->free_stream(res->dev, 818 &free_data); 819 820 return 0; 821 } 822 823 /* 824 * bank switch routines 825 */ 826 827 static int intel_pre_bank_switch(struct sdw_bus *bus) 828 { 829 struct sdw_cdns *cdns = bus_to_cdns(bus); 830 struct sdw_intel *sdw = cdns_to_intel(cdns); 831 832 /* Write to register only for multi-link */ 833 if (!bus->multi_link) 834 return 0; 835 836 intel_shim_sync_arm(sdw); 837 838 return 0; 839 } 840 841 static int intel_post_bank_switch(struct sdw_bus *bus) 842 { 843 struct sdw_cdns *cdns = bus_to_cdns(bus); 844 struct sdw_intel *sdw = cdns_to_intel(cdns); 845 void __iomem *shim = sdw->link_res->shim; 846 int sync_reg, ret; 847 848 /* Write to register only for multi-link */ 849 if (!bus->multi_link) 850 return 0; 851 852 mutex_lock(sdw->link_res->shim_lock); 853 854 /* Read SYNC register */ 855 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 856 857 /* 858 * post_bank_switch() ops is called from the bus in loop for 859 * all the Masters in the steam with the expectation that 860 * we trigger the bankswitch for the only first Master in the list 861 * and do nothing for the other Masters 862 * 863 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master. 864 */ 865 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) { 866 ret = 0; 867 goto unlock; 868 } 869 870 ret = intel_shim_sync_go_unlocked(sdw); 871 unlock: 872 mutex_unlock(sdw->link_res->shim_lock); 873 874 if (ret < 0) 875 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret); 876 877 return ret; 878 } 879 880 /* 881 * DAI routines 882 */ 883 884 static int intel_startup(struct snd_pcm_substream *substream, 885 struct snd_soc_dai *dai) 886 { 887 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 888 int ret; 889 890 ret = pm_runtime_get_sync(cdns->dev); 891 if (ret < 0 && ret != -EACCES) { 892 dev_err_ratelimited(cdns->dev, 893 "pm_runtime_get_sync failed in %s, ret %d\n", 894 __func__, ret); 895 pm_runtime_put_noidle(cdns->dev); 896 return ret; 897 } 898 return 0; 899 } 900 901 static int intel_hw_params(struct snd_pcm_substream *substream, 902 struct snd_pcm_hw_params *params, 903 struct snd_soc_dai *dai) 904 { 905 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 906 struct sdw_intel *sdw = cdns_to_intel(cdns); 907 struct sdw_cdns_dma_data *dma; 908 struct sdw_cdns_pdi *pdi; 909 struct sdw_stream_config sconfig; 910 struct sdw_port_config *pconfig; 911 int ch, dir; 912 int ret; 913 bool pcm = true; 914 915 dma = snd_soc_dai_get_dma_data(dai, substream); 916 if (!dma) 917 return -EIO; 918 919 ch = params_channels(params); 920 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 921 dir = SDW_DATA_DIR_RX; 922 else 923 dir = SDW_DATA_DIR_TX; 924 925 if (dma->stream_type == SDW_STREAM_PDM) 926 pcm = false; 927 928 if (pcm) 929 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id); 930 else 931 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id); 932 933 if (!pdi) { 934 ret = -EINVAL; 935 goto error; 936 } 937 938 /* do run-time configurations for SHIM, ALH and PDI/PORT */ 939 intel_pdi_shim_configure(sdw, pdi); 940 intel_pdi_alh_configure(sdw, pdi); 941 sdw_cdns_config_stream(cdns, ch, dir, pdi); 942 943 /* store pdi and hw_params, may be needed in prepare step */ 944 dma->suspended = false; 945 dma->pdi = pdi; 946 dma->hw_params = params; 947 948 /* Inform DSP about PDI stream number */ 949 ret = intel_params_stream(sdw, substream, dai, params, 950 sdw->instance, 951 pdi->intel_alh_id); 952 if (ret) 953 goto error; 954 955 sconfig.direction = dir; 956 sconfig.ch_count = ch; 957 sconfig.frame_rate = params_rate(params); 958 sconfig.type = dma->stream_type; 959 960 if (dma->stream_type == SDW_STREAM_PDM) { 961 sconfig.frame_rate *= 50; 962 sconfig.bps = 1; 963 } else { 964 sconfig.bps = snd_pcm_format_width(params_format(params)); 965 } 966 967 /* Port configuration */ 968 pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL); 969 if (!pconfig) { 970 ret = -ENOMEM; 971 goto error; 972 } 973 974 pconfig->num = pdi->num; 975 pconfig->ch_mask = (1 << ch) - 1; 976 977 ret = sdw_stream_add_master(&cdns->bus, &sconfig, 978 pconfig, 1, dma->stream); 979 if (ret) 980 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 981 982 kfree(pconfig); 983 error: 984 return ret; 985 } 986 987 static int intel_prepare(struct snd_pcm_substream *substream, 988 struct snd_soc_dai *dai) 989 { 990 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 991 struct sdw_intel *sdw = cdns_to_intel(cdns); 992 struct sdw_cdns_dma_data *dma; 993 int ch, dir; 994 int ret = 0; 995 996 dma = snd_soc_dai_get_dma_data(dai, substream); 997 if (!dma) { 998 dev_err(dai->dev, "failed to get dma data in %s\n", 999 __func__); 1000 return -EIO; 1001 } 1002 1003 if (dma->suspended) { 1004 dma->suspended = false; 1005 1006 /* 1007 * .prepare() is called after system resume, where we 1008 * need to reinitialize the SHIM/ALH/Cadence IP. 1009 * .prepare() is also called to deal with underflows, 1010 * but in those cases we cannot touch ALH/SHIM 1011 * registers 1012 */ 1013 1014 /* configure stream */ 1015 ch = params_channels(dma->hw_params); 1016 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1017 dir = SDW_DATA_DIR_RX; 1018 else 1019 dir = SDW_DATA_DIR_TX; 1020 1021 intel_pdi_shim_configure(sdw, dma->pdi); 1022 intel_pdi_alh_configure(sdw, dma->pdi); 1023 sdw_cdns_config_stream(cdns, ch, dir, dma->pdi); 1024 1025 /* Inform DSP about PDI stream number */ 1026 ret = intel_params_stream(sdw, substream, dai, 1027 dma->hw_params, 1028 sdw->instance, 1029 dma->pdi->intel_alh_id); 1030 } 1031 1032 return ret; 1033 } 1034 1035 static int 1036 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 1037 { 1038 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 1039 struct sdw_intel *sdw = cdns_to_intel(cdns); 1040 struct sdw_cdns_dma_data *dma; 1041 int ret; 1042 1043 dma = snd_soc_dai_get_dma_data(dai, substream); 1044 if (!dma) 1045 return -EIO; 1046 1047 /* 1048 * The sdw stream state will transition to RELEASED when stream-> 1049 * master_list is empty. So the stream state will transition to 1050 * DEPREPARED for the first cpu-dai and to RELEASED for the last 1051 * cpu-dai. 1052 */ 1053 ret = sdw_stream_remove_master(&cdns->bus, dma->stream); 1054 if (ret < 0) { 1055 dev_err(dai->dev, "remove master from stream %s failed: %d\n", 1056 dma->stream->name, ret); 1057 return ret; 1058 } 1059 1060 ret = intel_free_stream(sdw, substream, dai, sdw->instance); 1061 if (ret < 0) { 1062 dev_err(dai->dev, "intel_free_stream: failed %d\n", ret); 1063 return ret; 1064 } 1065 1066 dma->hw_params = NULL; 1067 dma->pdi = NULL; 1068 1069 return 0; 1070 } 1071 1072 static void intel_shutdown(struct snd_pcm_substream *substream, 1073 struct snd_soc_dai *dai) 1074 { 1075 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 1076 1077 pm_runtime_mark_last_busy(cdns->dev); 1078 pm_runtime_put_autosuspend(cdns->dev); 1079 } 1080 1081 static int intel_component_dais_suspend(struct snd_soc_component *component) 1082 { 1083 struct sdw_cdns_dma_data *dma; 1084 struct snd_soc_dai *dai; 1085 1086 for_each_component_dais(component, dai) { 1087 /* 1088 * we don't have a .suspend dai_ops, and we don't have access 1089 * to the substream, so let's mark both capture and playback 1090 * DMA contexts as suspended 1091 */ 1092 dma = dai->playback_dma_data; 1093 if (dma) 1094 dma->suspended = true; 1095 1096 dma = dai->capture_dma_data; 1097 if (dma) 1098 dma->suspended = true; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, 1105 void *stream, int direction) 1106 { 1107 return cdns_set_sdw_stream(dai, stream, true, direction); 1108 } 1109 1110 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai, 1111 void *stream, int direction) 1112 { 1113 return cdns_set_sdw_stream(dai, stream, false, direction); 1114 } 1115 1116 static void *intel_get_sdw_stream(struct snd_soc_dai *dai, 1117 int direction) 1118 { 1119 struct sdw_cdns_dma_data *dma; 1120 1121 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 1122 dma = dai->playback_dma_data; 1123 else 1124 dma = dai->capture_dma_data; 1125 1126 if (!dma) 1127 return ERR_PTR(-EINVAL); 1128 1129 return dma->stream; 1130 } 1131 1132 static const struct snd_soc_dai_ops intel_pcm_dai_ops = { 1133 .startup = intel_startup, 1134 .hw_params = intel_hw_params, 1135 .prepare = intel_prepare, 1136 .hw_free = intel_hw_free, 1137 .shutdown = intel_shutdown, 1138 .set_sdw_stream = intel_pcm_set_sdw_stream, 1139 .get_sdw_stream = intel_get_sdw_stream, 1140 }; 1141 1142 static const struct snd_soc_dai_ops intel_pdm_dai_ops = { 1143 .startup = intel_startup, 1144 .hw_params = intel_hw_params, 1145 .prepare = intel_prepare, 1146 .hw_free = intel_hw_free, 1147 .shutdown = intel_shutdown, 1148 .set_sdw_stream = intel_pdm_set_sdw_stream, 1149 .get_sdw_stream = intel_get_sdw_stream, 1150 }; 1151 1152 static const struct snd_soc_component_driver dai_component = { 1153 .name = "soundwire", 1154 .suspend = intel_component_dais_suspend 1155 }; 1156 1157 static int intel_create_dai(struct sdw_cdns *cdns, 1158 struct snd_soc_dai_driver *dais, 1159 enum intel_pdi_type type, 1160 u32 num, u32 off, u32 max_ch, bool pcm) 1161 { 1162 int i; 1163 1164 if (num == 0) 1165 return 0; 1166 1167 /* TODO: Read supported rates/formats from hardware */ 1168 for (i = off; i < (off + num); i++) { 1169 dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL, 1170 "SDW%d Pin%d", 1171 cdns->instance, i); 1172 if (!dais[i].name) 1173 return -ENOMEM; 1174 1175 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { 1176 dais[i].playback.channels_min = 1; 1177 dais[i].playback.channels_max = max_ch; 1178 dais[i].playback.rates = SNDRV_PCM_RATE_48000; 1179 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 1180 } 1181 1182 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { 1183 dais[i].capture.channels_min = 1; 1184 dais[i].capture.channels_max = max_ch; 1185 dais[i].capture.rates = SNDRV_PCM_RATE_48000; 1186 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 1187 } 1188 1189 if (pcm) 1190 dais[i].ops = &intel_pcm_dai_ops; 1191 else 1192 dais[i].ops = &intel_pdm_dai_ops; 1193 } 1194 1195 return 0; 1196 } 1197 1198 static int intel_register_dai(struct sdw_intel *sdw) 1199 { 1200 struct sdw_cdns *cdns = &sdw->cdns; 1201 struct sdw_cdns_streams *stream; 1202 struct snd_soc_dai_driver *dais; 1203 int num_dai, ret, off = 0; 1204 1205 /* DAIs are created based on total number of PDIs supported */ 1206 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; 1207 1208 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); 1209 if (!dais) 1210 return -ENOMEM; 1211 1212 /* Create PCM DAIs */ 1213 stream = &cdns->pcm; 1214 1215 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in, 1216 off, stream->num_ch_in, true); 1217 if (ret) 1218 return ret; 1219 1220 off += cdns->pcm.num_in; 1221 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, 1222 off, stream->num_ch_out, true); 1223 if (ret) 1224 return ret; 1225 1226 off += cdns->pcm.num_out; 1227 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, 1228 off, stream->num_ch_bd, true); 1229 if (ret) 1230 return ret; 1231 1232 /* Create PDM DAIs */ 1233 stream = &cdns->pdm; 1234 off += cdns->pcm.num_bd; 1235 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in, 1236 off, stream->num_ch_in, false); 1237 if (ret) 1238 return ret; 1239 1240 off += cdns->pdm.num_in; 1241 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out, 1242 off, stream->num_ch_out, false); 1243 if (ret) 1244 return ret; 1245 1246 off += cdns->pdm.num_out; 1247 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd, 1248 off, stream->num_ch_bd, false); 1249 if (ret) 1250 return ret; 1251 1252 return snd_soc_register_component(cdns->dev, &dai_component, 1253 dais, num_dai); 1254 } 1255 1256 static int sdw_master_read_intel_prop(struct sdw_bus *bus) 1257 { 1258 struct sdw_master_prop *prop = &bus->prop; 1259 struct fwnode_handle *link; 1260 char name[32]; 1261 u32 quirk_mask; 1262 1263 /* Find master handle */ 1264 snprintf(name, sizeof(name), 1265 "mipi-sdw-link-%d-subproperties", bus->link_id); 1266 1267 link = device_get_named_child_node(bus->dev, name); 1268 if (!link) { 1269 dev_err(bus->dev, "Master node %s not found\n", name); 1270 return -EIO; 1271 } 1272 1273 fwnode_property_read_u32(link, 1274 "intel-sdw-ip-clock", 1275 &prop->mclk_freq); 1276 1277 /* the values reported by BIOS are the 2x clock, not the bus clock */ 1278 prop->mclk_freq /= 2; 1279 1280 fwnode_property_read_u32(link, 1281 "intel-quirk-mask", 1282 &quirk_mask); 1283 1284 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE) 1285 prop->hw_disabled = true; 1286 1287 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH | 1288 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY; 1289 1290 return 0; 1291 } 1292 1293 static int intel_prop_read(struct sdw_bus *bus) 1294 { 1295 /* Initialize with default handler to read all DisCo properties */ 1296 sdw_master_read_prop(bus); 1297 1298 /* read Intel-specific properties */ 1299 sdw_master_read_intel_prop(bus); 1300 1301 return 0; 1302 } 1303 1304 static struct sdw_master_ops sdw_intel_ops = { 1305 .read_prop = sdw_master_read_prop, 1306 .override_adr = sdw_dmi_override_adr, 1307 .xfer_msg = cdns_xfer_msg, 1308 .xfer_msg_defer = cdns_xfer_msg_defer, 1309 .reset_page_addr = cdns_reset_page_addr, 1310 .set_bus_conf = cdns_bus_conf, 1311 .pre_bank_switch = intel_pre_bank_switch, 1312 .post_bank_switch = intel_post_bank_switch, 1313 }; 1314 1315 static int intel_init(struct sdw_intel *sdw) 1316 { 1317 bool clock_stop; 1318 1319 /* Initialize shim and controller */ 1320 intel_link_power_up(sdw); 1321 1322 clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns); 1323 1324 intel_shim_init(sdw, clock_stop); 1325 1326 return 0; 1327 } 1328 1329 /* 1330 * probe and init (aux_dev_id argument is required by function prototype but not used) 1331 */ 1332 static int intel_link_probe(struct auxiliary_device *auxdev, 1333 const struct auxiliary_device_id *aux_dev_id) 1334 1335 { 1336 struct device *dev = &auxdev->dev; 1337 struct sdw_intel_link_dev *ldev = auxiliary_dev_to_sdw_intel_link_dev(auxdev); 1338 struct sdw_intel *sdw; 1339 struct sdw_cdns *cdns; 1340 struct sdw_bus *bus; 1341 int ret; 1342 1343 sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL); 1344 if (!sdw) 1345 return -ENOMEM; 1346 1347 cdns = &sdw->cdns; 1348 bus = &cdns->bus; 1349 1350 sdw->instance = auxdev->id; 1351 sdw->link_res = &ldev->link_res; 1352 cdns->dev = dev; 1353 cdns->registers = sdw->link_res->registers; 1354 cdns->instance = sdw->instance; 1355 cdns->msg_count = 0; 1356 1357 bus->link_id = auxdev->id; 1358 1359 sdw_cdns_probe(cdns); 1360 1361 /* Set property read ops */ 1362 sdw_intel_ops.read_prop = intel_prop_read; 1363 bus->ops = &sdw_intel_ops; 1364 1365 /* set driver data, accessed by snd_soc_dai_get_drvdata() */ 1366 dev_set_drvdata(dev, cdns); 1367 1368 /* use generic bandwidth allocation algorithm */ 1369 sdw->cdns.bus.compute_params = sdw_compute_params; 1370 1371 ret = sdw_bus_master_add(bus, dev, dev->fwnode); 1372 if (ret) { 1373 dev_err(dev, "sdw_bus_master_add fail: %d\n", ret); 1374 return ret; 1375 } 1376 1377 if (bus->prop.hw_disabled) 1378 dev_info(dev, 1379 "SoundWire master %d is disabled, will be ignored\n", 1380 bus->link_id); 1381 /* 1382 * Ignore BIOS err_threshold, it's a really bad idea when dealing 1383 * with multiple hardware synchronized links 1384 */ 1385 bus->prop.err_threshold = 0; 1386 1387 return 0; 1388 } 1389 1390 int intel_link_startup(struct auxiliary_device *auxdev) 1391 { 1392 struct sdw_cdns_stream_config config; 1393 struct device *dev = &auxdev->dev; 1394 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1395 struct sdw_intel *sdw = cdns_to_intel(cdns); 1396 struct sdw_bus *bus = &cdns->bus; 1397 int link_flags; 1398 bool multi_link; 1399 u32 clock_stop_quirks; 1400 int ret; 1401 1402 if (bus->prop.hw_disabled) { 1403 dev_info(dev, 1404 "SoundWire master %d is disabled, ignoring\n", 1405 sdw->instance); 1406 return 0; 1407 } 1408 1409 link_flags = md_flags >> (bus->link_id * 8); 1410 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1411 if (!multi_link) { 1412 dev_dbg(dev, "Multi-link is disabled\n"); 1413 bus->multi_link = false; 1414 } else { 1415 /* 1416 * hardware-based synchronization is required regardless 1417 * of the number of segments used by a stream: SSP-based 1418 * synchronization is gated by gsync when the multi-master 1419 * mode is set. 1420 */ 1421 bus->multi_link = true; 1422 bus->hw_sync_min_links = 1; 1423 } 1424 1425 /* Initialize shim, controller */ 1426 ret = intel_init(sdw); 1427 if (ret) 1428 goto err_init; 1429 1430 /* Read the PDI config and initialize cadence PDI */ 1431 intel_pdi_init(sdw, &config); 1432 ret = sdw_cdns_pdi_init(cdns, config); 1433 if (ret) 1434 goto err_init; 1435 1436 intel_pdi_ch_update(sdw); 1437 1438 ret = sdw_cdns_enable_interrupt(cdns, true); 1439 if (ret < 0) { 1440 dev_err(dev, "cannot enable interrupts\n"); 1441 goto err_init; 1442 } 1443 1444 /* 1445 * follow recommended programming flows to avoid timeouts when 1446 * gsync is enabled 1447 */ 1448 if (multi_link) 1449 intel_shim_sync_arm(sdw); 1450 1451 ret = sdw_cdns_init(cdns); 1452 if (ret < 0) { 1453 dev_err(dev, "unable to initialize Cadence IP\n"); 1454 goto err_interrupt; 1455 } 1456 1457 ret = sdw_cdns_exit_reset(cdns); 1458 if (ret < 0) { 1459 dev_err(dev, "unable to exit bus reset sequence\n"); 1460 goto err_interrupt; 1461 } 1462 1463 if (multi_link) { 1464 ret = intel_shim_sync_go(sdw); 1465 if (ret < 0) { 1466 dev_err(dev, "sync go failed: %d\n", ret); 1467 goto err_interrupt; 1468 } 1469 } 1470 1471 /* Register DAIs */ 1472 ret = intel_register_dai(sdw); 1473 if (ret) { 1474 dev_err(dev, "DAI registration failed: %d\n", ret); 1475 snd_soc_unregister_component(dev); 1476 goto err_interrupt; 1477 } 1478 1479 intel_debugfs_init(sdw); 1480 1481 /* Enable runtime PM */ 1482 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) { 1483 pm_runtime_set_autosuspend_delay(dev, 1484 INTEL_MASTER_SUSPEND_DELAY_MS); 1485 pm_runtime_use_autosuspend(dev); 1486 pm_runtime_mark_last_busy(dev); 1487 1488 pm_runtime_set_active(dev); 1489 pm_runtime_enable(dev); 1490 } 1491 1492 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1493 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) { 1494 /* 1495 * To keep the clock running we need to prevent 1496 * pm_runtime suspend from happening by increasing the 1497 * reference count. 1498 * This quirk is specified by the parent PCI device in 1499 * case of specific latency requirements. It will have 1500 * no effect if pm_runtime is disabled by the user via 1501 * a module parameter for testing purposes. 1502 */ 1503 pm_runtime_get_noresume(dev); 1504 } 1505 1506 /* 1507 * The runtime PM status of Slave devices is "Unsupported" 1508 * until they report as ATTACHED. If they don't, e.g. because 1509 * there are no Slave devices populated or if the power-on is 1510 * delayed or dependent on a power switch, the Master will 1511 * remain active and prevent its parent from suspending. 1512 * 1513 * Conditionally force the pm_runtime core to re-evaluate the 1514 * Master status in the absence of any Slave activity. A quirk 1515 * is provided to e.g. deal with Slaves that may be powered on 1516 * with a delay. A more complete solution would require the 1517 * definition of Master properties. 1518 */ 1519 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE)) 1520 pm_runtime_idle(dev); 1521 1522 return 0; 1523 1524 err_interrupt: 1525 sdw_cdns_enable_interrupt(cdns, false); 1526 err_init: 1527 return ret; 1528 } 1529 1530 static void intel_link_remove(struct auxiliary_device *auxdev) 1531 { 1532 struct device *dev = &auxdev->dev; 1533 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1534 struct sdw_intel *sdw = cdns_to_intel(cdns); 1535 struct sdw_bus *bus = &cdns->bus; 1536 1537 /* 1538 * Since pm_runtime is already disabled, we don't decrease 1539 * the refcount when the clock_stop_quirk is 1540 * SDW_INTEL_CLK_STOP_NOT_ALLOWED 1541 */ 1542 if (!bus->prop.hw_disabled) { 1543 intel_debugfs_exit(sdw); 1544 sdw_cdns_enable_interrupt(cdns, false); 1545 snd_soc_unregister_component(dev); 1546 } 1547 sdw_bus_master_delete(bus); 1548 } 1549 1550 int intel_link_process_wakeen_event(struct auxiliary_device *auxdev) 1551 { 1552 struct device *dev = &auxdev->dev; 1553 struct sdw_intel *sdw; 1554 struct sdw_bus *bus; 1555 void __iomem *shim; 1556 u16 wake_sts; 1557 1558 sdw = dev_get_drvdata(dev); 1559 bus = &sdw->cdns.bus; 1560 1561 if (bus->prop.hw_disabled) { 1562 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", bus->link_id); 1563 return 0; 1564 } 1565 1566 shim = sdw->link_res->shim; 1567 wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS); 1568 1569 if (!(wake_sts & BIT(sdw->instance))) 1570 return 0; 1571 1572 /* disable WAKEEN interrupt ASAP to prevent interrupt flood */ 1573 intel_shim_wake(sdw, false); 1574 1575 /* 1576 * resume the Master, which will generate a bus reset and result in 1577 * Slaves re-attaching and be re-enumerated. The SoundWire physical 1578 * device which generated the wake will trigger an interrupt, which 1579 * will in turn cause the corresponding Linux Slave device to be 1580 * resumed and the Slave codec driver to check the status. 1581 */ 1582 pm_request_resume(dev); 1583 1584 return 0; 1585 } 1586 1587 /* 1588 * PM calls 1589 */ 1590 1591 static int __maybe_unused intel_suspend(struct device *dev) 1592 { 1593 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1594 struct sdw_intel *sdw = cdns_to_intel(cdns); 1595 struct sdw_bus *bus = &cdns->bus; 1596 u32 clock_stop_quirks; 1597 int ret; 1598 1599 if (bus->prop.hw_disabled) { 1600 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", 1601 bus->link_id); 1602 return 0; 1603 } 1604 1605 if (pm_runtime_suspended(dev)) { 1606 dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__); 1607 1608 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1609 1610 if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET || 1611 !clock_stop_quirks) && 1612 !pm_runtime_suspended(dev->parent)) { 1613 1614 /* 1615 * if we've enabled clock stop, and the parent 1616 * is still active, disable shim wake. The 1617 * SHIM registers are not accessible if the 1618 * parent is already pm_runtime suspended so 1619 * it's too late to change that configuration 1620 */ 1621 1622 intel_shim_wake(sdw, false); 1623 } 1624 1625 return 0; 1626 } 1627 1628 ret = sdw_cdns_enable_interrupt(cdns, false); 1629 if (ret < 0) { 1630 dev_err(dev, "cannot disable interrupts on suspend\n"); 1631 return ret; 1632 } 1633 1634 ret = intel_link_power_down(sdw); 1635 if (ret) { 1636 dev_err(dev, "Link power down failed: %d\n", ret); 1637 return ret; 1638 } 1639 1640 intel_shim_wake(sdw, false); 1641 1642 return 0; 1643 } 1644 1645 static int __maybe_unused intel_suspend_runtime(struct device *dev) 1646 { 1647 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1648 struct sdw_intel *sdw = cdns_to_intel(cdns); 1649 struct sdw_bus *bus = &cdns->bus; 1650 u32 clock_stop_quirks; 1651 int ret; 1652 1653 if (bus->prop.hw_disabled) { 1654 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", 1655 bus->link_id); 1656 return 0; 1657 } 1658 1659 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1660 1661 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) { 1662 1663 ret = sdw_cdns_enable_interrupt(cdns, false); 1664 if (ret < 0) { 1665 dev_err(dev, "cannot disable interrupts on suspend\n"); 1666 return ret; 1667 } 1668 1669 ret = intel_link_power_down(sdw); 1670 if (ret) { 1671 dev_err(dev, "Link power down failed: %d\n", ret); 1672 return ret; 1673 } 1674 1675 intel_shim_wake(sdw, false); 1676 1677 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET || 1678 !clock_stop_quirks) { 1679 bool wake_enable = true; 1680 1681 ret = sdw_cdns_clock_stop(cdns, true); 1682 if (ret < 0) { 1683 dev_err(dev, "cannot enable clock stop on suspend\n"); 1684 wake_enable = false; 1685 } 1686 1687 ret = sdw_cdns_enable_interrupt(cdns, false); 1688 if (ret < 0) { 1689 dev_err(dev, "cannot disable interrupts on suspend\n"); 1690 return ret; 1691 } 1692 1693 ret = intel_link_power_down(sdw); 1694 if (ret) { 1695 dev_err(dev, "Link power down failed: %d\n", ret); 1696 return ret; 1697 } 1698 1699 intel_shim_wake(sdw, wake_enable); 1700 } else { 1701 dev_err(dev, "%s clock_stop_quirks %x unsupported\n", 1702 __func__, clock_stop_quirks); 1703 ret = -EINVAL; 1704 } 1705 1706 return ret; 1707 } 1708 1709 static int __maybe_unused intel_resume(struct device *dev) 1710 { 1711 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1712 struct sdw_intel *sdw = cdns_to_intel(cdns); 1713 struct sdw_bus *bus = &cdns->bus; 1714 int link_flags; 1715 bool multi_link; 1716 int ret; 1717 1718 if (bus->prop.hw_disabled) { 1719 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", 1720 bus->link_id); 1721 return 0; 1722 } 1723 1724 link_flags = md_flags >> (bus->link_id * 8); 1725 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1726 1727 if (pm_runtime_suspended(dev)) { 1728 dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__); 1729 1730 /* follow required sequence from runtime_pm.rst */ 1731 pm_runtime_disable(dev); 1732 pm_runtime_set_active(dev); 1733 pm_runtime_mark_last_busy(dev); 1734 pm_runtime_enable(dev); 1735 1736 link_flags = md_flags >> (bus->link_id * 8); 1737 1738 if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE)) 1739 pm_runtime_idle(dev); 1740 } 1741 1742 ret = intel_init(sdw); 1743 if (ret) { 1744 dev_err(dev, "%s failed: %d\n", __func__, ret); 1745 return ret; 1746 } 1747 1748 /* 1749 * make sure all Slaves are tagged as UNATTACHED and provide 1750 * reason for reinitialization 1751 */ 1752 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1753 1754 ret = sdw_cdns_enable_interrupt(cdns, true); 1755 if (ret < 0) { 1756 dev_err(dev, "cannot enable interrupts during resume\n"); 1757 return ret; 1758 } 1759 1760 /* 1761 * follow recommended programming flows to avoid timeouts when 1762 * gsync is enabled 1763 */ 1764 if (multi_link) 1765 intel_shim_sync_arm(sdw); 1766 1767 ret = sdw_cdns_init(&sdw->cdns); 1768 if (ret < 0) { 1769 dev_err(dev, "unable to initialize Cadence IP during resume\n"); 1770 return ret; 1771 } 1772 1773 ret = sdw_cdns_exit_reset(cdns); 1774 if (ret < 0) { 1775 dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1776 return ret; 1777 } 1778 1779 if (multi_link) { 1780 ret = intel_shim_sync_go(sdw); 1781 if (ret < 0) { 1782 dev_err(dev, "sync go failed during resume\n"); 1783 return ret; 1784 } 1785 } 1786 1787 /* 1788 * after system resume, the pm_runtime suspend() may kick in 1789 * during the enumeration, before any children device force the 1790 * master device to remain active. Using pm_runtime_get() 1791 * routines is not really possible, since it'd prevent the 1792 * master from suspending. 1793 * A reasonable compromise is to update the pm_runtime 1794 * counters and delay the pm_runtime suspend by several 1795 * seconds, by when all enumeration should be complete. 1796 */ 1797 pm_runtime_mark_last_busy(dev); 1798 1799 return ret; 1800 } 1801 1802 static int __maybe_unused intel_resume_runtime(struct device *dev) 1803 { 1804 struct sdw_cdns *cdns = dev_get_drvdata(dev); 1805 struct sdw_intel *sdw = cdns_to_intel(cdns); 1806 struct sdw_bus *bus = &cdns->bus; 1807 u32 clock_stop_quirks; 1808 bool clock_stop0; 1809 int link_flags; 1810 bool multi_link; 1811 int status; 1812 int ret; 1813 1814 if (bus->prop.hw_disabled) { 1815 dev_dbg(dev, "SoundWire master %d is disabled, ignoring\n", 1816 bus->link_id); 1817 return 0; 1818 } 1819 1820 link_flags = md_flags >> (bus->link_id * 8); 1821 multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK); 1822 1823 clock_stop_quirks = sdw->link_res->clock_stop_quirks; 1824 1825 if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) { 1826 ret = intel_init(sdw); 1827 if (ret) { 1828 dev_err(dev, "%s failed: %d\n", __func__, ret); 1829 return ret; 1830 } 1831 1832 /* 1833 * make sure all Slaves are tagged as UNATTACHED and provide 1834 * reason for reinitialization 1835 */ 1836 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET); 1837 1838 ret = sdw_cdns_enable_interrupt(cdns, true); 1839 if (ret < 0) { 1840 dev_err(dev, "cannot enable interrupts during resume\n"); 1841 return ret; 1842 } 1843 1844 /* 1845 * follow recommended programming flows to avoid 1846 * timeouts when gsync is enabled 1847 */ 1848 if (multi_link) 1849 intel_shim_sync_arm(sdw); 1850 1851 ret = sdw_cdns_init(&sdw->cdns); 1852 if (ret < 0) { 1853 dev_err(dev, "unable to initialize Cadence IP during resume\n"); 1854 return ret; 1855 } 1856 1857 ret = sdw_cdns_exit_reset(cdns); 1858 if (ret < 0) { 1859 dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1860 return ret; 1861 } 1862 1863 if (multi_link) { 1864 ret = intel_shim_sync_go(sdw); 1865 if (ret < 0) { 1866 dev_err(dev, "sync go failed during resume\n"); 1867 return ret; 1868 } 1869 } 1870 } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) { 1871 ret = intel_init(sdw); 1872 if (ret) { 1873 dev_err(dev, "%s failed: %d\n", __func__, ret); 1874 return ret; 1875 } 1876 1877 /* 1878 * An exception condition occurs for the CLK_STOP_BUS_RESET 1879 * case if one or more masters remain active. In this condition, 1880 * all the masters are powered on for they are in the same power 1881 * domain. Master can preserve its context for clock stop0, so 1882 * there is no need to clear slave status and reset bus. 1883 */ 1884 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); 1885 1886 if (!clock_stop0) { 1887 1888 /* 1889 * make sure all Slaves are tagged as UNATTACHED and 1890 * provide reason for reinitialization 1891 */ 1892 1893 status = SDW_UNATTACH_REQUEST_MASTER_RESET; 1894 sdw_clear_slave_status(bus, status); 1895 1896 ret = sdw_cdns_enable_interrupt(cdns, true); 1897 if (ret < 0) { 1898 dev_err(dev, "cannot enable interrupts during resume\n"); 1899 return ret; 1900 } 1901 1902 /* 1903 * follow recommended programming flows to avoid 1904 * timeouts when gsync is enabled 1905 */ 1906 if (multi_link) 1907 intel_shim_sync_arm(sdw); 1908 1909 /* 1910 * Re-initialize the IP since it was powered-off 1911 */ 1912 sdw_cdns_init(&sdw->cdns); 1913 1914 } else { 1915 ret = sdw_cdns_enable_interrupt(cdns, true); 1916 if (ret < 0) { 1917 dev_err(dev, "cannot enable interrupts during resume\n"); 1918 return ret; 1919 } 1920 } 1921 1922 ret = sdw_cdns_clock_restart(cdns, !clock_stop0); 1923 if (ret < 0) { 1924 dev_err(dev, "unable to restart clock during resume\n"); 1925 return ret; 1926 } 1927 1928 if (!clock_stop0) { 1929 ret = sdw_cdns_exit_reset(cdns); 1930 if (ret < 0) { 1931 dev_err(dev, "unable to exit bus reset sequence during resume\n"); 1932 return ret; 1933 } 1934 1935 if (multi_link) { 1936 ret = intel_shim_sync_go(sdw); 1937 if (ret < 0) { 1938 dev_err(sdw->cdns.dev, "sync go failed during resume\n"); 1939 return ret; 1940 } 1941 } 1942 } 1943 } else if (!clock_stop_quirks) { 1944 1945 clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns); 1946 if (!clock_stop0) 1947 dev_err(dev, "%s invalid configuration, clock was not stopped", __func__); 1948 1949 ret = intel_init(sdw); 1950 if (ret) { 1951 dev_err(dev, "%s failed: %d\n", __func__, ret); 1952 return ret; 1953 } 1954 1955 ret = sdw_cdns_enable_interrupt(cdns, true); 1956 if (ret < 0) { 1957 dev_err(dev, "cannot enable interrupts during resume\n"); 1958 return ret; 1959 } 1960 1961 ret = sdw_cdns_clock_restart(cdns, false); 1962 if (ret < 0) { 1963 dev_err(dev, "unable to resume master during resume\n"); 1964 return ret; 1965 } 1966 } else { 1967 dev_err(dev, "%s clock_stop_quirks %x unsupported\n", 1968 __func__, clock_stop_quirks); 1969 ret = -EINVAL; 1970 } 1971 1972 return ret; 1973 } 1974 1975 static const struct dev_pm_ops intel_pm = { 1976 SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume) 1977 SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL) 1978 }; 1979 1980 static const struct auxiliary_device_id intel_link_id_table[] = { 1981 { .name = "soundwire_intel.link" }, 1982 {}, 1983 }; 1984 MODULE_DEVICE_TABLE(auxiliary, intel_link_id_table); 1985 1986 static struct auxiliary_driver sdw_intel_drv = { 1987 .probe = intel_link_probe, 1988 .remove = intel_link_remove, 1989 .driver = { 1990 /* auxiliary_driver_register() sets .name to be the modname */ 1991 .pm = &intel_pm, 1992 }, 1993 .id_table = intel_link_id_table 1994 }; 1995 module_auxiliary_driver(sdw_intel_drv); 1996 1997 MODULE_LICENSE("Dual BSD/GPL"); 1998 MODULE_DESCRIPTION("Intel Soundwire Link Driver"); 1999