1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 // Copyright(c) 2015-17 Intel Corporation. 3 4 /* 5 * Soundwire Intel Master Driver 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/delay.h> 10 #include <linux/module.h> 11 #include <linux/interrupt.h> 12 #include <linux/platform_device.h> 13 #include <sound/pcm_params.h> 14 #include <sound/soc.h> 15 #include <linux/soundwire/sdw_registers.h> 16 #include <linux/soundwire/sdw.h> 17 #include <linux/soundwire/sdw_intel.h> 18 #include "cadence_master.h" 19 #include "intel.h" 20 21 /* Intel SHIM Registers Definition */ 22 #define SDW_SHIM_LCAP 0x0 23 #define SDW_SHIM_LCTL 0x4 24 #define SDW_SHIM_IPPTR 0x8 25 #define SDW_SHIM_SYNC 0xC 26 27 #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x)) 28 #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x)) 29 #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x)) 30 #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x)) 31 #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x)) 32 #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x)) 33 34 #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y))) 35 #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y))) 36 #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x)) 37 #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x)) 38 #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x)) 39 40 #define SDW_SHIM_WAKEEN 0x190 41 #define SDW_SHIM_WAKESTS 0x192 42 43 #define SDW_SHIM_LCTL_SPA BIT(0) 44 #define SDW_SHIM_LCTL_CPA BIT(8) 45 46 #define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F 47 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) 48 #define SDW_SHIM_SYNC_SYNCCPU BIT(15) 49 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) 50 #define SDW_SHIM_SYNC_CMDSYNC BIT(16) 51 #define SDW_SHIM_SYNC_SYNCGO BIT(24) 52 53 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) 54 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) 55 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) 56 57 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) 58 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) 59 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) 60 #define SDW_SHIM_PCMSYCM_DIR BIT(15) 61 62 #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) 63 #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) 64 #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) 65 #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) 66 67 #define SDW_SHIM_IOCTL_MIF BIT(0) 68 #define SDW_SHIM_IOCTL_CO BIT(1) 69 #define SDW_SHIM_IOCTL_COE BIT(2) 70 #define SDW_SHIM_IOCTL_DO BIT(3) 71 #define SDW_SHIM_IOCTL_DOE BIT(4) 72 #define SDW_SHIM_IOCTL_BKE BIT(5) 73 #define SDW_SHIM_IOCTL_WPDD BIT(6) 74 #define SDW_SHIM_IOCTL_CIBD BIT(8) 75 #define SDW_SHIM_IOCTL_DIBD BIT(9) 76 77 #define SDW_SHIM_CTMCTL_DACTQE BIT(0) 78 #define SDW_SHIM_CTMCTL_DODS BIT(1) 79 #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) 80 81 #define SDW_SHIM_WAKEEN_ENABLE BIT(0) 82 #define SDW_SHIM_WAKESTS_STATUS BIT(0) 83 84 /* Intel ALH Register definitions */ 85 #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x))) 86 87 #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 88 #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) 89 #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) 90 91 enum intel_pdi_type { 92 INTEL_PDI_IN = 0, 93 INTEL_PDI_OUT = 1, 94 INTEL_PDI_BD = 2, 95 }; 96 97 struct sdw_intel { 98 struct sdw_cdns cdns; 99 int instance; 100 struct sdw_intel_link_res *res; 101 }; 102 103 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) 104 105 /* 106 * Read, write helpers for HW registers 107 */ 108 static inline int intel_readl(void __iomem *base, int offset) 109 { 110 return readl(base + offset); 111 } 112 113 static inline void intel_writel(void __iomem *base, int offset, int value) 114 { 115 writel(value, base + offset); 116 } 117 118 static inline u16 intel_readw(void __iomem *base, int offset) 119 { 120 return readw(base + offset); 121 } 122 123 static inline void intel_writew(void __iomem *base, int offset, u16 value) 124 { 125 writew(value, base + offset); 126 } 127 128 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) 129 { 130 int timeout = 10; 131 u32 reg_read; 132 133 writel(value, base + offset); 134 do { 135 reg_read = readl(base + offset); 136 if (!(reg_read & mask)) 137 return 0; 138 139 timeout--; 140 udelay(50); 141 } while (timeout != 0); 142 143 return -EAGAIN; 144 } 145 146 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) 147 { 148 int timeout = 10; 149 u32 reg_read; 150 151 writel(value, base + offset); 152 do { 153 reg_read = readl(base + offset); 154 if (reg_read & mask) 155 return 0; 156 157 timeout--; 158 udelay(50); 159 } while (timeout != 0); 160 161 return -EAGAIN; 162 } 163 164 /* 165 * shim ops 166 */ 167 168 static int intel_link_power_up(struct sdw_intel *sdw) 169 { 170 unsigned int link_id = sdw->instance; 171 void __iomem *shim = sdw->res->shim; 172 int spa_mask, cpa_mask; 173 int link_control, ret; 174 175 /* Link power up sequence */ 176 link_control = intel_readl(shim, SDW_SHIM_LCTL); 177 spa_mask = (SDW_SHIM_LCTL_SPA << link_id); 178 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id); 179 link_control |= spa_mask; 180 181 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); 182 if (ret < 0) 183 return ret; 184 185 sdw->cdns.link_up = true; 186 return 0; 187 } 188 189 static int intel_shim_init(struct sdw_intel *sdw) 190 { 191 void __iomem *shim = sdw->res->shim; 192 unsigned int link_id = sdw->instance; 193 int sync_reg, ret; 194 u16 ioctl = 0, act = 0; 195 196 /* Initialize Shim */ 197 ioctl |= SDW_SHIM_IOCTL_BKE; 198 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 199 200 ioctl |= SDW_SHIM_IOCTL_WPDD; 201 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 202 203 ioctl |= SDW_SHIM_IOCTL_DO; 204 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 205 206 ioctl |= SDW_SHIM_IOCTL_DOE; 207 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 208 209 /* Switch to MIP from Glue logic */ 210 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); 211 212 ioctl &= ~(SDW_SHIM_IOCTL_DOE); 213 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 214 215 ioctl &= ~(SDW_SHIM_IOCTL_DO); 216 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 217 218 ioctl |= (SDW_SHIM_IOCTL_MIF); 219 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 220 221 ioctl &= ~(SDW_SHIM_IOCTL_BKE); 222 ioctl &= ~(SDW_SHIM_IOCTL_COE); 223 224 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); 225 226 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS); 227 act |= SDW_SHIM_CTMCTL_DACTQE; 228 act |= SDW_SHIM_CTMCTL_DODS; 229 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); 230 231 /* Now set SyncPRD period */ 232 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 233 sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL << 234 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD)); 235 236 /* Set SyncCPU bit */ 237 sync_reg |= SDW_SHIM_SYNC_SYNCCPU; 238 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, 239 SDW_SHIM_SYNC_SYNCCPU); 240 if (ret < 0) 241 dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret); 242 243 return ret; 244 } 245 246 /* 247 * PDI routines 248 */ 249 static void intel_pdi_init(struct sdw_intel *sdw, 250 struct sdw_cdns_stream_config *config) 251 { 252 void __iomem *shim = sdw->res->shim; 253 unsigned int link_id = sdw->instance; 254 int pcm_cap, pdm_cap; 255 256 /* PCM Stream Capability */ 257 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); 258 259 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >> 260 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS); 261 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >> 262 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS); 263 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >> 264 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS); 265 266 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n", 267 config->pcm_bd, config->pcm_in, config->pcm_out); 268 269 /* PDM Stream Capability */ 270 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 271 272 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >> 273 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS); 274 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >> 275 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS); 276 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >> 277 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS); 278 279 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n", 280 config->pdm_bd, config->pdm_in, config->pdm_out); 281 } 282 283 static int 284 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm) 285 { 286 void __iomem *shim = sdw->res->shim; 287 unsigned int link_id = sdw->instance; 288 int count; 289 290 if (pcm) { 291 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); 292 } else { 293 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); 294 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >> 295 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS)); 296 } 297 298 /* zero based values for channel count in register */ 299 count++; 300 301 return count; 302 } 303 304 static int intel_pdi_get_ch_update(struct sdw_intel *sdw, 305 struct sdw_cdns_pdi *pdi, 306 unsigned int num_pdi, 307 unsigned int *num_ch, bool pcm) 308 { 309 int i, ch_count = 0; 310 311 for (i = 0; i < num_pdi; i++) { 312 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); 313 ch_count += pdi->ch_count; 314 pdi++; 315 } 316 317 *num_ch = ch_count; 318 return 0; 319 } 320 321 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw, 322 struct sdw_cdns_streams *stream, bool pcm) 323 { 324 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, 325 &stream->num_ch_bd, pcm); 326 327 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, 328 &stream->num_ch_in, pcm); 329 330 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, 331 &stream->num_ch_out, pcm); 332 333 return 0; 334 } 335 336 static int intel_pdi_ch_update(struct sdw_intel *sdw) 337 { 338 /* First update PCM streams followed by PDM streams */ 339 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); 340 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); 341 342 return 0; 343 } 344 345 static void 346 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 347 { 348 void __iomem *shim = sdw->res->shim; 349 unsigned int link_id = sdw->instance; 350 int pdi_conf = 0; 351 352 pdi->intel_alh_id = (link_id * 16) + pdi->num + 5; 353 354 /* 355 * Program stream parameters to stream SHIM register 356 * This is applicable for PCM stream only. 357 */ 358 if (pdi->type != SDW_STREAM_PCM) 359 return; 360 361 if (pdi->dir == SDW_DATA_DIR_RX) 362 pdi_conf |= SDW_SHIM_PCMSYCM_DIR; 363 else 364 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR); 365 366 pdi_conf |= (pdi->intel_alh_id << 367 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM)); 368 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN)); 369 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN)); 370 371 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); 372 } 373 374 static void 375 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) 376 { 377 void __iomem *alh = sdw->res->alh; 378 unsigned int link_id = sdw->instance; 379 unsigned int conf; 380 381 pdi->intel_alh_id = (link_id * 16) + pdi->num + 5; 382 383 /* Program Stream config ALH register */ 384 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); 385 386 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL << 387 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT)); 388 389 conf |= ((pdi->ch_count - 1) << 390 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN)); 391 392 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); 393 } 394 395 static int intel_config_stream(struct sdw_intel *sdw, 396 struct snd_pcm_substream *substream, 397 struct snd_soc_dai *dai, 398 struct snd_pcm_hw_params *hw_params, int link_id) 399 { 400 if (sdw->res->ops && sdw->res->ops->config_stream) 401 return sdw->res->ops->config_stream(sdw->res->arg, 402 substream, dai, hw_params, link_id); 403 404 return -EIO; 405 } 406 407 /* 408 * bank switch routines 409 */ 410 411 static int intel_pre_bank_switch(struct sdw_bus *bus) 412 { 413 struct sdw_cdns *cdns = bus_to_cdns(bus); 414 struct sdw_intel *sdw = cdns_to_intel(cdns); 415 void __iomem *shim = sdw->res->shim; 416 int sync_reg; 417 418 /* Write to register only for multi-link */ 419 if (!bus->multi_link) 420 return 0; 421 422 /* Read SYNC register */ 423 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 424 sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance; 425 intel_writel(shim, SDW_SHIM_SYNC, sync_reg); 426 427 return 0; 428 } 429 430 static int intel_post_bank_switch(struct sdw_bus *bus) 431 { 432 struct sdw_cdns *cdns = bus_to_cdns(bus); 433 struct sdw_intel *sdw = cdns_to_intel(cdns); 434 void __iomem *shim = sdw->res->shim; 435 int sync_reg, ret; 436 437 /* Write to register only for multi-link */ 438 if (!bus->multi_link) 439 return 0; 440 441 /* Read SYNC register */ 442 sync_reg = intel_readl(shim, SDW_SHIM_SYNC); 443 444 /* 445 * post_bank_switch() ops is called from the bus in loop for 446 * all the Masters in the steam with the expectation that 447 * we trigger the bankswitch for the only first Master in the list 448 * and do nothing for the other Masters 449 * 450 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master. 451 */ 452 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) 453 return 0; 454 455 /* 456 * Set SyncGO bit to synchronously trigger a bank switch for 457 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all 458 * the Masters. 459 */ 460 sync_reg |= SDW_SHIM_SYNC_SYNCGO; 461 462 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, 463 SDW_SHIM_SYNC_SYNCGO); 464 if (ret < 0) 465 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret); 466 467 return ret; 468 } 469 470 /* 471 * DAI routines 472 */ 473 474 static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw, 475 u32 ch, u32 dir, bool pcm) 476 { 477 struct sdw_cdns *cdns = &sdw->cdns; 478 struct sdw_cdns_port *port = NULL; 479 int i, ret = 0; 480 481 for (i = 0; i < cdns->num_ports; i++) { 482 if (cdns->ports[i].assigned) 483 continue; 484 485 port = &cdns->ports[i]; 486 port->assigned = true; 487 port->direction = dir; 488 port->ch = ch; 489 break; 490 } 491 492 if (!port) { 493 dev_err(cdns->dev, "Unable to find a free port\n"); 494 return NULL; 495 } 496 497 if (pcm) { 498 ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir); 499 if (ret) 500 goto out; 501 502 intel_pdi_shim_configure(sdw, port->pdi); 503 sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi); 504 505 intel_pdi_alh_configure(sdw, port->pdi); 506 507 } else { 508 ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir); 509 } 510 511 out: 512 if (ret) { 513 port->assigned = false; 514 port = NULL; 515 } 516 517 return port; 518 } 519 520 static void intel_port_cleanup(struct sdw_cdns_dma_data *dma) 521 { 522 int i; 523 524 for (i = 0; i < dma->nr_ports; i++) { 525 if (dma->port[i]) { 526 dma->port[i]->pdi->assigned = false; 527 dma->port[i]->pdi = NULL; 528 dma->port[i]->assigned = false; 529 dma->port[i] = NULL; 530 } 531 } 532 } 533 534 static int intel_hw_params(struct snd_pcm_substream *substream, 535 struct snd_pcm_hw_params *params, 536 struct snd_soc_dai *dai) 537 { 538 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 539 struct sdw_intel *sdw = cdns_to_intel(cdns); 540 struct sdw_cdns_dma_data *dma; 541 struct sdw_stream_config sconfig; 542 struct sdw_port_config *pconfig; 543 int ret, i, ch, dir; 544 bool pcm = true; 545 546 dma = snd_soc_dai_get_dma_data(dai, substream); 547 if (!dma) 548 return -EIO; 549 550 ch = params_channels(params); 551 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 552 dir = SDW_DATA_DIR_RX; 553 else 554 dir = SDW_DATA_DIR_TX; 555 556 if (dma->stream_type == SDW_STREAM_PDM) { 557 /* TODO: Check whether PDM decimator is already in use */ 558 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir); 559 pcm = false; 560 } else { 561 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir); 562 } 563 564 if (!dma->nr_ports) { 565 dev_err(dai->dev, "ports/resources not available\n"); 566 return -EINVAL; 567 } 568 569 dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL); 570 if (!dma->port) 571 return -ENOMEM; 572 573 for (i = 0; i < dma->nr_ports; i++) { 574 dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm); 575 if (!dma->port[i]) { 576 ret = -EINVAL; 577 goto port_error; 578 } 579 } 580 581 /* Inform DSP about PDI stream number */ 582 for (i = 0; i < dma->nr_ports; i++) { 583 ret = intel_config_stream(sdw, substream, dai, params, 584 dma->port[i]->pdi->intel_alh_id); 585 if (ret) 586 goto port_error; 587 } 588 589 sconfig.direction = dir; 590 sconfig.ch_count = ch; 591 sconfig.frame_rate = params_rate(params); 592 sconfig.type = dma->stream_type; 593 594 if (dma->stream_type == SDW_STREAM_PDM) { 595 sconfig.frame_rate *= 50; 596 sconfig.bps = 1; 597 } else { 598 sconfig.bps = snd_pcm_format_width(params_format(params)); 599 } 600 601 /* Port configuration */ 602 pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL); 603 if (!pconfig) { 604 ret = -ENOMEM; 605 goto port_error; 606 } 607 608 for (i = 0; i < dma->nr_ports; i++) { 609 pconfig[i].num = dma->port[i]->num; 610 pconfig[i].ch_mask = (1 << ch) - 1; 611 } 612 613 ret = sdw_stream_add_master(&cdns->bus, &sconfig, 614 pconfig, dma->nr_ports, dma->stream); 615 if (ret) { 616 dev_err(cdns->dev, "add master to stream failed:%d\n", ret); 617 goto stream_error; 618 } 619 620 kfree(pconfig); 621 return ret; 622 623 stream_error: 624 kfree(pconfig); 625 port_error: 626 intel_port_cleanup(dma); 627 kfree(dma->port); 628 return ret; 629 } 630 631 static int 632 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 633 { 634 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); 635 struct sdw_cdns_dma_data *dma; 636 int ret; 637 638 dma = snd_soc_dai_get_dma_data(dai, substream); 639 if (!dma) 640 return -EIO; 641 642 ret = sdw_stream_remove_master(&cdns->bus, dma->stream); 643 if (ret < 0) 644 dev_err(dai->dev, "remove master from stream %s failed: %d\n", 645 dma->stream->name, ret); 646 647 intel_port_cleanup(dma); 648 kfree(dma->port); 649 return ret; 650 } 651 652 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, 653 void *stream, int direction) 654 { 655 return cdns_set_sdw_stream(dai, stream, true, direction); 656 } 657 658 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai, 659 void *stream, int direction) 660 { 661 return cdns_set_sdw_stream(dai, stream, false, direction); 662 } 663 664 static const struct snd_soc_dai_ops intel_pcm_dai_ops = { 665 .hw_params = intel_hw_params, 666 .hw_free = intel_hw_free, 667 .shutdown = sdw_cdns_shutdown, 668 .set_sdw_stream = intel_pcm_set_sdw_stream, 669 }; 670 671 static const struct snd_soc_dai_ops intel_pdm_dai_ops = { 672 .hw_params = intel_hw_params, 673 .hw_free = intel_hw_free, 674 .shutdown = sdw_cdns_shutdown, 675 .set_sdw_stream = intel_pdm_set_sdw_stream, 676 }; 677 678 static const struct snd_soc_component_driver dai_component = { 679 .name = "soundwire", 680 }; 681 682 static int intel_create_dai(struct sdw_cdns *cdns, 683 struct snd_soc_dai_driver *dais, 684 enum intel_pdi_type type, 685 u32 num, u32 off, u32 max_ch, bool pcm) 686 { 687 int i; 688 689 if (num == 0) 690 return 0; 691 692 /* TODO: Read supported rates/formats from hardware */ 693 for (i = off; i < (off + num); i++) { 694 dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d", 695 cdns->instance, i); 696 if (!dais[i].name) 697 return -ENOMEM; 698 699 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { 700 dais[i].playback.stream_name = 701 kasprintf(GFP_KERNEL, "SDW%d Tx%d", 702 cdns->instance, i); 703 if (!dais[i].playback.stream_name) { 704 kfree(dais[i].name); 705 return -ENOMEM; 706 } 707 708 dais[i].playback.channels_min = 1; 709 dais[i].playback.channels_max = max_ch; 710 dais[i].playback.rates = SNDRV_PCM_RATE_48000; 711 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE; 712 } 713 714 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { 715 dais[i].capture.stream_name = 716 kasprintf(GFP_KERNEL, "SDW%d Rx%d", 717 cdns->instance, i); 718 if (!dais[i].capture.stream_name) { 719 kfree(dais[i].name); 720 kfree(dais[i].playback.stream_name); 721 return -ENOMEM; 722 } 723 724 dais[i].capture.channels_min = 1; 725 dais[i].capture.channels_max = max_ch; 726 dais[i].capture.rates = SNDRV_PCM_RATE_48000; 727 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE; 728 } 729 730 dais[i].id = SDW_DAI_ID_RANGE_START + i; 731 732 if (pcm) 733 dais[i].ops = &intel_pcm_dai_ops; 734 else 735 dais[i].ops = &intel_pdm_dai_ops; 736 } 737 738 return 0; 739 } 740 741 static int intel_register_dai(struct sdw_intel *sdw) 742 { 743 struct sdw_cdns *cdns = &sdw->cdns; 744 struct sdw_cdns_streams *stream; 745 struct snd_soc_dai_driver *dais; 746 int num_dai, ret, off = 0; 747 748 /* DAIs are created based on total number of PDIs supported */ 749 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; 750 751 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); 752 if (!dais) 753 return -ENOMEM; 754 755 /* Create PCM DAIs */ 756 stream = &cdns->pcm; 757 758 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, stream->num_in, 759 off, stream->num_ch_in, true); 760 if (ret) 761 return ret; 762 763 off += cdns->pcm.num_in; 764 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out, 765 off, stream->num_ch_out, true); 766 if (ret) 767 return ret; 768 769 off += cdns->pcm.num_out; 770 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd, 771 off, stream->num_ch_bd, true); 772 if (ret) 773 return ret; 774 775 /* Create PDM DAIs */ 776 stream = &cdns->pdm; 777 off += cdns->pcm.num_bd; 778 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in, 779 off, stream->num_ch_in, false); 780 if (ret) 781 return ret; 782 783 off += cdns->pdm.num_in; 784 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out, 785 off, stream->num_ch_out, false); 786 if (ret) 787 return ret; 788 789 off += cdns->pdm.num_bd; 790 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd, 791 off, stream->num_ch_bd, false); 792 if (ret) 793 return ret; 794 795 return snd_soc_register_component(cdns->dev, &dai_component, 796 dais, num_dai); 797 } 798 799 static int intel_prop_read(struct sdw_bus *bus) 800 { 801 /* Initialize with default handler to read all DisCo properties */ 802 sdw_master_read_prop(bus); 803 804 /* BIOS is not giving some values correctly. So, lets override them */ 805 bus->prop.num_clk_freq = 1; 806 bus->prop.clk_freq = devm_kcalloc(bus->dev, bus->prop.num_clk_freq, 807 sizeof(*bus->prop.clk_freq), 808 GFP_KERNEL); 809 if (!bus->prop.clk_freq) 810 return -ENOMEM; 811 812 bus->prop.clk_freq[0] = bus->prop.max_clk_freq; 813 bus->prop.err_threshold = 5; 814 815 return 0; 816 } 817 818 static struct sdw_master_ops sdw_intel_ops = { 819 .read_prop = sdw_master_read_prop, 820 .xfer_msg = cdns_xfer_msg, 821 .xfer_msg_defer = cdns_xfer_msg_defer, 822 .reset_page_addr = cdns_reset_page_addr, 823 .set_bus_conf = cdns_bus_conf, 824 .pre_bank_switch = intel_pre_bank_switch, 825 .post_bank_switch = intel_post_bank_switch, 826 }; 827 828 /* 829 * probe and init 830 */ 831 static int intel_probe(struct platform_device *pdev) 832 { 833 struct sdw_cdns_stream_config config; 834 struct sdw_intel *sdw; 835 int ret; 836 837 sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL); 838 if (!sdw) 839 return -ENOMEM; 840 841 sdw->instance = pdev->id; 842 sdw->res = dev_get_platdata(&pdev->dev); 843 sdw->cdns.dev = &pdev->dev; 844 sdw->cdns.registers = sdw->res->registers; 845 sdw->cdns.instance = sdw->instance; 846 sdw->cdns.msg_count = 0; 847 sdw->cdns.bus.dev = &pdev->dev; 848 sdw->cdns.bus.link_id = pdev->id; 849 850 sdw_cdns_probe(&sdw->cdns); 851 852 /* Set property read ops */ 853 sdw_intel_ops.read_prop = intel_prop_read; 854 sdw->cdns.bus.ops = &sdw_intel_ops; 855 856 platform_set_drvdata(pdev, sdw); 857 858 ret = sdw_add_bus_master(&sdw->cdns.bus); 859 if (ret) { 860 dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret); 861 goto err_master_reg; 862 } 863 864 /* Initialize shim and controller */ 865 intel_link_power_up(sdw); 866 intel_shim_init(sdw); 867 868 ret = sdw_cdns_init(&sdw->cdns); 869 if (ret) 870 goto err_init; 871 872 ret = sdw_cdns_enable_interrupt(&sdw->cdns); 873 874 /* Read the PDI config and initialize cadence PDI */ 875 intel_pdi_init(sdw, &config); 876 ret = sdw_cdns_pdi_init(&sdw->cdns, config); 877 if (ret) 878 goto err_init; 879 880 intel_pdi_ch_update(sdw); 881 882 /* Acquire IRQ */ 883 ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread, 884 IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns); 885 if (ret < 0) { 886 dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n", 887 sdw->res->irq); 888 goto err_init; 889 } 890 891 /* Register DAIs */ 892 ret = intel_register_dai(sdw); 893 if (ret) { 894 dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret); 895 snd_soc_unregister_component(sdw->cdns.dev); 896 goto err_dai; 897 } 898 899 return 0; 900 901 err_dai: 902 free_irq(sdw->res->irq, sdw); 903 err_init: 904 sdw_delete_bus_master(&sdw->cdns.bus); 905 err_master_reg: 906 return ret; 907 } 908 909 static int intel_remove(struct platform_device *pdev) 910 { 911 struct sdw_intel *sdw; 912 913 sdw = platform_get_drvdata(pdev); 914 915 free_irq(sdw->res->irq, sdw); 916 snd_soc_unregister_component(sdw->cdns.dev); 917 sdw_delete_bus_master(&sdw->cdns.bus); 918 919 return 0; 920 } 921 922 static struct platform_driver sdw_intel_drv = { 923 .probe = intel_probe, 924 .remove = intel_remove, 925 .driver = { 926 .name = "int-sdw", 927 928 }, 929 }; 930 931 module_platform_driver(sdw_intel_drv); 932 933 MODULE_LICENSE("Dual BSD/GPL"); 934 MODULE_ALIAS("platform:int-sdw"); 935 MODULE_DESCRIPTION("Intel Soundwire Master Driver"); 936