1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2f956a785SLinus Walleij /*
3f956a785SLinus Walleij  * Copyright (C) 2014 Linaro Ltd.
4f956a785SLinus Walleij  *
5f956a785SLinus Walleij  * Author: Linus Walleij <linus.walleij@linaro.org>
6f956a785SLinus Walleij  */
7f956a785SLinus Walleij #include <linux/init.h>
8f956a785SLinus Walleij #include <linux/io.h>
9f956a785SLinus Walleij #include <linux/slab.h>
10f956a785SLinus Walleij #include <linux/sys_soc.h>
11f956a785SLinus Walleij #include <linux/platform_device.h>
12f956a785SLinus Walleij #include <linux/mfd/syscon.h>
13f956a785SLinus Walleij #include <linux/regmap.h>
14f956a785SLinus Walleij #include <linux/of.h>
15f956a785SLinus Walleij 
16f956a785SLinus Walleij #define INTEGRATOR_HDR_ID_OFFSET	0x00
17f956a785SLinus Walleij 
18f956a785SLinus Walleij static u32 integrator_coreid;
19f956a785SLinus Walleij 
20f956a785SLinus Walleij static const struct of_device_id integrator_cm_match[] = {
21f956a785SLinus Walleij 	{ .compatible = "arm,core-module-integrator", },
22c7478038SAxel Lin 	{ }
23f956a785SLinus Walleij };
24f956a785SLinus Walleij 
25f956a785SLinus Walleij static const char *integrator_arch_str(u32 id)
26f956a785SLinus Walleij {
27f956a785SLinus Walleij 	switch ((id >> 16) & 0xff) {
28f956a785SLinus Walleij 	case 0x00:
29f956a785SLinus Walleij 		return "ASB little-endian";
30f956a785SLinus Walleij 	case 0x01:
31f956a785SLinus Walleij 		return "AHB little-endian";
32f956a785SLinus Walleij 	case 0x03:
33f956a785SLinus Walleij 		return "AHB-Lite system bus, bi-endian";
34f956a785SLinus Walleij 	case 0x04:
35f956a785SLinus Walleij 		return "AHB";
36f956a785SLinus Walleij 	case 0x08:
37f956a785SLinus Walleij 		return "AHB system bus, ASB processor bus";
38f956a785SLinus Walleij 	default:
39f956a785SLinus Walleij 		return "Unknown";
40f956a785SLinus Walleij 	}
41f956a785SLinus Walleij }
42f956a785SLinus Walleij 
43f956a785SLinus Walleij static const char *integrator_fpga_str(u32 id)
44f956a785SLinus Walleij {
45f956a785SLinus Walleij 	switch ((id >> 12) & 0xf) {
46f956a785SLinus Walleij 	case 0x01:
47f956a785SLinus Walleij 		return "XC4062";
48f956a785SLinus Walleij 	case 0x02:
49f956a785SLinus Walleij 		return "XC4085";
50f956a785SLinus Walleij 	case 0x03:
51f956a785SLinus Walleij 		return "XVC600";
52f956a785SLinus Walleij 	case 0x04:
53f956a785SLinus Walleij 		return "EPM7256AE (Altera PLD)";
54f956a785SLinus Walleij 	default:
55f956a785SLinus Walleij 		return "Unknown";
56f956a785SLinus Walleij 	}
57f956a785SLinus Walleij }
58f956a785SLinus Walleij 
59f956a785SLinus Walleij static ssize_t integrator_get_manf(struct device *dev,
60f956a785SLinus Walleij 			      struct device_attribute *attr,
61f956a785SLinus Walleij 			      char *buf)
62f956a785SLinus Walleij {
63f956a785SLinus Walleij 	return sprintf(buf, "%02x\n", integrator_coreid >> 24);
64f956a785SLinus Walleij }
65f956a785SLinus Walleij 
66f956a785SLinus Walleij static struct device_attribute integrator_manf_attr =
67f956a785SLinus Walleij 	__ATTR(manufacturer,  S_IRUGO, integrator_get_manf,  NULL);
68f956a785SLinus Walleij 
69f956a785SLinus Walleij static ssize_t integrator_get_arch(struct device *dev,
70f956a785SLinus Walleij 			      struct device_attribute *attr,
71f956a785SLinus Walleij 			      char *buf)
72f956a785SLinus Walleij {
73f956a785SLinus Walleij 	return sprintf(buf, "%s\n", integrator_arch_str(integrator_coreid));
74f956a785SLinus Walleij }
75f956a785SLinus Walleij 
76f956a785SLinus Walleij static struct device_attribute integrator_arch_attr =
77f956a785SLinus Walleij 	__ATTR(arch,  S_IRUGO, integrator_get_arch,  NULL);
78f956a785SLinus Walleij 
79f956a785SLinus Walleij static ssize_t integrator_get_fpga(struct device *dev,
80f956a785SLinus Walleij 			      struct device_attribute *attr,
81f956a785SLinus Walleij 			      char *buf)
82f956a785SLinus Walleij {
83f956a785SLinus Walleij 	return sprintf(buf, "%s\n", integrator_fpga_str(integrator_coreid));
84f956a785SLinus Walleij }
85f956a785SLinus Walleij 
86f956a785SLinus Walleij static struct device_attribute integrator_fpga_attr =
87f956a785SLinus Walleij 	__ATTR(fpga,  S_IRUGO, integrator_get_fpga,  NULL);
88f956a785SLinus Walleij 
89f956a785SLinus Walleij static ssize_t integrator_get_build(struct device *dev,
90f956a785SLinus Walleij 			       struct device_attribute *attr,
91f956a785SLinus Walleij 			       char *buf)
92f956a785SLinus Walleij {
93f956a785SLinus Walleij 	return sprintf(buf, "%02x\n", (integrator_coreid >> 4) & 0xFF);
94f956a785SLinus Walleij }
95f956a785SLinus Walleij 
96f956a785SLinus Walleij static struct device_attribute integrator_build_attr =
97f956a785SLinus Walleij 	__ATTR(build,  S_IRUGO, integrator_get_build,  NULL);
98f956a785SLinus Walleij 
99f956a785SLinus Walleij static int __init integrator_soc_init(void)
100f956a785SLinus Walleij {
101f956a785SLinus Walleij 	static struct regmap *syscon_regmap;
102f956a785SLinus Walleij 	struct soc_device *soc_dev;
103f956a785SLinus Walleij 	struct soc_device_attribute *soc_dev_attr;
104f956a785SLinus Walleij 	struct device_node *np;
105f956a785SLinus Walleij 	struct device *dev;
106f956a785SLinus Walleij 	u32 val;
107f956a785SLinus Walleij 	int ret;
108f956a785SLinus Walleij 
109f956a785SLinus Walleij 	np = of_find_matching_node(NULL, integrator_cm_match);
110f956a785SLinus Walleij 	if (!np)
111f956a785SLinus Walleij 		return -ENODEV;
112f956a785SLinus Walleij 
113f956a785SLinus Walleij 	syscon_regmap = syscon_node_to_regmap(np);
114f956a785SLinus Walleij 	if (IS_ERR(syscon_regmap))
115f956a785SLinus Walleij 		return PTR_ERR(syscon_regmap);
116f956a785SLinus Walleij 
117f956a785SLinus Walleij 	ret = regmap_read(syscon_regmap, INTEGRATOR_HDR_ID_OFFSET,
118f956a785SLinus Walleij 			  &val);
119f956a785SLinus Walleij 	if (ret)
120f956a785SLinus Walleij 		return -ENODEV;
121f956a785SLinus Walleij 	integrator_coreid = val;
122f956a785SLinus Walleij 
123f956a785SLinus Walleij 	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
124f956a785SLinus Walleij 	if (!soc_dev_attr)
125f956a785SLinus Walleij 		return -ENOMEM;
126f956a785SLinus Walleij 
127f956a785SLinus Walleij 	soc_dev_attr->soc_id = "Integrator";
128f956a785SLinus Walleij 	soc_dev_attr->machine = "Integrator";
129f956a785SLinus Walleij 	soc_dev_attr->family = "Versatile";
130f956a785SLinus Walleij 	soc_dev = soc_device_register(soc_dev_attr);
131f956a785SLinus Walleij 	if (IS_ERR(soc_dev)) {
132f956a785SLinus Walleij 		kfree(soc_dev_attr);
133f956a785SLinus Walleij 		return -ENODEV;
134f956a785SLinus Walleij 	}
135f956a785SLinus Walleij 	dev = soc_device_to_device(soc_dev);
136f956a785SLinus Walleij 
137f956a785SLinus Walleij 	device_create_file(dev, &integrator_manf_attr);
138f956a785SLinus Walleij 	device_create_file(dev, &integrator_arch_attr);
139f956a785SLinus Walleij 	device_create_file(dev, &integrator_fpga_attr);
140f956a785SLinus Walleij 	device_create_file(dev, &integrator_build_attr);
141f956a785SLinus Walleij 
142f956a785SLinus Walleij 	dev_info(dev, "Detected ARM core module:\n");
143f956a785SLinus Walleij 	dev_info(dev, "    Manufacturer: %02x\n", (val >> 24));
144f956a785SLinus Walleij 	dev_info(dev, "    Architecture: %s\n", integrator_arch_str(val));
145f956a785SLinus Walleij 	dev_info(dev, "    FPGA: %s\n", integrator_fpga_str(val));
146f956a785SLinus Walleij 	dev_info(dev, "    Build: %02x\n", (val >> 4) & 0xFF);
147f956a785SLinus Walleij 	dev_info(dev, "    Rev: %c\n", ('A' + (val & 0x03)));
148f956a785SLinus Walleij 
149f956a785SLinus Walleij 	return 0;
150f956a785SLinus Walleij }
151f956a785SLinus Walleij device_initcall(integrator_soc_init);
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