1 /* 2 * AMx3 Wkup M3 IPC driver 3 * 4 * Copyright (C) 2015 Texas Instruments, Inc. 5 * 6 * Dave Gerlach <d-gerlach@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/err.h> 19 #include <linux/kernel.h> 20 #include <linux/kthread.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/omap-mailbox.h> 26 #include <linux/platform_device.h> 27 #include <linux/remoteproc.h> 28 #include <linux/suspend.h> 29 #include <linux/wkup_m3_ipc.h> 30 31 #define AM33XX_CTRL_IPC_REG_COUNT 0x8 32 #define AM33XX_CTRL_IPC_REG_OFFSET(m) (0x4 + 4 * (m)) 33 34 /* AM33XX M3_TXEV_EOI register */ 35 #define AM33XX_CONTROL_M3_TXEV_EOI 0x00 36 37 #define AM33XX_M3_TXEV_ACK (0x1 << 0) 38 #define AM33XX_M3_TXEV_ENABLE (0x0 << 0) 39 40 #define IPC_CMD_DS0 0x4 41 #define IPC_CMD_STANDBY 0xc 42 #define IPC_CMD_IDLE 0x10 43 #define IPC_CMD_RESET 0xe 44 #define DS_IPC_DEFAULT 0xffffffff 45 #define M3_VERSION_UNKNOWN 0x0000ffff 46 #define M3_BASELINE_VERSION 0x191 47 #define M3_STATUS_RESP_MASK (0xffff << 16) 48 #define M3_FW_VERSION_MASK 0xffff 49 #define M3_WAKE_SRC_MASK 0xff 50 51 #define M3_STATE_UNKNOWN 0 52 #define M3_STATE_RESET 1 53 #define M3_STATE_INITED 2 54 #define M3_STATE_MSG_FOR_LP 3 55 #define M3_STATE_MSG_FOR_RESET 4 56 57 static struct wkup_m3_ipc *m3_ipc_state; 58 59 static const struct wkup_m3_wakeup_src wakeups[] = { 60 {.irq_nr = 35, .src = "USB0_PHY"}, 61 {.irq_nr = 36, .src = "USB1_PHY"}, 62 {.irq_nr = 40, .src = "I2C0"}, 63 {.irq_nr = 41, .src = "RTC Timer"}, 64 {.irq_nr = 42, .src = "RTC Alarm"}, 65 {.irq_nr = 43, .src = "Timer0"}, 66 {.irq_nr = 44, .src = "Timer1"}, 67 {.irq_nr = 45, .src = "UART"}, 68 {.irq_nr = 46, .src = "GPIO0"}, 69 {.irq_nr = 48, .src = "MPU_WAKE"}, 70 {.irq_nr = 49, .src = "WDT0"}, 71 {.irq_nr = 50, .src = "WDT1"}, 72 {.irq_nr = 51, .src = "ADC_TSC"}, 73 {.irq_nr = 0, .src = "Unknown"}, 74 }; 75 76 static void am33xx_txev_eoi(struct wkup_m3_ipc *m3_ipc) 77 { 78 writel(AM33XX_M3_TXEV_ACK, 79 m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI); 80 } 81 82 static void am33xx_txev_enable(struct wkup_m3_ipc *m3_ipc) 83 { 84 writel(AM33XX_M3_TXEV_ENABLE, 85 m3_ipc->ipc_mem_base + AM33XX_CONTROL_M3_TXEV_EOI); 86 } 87 88 static void wkup_m3_ctrl_ipc_write(struct wkup_m3_ipc *m3_ipc, 89 u32 val, int ipc_reg_num) 90 { 91 if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT, 92 "ipc register operation out of range")) 93 return; 94 95 writel(val, m3_ipc->ipc_mem_base + 96 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num)); 97 } 98 99 static unsigned int wkup_m3_ctrl_ipc_read(struct wkup_m3_ipc *m3_ipc, 100 int ipc_reg_num) 101 { 102 if (WARN(ipc_reg_num < 0 || ipc_reg_num > AM33XX_CTRL_IPC_REG_COUNT, 103 "ipc register operation out of range")) 104 return 0; 105 106 return readl(m3_ipc->ipc_mem_base + 107 AM33XX_CTRL_IPC_REG_OFFSET(ipc_reg_num)); 108 } 109 110 static int wkup_m3_fw_version_read(struct wkup_m3_ipc *m3_ipc) 111 { 112 int val; 113 114 val = wkup_m3_ctrl_ipc_read(m3_ipc, 2); 115 116 return val & M3_FW_VERSION_MASK; 117 } 118 119 static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data) 120 { 121 struct wkup_m3_ipc *m3_ipc = ipc_data; 122 struct device *dev = m3_ipc->dev; 123 int ver = 0; 124 125 am33xx_txev_eoi(m3_ipc); 126 127 switch (m3_ipc->state) { 128 case M3_STATE_RESET: 129 ver = wkup_m3_fw_version_read(m3_ipc); 130 131 if (ver == M3_VERSION_UNKNOWN || 132 ver < M3_BASELINE_VERSION) { 133 dev_warn(dev, "CM3 Firmware Version %x not supported\n", 134 ver); 135 } else { 136 dev_info(dev, "CM3 Firmware Version = 0x%x\n", ver); 137 } 138 139 m3_ipc->state = M3_STATE_INITED; 140 complete(&m3_ipc->sync_complete); 141 break; 142 case M3_STATE_MSG_FOR_RESET: 143 m3_ipc->state = M3_STATE_INITED; 144 complete(&m3_ipc->sync_complete); 145 break; 146 case M3_STATE_MSG_FOR_LP: 147 complete(&m3_ipc->sync_complete); 148 break; 149 case M3_STATE_UNKNOWN: 150 dev_warn(dev, "Unknown CM3 State\n"); 151 } 152 153 am33xx_txev_enable(m3_ipc); 154 155 return IRQ_HANDLED; 156 } 157 158 static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc) 159 { 160 struct device *dev = m3_ipc->dev; 161 mbox_msg_t dummy_msg = 0; 162 int ret; 163 164 if (!m3_ipc->mbox) { 165 dev_err(dev, 166 "No IPC channel to communicate with wkup_m3!\n"); 167 return -EIO; 168 } 169 170 /* 171 * Write a dummy message to the mailbox in order to trigger the RX 172 * interrupt to alert the M3 that data is available in the IPC 173 * registers. We must enable the IRQ here and disable it after in 174 * the RX callback to avoid multiple interrupts being received 175 * by the CM3. 176 */ 177 ret = mbox_send_message(m3_ipc->mbox, &dummy_msg); 178 if (ret < 0) { 179 dev_err(dev, "%s: mbox_send_message() failed: %d\n", 180 __func__, ret); 181 return ret; 182 } 183 184 ret = wait_for_completion_timeout(&m3_ipc->sync_complete, 185 msecs_to_jiffies(500)); 186 if (!ret) { 187 dev_err(dev, "MPU<->CM3 sync failure\n"); 188 m3_ipc->state = M3_STATE_UNKNOWN; 189 return -EIO; 190 } 191 192 mbox_client_txdone(m3_ipc->mbox, 0); 193 return 0; 194 } 195 196 static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc) 197 { 198 struct device *dev = m3_ipc->dev; 199 mbox_msg_t dummy_msg = 0; 200 int ret; 201 202 if (!m3_ipc->mbox) { 203 dev_err(dev, 204 "No IPC channel to communicate with wkup_m3!\n"); 205 return -EIO; 206 } 207 208 ret = mbox_send_message(m3_ipc->mbox, &dummy_msg); 209 if (ret < 0) { 210 dev_err(dev, "%s: mbox_send_message() failed: %d\n", 211 __func__, ret); 212 return ret; 213 } 214 215 mbox_client_txdone(m3_ipc->mbox, 0); 216 return 0; 217 } 218 219 static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc) 220 { 221 return ((m3_ipc->state != M3_STATE_RESET) && 222 (m3_ipc->state != M3_STATE_UNKNOWN)); 223 } 224 225 /* Public functions */ 226 /** 227 * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use 228 * @mem_type: memory type value read directly from emif 229 * 230 * wkup_m3 must know what memory type is in use to properly suspend 231 * and resume. 232 */ 233 static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type) 234 { 235 m3_ipc->mem_type = mem_type; 236 } 237 238 /** 239 * wkup_m3_set_resume_address - Pass wkup_m3 resume address 240 * @addr: Physical address from which resume code should execute 241 */ 242 static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr) 243 { 244 m3_ipc->resume_addr = (unsigned long)addr; 245 } 246 247 /** 248 * wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend 249 * 250 * Returns code representing the status of a low power mode transition. 251 * 0 - Successful transition 252 * 1 - Failure to transition to low power state 253 */ 254 static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc) 255 { 256 unsigned int i; 257 int val; 258 259 val = wkup_m3_ctrl_ipc_read(m3_ipc, 1); 260 261 i = M3_STATUS_RESP_MASK & val; 262 i >>= __ffs(M3_STATUS_RESP_MASK); 263 264 return i; 265 } 266 267 /** 268 * wkup_m3_prepare_low_power - Request preparation for transition to 269 * low power state 270 * @state: A kernel suspend state to enter, either MEM or STANDBY 271 * 272 * Returns 0 if preparation was successful, otherwise returns error code 273 */ 274 static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state) 275 { 276 struct device *dev = m3_ipc->dev; 277 int m3_power_state; 278 int ret = 0; 279 280 if (!wkup_m3_is_available(m3_ipc)) 281 return -ENODEV; 282 283 switch (state) { 284 case WKUP_M3_DEEPSLEEP: 285 m3_power_state = IPC_CMD_DS0; 286 break; 287 case WKUP_M3_STANDBY: 288 m3_power_state = IPC_CMD_STANDBY; 289 break; 290 case WKUP_M3_IDLE: 291 m3_power_state = IPC_CMD_IDLE; 292 break; 293 default: 294 return 1; 295 } 296 297 /* Program each required IPC register then write defaults to others */ 298 wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->resume_addr, 0); 299 wkup_m3_ctrl_ipc_write(m3_ipc, m3_power_state, 1); 300 wkup_m3_ctrl_ipc_write(m3_ipc, m3_ipc->mem_type, 4); 301 302 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2); 303 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 3); 304 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 5); 305 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 6); 306 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 7); 307 308 m3_ipc->state = M3_STATE_MSG_FOR_LP; 309 310 if (state == WKUP_M3_IDLE) 311 ret = wkup_m3_ping_noirq(m3_ipc); 312 else 313 ret = wkup_m3_ping(m3_ipc); 314 315 if (ret) { 316 dev_err(dev, "Unable to ping CM3\n"); 317 return ret; 318 } 319 320 return 0; 321 } 322 323 /** 324 * wkup_m3_finish_low_power - Return m3 to reset state 325 * 326 * Returns 0 if reset was successful, otherwise returns error code 327 */ 328 static int wkup_m3_finish_low_power(struct wkup_m3_ipc *m3_ipc) 329 { 330 struct device *dev = m3_ipc->dev; 331 int ret = 0; 332 333 if (!wkup_m3_is_available(m3_ipc)) 334 return -ENODEV; 335 336 wkup_m3_ctrl_ipc_write(m3_ipc, IPC_CMD_RESET, 1); 337 wkup_m3_ctrl_ipc_write(m3_ipc, DS_IPC_DEFAULT, 2); 338 339 m3_ipc->state = M3_STATE_MSG_FOR_RESET; 340 341 ret = wkup_m3_ping(m3_ipc); 342 if (ret) { 343 dev_err(dev, "Unable to ping CM3\n"); 344 return ret; 345 } 346 347 return 0; 348 } 349 350 /** 351 * wkup_m3_request_wake_src - Get the wakeup source info passed from wkup_m3 352 * @m3_ipc: Pointer to wkup_m3_ipc context 353 */ 354 static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc) 355 { 356 unsigned int wakeup_src_idx; 357 int j, val; 358 359 val = wkup_m3_ctrl_ipc_read(m3_ipc, 6); 360 361 wakeup_src_idx = val & M3_WAKE_SRC_MASK; 362 363 for (j = 0; j < ARRAY_SIZE(wakeups) - 1; j++) { 364 if (wakeups[j].irq_nr == wakeup_src_idx) 365 return wakeups[j].src; 366 } 367 return wakeups[j].src; 368 } 369 370 /** 371 * wkup_m3_set_rtc_only - Set the rtc_only flag 372 * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the 373 * wakeup src value 374 */ 375 static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc) 376 { 377 if (m3_ipc_state) 378 m3_ipc_state->is_rtc_only = true; 379 } 380 381 static struct wkup_m3_ipc_ops ipc_ops = { 382 .set_mem_type = wkup_m3_set_mem_type, 383 .set_resume_address = wkup_m3_set_resume_address, 384 .prepare_low_power = wkup_m3_prepare_low_power, 385 .finish_low_power = wkup_m3_finish_low_power, 386 .request_pm_status = wkup_m3_request_pm_status, 387 .request_wake_src = wkup_m3_request_wake_src, 388 .set_rtc_only = wkup_m3_set_rtc_only, 389 }; 390 391 /** 392 * wkup_m3_ipc_get - Return handle to wkup_m3_ipc 393 * 394 * Returns NULL if the wkup_m3 is not yet available, otherwise returns 395 * pointer to wkup_m3_ipc struct. 396 */ 397 struct wkup_m3_ipc *wkup_m3_ipc_get(void) 398 { 399 if (m3_ipc_state) 400 get_device(m3_ipc_state->dev); 401 else 402 return NULL; 403 404 return m3_ipc_state; 405 } 406 EXPORT_SYMBOL_GPL(wkup_m3_ipc_get); 407 408 /** 409 * wkup_m3_ipc_put - Free handle to wkup_m3_ipc returned from wkup_m3_ipc_get 410 * @m3_ipc: A pointer to wkup_m3_ipc struct returned by wkup_m3_ipc_get 411 */ 412 void wkup_m3_ipc_put(struct wkup_m3_ipc *m3_ipc) 413 { 414 if (m3_ipc_state) 415 put_device(m3_ipc_state->dev); 416 } 417 EXPORT_SYMBOL_GPL(wkup_m3_ipc_put); 418 419 static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc) 420 { 421 struct device *dev = m3_ipc->dev; 422 int ret; 423 424 init_completion(&m3_ipc->sync_complete); 425 426 ret = rproc_boot(m3_ipc->rproc); 427 if (ret) 428 dev_err(dev, "rproc_boot failed\n"); 429 430 do_exit(0); 431 } 432 433 static int wkup_m3_ipc_probe(struct platform_device *pdev) 434 { 435 struct device *dev = &pdev->dev; 436 int irq, ret; 437 phandle rproc_phandle; 438 struct rproc *m3_rproc; 439 struct resource *res; 440 struct task_struct *task; 441 struct wkup_m3_ipc *m3_ipc; 442 443 m3_ipc = devm_kzalloc(dev, sizeof(*m3_ipc), GFP_KERNEL); 444 if (!m3_ipc) 445 return -ENOMEM; 446 447 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 448 m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res); 449 if (IS_ERR(m3_ipc->ipc_mem_base)) { 450 dev_err(dev, "could not ioremap ipc_mem\n"); 451 return PTR_ERR(m3_ipc->ipc_mem_base); 452 } 453 454 irq = platform_get_irq(pdev, 0); 455 if (!irq) { 456 dev_err(&pdev->dev, "no irq resource\n"); 457 return -ENXIO; 458 } 459 460 ret = devm_request_irq(dev, irq, wkup_m3_txev_handler, 461 0, "wkup_m3_txev", m3_ipc); 462 if (ret) { 463 dev_err(dev, "request_irq failed\n"); 464 return ret; 465 } 466 467 m3_ipc->mbox_client.dev = dev; 468 m3_ipc->mbox_client.tx_done = NULL; 469 m3_ipc->mbox_client.tx_prepare = NULL; 470 m3_ipc->mbox_client.rx_callback = NULL; 471 m3_ipc->mbox_client.tx_block = false; 472 m3_ipc->mbox_client.knows_txdone = false; 473 474 m3_ipc->mbox = mbox_request_channel(&m3_ipc->mbox_client, 0); 475 476 if (IS_ERR(m3_ipc->mbox)) { 477 dev_err(dev, "IPC Request for A8->M3 Channel failed! %ld\n", 478 PTR_ERR(m3_ipc->mbox)); 479 return PTR_ERR(m3_ipc->mbox); 480 } 481 482 if (of_property_read_u32(dev->of_node, "ti,rproc", &rproc_phandle)) { 483 dev_err(&pdev->dev, "could not get rproc phandle\n"); 484 ret = -ENODEV; 485 goto err_free_mbox; 486 } 487 488 m3_rproc = rproc_get_by_phandle(rproc_phandle); 489 if (!m3_rproc) { 490 dev_err(&pdev->dev, "could not get rproc handle\n"); 491 ret = -EPROBE_DEFER; 492 goto err_free_mbox; 493 } 494 495 m3_ipc->rproc = m3_rproc; 496 m3_ipc->dev = dev; 497 m3_ipc->state = M3_STATE_RESET; 498 499 m3_ipc->ops = &ipc_ops; 500 501 /* 502 * Wait for firmware loading completion in a thread so we 503 * can boot the wkup_m3 as soon as it's ready without holding 504 * up kernel boot 505 */ 506 task = kthread_run((void *)wkup_m3_rproc_boot_thread, m3_ipc, 507 "wkup_m3_rproc_loader"); 508 509 if (IS_ERR(task)) { 510 dev_err(dev, "can't create rproc_boot thread\n"); 511 ret = PTR_ERR(task); 512 goto err_put_rproc; 513 } 514 515 m3_ipc_state = m3_ipc; 516 517 return 0; 518 519 err_put_rproc: 520 rproc_put(m3_rproc); 521 err_free_mbox: 522 mbox_free_channel(m3_ipc->mbox); 523 return ret; 524 } 525 526 static int wkup_m3_ipc_remove(struct platform_device *pdev) 527 { 528 mbox_free_channel(m3_ipc_state->mbox); 529 530 rproc_shutdown(m3_ipc_state->rproc); 531 rproc_put(m3_ipc_state->rproc); 532 533 m3_ipc_state = NULL; 534 535 return 0; 536 } 537 538 static int __maybe_unused wkup_m3_ipc_suspend(struct device *dev) 539 { 540 /* 541 * Nothing needs to be done on suspend even with rtc_only flag set 542 */ 543 return 0; 544 } 545 546 static int __maybe_unused wkup_m3_ipc_resume(struct device *dev) 547 { 548 if (m3_ipc_state->is_rtc_only) { 549 rproc_shutdown(m3_ipc_state->rproc); 550 rproc_boot(m3_ipc_state->rproc); 551 } 552 553 m3_ipc_state->is_rtc_only = false; 554 555 return 0; 556 } 557 558 static const struct dev_pm_ops wkup_m3_ipc_pm_ops = { 559 SET_SYSTEM_SLEEP_PM_OPS(wkup_m3_ipc_suspend, wkup_m3_ipc_resume) 560 }; 561 562 static const struct of_device_id wkup_m3_ipc_of_match[] = { 563 { .compatible = "ti,am3352-wkup-m3-ipc", }, 564 { .compatible = "ti,am4372-wkup-m3-ipc", }, 565 {}, 566 }; 567 MODULE_DEVICE_TABLE(of, wkup_m3_ipc_of_match); 568 569 static struct platform_driver wkup_m3_ipc_driver = { 570 .probe = wkup_m3_ipc_probe, 571 .remove = wkup_m3_ipc_remove, 572 .driver = { 573 .name = "wkup_m3_ipc", 574 .of_match_table = wkup_m3_ipc_of_match, 575 .pm = &wkup_m3_ipc_pm_ops, 576 }, 577 }; 578 579 module_platform_driver(wkup_m3_ipc_driver); 580 581 MODULE_LICENSE("GPL v2"); 582 MODULE_DESCRIPTION("wkup m3 remote processor ipc driver"); 583 MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>"); 584