1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AM33XX Power Management Routines 4 * 5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 * Vaibhav Bedia, Dave Gerlach 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/err.h> 12 #include <linux/genalloc.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/nvmem-consumer.h> 18 #include <linux/of.h> 19 #include <linux/platform_data/pm33xx.h> 20 #include <linux/platform_device.h> 21 #include <linux/rtc.h> 22 #include <linux/rtc/rtc-omap.h> 23 #include <linux/sizes.h> 24 #include <linux/sram.h> 25 #include <linux/suspend.h> 26 #include <linux/ti-emif-sram.h> 27 #include <linux/wkup_m3_ipc.h> 28 29 #include <asm/proc-fns.h> 30 #include <asm/suspend.h> 31 #include <asm/system_misc.h> 32 33 #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \ 34 (unsigned long)pm_sram->do_wfi) 35 36 #define RTC_SCRATCH_RESUME_REG 0 37 #define RTC_SCRATCH_MAGIC_REG 1 38 #define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */ 39 #define GIC_INT_SET_PENDING_BASE 0x200 40 #define AM43XX_GIC_DIST_BASE 0x48241000 41 42 static u32 rtc_magic_val; 43 44 static int (*am33xx_do_wfi_sram)(unsigned long unused); 45 static phys_addr_t am33xx_do_wfi_sram_phys; 46 47 static struct gen_pool *sram_pool, *sram_pool_data; 48 static unsigned long ocmcram_location, ocmcram_location_data; 49 50 static struct rtc_device *omap_rtc; 51 static void __iomem *gic_dist_base; 52 53 static struct am33xx_pm_platform_data *pm_ops; 54 static struct am33xx_pm_sram_addr *pm_sram; 55 56 static struct device *pm33xx_dev; 57 static struct wkup_m3_ipc *m3_ipc; 58 59 #ifdef CONFIG_SUSPEND 60 static int rtc_only_idle; 61 static int retrigger_irq; 62 static unsigned long suspend_wfi_flags; 63 64 static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0, 65 .src = "Unknown", 66 }; 67 68 static struct wkup_m3_wakeup_src rtc_alarm_wakeup = { 69 .irq_nr = 108, .src = "RTC Alarm", 70 }; 71 72 static struct wkup_m3_wakeup_src rtc_ext_wakeup = { 73 .irq_nr = 0, .src = "Ext wakeup", 74 }; 75 #endif 76 77 static u32 sram_suspend_address(unsigned long addr) 78 { 79 return ((unsigned long)am33xx_do_wfi_sram + 80 AMX3_PM_SRAM_SYMBOL_OFFSET(addr)); 81 } 82 83 static int am33xx_push_sram_idle(void) 84 { 85 struct am33xx_pm_ro_sram_data ro_sram_data; 86 int ret; 87 u32 table_addr, ro_data_addr; 88 void *copy_addr; 89 90 ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data; 91 ro_sram_data.amx3_pm_sram_data_phys = 92 gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data); 93 ro_sram_data.rtc_base_virt = pm_ops->get_rtc_base_addr(); 94 95 /* Save physical address to calculate resume offset during pm init */ 96 am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool, 97 ocmcram_location); 98 99 am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location, 100 pm_sram->do_wfi, 101 *pm_sram->do_wfi_sz); 102 if (!am33xx_do_wfi_sram) { 103 dev_err(pm33xx_dev, 104 "PM: %s: am33xx_do_wfi copy to sram failed\n", 105 __func__); 106 return -ENODEV; 107 } 108 109 table_addr = 110 sram_suspend_address((unsigned long)pm_sram->emif_sram_table); 111 ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr); 112 if (ret) { 113 dev_dbg(pm33xx_dev, 114 "PM: %s: EMIF function copy failed\n", __func__); 115 return -EPROBE_DEFER; 116 } 117 118 ro_data_addr = 119 sram_suspend_address((unsigned long)pm_sram->ro_sram_data); 120 copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr, 121 &ro_sram_data, 122 sizeof(ro_sram_data)); 123 if (!copy_addr) { 124 dev_err(pm33xx_dev, 125 "PM: %s: ro_sram_data copy to sram failed\n", 126 __func__); 127 return -ENODEV; 128 } 129 130 return 0; 131 } 132 133 static int __init am43xx_map_gic(void) 134 { 135 gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K); 136 137 if (!gic_dist_base) 138 return -ENOMEM; 139 140 return 0; 141 } 142 143 #ifdef CONFIG_SUSPEND 144 struct wkup_m3_wakeup_src rtc_wake_src(void) 145 { 146 u32 i; 147 148 i = __raw_readl(pm_ops->get_rtc_base_addr() + 0x44) & 0x40; 149 150 if (i) { 151 retrigger_irq = rtc_alarm_wakeup.irq_nr; 152 return rtc_alarm_wakeup; 153 } 154 155 retrigger_irq = rtc_ext_wakeup.irq_nr; 156 157 return rtc_ext_wakeup; 158 } 159 160 int am33xx_rtc_only_idle(unsigned long wfi_flags) 161 { 162 omap_rtc_power_off_program(&omap_rtc->dev); 163 am33xx_do_wfi_sram(wfi_flags); 164 return 0; 165 } 166 167 static int am33xx_pm_suspend(suspend_state_t suspend_state) 168 { 169 int i, ret = 0; 170 171 if (suspend_state == PM_SUSPEND_MEM && 172 pm_ops->check_off_mode_enable()) { 173 pm_ops->prepare_rtc_suspend(); 174 pm_ops->save_context(); 175 suspend_wfi_flags |= WFI_FLAG_RTC_ONLY; 176 clk_save_context(); 177 ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle, 178 suspend_wfi_flags); 179 180 suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY; 181 182 if (!ret) { 183 clk_restore_context(); 184 pm_ops->restore_context(); 185 m3_ipc->ops->set_rtc_only(m3_ipc); 186 am33xx_push_sram_idle(); 187 } 188 } else { 189 ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram, 190 suspend_wfi_flags); 191 } 192 193 if (ret) { 194 dev_err(pm33xx_dev, "PM: Kernel suspend failure\n"); 195 } else { 196 i = m3_ipc->ops->request_pm_status(m3_ipc); 197 198 switch (i) { 199 case 0: 200 dev_info(pm33xx_dev, 201 "PM: Successfully put all powerdomains to target state\n"); 202 break; 203 case 1: 204 dev_err(pm33xx_dev, 205 "PM: Could not transition all powerdomains to target state\n"); 206 ret = -1; 207 break; 208 default: 209 dev_err(pm33xx_dev, 210 "PM: CM3 returned unknown result = %d\n", i); 211 ret = -1; 212 } 213 214 /* print the wakeup reason */ 215 if (rtc_only_idle) { 216 wakeup_src = rtc_wake_src(); 217 pr_info("PM: Wakeup source %s\n", wakeup_src.src); 218 } else { 219 pr_info("PM: Wakeup source %s\n", 220 m3_ipc->ops->request_wake_src(m3_ipc)); 221 } 222 } 223 224 if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) 225 pm_ops->prepare_rtc_resume(); 226 227 return ret; 228 } 229 230 static int am33xx_pm_enter(suspend_state_t suspend_state) 231 { 232 int ret = 0; 233 234 switch (suspend_state) { 235 case PM_SUSPEND_MEM: 236 case PM_SUSPEND_STANDBY: 237 ret = am33xx_pm_suspend(suspend_state); 238 break; 239 default: 240 ret = -EINVAL; 241 } 242 243 return ret; 244 } 245 246 static int am33xx_pm_begin(suspend_state_t state) 247 { 248 int ret = -EINVAL; 249 struct nvmem_device *nvmem; 250 251 if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) { 252 nvmem = devm_nvmem_device_get(&omap_rtc->dev, 253 "omap_rtc_scratch0"); 254 if (nvmem) 255 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4, 256 (void *)&rtc_magic_val); 257 rtc_only_idle = 1; 258 } else { 259 rtc_only_idle = 0; 260 } 261 262 switch (state) { 263 case PM_SUSPEND_MEM: 264 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP); 265 break; 266 case PM_SUSPEND_STANDBY: 267 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY); 268 break; 269 } 270 271 return ret; 272 } 273 274 static void am33xx_pm_end(void) 275 { 276 u32 val = 0; 277 struct nvmem_device *nvmem; 278 279 nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0"); 280 m3_ipc->ops->finish_low_power(m3_ipc); 281 if (rtc_only_idle) { 282 if (retrigger_irq) 283 /* 284 * 32 bits of Interrupt Set-Pending correspond to 32 285 * 32 interrupts. Compute the bit offset of the 286 * Interrupt and set that particular bit 287 * Compute the register offset by dividing interrupt 288 * number by 32 and mutiplying by 4 289 */ 290 writel_relaxed(1 << (retrigger_irq & 31), 291 gic_dist_base + GIC_INT_SET_PENDING_BASE 292 + retrigger_irq / 32 * 4); 293 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4, 294 (void *)&val); 295 } 296 297 rtc_only_idle = 0; 298 } 299 300 static int am33xx_pm_valid(suspend_state_t state) 301 { 302 switch (state) { 303 case PM_SUSPEND_STANDBY: 304 case PM_SUSPEND_MEM: 305 return 1; 306 default: 307 return 0; 308 } 309 } 310 311 static const struct platform_suspend_ops am33xx_pm_ops = { 312 .begin = am33xx_pm_begin, 313 .end = am33xx_pm_end, 314 .enter = am33xx_pm_enter, 315 .valid = am33xx_pm_valid, 316 }; 317 #endif /* CONFIG_SUSPEND */ 318 319 static void am33xx_pm_set_ipc_ops(void) 320 { 321 u32 resume_address; 322 int temp; 323 324 temp = ti_emif_get_mem_type(); 325 if (temp < 0) { 326 dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n"); 327 return; 328 } 329 m3_ipc->ops->set_mem_type(m3_ipc, temp); 330 331 /* Physical resume address to be used by ROM code */ 332 resume_address = am33xx_do_wfi_sram_phys + 333 *pm_sram->resume_offset + 0x4; 334 335 m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address); 336 } 337 338 static void am33xx_pm_free_sram(void) 339 { 340 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz); 341 gen_pool_free(sram_pool_data, ocmcram_location_data, 342 sizeof(struct am33xx_pm_ro_sram_data)); 343 } 344 345 /* 346 * Push the minimal suspend-resume code to SRAM 347 */ 348 static int am33xx_pm_alloc_sram(void) 349 { 350 struct device_node *np; 351 int ret = 0; 352 353 np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu"); 354 if (!np) { 355 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); 356 if (!np) { 357 dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n", 358 __func__); 359 return -ENODEV; 360 } 361 } 362 363 sram_pool = of_gen_pool_get(np, "pm-sram", 0); 364 if (!sram_pool) { 365 dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n", 366 __func__); 367 ret = -ENODEV; 368 goto mpu_put_node; 369 } 370 371 sram_pool_data = of_gen_pool_get(np, "pm-sram", 1); 372 if (!sram_pool_data) { 373 dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n", 374 __func__); 375 ret = -ENODEV; 376 goto mpu_put_node; 377 } 378 379 ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz); 380 if (!ocmcram_location) { 381 dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n", 382 __func__); 383 ret = -ENOMEM; 384 goto mpu_put_node; 385 } 386 387 ocmcram_location_data = gen_pool_alloc(sram_pool_data, 388 sizeof(struct emif_regs_amx3)); 389 if (!ocmcram_location_data) { 390 dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n"); 391 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz); 392 ret = -ENOMEM; 393 } 394 395 mpu_put_node: 396 of_node_put(np); 397 return ret; 398 } 399 400 static int am33xx_pm_rtc_setup(void) 401 { 402 struct device_node *np; 403 unsigned long val = 0; 404 struct nvmem_device *nvmem; 405 406 np = of_find_node_by_name(NULL, "rtc"); 407 408 if (of_device_is_available(np)) { 409 omap_rtc = rtc_class_open("rtc0"); 410 if (!omap_rtc) { 411 pr_warn("PM: rtc0 not available"); 412 return -EPROBE_DEFER; 413 } 414 415 nvmem = devm_nvmem_device_get(&omap_rtc->dev, 416 "omap_rtc_scratch0"); 417 if (nvmem) { 418 nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 419 4, (void *)&rtc_magic_val); 420 if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC) 421 pr_warn("PM: bootloader does not support rtc-only!\n"); 422 423 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 424 4, (void *)&val); 425 val = pm_sram->resume_address; 426 nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4, 427 4, (void *)&val); 428 } 429 } else { 430 pr_warn("PM: no-rtc available, rtc-only mode disabled.\n"); 431 } 432 433 return 0; 434 } 435 436 static int am33xx_pm_probe(struct platform_device *pdev) 437 { 438 struct device *dev = &pdev->dev; 439 int ret; 440 441 if (!of_machine_is_compatible("ti,am33xx") && 442 !of_machine_is_compatible("ti,am43")) 443 return -ENODEV; 444 445 pm_ops = dev->platform_data; 446 if (!pm_ops) { 447 dev_err(dev, "PM: Cannot get core PM ops!\n"); 448 return -ENODEV; 449 } 450 451 ret = am43xx_map_gic(); 452 if (ret) { 453 pr_err("PM: Could not ioremap GIC base\n"); 454 return ret; 455 } 456 457 pm_sram = pm_ops->get_sram_addrs(); 458 if (!pm_sram) { 459 dev_err(dev, "PM: Cannot get PM asm function addresses!!\n"); 460 return -ENODEV; 461 } 462 463 m3_ipc = wkup_m3_ipc_get(); 464 if (!m3_ipc) { 465 pr_err("PM: Cannot get wkup_m3_ipc handle\n"); 466 return -EPROBE_DEFER; 467 } 468 469 pm33xx_dev = dev; 470 471 ret = am33xx_pm_alloc_sram(); 472 if (ret) 473 return ret; 474 475 ret = am33xx_pm_rtc_setup(); 476 if (ret) 477 goto err_free_sram; 478 479 ret = am33xx_push_sram_idle(); 480 if (ret) 481 goto err_free_sram; 482 483 am33xx_pm_set_ipc_ops(); 484 485 #ifdef CONFIG_SUSPEND 486 suspend_set_ops(&am33xx_pm_ops); 487 488 /* 489 * For a system suspend we must flush the caches, we want 490 * the DDR in self-refresh, we want to save the context 491 * of the EMIF, and we want the wkup_m3 to handle low-power 492 * transition. 493 */ 494 suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE; 495 suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH; 496 suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF; 497 suspend_wfi_flags |= WFI_FLAG_WAKE_M3; 498 #endif /* CONFIG_SUSPEND */ 499 500 ret = pm_ops->init(); 501 if (ret) { 502 dev_err(dev, "Unable to call core pm init!\n"); 503 ret = -ENODEV; 504 goto err_put_wkup_m3_ipc; 505 } 506 507 return 0; 508 509 err_put_wkup_m3_ipc: 510 wkup_m3_ipc_put(m3_ipc); 511 err_free_sram: 512 am33xx_pm_free_sram(); 513 pm33xx_dev = NULL; 514 return ret; 515 } 516 517 static int am33xx_pm_remove(struct platform_device *pdev) 518 { 519 suspend_set_ops(NULL); 520 wkup_m3_ipc_put(m3_ipc); 521 am33xx_pm_free_sram(); 522 return 0; 523 } 524 525 static struct platform_driver am33xx_pm_driver = { 526 .driver = { 527 .name = "pm33xx", 528 }, 529 .probe = am33xx_pm_probe, 530 .remove = am33xx_pm_remove, 531 }; 532 module_platform_driver(am33xx_pm_driver); 533 534 MODULE_ALIAS("platform:pm33xx"); 535 MODULE_LICENSE("GPL v2"); 536 MODULE_DESCRIPTION("am33xx power management driver"); 537