1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AM33XX Power Management Routines 4 * 5 * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 * Vaibhav Bedia, Dave Gerlach 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/cpu.h> 11 #include <linux/err.h> 12 #include <linux/genalloc.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/nvmem-consumer.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/platform_data/pm33xx.h> 21 #include <linux/platform_device.h> 22 #include <linux/rtc.h> 23 #include <linux/rtc/rtc-omap.h> 24 #include <linux/sizes.h> 25 #include <linux/sram.h> 26 #include <linux/suspend.h> 27 #include <linux/ti-emif-sram.h> 28 #include <linux/wkup_m3_ipc.h> 29 30 #include <asm/proc-fns.h> 31 #include <asm/suspend.h> 32 #include <asm/system_misc.h> 33 34 #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \ 35 (unsigned long)pm_sram->do_wfi) 36 37 #define RTC_SCRATCH_RESUME_REG 0 38 #define RTC_SCRATCH_MAGIC_REG 1 39 #define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */ 40 #define GIC_INT_SET_PENDING_BASE 0x200 41 #define AM43XX_GIC_DIST_BASE 0x48241000 42 43 static void __iomem *rtc_base_virt; 44 static struct clk *rtc_fck; 45 static u32 rtc_magic_val; 46 47 static int (*am33xx_do_wfi_sram)(unsigned long unused); 48 static phys_addr_t am33xx_do_wfi_sram_phys; 49 50 static struct gen_pool *sram_pool, *sram_pool_data; 51 static unsigned long ocmcram_location, ocmcram_location_data; 52 53 static struct rtc_device *omap_rtc; 54 static void __iomem *gic_dist_base; 55 56 static struct am33xx_pm_platform_data *pm_ops; 57 static struct am33xx_pm_sram_addr *pm_sram; 58 59 static struct device *pm33xx_dev; 60 static struct wkup_m3_ipc *m3_ipc; 61 62 #ifdef CONFIG_SUSPEND 63 static int rtc_only_idle; 64 static int retrigger_irq; 65 static unsigned long suspend_wfi_flags; 66 67 static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0, 68 .src = "Unknown", 69 }; 70 71 static struct wkup_m3_wakeup_src rtc_alarm_wakeup = { 72 .irq_nr = 108, .src = "RTC Alarm", 73 }; 74 75 static struct wkup_m3_wakeup_src rtc_ext_wakeup = { 76 .irq_nr = 0, .src = "Ext wakeup", 77 }; 78 #endif 79 80 static u32 sram_suspend_address(unsigned long addr) 81 { 82 return ((unsigned long)am33xx_do_wfi_sram + 83 AMX3_PM_SRAM_SYMBOL_OFFSET(addr)); 84 } 85 86 static int am33xx_push_sram_idle(void) 87 { 88 struct am33xx_pm_ro_sram_data ro_sram_data; 89 int ret; 90 u32 table_addr, ro_data_addr; 91 void *copy_addr; 92 93 ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data; 94 ro_sram_data.amx3_pm_sram_data_phys = 95 gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data); 96 ro_sram_data.rtc_base_virt = rtc_base_virt; 97 98 /* Save physical address to calculate resume offset during pm init */ 99 am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool, 100 ocmcram_location); 101 102 am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location, 103 pm_sram->do_wfi, 104 *pm_sram->do_wfi_sz); 105 if (!am33xx_do_wfi_sram) { 106 dev_err(pm33xx_dev, 107 "PM: %s: am33xx_do_wfi copy to sram failed\n", 108 __func__); 109 return -ENODEV; 110 } 111 112 table_addr = 113 sram_suspend_address((unsigned long)pm_sram->emif_sram_table); 114 ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr); 115 if (ret) { 116 dev_dbg(pm33xx_dev, 117 "PM: %s: EMIF function copy failed\n", __func__); 118 return -EPROBE_DEFER; 119 } 120 121 ro_data_addr = 122 sram_suspend_address((unsigned long)pm_sram->ro_sram_data); 123 copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr, 124 &ro_sram_data, 125 sizeof(ro_sram_data)); 126 if (!copy_addr) { 127 dev_err(pm33xx_dev, 128 "PM: %s: ro_sram_data copy to sram failed\n", 129 __func__); 130 return -ENODEV; 131 } 132 133 return 0; 134 } 135 136 static int am33xx_do_sram_idle(u32 wfi_flags) 137 { 138 if (!m3_ipc || !pm_ops) 139 return 0; 140 141 if (wfi_flags & WFI_FLAG_WAKE_M3) 142 m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE); 143 144 return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags); 145 } 146 147 static int __init am43xx_map_gic(void) 148 { 149 gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K); 150 151 if (!gic_dist_base) 152 return -ENOMEM; 153 154 return 0; 155 } 156 157 #ifdef CONFIG_SUSPEND 158 static struct wkup_m3_wakeup_src rtc_wake_src(void) 159 { 160 u32 i; 161 162 i = __raw_readl(rtc_base_virt + 0x44) & 0x40; 163 164 if (i) { 165 retrigger_irq = rtc_alarm_wakeup.irq_nr; 166 return rtc_alarm_wakeup; 167 } 168 169 retrigger_irq = rtc_ext_wakeup.irq_nr; 170 171 return rtc_ext_wakeup; 172 } 173 174 static int am33xx_rtc_only_idle(unsigned long wfi_flags) 175 { 176 omap_rtc_power_off_program(&omap_rtc->dev); 177 am33xx_do_wfi_sram(wfi_flags); 178 return 0; 179 } 180 181 /* 182 * Note that the RTC module clock must be re-enabled only for rtc+ddr suspend. 183 * And looks like the module can stay in SYSC_IDLE_SMART_WKUP mode configured 184 * by the interconnect code just fine for both rtc+ddr suspend and retention 185 * suspend. 186 */ 187 static int am33xx_pm_suspend(suspend_state_t suspend_state) 188 { 189 int i, ret = 0; 190 191 if (suspend_state == PM_SUSPEND_MEM && 192 pm_ops->check_off_mode_enable()) { 193 ret = clk_prepare_enable(rtc_fck); 194 if (ret) { 195 dev_err(pm33xx_dev, "Failed to enable clock: %i\n", ret); 196 return ret; 197 } 198 199 pm_ops->save_context(); 200 suspend_wfi_flags |= WFI_FLAG_RTC_ONLY; 201 clk_save_context(); 202 ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle, 203 suspend_wfi_flags); 204 205 suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY; 206 dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n"); 207 208 if (!ret) { 209 clk_restore_context(); 210 pm_ops->restore_context(); 211 m3_ipc->ops->set_rtc_only(m3_ipc); 212 am33xx_push_sram_idle(); 213 } 214 } else { 215 ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram, 216 suspend_wfi_flags); 217 } 218 219 if (ret) { 220 dev_err(pm33xx_dev, "PM: Kernel suspend failure\n"); 221 } else { 222 i = m3_ipc->ops->request_pm_status(m3_ipc); 223 224 switch (i) { 225 case 0: 226 dev_info(pm33xx_dev, 227 "PM: Successfully put all powerdomains to target state\n"); 228 break; 229 case 1: 230 dev_err(pm33xx_dev, 231 "PM: Could not transition all powerdomains to target state\n"); 232 ret = -1; 233 break; 234 default: 235 dev_err(pm33xx_dev, 236 "PM: CM3 returned unknown result = %d\n", i); 237 ret = -1; 238 } 239 240 /* print the wakeup reason */ 241 if (rtc_only_idle) { 242 wakeup_src = rtc_wake_src(); 243 pr_info("PM: Wakeup source %s\n", wakeup_src.src); 244 } else { 245 pr_info("PM: Wakeup source %s\n", 246 m3_ipc->ops->request_wake_src(m3_ipc)); 247 } 248 } 249 250 if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) 251 clk_disable_unprepare(rtc_fck); 252 253 return ret; 254 } 255 256 static int am33xx_pm_enter(suspend_state_t suspend_state) 257 { 258 int ret = 0; 259 260 switch (suspend_state) { 261 case PM_SUSPEND_MEM: 262 case PM_SUSPEND_STANDBY: 263 ret = am33xx_pm_suspend(suspend_state); 264 break; 265 default: 266 ret = -EINVAL; 267 } 268 269 return ret; 270 } 271 272 static int am33xx_pm_begin(suspend_state_t state) 273 { 274 int ret = -EINVAL; 275 struct nvmem_device *nvmem; 276 277 if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) { 278 nvmem = devm_nvmem_device_get(&omap_rtc->dev, 279 "omap_rtc_scratch0"); 280 if (!IS_ERR(nvmem)) 281 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4, 282 (void *)&rtc_magic_val); 283 rtc_only_idle = 1; 284 } else { 285 rtc_only_idle = 0; 286 } 287 288 pm_ops->begin_suspend(); 289 290 switch (state) { 291 case PM_SUSPEND_MEM: 292 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP); 293 break; 294 case PM_SUSPEND_STANDBY: 295 ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY); 296 break; 297 } 298 299 return ret; 300 } 301 302 static void am33xx_pm_end(void) 303 { 304 u32 val = 0; 305 struct nvmem_device *nvmem; 306 307 nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0"); 308 if (IS_ERR(nvmem)) 309 return; 310 311 m3_ipc->ops->finish_low_power(m3_ipc); 312 if (rtc_only_idle) { 313 if (retrigger_irq) { 314 /* 315 * 32 bits of Interrupt Set-Pending correspond to 32 316 * 32 interrupts. Compute the bit offset of the 317 * Interrupt and set that particular bit 318 * Compute the register offset by dividing interrupt 319 * number by 32 and mutiplying by 4 320 */ 321 writel_relaxed(1 << (retrigger_irq & 31), 322 gic_dist_base + GIC_INT_SET_PENDING_BASE 323 + retrigger_irq / 32 * 4); 324 } 325 326 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4, 327 (void *)&val); 328 } 329 330 rtc_only_idle = 0; 331 332 pm_ops->finish_suspend(); 333 } 334 335 static int am33xx_pm_valid(suspend_state_t state) 336 { 337 switch (state) { 338 case PM_SUSPEND_STANDBY: 339 case PM_SUSPEND_MEM: 340 return 1; 341 default: 342 return 0; 343 } 344 } 345 346 static const struct platform_suspend_ops am33xx_pm_ops = { 347 .begin = am33xx_pm_begin, 348 .end = am33xx_pm_end, 349 .enter = am33xx_pm_enter, 350 .valid = am33xx_pm_valid, 351 }; 352 #endif /* CONFIG_SUSPEND */ 353 354 static void am33xx_pm_set_ipc_ops(void) 355 { 356 u32 resume_address; 357 int temp; 358 359 temp = ti_emif_get_mem_type(); 360 if (temp < 0) { 361 dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n"); 362 return; 363 } 364 m3_ipc->ops->set_mem_type(m3_ipc, temp); 365 366 /* Physical resume address to be used by ROM code */ 367 resume_address = am33xx_do_wfi_sram_phys + 368 *pm_sram->resume_offset + 0x4; 369 370 m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address); 371 } 372 373 static void am33xx_pm_free_sram(void) 374 { 375 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz); 376 gen_pool_free(sram_pool_data, ocmcram_location_data, 377 sizeof(struct am33xx_pm_ro_sram_data)); 378 } 379 380 /* 381 * Push the minimal suspend-resume code to SRAM 382 */ 383 static int am33xx_pm_alloc_sram(void) 384 { 385 struct device_node *np; 386 int ret = 0; 387 388 np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu"); 389 if (!np) { 390 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu"); 391 if (!np) { 392 dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n", 393 __func__); 394 return -ENODEV; 395 } 396 } 397 398 sram_pool = of_gen_pool_get(np, "pm-sram", 0); 399 if (!sram_pool) { 400 dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n", 401 __func__); 402 ret = -ENODEV; 403 goto mpu_put_node; 404 } 405 406 sram_pool_data = of_gen_pool_get(np, "pm-sram", 1); 407 if (!sram_pool_data) { 408 dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n", 409 __func__); 410 ret = -ENODEV; 411 goto mpu_put_node; 412 } 413 414 ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz); 415 if (!ocmcram_location) { 416 dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n", 417 __func__); 418 ret = -ENOMEM; 419 goto mpu_put_node; 420 } 421 422 ocmcram_location_data = gen_pool_alloc(sram_pool_data, 423 sizeof(struct emif_regs_amx3)); 424 if (!ocmcram_location_data) { 425 dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n"); 426 gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz); 427 ret = -ENOMEM; 428 } 429 430 mpu_put_node: 431 of_node_put(np); 432 return ret; 433 } 434 435 static int am33xx_pm_rtc_setup(void) 436 { 437 struct device_node *np; 438 unsigned long val = 0; 439 struct nvmem_device *nvmem; 440 int error; 441 442 np = of_find_node_by_name(NULL, "rtc"); 443 444 if (of_device_is_available(np)) { 445 /* RTC interconnect target module clock */ 446 rtc_fck = of_clk_get_by_name(np->parent, "fck"); 447 if (IS_ERR(rtc_fck)) 448 return PTR_ERR(rtc_fck); 449 450 rtc_base_virt = of_iomap(np, 0); 451 if (!rtc_base_virt) { 452 pr_warn("PM: could not iomap rtc"); 453 error = -ENODEV; 454 goto err_clk_put; 455 } 456 457 omap_rtc = rtc_class_open("rtc0"); 458 if (!omap_rtc) { 459 pr_warn("PM: rtc0 not available"); 460 error = -EPROBE_DEFER; 461 goto err_iounmap; 462 } 463 464 nvmem = devm_nvmem_device_get(&omap_rtc->dev, 465 "omap_rtc_scratch0"); 466 if (!IS_ERR(nvmem)) { 467 nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 468 4, (void *)&rtc_magic_val); 469 if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC) 470 pr_warn("PM: bootloader does not support rtc-only!\n"); 471 472 nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 473 4, (void *)&val); 474 val = pm_sram->resume_address; 475 nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4, 476 4, (void *)&val); 477 } 478 } else { 479 pr_warn("PM: no-rtc available, rtc-only mode disabled.\n"); 480 } 481 482 return 0; 483 484 err_iounmap: 485 iounmap(rtc_base_virt); 486 err_clk_put: 487 clk_put(rtc_fck); 488 489 return error; 490 } 491 492 static int am33xx_pm_probe(struct platform_device *pdev) 493 { 494 struct device *dev = &pdev->dev; 495 int ret; 496 497 if (!of_machine_is_compatible("ti,am33xx") && 498 !of_machine_is_compatible("ti,am43")) 499 return -ENODEV; 500 501 pm_ops = dev->platform_data; 502 if (!pm_ops) { 503 dev_err(dev, "PM: Cannot get core PM ops!\n"); 504 return -ENODEV; 505 } 506 507 ret = am43xx_map_gic(); 508 if (ret) { 509 pr_err("PM: Could not ioremap GIC base\n"); 510 return ret; 511 } 512 513 pm_sram = pm_ops->get_sram_addrs(); 514 if (!pm_sram) { 515 dev_err(dev, "PM: Cannot get PM asm function addresses!!\n"); 516 return -ENODEV; 517 } 518 519 m3_ipc = wkup_m3_ipc_get(); 520 if (!m3_ipc) { 521 pr_err("PM: Cannot get wkup_m3_ipc handle\n"); 522 return -EPROBE_DEFER; 523 } 524 525 pm33xx_dev = dev; 526 527 ret = am33xx_pm_alloc_sram(); 528 if (ret) 529 return ret; 530 531 ret = am33xx_pm_rtc_setup(); 532 if (ret) 533 goto err_free_sram; 534 535 ret = am33xx_push_sram_idle(); 536 if (ret) 537 goto err_free_sram; 538 539 am33xx_pm_set_ipc_ops(); 540 541 #ifdef CONFIG_SUSPEND 542 suspend_set_ops(&am33xx_pm_ops); 543 544 /* 545 * For a system suspend we must flush the caches, we want 546 * the DDR in self-refresh, we want to save the context 547 * of the EMIF, and we want the wkup_m3 to handle low-power 548 * transition. 549 */ 550 suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE; 551 suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH; 552 suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF; 553 suspend_wfi_flags |= WFI_FLAG_WAKE_M3; 554 #endif /* CONFIG_SUSPEND */ 555 556 ret = pm_ops->init(am33xx_do_sram_idle); 557 if (ret) { 558 dev_err(dev, "Unable to call core pm init!\n"); 559 ret = -ENODEV; 560 goto err_put_wkup_m3_ipc; 561 } 562 563 return 0; 564 565 err_put_wkup_m3_ipc: 566 wkup_m3_ipc_put(m3_ipc); 567 err_free_sram: 568 am33xx_pm_free_sram(); 569 pm33xx_dev = NULL; 570 return ret; 571 } 572 573 static int am33xx_pm_remove(struct platform_device *pdev) 574 { 575 if (pm_ops->deinit) 576 pm_ops->deinit(); 577 suspend_set_ops(NULL); 578 wkup_m3_ipc_put(m3_ipc); 579 am33xx_pm_free_sram(); 580 iounmap(rtc_base_virt); 581 clk_put(rtc_fck); 582 return 0; 583 } 584 585 static struct platform_driver am33xx_pm_driver = { 586 .driver = { 587 .name = "pm33xx", 588 }, 589 .probe = am33xx_pm_probe, 590 .remove = am33xx_pm_remove, 591 }; 592 module_platform_driver(am33xx_pm_driver); 593 594 MODULE_ALIAS("platform:pm33xx"); 595 MODULE_LICENSE("GPL v2"); 596 MODULE_DESCRIPTION("am33xx power management driver"); 597