1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Keystone Navigator QMSS driver internal header 4 * 5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Sandeep Nair <sandeep_n@ti.com> 7 * Cyril Chemparathy <cyril@ti.com> 8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 */ 10 11 #ifndef __KNAV_QMSS_H__ 12 #define __KNAV_QMSS_H__ 13 14 #include <linux/percpu.h> 15 16 #define THRESH_GTE BIT(7) 17 #define THRESH_LT 0 18 19 #define PDSP_CTRL_PC_MASK 0xffff0000 20 #define PDSP_CTRL_SOFT_RESET BIT(0) 21 #define PDSP_CTRL_ENABLE BIT(1) 22 #define PDSP_CTRL_RUNNING BIT(15) 23 24 #define ACC_MAX_CHANNEL 48 25 #define ACC_DEFAULT_PERIOD 25 /* usecs */ 26 27 #define ACC_CHANNEL_INT_BASE 2 28 29 #define ACC_LIST_ENTRY_TYPE 1 30 #define ACC_LIST_ENTRY_WORDS (1 << ACC_LIST_ENTRY_TYPE) 31 #define ACC_LIST_ENTRY_QUEUE_IDX 0 32 #define ACC_LIST_ENTRY_DESC_IDX (ACC_LIST_ENTRY_WORDS - 1) 33 34 #define ACC_CMD_DISABLE_CHANNEL 0x80 35 #define ACC_CMD_ENABLE_CHANNEL 0x81 36 #define ACC_CFG_MULTI_QUEUE BIT(21) 37 38 #define ACC_INTD_OFFSET_EOI (0x0010) 39 #define ACC_INTD_OFFSET_COUNT(ch) (0x0300 + 4 * (ch)) 40 #define ACC_INTD_OFFSET_STATUS(ch) (0x0200 + 4 * ((ch) / 32)) 41 42 #define RANGE_MAX_IRQS 64 43 44 #define ACC_DESCS_MAX SZ_1K 45 #define ACC_DESCS_MASK (ACC_DESCS_MAX - 1) 46 #define DESC_SIZE_MASK 0xful 47 #define DESC_PTR_MASK (~DESC_SIZE_MASK) 48 49 #define KNAV_NAME_SIZE 32 50 51 enum knav_acc_result { 52 ACC_RET_IDLE, 53 ACC_RET_SUCCESS, 54 ACC_RET_INVALID_COMMAND, 55 ACC_RET_INVALID_CHANNEL, 56 ACC_RET_INACTIVE_CHANNEL, 57 ACC_RET_ACTIVE_CHANNEL, 58 ACC_RET_INVALID_QUEUE, 59 ACC_RET_INVALID_RET, 60 }; 61 62 struct knav_reg_config { 63 u32 revision; 64 u32 __pad1; 65 u32 divert; 66 u32 link_ram_base0; 67 u32 link_ram_size0; 68 u32 link_ram_base1; 69 u32 __pad2[2]; 70 u32 starvation[0]; 71 }; 72 73 struct knav_reg_region { 74 u32 base; 75 u32 start_index; 76 u32 size_count; 77 u32 __pad; 78 }; 79 80 struct knav_reg_pdsp_regs { 81 u32 control; 82 u32 status; 83 u32 cycle_count; 84 u32 stall_count; 85 }; 86 87 struct knav_reg_acc_command { 88 u32 command; 89 u32 queue_mask; 90 u32 list_dma; 91 u32 queue_num; 92 u32 timer_config; 93 }; 94 95 struct knav_link_ram_block { 96 dma_addr_t dma; 97 void *virt; 98 size_t size; 99 }; 100 101 struct knav_acc_info { 102 u32 pdsp_id; 103 u32 start_channel; 104 u32 list_entries; 105 u32 pacing_mode; 106 u32 timer_count; 107 int mem_size; 108 int list_size; 109 struct knav_pdsp_info *pdsp; 110 }; 111 112 struct knav_acc_channel { 113 u32 channel; 114 u32 list_index; 115 u32 open_mask; 116 u32 *list_cpu[2]; 117 dma_addr_t list_dma[2]; 118 char name[KNAV_NAME_SIZE]; 119 atomic_t retrigger_count; 120 }; 121 122 struct knav_pdsp_info { 123 const char *name; 124 struct knav_reg_pdsp_regs __iomem *regs; 125 union { 126 void __iomem *command; 127 struct knav_reg_acc_command __iomem *acc_command; 128 u32 __iomem *qos_command; 129 }; 130 void __iomem *intd; 131 u32 __iomem *iram; 132 u32 id; 133 struct list_head list; 134 bool loaded; 135 bool started; 136 }; 137 138 struct knav_qmgr_info { 139 unsigned start_queue; 140 unsigned num_queues; 141 struct knav_reg_config __iomem *reg_config; 142 struct knav_reg_region __iomem *reg_region; 143 struct knav_reg_queue __iomem *reg_push, *reg_pop, *reg_peek; 144 void __iomem *reg_status; 145 struct list_head list; 146 }; 147 148 #define KNAV_NUM_LINKRAM 2 149 150 /** 151 * struct knav_queue_stats: queue statistics 152 * pushes: number of push operations 153 * pops: number of pop operations 154 * push_errors: number of push errors 155 * pop_errors: number of pop errors 156 * notifies: notifier counts 157 */ 158 struct knav_queue_stats { 159 unsigned int pushes; 160 unsigned int pops; 161 unsigned int push_errors; 162 unsigned int pop_errors; 163 unsigned int notifies; 164 }; 165 166 /** 167 * struct knav_reg_queue: queue registers 168 * @entry_count: valid entries in the queue 169 * @byte_count: total byte count in thhe queue 170 * @packet_size: packet size for the queue 171 * @ptr_size_thresh: packet pointer size threshold 172 */ 173 struct knav_reg_queue { 174 u32 entry_count; 175 u32 byte_count; 176 u32 packet_size; 177 u32 ptr_size_thresh; 178 }; 179 180 /** 181 * struct knav_region: qmss region info 182 * @dma_start, dma_end: start and end dma address 183 * @virt_start, virt_end: start and end virtual address 184 * @desc_size: descriptor size 185 * @used_desc: consumed descriptors 186 * @id: region number 187 * @num_desc: total descriptors 188 * @link_index: index of the first descriptor 189 * @name: region name 190 * @list: instance in the device's region list 191 * @pools: list of descriptor pools in the region 192 */ 193 struct knav_region { 194 dma_addr_t dma_start, dma_end; 195 void *virt_start, *virt_end; 196 unsigned desc_size; 197 unsigned used_desc; 198 unsigned id; 199 unsigned num_desc; 200 unsigned link_index; 201 const char *name; 202 struct list_head list; 203 struct list_head pools; 204 }; 205 206 /** 207 * struct knav_pool: qmss pools 208 * @dev: device pointer 209 * @region: qmss region info 210 * @queue: queue registers 211 * @kdev: qmss device pointer 212 * @region_offset: offset from the base 213 * @num_desc: total descriptors 214 * @desc_size: descriptor size 215 * @region_id: region number 216 * @name: pool name 217 * @list: list head 218 * @region_inst: instance in the region's pool list 219 */ 220 struct knav_pool { 221 struct device *dev; 222 struct knav_region *region; 223 struct knav_queue *queue; 224 struct knav_device *kdev; 225 int region_offset; 226 int num_desc; 227 int desc_size; 228 int region_id; 229 const char *name; 230 struct list_head list; 231 struct list_head region_inst; 232 }; 233 234 /** 235 * struct knav_queue_inst: qmss queue instance properties 236 * @descs: descriptor pointer 237 * @desc_head, desc_tail, desc_count: descriptor counters 238 * @acc: accumulator channel pointer 239 * @kdev: qmss device pointer 240 * @range: range info 241 * @qmgr: queue manager info 242 * @id: queue instance id 243 * @irq_num: irq line number 244 * @notify_needed: notifier needed based on queue type 245 * @num_notifiers: total notifiers 246 * @handles: list head 247 * @name: queue instance name 248 * @irq_name: irq line name 249 */ 250 struct knav_queue_inst { 251 u32 *descs; 252 atomic_t desc_head, desc_tail, desc_count; 253 struct knav_acc_channel *acc; 254 struct knav_device *kdev; 255 struct knav_range_info *range; 256 struct knav_qmgr_info *qmgr; 257 u32 id; 258 int irq_num; 259 int notify_needed; 260 atomic_t num_notifiers; 261 struct list_head handles; 262 const char *name; 263 const char *irq_name; 264 }; 265 266 /** 267 * struct knav_queue: qmss queue properties 268 * @reg_push, reg_pop, reg_peek: push, pop queue registers 269 * @inst: qmss queue instance properties 270 * @notifier_fn: notifier function 271 * @notifier_fn_arg: notifier function argument 272 * @notifier_enabled: notier enabled for a give queue 273 * @rcu: rcu head 274 * @flags: queue flags 275 * @list: list head 276 */ 277 struct knav_queue { 278 struct knav_reg_queue __iomem *reg_push, *reg_pop, *reg_peek; 279 struct knav_queue_inst *inst; 280 struct knav_queue_stats __percpu *stats; 281 knav_queue_notify_fn notifier_fn; 282 void *notifier_fn_arg; 283 atomic_t notifier_enabled; 284 struct rcu_head rcu; 285 unsigned flags; 286 struct list_head list; 287 }; 288 289 enum qmss_version { 290 QMSS, 291 QMSS_66AK2G, 292 }; 293 294 struct knav_device { 295 struct device *dev; 296 unsigned base_id; 297 unsigned num_queues; 298 unsigned num_queues_in_use; 299 unsigned inst_shift; 300 struct knav_link_ram_block link_rams[KNAV_NUM_LINKRAM]; 301 void *instances; 302 struct list_head regions; 303 struct list_head queue_ranges; 304 struct list_head pools; 305 struct list_head pdsps; 306 struct list_head qmgrs; 307 enum qmss_version version; 308 }; 309 310 struct knav_range_ops { 311 int (*init_range)(struct knav_range_info *range); 312 int (*free_range)(struct knav_range_info *range); 313 int (*init_queue)(struct knav_range_info *range, 314 struct knav_queue_inst *inst); 315 int (*open_queue)(struct knav_range_info *range, 316 struct knav_queue_inst *inst, unsigned flags); 317 int (*close_queue)(struct knav_range_info *range, 318 struct knav_queue_inst *inst); 319 int (*set_notify)(struct knav_range_info *range, 320 struct knav_queue_inst *inst, bool enabled); 321 }; 322 323 struct knav_irq_info { 324 int irq; 325 struct cpumask *cpu_mask; 326 }; 327 328 struct knav_range_info { 329 const char *name; 330 struct knav_device *kdev; 331 unsigned queue_base; 332 unsigned num_queues; 333 void *queue_base_inst; 334 unsigned flags; 335 struct list_head list; 336 struct knav_range_ops *ops; 337 struct knav_acc_info acc_info; 338 struct knav_acc_channel *acc; 339 unsigned num_irqs; 340 struct knav_irq_info irqs[RANGE_MAX_IRQS]; 341 }; 342 343 #define RANGE_RESERVED BIT(0) 344 #define RANGE_HAS_IRQ BIT(1) 345 #define RANGE_HAS_ACCUMULATOR BIT(2) 346 #define RANGE_MULTI_QUEUE BIT(3) 347 348 #define for_each_region(kdev, region) \ 349 list_for_each_entry(region, &kdev->regions, list) 350 351 #define first_region(kdev) \ 352 list_first_entry_or_null(&kdev->regions, \ 353 struct knav_region, list) 354 355 #define for_each_queue_range(kdev, range) \ 356 list_for_each_entry(range, &kdev->queue_ranges, list) 357 358 #define first_queue_range(kdev) \ 359 list_first_entry_or_null(&kdev->queue_ranges, \ 360 struct knav_range_info, list) 361 362 #define for_each_pool(kdev, pool) \ 363 list_for_each_entry(pool, &kdev->pools, list) 364 365 #define for_each_pdsp(kdev, pdsp) \ 366 list_for_each_entry(pdsp, &kdev->pdsps, list) 367 368 #define for_each_qmgr(kdev, qmgr) \ 369 list_for_each_entry(qmgr, &kdev->qmgrs, list) 370 371 static inline struct knav_pdsp_info * 372 knav_find_pdsp(struct knav_device *kdev, unsigned pdsp_id) 373 { 374 struct knav_pdsp_info *pdsp; 375 376 for_each_pdsp(kdev, pdsp) 377 if (pdsp_id == pdsp->id) 378 return pdsp; 379 return NULL; 380 } 381 382 extern int knav_init_acc_range(struct knav_device *kdev, 383 struct device_node *node, 384 struct knav_range_info *range); 385 extern void knav_queue_notify(struct knav_queue_inst *inst); 386 387 #endif /* __KNAV_QMSS_H__ */ 388