12aec85b2SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
288139ed0SSantosh Shilimkar /*
388139ed0SSantosh Shilimkar * Copyright (C) 2014 Texas Instruments Incorporated
488139ed0SSantosh Shilimkar * Authors: Santosh Shilimkar <santosh.shilimkar@ti.com>
588139ed0SSantosh Shilimkar * Sandeep Nair <sandeep_n@ti.com>
688139ed0SSantosh Shilimkar * Cyril Chemparathy <cyril@ti.com>
788139ed0SSantosh Shilimkar */
888139ed0SSantosh Shilimkar
988139ed0SSantosh Shilimkar #include <linux/io.h>
1088139ed0SSantosh Shilimkar #include <linux/sched.h>
1188139ed0SSantosh Shilimkar #include <linux/module.h>
1288139ed0SSantosh Shilimkar #include <linux/dma-direction.h>
1388139ed0SSantosh Shilimkar #include <linux/interrupt.h>
1488139ed0SSantosh Shilimkar #include <linux/pm_runtime.h>
1588139ed0SSantosh Shilimkar #include <linux/of_dma.h>
1688139ed0SSantosh Shilimkar #include <linux/of_address.h>
1788139ed0SSantosh Shilimkar #include <linux/platform_device.h>
1888139ed0SSantosh Shilimkar #include <linux/soc/ti/knav_dma.h>
1988139ed0SSantosh Shilimkar #include <linux/debugfs.h>
2088139ed0SSantosh Shilimkar #include <linux/seq_file.h>
2188139ed0SSantosh Shilimkar
2288139ed0SSantosh Shilimkar #define REG_MASK 0xffffffff
2388139ed0SSantosh Shilimkar
2488139ed0SSantosh Shilimkar #define DMA_LOOPBACK BIT(31)
2588139ed0SSantosh Shilimkar #define DMA_ENABLE BIT(31)
2688139ed0SSantosh Shilimkar #define DMA_TEARDOWN BIT(30)
2788139ed0SSantosh Shilimkar
2888139ed0SSantosh Shilimkar #define DMA_TX_FILT_PSWORDS BIT(29)
2988139ed0SSantosh Shilimkar #define DMA_TX_FILT_EINFO BIT(30)
3088139ed0SSantosh Shilimkar #define DMA_TX_PRIO_SHIFT 0
3188139ed0SSantosh Shilimkar #define DMA_RX_PRIO_SHIFT 16
3288139ed0SSantosh Shilimkar #define DMA_PRIO_MASK GENMASK(3, 0)
3388139ed0SSantosh Shilimkar #define DMA_PRIO_DEFAULT 0
3488139ed0SSantosh Shilimkar #define DMA_RX_TIMEOUT_DEFAULT 17500 /* cycles */
3588139ed0SSantosh Shilimkar #define DMA_RX_TIMEOUT_MASK GENMASK(16, 0)
3688139ed0SSantosh Shilimkar #define DMA_RX_TIMEOUT_SHIFT 0
3788139ed0SSantosh Shilimkar
3888139ed0SSantosh Shilimkar #define CHAN_HAS_EPIB BIT(30)
3988139ed0SSantosh Shilimkar #define CHAN_HAS_PSINFO BIT(29)
4088139ed0SSantosh Shilimkar #define CHAN_ERR_RETRY BIT(28)
4188139ed0SSantosh Shilimkar #define CHAN_PSINFO_AT_SOP BIT(25)
4288139ed0SSantosh Shilimkar #define CHAN_SOP_OFF_SHIFT 16
4388139ed0SSantosh Shilimkar #define CHAN_SOP_OFF_MASK GENMASK(9, 0)
4488139ed0SSantosh Shilimkar #define DESC_TYPE_SHIFT 26
4588139ed0SSantosh Shilimkar #define DESC_TYPE_MASK GENMASK(2, 0)
4688139ed0SSantosh Shilimkar
4788139ed0SSantosh Shilimkar /*
4888139ed0SSantosh Shilimkar * QMGR & QNUM together make up 14 bits with QMGR as the 2 MSb's in the logical
4988139ed0SSantosh Shilimkar * navigator cloud mapping scheme.
5088139ed0SSantosh Shilimkar * using the 14bit physical queue numbers directly maps into this scheme.
5188139ed0SSantosh Shilimkar */
5288139ed0SSantosh Shilimkar #define CHAN_QNUM_MASK GENMASK(14, 0)
5388139ed0SSantosh Shilimkar #define DMA_MAX_QMS 4
5488139ed0SSantosh Shilimkar #define DMA_TIMEOUT 1 /* msecs */
5588139ed0SSantosh Shilimkar #define DMA_INVALID_ID 0xffff
5688139ed0SSantosh Shilimkar
5788139ed0SSantosh Shilimkar struct reg_global {
5888139ed0SSantosh Shilimkar u32 revision;
5988139ed0SSantosh Shilimkar u32 perf_control;
6088139ed0SSantosh Shilimkar u32 emulation_control;
6188139ed0SSantosh Shilimkar u32 priority_control;
6288139ed0SSantosh Shilimkar u32 qm_base_address[DMA_MAX_QMS];
6388139ed0SSantosh Shilimkar };
6488139ed0SSantosh Shilimkar
6588139ed0SSantosh Shilimkar struct reg_chan {
6688139ed0SSantosh Shilimkar u32 control;
6788139ed0SSantosh Shilimkar u32 mode;
6888139ed0SSantosh Shilimkar u32 __rsvd[6];
6988139ed0SSantosh Shilimkar };
7088139ed0SSantosh Shilimkar
7188139ed0SSantosh Shilimkar struct reg_tx_sched {
7288139ed0SSantosh Shilimkar u32 prio;
7388139ed0SSantosh Shilimkar };
7488139ed0SSantosh Shilimkar
7588139ed0SSantosh Shilimkar struct reg_rx_flow {
7688139ed0SSantosh Shilimkar u32 control;
7788139ed0SSantosh Shilimkar u32 tags;
7888139ed0SSantosh Shilimkar u32 tag_sel;
7988139ed0SSantosh Shilimkar u32 fdq_sel[2];
8088139ed0SSantosh Shilimkar u32 thresh[3];
8188139ed0SSantosh Shilimkar };
8288139ed0SSantosh Shilimkar
8388139ed0SSantosh Shilimkar struct knav_dma_pool_device {
8488139ed0SSantosh Shilimkar struct device *dev;
8588139ed0SSantosh Shilimkar struct list_head list;
8688139ed0SSantosh Shilimkar };
8788139ed0SSantosh Shilimkar
8888139ed0SSantosh Shilimkar struct knav_dma_device {
8988139ed0SSantosh Shilimkar bool loopback, enable_all;
9088139ed0SSantosh Shilimkar unsigned tx_priority, rx_priority, rx_timeout;
9188139ed0SSantosh Shilimkar unsigned logical_queue_managers;
9288139ed0SSantosh Shilimkar unsigned qm_base_address[DMA_MAX_QMS];
9388139ed0SSantosh Shilimkar struct reg_global __iomem *reg_global;
9488139ed0SSantosh Shilimkar struct reg_chan __iomem *reg_tx_chan;
9588139ed0SSantosh Shilimkar struct reg_rx_flow __iomem *reg_rx_flow;
9688139ed0SSantosh Shilimkar struct reg_chan __iomem *reg_rx_chan;
9788139ed0SSantosh Shilimkar struct reg_tx_sched __iomem *reg_tx_sched;
9888139ed0SSantosh Shilimkar unsigned max_rx_chan, max_tx_chan;
9988139ed0SSantosh Shilimkar unsigned max_rx_flow;
10088139ed0SSantosh Shilimkar char name[32];
10188139ed0SSantosh Shilimkar atomic_t ref_count;
10288139ed0SSantosh Shilimkar struct list_head list;
10388139ed0SSantosh Shilimkar struct list_head chan_list;
10488139ed0SSantosh Shilimkar spinlock_t lock;
10588139ed0SSantosh Shilimkar };
10688139ed0SSantosh Shilimkar
10788139ed0SSantosh Shilimkar struct knav_dma_chan {
10888139ed0SSantosh Shilimkar enum dma_transfer_direction direction;
10988139ed0SSantosh Shilimkar struct knav_dma_device *dma;
11088139ed0SSantosh Shilimkar atomic_t ref_count;
11188139ed0SSantosh Shilimkar
11288139ed0SSantosh Shilimkar /* registers */
11388139ed0SSantosh Shilimkar struct reg_chan __iomem *reg_chan;
11488139ed0SSantosh Shilimkar struct reg_tx_sched __iomem *reg_tx_sched;
11588139ed0SSantosh Shilimkar struct reg_rx_flow __iomem *reg_rx_flow;
11688139ed0SSantosh Shilimkar
11788139ed0SSantosh Shilimkar /* configuration stuff */
11888139ed0SSantosh Shilimkar unsigned channel, flow;
11988139ed0SSantosh Shilimkar struct knav_dma_cfg cfg;
12088139ed0SSantosh Shilimkar struct list_head list;
12188139ed0SSantosh Shilimkar spinlock_t lock;
12288139ed0SSantosh Shilimkar };
12388139ed0SSantosh Shilimkar
12488139ed0SSantosh Shilimkar #define chan_number(ch) ((ch->direction == DMA_MEM_TO_DEV) ? \
12588139ed0SSantosh Shilimkar ch->channel : ch->flow)
12688139ed0SSantosh Shilimkar
12788139ed0SSantosh Shilimkar static struct knav_dma_pool_device *kdev;
12888139ed0SSantosh Shilimkar
129a2dd6877SMurali Karicheri static bool device_ready;
knav_dma_device_ready(void)130a2dd6877SMurali Karicheri bool knav_dma_device_ready(void)
131a2dd6877SMurali Karicheri {
132a2dd6877SMurali Karicheri return device_ready;
133a2dd6877SMurali Karicheri }
134a2dd6877SMurali Karicheri EXPORT_SYMBOL_GPL(knav_dma_device_ready);
135a2dd6877SMurali Karicheri
check_config(struct knav_dma_chan * chan,struct knav_dma_cfg * cfg)13688139ed0SSantosh Shilimkar static bool check_config(struct knav_dma_chan *chan, struct knav_dma_cfg *cfg)
13788139ed0SSantosh Shilimkar {
13888139ed0SSantosh Shilimkar if (!memcmp(&chan->cfg, cfg, sizeof(*cfg)))
13988139ed0SSantosh Shilimkar return true;
14088139ed0SSantosh Shilimkar else
14188139ed0SSantosh Shilimkar return false;
14288139ed0SSantosh Shilimkar }
14388139ed0SSantosh Shilimkar
chan_start(struct knav_dma_chan * chan,struct knav_dma_cfg * cfg)14488139ed0SSantosh Shilimkar static int chan_start(struct knav_dma_chan *chan,
14588139ed0SSantosh Shilimkar struct knav_dma_cfg *cfg)
14688139ed0SSantosh Shilimkar {
14788139ed0SSantosh Shilimkar u32 v = 0;
14888139ed0SSantosh Shilimkar
14988139ed0SSantosh Shilimkar spin_lock(&chan->lock);
15088139ed0SSantosh Shilimkar if ((chan->direction == DMA_MEM_TO_DEV) && chan->reg_chan) {
15188139ed0SSantosh Shilimkar if (cfg->u.tx.filt_pswords)
15288139ed0SSantosh Shilimkar v |= DMA_TX_FILT_PSWORDS;
15388139ed0SSantosh Shilimkar if (cfg->u.tx.filt_einfo)
15488139ed0SSantosh Shilimkar v |= DMA_TX_FILT_EINFO;
15588139ed0SSantosh Shilimkar writel_relaxed(v, &chan->reg_chan->mode);
15688139ed0SSantosh Shilimkar writel_relaxed(DMA_ENABLE, &chan->reg_chan->control);
15788139ed0SSantosh Shilimkar }
15888139ed0SSantosh Shilimkar
15988139ed0SSantosh Shilimkar if (chan->reg_tx_sched)
16088139ed0SSantosh Shilimkar writel_relaxed(cfg->u.tx.priority, &chan->reg_tx_sched->prio);
16188139ed0SSantosh Shilimkar
16288139ed0SSantosh Shilimkar if (chan->reg_rx_flow) {
16388139ed0SSantosh Shilimkar v = 0;
16488139ed0SSantosh Shilimkar
16588139ed0SSantosh Shilimkar if (cfg->u.rx.einfo_present)
16688139ed0SSantosh Shilimkar v |= CHAN_HAS_EPIB;
16788139ed0SSantosh Shilimkar if (cfg->u.rx.psinfo_present)
16888139ed0SSantosh Shilimkar v |= CHAN_HAS_PSINFO;
16988139ed0SSantosh Shilimkar if (cfg->u.rx.err_mode == DMA_RETRY)
17088139ed0SSantosh Shilimkar v |= CHAN_ERR_RETRY;
17188139ed0SSantosh Shilimkar v |= (cfg->u.rx.desc_type & DESC_TYPE_MASK) << DESC_TYPE_SHIFT;
17288139ed0SSantosh Shilimkar if (cfg->u.rx.psinfo_at_sop)
17388139ed0SSantosh Shilimkar v |= CHAN_PSINFO_AT_SOP;
17488139ed0SSantosh Shilimkar v |= (cfg->u.rx.sop_offset & CHAN_SOP_OFF_MASK)
17588139ed0SSantosh Shilimkar << CHAN_SOP_OFF_SHIFT;
17688139ed0SSantosh Shilimkar v |= cfg->u.rx.dst_q & CHAN_QNUM_MASK;
17788139ed0SSantosh Shilimkar
17888139ed0SSantosh Shilimkar writel_relaxed(v, &chan->reg_rx_flow->control);
17988139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->tags);
18088139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
18188139ed0SSantosh Shilimkar
18288139ed0SSantosh Shilimkar v = cfg->u.rx.fdq[0] << 16;
18388139ed0SSantosh Shilimkar v |= cfg->u.rx.fdq[1] & CHAN_QNUM_MASK;
18488139ed0SSantosh Shilimkar writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[0]);
18588139ed0SSantosh Shilimkar
18688139ed0SSantosh Shilimkar v = cfg->u.rx.fdq[2] << 16;
18788139ed0SSantosh Shilimkar v |= cfg->u.rx.fdq[3] & CHAN_QNUM_MASK;
18888139ed0SSantosh Shilimkar writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[1]);
18988139ed0SSantosh Shilimkar
19088139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
19188139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
19288139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
19388139ed0SSantosh Shilimkar }
19488139ed0SSantosh Shilimkar
19588139ed0SSantosh Shilimkar /* Keep a copy of the cfg */
19688139ed0SSantosh Shilimkar memcpy(&chan->cfg, cfg, sizeof(*cfg));
19788139ed0SSantosh Shilimkar spin_unlock(&chan->lock);
19888139ed0SSantosh Shilimkar
19988139ed0SSantosh Shilimkar return 0;
20088139ed0SSantosh Shilimkar }
20188139ed0SSantosh Shilimkar
chan_teardown(struct knav_dma_chan * chan)20288139ed0SSantosh Shilimkar static int chan_teardown(struct knav_dma_chan *chan)
20388139ed0SSantosh Shilimkar {
20488139ed0SSantosh Shilimkar unsigned long end, value;
20588139ed0SSantosh Shilimkar
20688139ed0SSantosh Shilimkar if (!chan->reg_chan)
20788139ed0SSantosh Shilimkar return 0;
20888139ed0SSantosh Shilimkar
20988139ed0SSantosh Shilimkar /* indicate teardown */
21088139ed0SSantosh Shilimkar writel_relaxed(DMA_TEARDOWN, &chan->reg_chan->control);
21188139ed0SSantosh Shilimkar
21288139ed0SSantosh Shilimkar /* wait for the dma to shut itself down */
21388139ed0SSantosh Shilimkar end = jiffies + msecs_to_jiffies(DMA_TIMEOUT);
21488139ed0SSantosh Shilimkar do {
21588139ed0SSantosh Shilimkar value = readl_relaxed(&chan->reg_chan->control);
21688139ed0SSantosh Shilimkar if ((value & DMA_ENABLE) == 0)
21788139ed0SSantosh Shilimkar break;
21888139ed0SSantosh Shilimkar } while (time_after(end, jiffies));
21988139ed0SSantosh Shilimkar
22088139ed0SSantosh Shilimkar if (readl_relaxed(&chan->reg_chan->control) & DMA_ENABLE) {
22188139ed0SSantosh Shilimkar dev_err(kdev->dev, "timeout waiting for teardown\n");
22288139ed0SSantosh Shilimkar return -ETIMEDOUT;
22388139ed0SSantosh Shilimkar }
22488139ed0SSantosh Shilimkar
22588139ed0SSantosh Shilimkar return 0;
22688139ed0SSantosh Shilimkar }
22788139ed0SSantosh Shilimkar
chan_stop(struct knav_dma_chan * chan)22888139ed0SSantosh Shilimkar static void chan_stop(struct knav_dma_chan *chan)
22988139ed0SSantosh Shilimkar {
23088139ed0SSantosh Shilimkar spin_lock(&chan->lock);
23188139ed0SSantosh Shilimkar if (chan->reg_rx_flow) {
23288139ed0SSantosh Shilimkar /* first detach fdqs, starve out the flow */
23388139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[0]);
23488139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[1]);
23588139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
23688139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
23788139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
23888139ed0SSantosh Shilimkar }
23988139ed0SSantosh Shilimkar
24088139ed0SSantosh Shilimkar /* teardown the dma channel */
24188139ed0SSantosh Shilimkar chan_teardown(chan);
24288139ed0SSantosh Shilimkar
24388139ed0SSantosh Shilimkar /* then disconnect the completion side */
24488139ed0SSantosh Shilimkar if (chan->reg_rx_flow) {
24588139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->control);
24688139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->tags);
24788139ed0SSantosh Shilimkar writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
24888139ed0SSantosh Shilimkar }
24988139ed0SSantosh Shilimkar
25088139ed0SSantosh Shilimkar memset(&chan->cfg, 0, sizeof(struct knav_dma_cfg));
25188139ed0SSantosh Shilimkar spin_unlock(&chan->lock);
25288139ed0SSantosh Shilimkar
25388139ed0SSantosh Shilimkar dev_dbg(kdev->dev, "channel stopped\n");
25488139ed0SSantosh Shilimkar }
25588139ed0SSantosh Shilimkar
dma_hw_enable_all(struct knav_dma_device * dma)25688139ed0SSantosh Shilimkar static void dma_hw_enable_all(struct knav_dma_device *dma)
25788139ed0SSantosh Shilimkar {
25888139ed0SSantosh Shilimkar int i;
25988139ed0SSantosh Shilimkar
26088139ed0SSantosh Shilimkar for (i = 0; i < dma->max_tx_chan; i++) {
26188139ed0SSantosh Shilimkar writel_relaxed(0, &dma->reg_tx_chan[i].mode);
26288139ed0SSantosh Shilimkar writel_relaxed(DMA_ENABLE, &dma->reg_tx_chan[i].control);
26388139ed0SSantosh Shilimkar }
26488139ed0SSantosh Shilimkar }
26588139ed0SSantosh Shilimkar
26688139ed0SSantosh Shilimkar
knav_dma_hw_init(struct knav_dma_device * dma)26788139ed0SSantosh Shilimkar static void knav_dma_hw_init(struct knav_dma_device *dma)
26888139ed0SSantosh Shilimkar {
26988139ed0SSantosh Shilimkar unsigned v;
27088139ed0SSantosh Shilimkar int i;
27188139ed0SSantosh Shilimkar
27288139ed0SSantosh Shilimkar spin_lock(&dma->lock);
27388139ed0SSantosh Shilimkar v = dma->loopback ? DMA_LOOPBACK : 0;
27488139ed0SSantosh Shilimkar writel_relaxed(v, &dma->reg_global->emulation_control);
27588139ed0SSantosh Shilimkar
27688139ed0SSantosh Shilimkar v = readl_relaxed(&dma->reg_global->perf_control);
27788139ed0SSantosh Shilimkar v |= ((dma->rx_timeout & DMA_RX_TIMEOUT_MASK) << DMA_RX_TIMEOUT_SHIFT);
27888139ed0SSantosh Shilimkar writel_relaxed(v, &dma->reg_global->perf_control);
27988139ed0SSantosh Shilimkar
28088139ed0SSantosh Shilimkar v = ((dma->tx_priority << DMA_TX_PRIO_SHIFT) |
28188139ed0SSantosh Shilimkar (dma->rx_priority << DMA_RX_PRIO_SHIFT));
28288139ed0SSantosh Shilimkar
28388139ed0SSantosh Shilimkar writel_relaxed(v, &dma->reg_global->priority_control);
28488139ed0SSantosh Shilimkar
28588139ed0SSantosh Shilimkar /* Always enable all Rx channels. Rx paths are managed using flows */
28688139ed0SSantosh Shilimkar for (i = 0; i < dma->max_rx_chan; i++)
28788139ed0SSantosh Shilimkar writel_relaxed(DMA_ENABLE, &dma->reg_rx_chan[i].control);
28888139ed0SSantosh Shilimkar
28988139ed0SSantosh Shilimkar for (i = 0; i < dma->logical_queue_managers; i++)
29088139ed0SSantosh Shilimkar writel_relaxed(dma->qm_base_address[i],
29188139ed0SSantosh Shilimkar &dma->reg_global->qm_base_address[i]);
29288139ed0SSantosh Shilimkar spin_unlock(&dma->lock);
29388139ed0SSantosh Shilimkar }
29488139ed0SSantosh Shilimkar
knav_dma_hw_destroy(struct knav_dma_device * dma)29588139ed0SSantosh Shilimkar static void knav_dma_hw_destroy(struct knav_dma_device *dma)
29688139ed0SSantosh Shilimkar {
29788139ed0SSantosh Shilimkar int i;
29888139ed0SSantosh Shilimkar unsigned v;
29988139ed0SSantosh Shilimkar
30088139ed0SSantosh Shilimkar spin_lock(&dma->lock);
30188139ed0SSantosh Shilimkar v = ~DMA_ENABLE & REG_MASK;
30288139ed0SSantosh Shilimkar
30388139ed0SSantosh Shilimkar for (i = 0; i < dma->max_rx_chan; i++)
30488139ed0SSantosh Shilimkar writel_relaxed(v, &dma->reg_rx_chan[i].control);
30588139ed0SSantosh Shilimkar
30688139ed0SSantosh Shilimkar for (i = 0; i < dma->max_tx_chan; i++)
30788139ed0SSantosh Shilimkar writel_relaxed(v, &dma->reg_tx_chan[i].control);
30888139ed0SSantosh Shilimkar spin_unlock(&dma->lock);
30988139ed0SSantosh Shilimkar }
31088139ed0SSantosh Shilimkar
dma_debug_show_channels(struct seq_file * s,struct knav_dma_chan * chan)31188139ed0SSantosh Shilimkar static void dma_debug_show_channels(struct seq_file *s,
31288139ed0SSantosh Shilimkar struct knav_dma_chan *chan)
31388139ed0SSantosh Shilimkar {
31488139ed0SSantosh Shilimkar int i;
31588139ed0SSantosh Shilimkar
31688139ed0SSantosh Shilimkar seq_printf(s, "\t%s %d:\t",
31788139ed0SSantosh Shilimkar ((chan->direction == DMA_MEM_TO_DEV) ? "tx chan" : "rx flow"),
31888139ed0SSantosh Shilimkar chan_number(chan));
31988139ed0SSantosh Shilimkar
32088139ed0SSantosh Shilimkar if (chan->direction == DMA_MEM_TO_DEV) {
32188139ed0SSantosh Shilimkar seq_printf(s, "einfo - %d, pswords - %d, priority - %d\n",
32288139ed0SSantosh Shilimkar chan->cfg.u.tx.filt_einfo,
32388139ed0SSantosh Shilimkar chan->cfg.u.tx.filt_pswords,
32488139ed0SSantosh Shilimkar chan->cfg.u.tx.priority);
32588139ed0SSantosh Shilimkar } else {
32688139ed0SSantosh Shilimkar seq_printf(s, "einfo - %d, psinfo - %d, desc_type - %d\n",
32788139ed0SSantosh Shilimkar chan->cfg.u.rx.einfo_present,
32888139ed0SSantosh Shilimkar chan->cfg.u.rx.psinfo_present,
32988139ed0SSantosh Shilimkar chan->cfg.u.rx.desc_type);
33088139ed0SSantosh Shilimkar seq_printf(s, "\t\t\tdst_q: [%d], thresh: %d fdq: ",
33188139ed0SSantosh Shilimkar chan->cfg.u.rx.dst_q,
33288139ed0SSantosh Shilimkar chan->cfg.u.rx.thresh);
33388139ed0SSantosh Shilimkar for (i = 0; i < KNAV_DMA_FDQ_PER_CHAN; i++)
33488139ed0SSantosh Shilimkar seq_printf(s, "[%d]", chan->cfg.u.rx.fdq[i]);
33588139ed0SSantosh Shilimkar seq_printf(s, "\n");
33688139ed0SSantosh Shilimkar }
33788139ed0SSantosh Shilimkar }
33888139ed0SSantosh Shilimkar
dma_debug_show_devices(struct seq_file * s,struct knav_dma_device * dma)33988139ed0SSantosh Shilimkar static void dma_debug_show_devices(struct seq_file *s,
34088139ed0SSantosh Shilimkar struct knav_dma_device *dma)
34188139ed0SSantosh Shilimkar {
34288139ed0SSantosh Shilimkar struct knav_dma_chan *chan;
34388139ed0SSantosh Shilimkar
34488139ed0SSantosh Shilimkar list_for_each_entry(chan, &dma->chan_list, list) {
34588139ed0SSantosh Shilimkar if (atomic_read(&chan->ref_count))
34688139ed0SSantosh Shilimkar dma_debug_show_channels(s, chan);
34788139ed0SSantosh Shilimkar }
34888139ed0SSantosh Shilimkar }
34988139ed0SSantosh Shilimkar
knav_dma_debug_show(struct seq_file * s,void * v)35074e0e43aSQinglang Miao static int knav_dma_debug_show(struct seq_file *s, void *v)
35188139ed0SSantosh Shilimkar {
35288139ed0SSantosh Shilimkar struct knav_dma_device *dma;
35388139ed0SSantosh Shilimkar
35488139ed0SSantosh Shilimkar list_for_each_entry(dma, &kdev->list, list) {
35588139ed0SSantosh Shilimkar if (atomic_read(&dma->ref_count)) {
35688139ed0SSantosh Shilimkar seq_printf(s, "%s : max_tx_chan: (%d), max_rx_flows: (%d)\n",
35788139ed0SSantosh Shilimkar dma->name, dma->max_tx_chan, dma->max_rx_flow);
35888139ed0SSantosh Shilimkar dma_debug_show_devices(s, dma);
35988139ed0SSantosh Shilimkar }
36088139ed0SSantosh Shilimkar }
36188139ed0SSantosh Shilimkar
36288139ed0SSantosh Shilimkar return 0;
36388139ed0SSantosh Shilimkar }
36488139ed0SSantosh Shilimkar
36574e0e43aSQinglang Miao DEFINE_SHOW_ATTRIBUTE(knav_dma_debug);
36688139ed0SSantosh Shilimkar
of_channel_match_helper(struct device_node * np,const char * name,const char ** dma_instance)36788139ed0SSantosh Shilimkar static int of_channel_match_helper(struct device_node *np, const char *name,
36888139ed0SSantosh Shilimkar const char **dma_instance)
36988139ed0SSantosh Shilimkar {
37088139ed0SSantosh Shilimkar struct of_phandle_args args;
37188139ed0SSantosh Shilimkar struct device_node *dma_node;
37288139ed0SSantosh Shilimkar int index;
37388139ed0SSantosh Shilimkar
37488139ed0SSantosh Shilimkar dma_node = of_parse_phandle(np, "ti,navigator-dmas", 0);
37588139ed0SSantosh Shilimkar if (!dma_node)
37688139ed0SSantosh Shilimkar return -ENODEV;
37788139ed0SSantosh Shilimkar
37888139ed0SSantosh Shilimkar *dma_instance = dma_node->name;
37988139ed0SSantosh Shilimkar index = of_property_match_string(np, "ti,navigator-dma-names", name);
38088139ed0SSantosh Shilimkar if (index < 0) {
381e3d132d1SMasanari Iida dev_err(kdev->dev, "No 'ti,navigator-dma-names' property\n");
38288139ed0SSantosh Shilimkar return -ENODEV;
38388139ed0SSantosh Shilimkar }
38488139ed0SSantosh Shilimkar
38588139ed0SSantosh Shilimkar if (of_parse_phandle_with_fixed_args(np, "ti,navigator-dmas",
38688139ed0SSantosh Shilimkar 1, index, &args)) {
3874ee34aaeSMurali Karicheri dev_err(kdev->dev, "Missing the phandle args name %s\n", name);
38888139ed0SSantosh Shilimkar return -ENODEV;
38988139ed0SSantosh Shilimkar }
39088139ed0SSantosh Shilimkar
39188139ed0SSantosh Shilimkar if (args.args[0] < 0) {
39288139ed0SSantosh Shilimkar dev_err(kdev->dev, "Missing args for %s\n", name);
39388139ed0SSantosh Shilimkar return -ENODEV;
39488139ed0SSantosh Shilimkar }
39588139ed0SSantosh Shilimkar
39688139ed0SSantosh Shilimkar return args.args[0];
39788139ed0SSantosh Shilimkar }
39888139ed0SSantosh Shilimkar
39988139ed0SSantosh Shilimkar /**
40088139ed0SSantosh Shilimkar * knav_dma_open_channel() - try to setup an exclusive slave channel
40188139ed0SSantosh Shilimkar * @dev: pointer to client device structure
40288139ed0SSantosh Shilimkar * @name: slave channel name
40388139ed0SSantosh Shilimkar * @config: dma configuration parameters
40488139ed0SSantosh Shilimkar *
4055b6cb43bSIvan Khoronzhuk * Returns pointer to appropriate DMA channel on success or error.
40688139ed0SSantosh Shilimkar */
knav_dma_open_channel(struct device * dev,const char * name,struct knav_dma_cfg * config)40788139ed0SSantosh Shilimkar void *knav_dma_open_channel(struct device *dev, const char *name,
40888139ed0SSantosh Shilimkar struct knav_dma_cfg *config)
40988139ed0SSantosh Shilimkar {
410d281a982SJakob Koschel struct knav_dma_device *dma = NULL, *iter1;
411d281a982SJakob Koschel struct knav_dma_chan *chan = NULL, *iter2;
41288139ed0SSantosh Shilimkar int chan_num = -1;
41388139ed0SSantosh Shilimkar const char *instance;
41488139ed0SSantosh Shilimkar
41588139ed0SSantosh Shilimkar if (!kdev) {
41688139ed0SSantosh Shilimkar pr_err("keystone-navigator-dma driver not registered\n");
41788139ed0SSantosh Shilimkar return (void *)-EINVAL;
41888139ed0SSantosh Shilimkar }
41988139ed0SSantosh Shilimkar
42088139ed0SSantosh Shilimkar chan_num = of_channel_match_helper(dev->of_node, name, &instance);
42188139ed0SSantosh Shilimkar if (chan_num < 0) {
4227bcfe20dSColin King dev_err(kdev->dev, "No DMA instance with name %s\n", name);
42388139ed0SSantosh Shilimkar return (void *)-EINVAL;
42488139ed0SSantosh Shilimkar }
42588139ed0SSantosh Shilimkar
42688139ed0SSantosh Shilimkar dev_dbg(kdev->dev, "initializing %s channel %d from DMA %s\n",
42788139ed0SSantosh Shilimkar config->direction == DMA_MEM_TO_DEV ? "transmit" :
42888139ed0SSantosh Shilimkar config->direction == DMA_DEV_TO_MEM ? "receive" :
42988139ed0SSantosh Shilimkar "unknown", chan_num, instance);
43088139ed0SSantosh Shilimkar
43188139ed0SSantosh Shilimkar if (config->direction != DMA_MEM_TO_DEV &&
43288139ed0SSantosh Shilimkar config->direction != DMA_DEV_TO_MEM) {
43388139ed0SSantosh Shilimkar dev_err(kdev->dev, "bad direction\n");
43488139ed0SSantosh Shilimkar return (void *)-EINVAL;
43588139ed0SSantosh Shilimkar }
43688139ed0SSantosh Shilimkar
43788139ed0SSantosh Shilimkar /* Look for correct dma instance */
438d281a982SJakob Koschel list_for_each_entry(iter1, &kdev->list, list) {
439d281a982SJakob Koschel if (!strcmp(iter1->name, instance)) {
440d281a982SJakob Koschel dma = iter1;
44188139ed0SSantosh Shilimkar break;
44288139ed0SSantosh Shilimkar }
44388139ed0SSantosh Shilimkar }
444d281a982SJakob Koschel if (!dma) {
4457bcfe20dSColin King dev_err(kdev->dev, "No DMA instance with name %s\n", instance);
44688139ed0SSantosh Shilimkar return (void *)-EINVAL;
44788139ed0SSantosh Shilimkar }
44888139ed0SSantosh Shilimkar
44988139ed0SSantosh Shilimkar /* Look for correct dma channel from dma instance */
450d281a982SJakob Koschel list_for_each_entry(iter2, &dma->chan_list, list) {
45188139ed0SSantosh Shilimkar if (config->direction == DMA_MEM_TO_DEV) {
452d281a982SJakob Koschel if (iter2->channel == chan_num) {
453d281a982SJakob Koschel chan = iter2;
45488139ed0SSantosh Shilimkar break;
45588139ed0SSantosh Shilimkar }
45688139ed0SSantosh Shilimkar } else {
457d281a982SJakob Koschel if (iter2->flow == chan_num) {
458d281a982SJakob Koschel chan = iter2;
45988139ed0SSantosh Shilimkar break;
46088139ed0SSantosh Shilimkar }
46188139ed0SSantosh Shilimkar }
46288139ed0SSantosh Shilimkar }
463d281a982SJakob Koschel if (!chan) {
46488139ed0SSantosh Shilimkar dev_err(kdev->dev, "channel %d is not in DMA %s\n",
46588139ed0SSantosh Shilimkar chan_num, instance);
46688139ed0SSantosh Shilimkar return (void *)-EINVAL;
46788139ed0SSantosh Shilimkar }
46888139ed0SSantosh Shilimkar
46988139ed0SSantosh Shilimkar if (atomic_read(&chan->ref_count) >= 1) {
47088139ed0SSantosh Shilimkar if (!check_config(chan, config)) {
47188139ed0SSantosh Shilimkar dev_err(kdev->dev, "channel %d config miss-match\n",
47288139ed0SSantosh Shilimkar chan_num);
47388139ed0SSantosh Shilimkar return (void *)-EINVAL;
47488139ed0SSantosh Shilimkar }
47588139ed0SSantosh Shilimkar }
47688139ed0SSantosh Shilimkar
47788139ed0SSantosh Shilimkar if (atomic_inc_return(&chan->dma->ref_count) <= 1)
47888139ed0SSantosh Shilimkar knav_dma_hw_init(chan->dma);
47988139ed0SSantosh Shilimkar
48088139ed0SSantosh Shilimkar if (atomic_inc_return(&chan->ref_count) <= 1)
48188139ed0SSantosh Shilimkar chan_start(chan, config);
48288139ed0SSantosh Shilimkar
48388139ed0SSantosh Shilimkar dev_dbg(kdev->dev, "channel %d opened from DMA %s\n",
48488139ed0SSantosh Shilimkar chan_num, instance);
48588139ed0SSantosh Shilimkar
48688139ed0SSantosh Shilimkar return chan;
48788139ed0SSantosh Shilimkar }
48888139ed0SSantosh Shilimkar EXPORT_SYMBOL_GPL(knav_dma_open_channel);
48988139ed0SSantosh Shilimkar
49088139ed0SSantosh Shilimkar /**
49188139ed0SSantosh Shilimkar * knav_dma_close_channel() - Destroy a dma channel
49288139ed0SSantosh Shilimkar *
493ed93a9e2SLee Jones * @channel: dma channel handle
49488139ed0SSantosh Shilimkar *
49588139ed0SSantosh Shilimkar */
knav_dma_close_channel(void * channel)49688139ed0SSantosh Shilimkar void knav_dma_close_channel(void *channel)
49788139ed0SSantosh Shilimkar {
49888139ed0SSantosh Shilimkar struct knav_dma_chan *chan = channel;
49988139ed0SSantosh Shilimkar
50088139ed0SSantosh Shilimkar if (!kdev) {
50188139ed0SSantosh Shilimkar pr_err("keystone-navigator-dma driver not registered\n");
50288139ed0SSantosh Shilimkar return;
50388139ed0SSantosh Shilimkar }
50488139ed0SSantosh Shilimkar
50588139ed0SSantosh Shilimkar if (atomic_dec_return(&chan->ref_count) <= 0)
50688139ed0SSantosh Shilimkar chan_stop(chan);
50788139ed0SSantosh Shilimkar
50888139ed0SSantosh Shilimkar if (atomic_dec_return(&chan->dma->ref_count) <= 0)
50988139ed0SSantosh Shilimkar knav_dma_hw_destroy(chan->dma);
51088139ed0SSantosh Shilimkar
51188139ed0SSantosh Shilimkar dev_dbg(kdev->dev, "channel %d or flow %d closed from DMA %s\n",
51288139ed0SSantosh Shilimkar chan->channel, chan->flow, chan->dma->name);
51388139ed0SSantosh Shilimkar }
51488139ed0SSantosh Shilimkar EXPORT_SYMBOL_GPL(knav_dma_close_channel);
51588139ed0SSantosh Shilimkar
pktdma_get_regs(struct knav_dma_device * dma,struct device_node * node,unsigned index,resource_size_t * _size)51688139ed0SSantosh Shilimkar static void __iomem *pktdma_get_regs(struct knav_dma_device *dma,
51788139ed0SSantosh Shilimkar struct device_node *node,
51888139ed0SSantosh Shilimkar unsigned index, resource_size_t *_size)
51988139ed0SSantosh Shilimkar {
52088139ed0SSantosh Shilimkar struct device *dev = kdev->dev;
52188139ed0SSantosh Shilimkar struct resource res;
52288139ed0SSantosh Shilimkar void __iomem *regs;
52388139ed0SSantosh Shilimkar int ret;
52488139ed0SSantosh Shilimkar
52588139ed0SSantosh Shilimkar ret = of_address_to_resource(node, index, &res);
52688139ed0SSantosh Shilimkar if (ret) {
527dc37a252SRob Herring dev_err(dev, "Can't translate of node(%pOFn) address for index(%d)\n",
528dc37a252SRob Herring node, index);
52988139ed0SSantosh Shilimkar return ERR_PTR(ret);
53088139ed0SSantosh Shilimkar }
53188139ed0SSantosh Shilimkar
53288139ed0SSantosh Shilimkar regs = devm_ioremap_resource(kdev->dev, &res);
53388139ed0SSantosh Shilimkar if (IS_ERR(regs))
534dc37a252SRob Herring dev_err(dev, "Failed to map register base for index(%d) node(%pOFn)\n",
535dc37a252SRob Herring index, node);
53688139ed0SSantosh Shilimkar if (_size)
53788139ed0SSantosh Shilimkar *_size = resource_size(&res);
53888139ed0SSantosh Shilimkar
53988139ed0SSantosh Shilimkar return regs;
54088139ed0SSantosh Shilimkar }
54188139ed0SSantosh Shilimkar
pktdma_init_rx_chan(struct knav_dma_chan * chan,u32 flow)54288139ed0SSantosh Shilimkar static int pktdma_init_rx_chan(struct knav_dma_chan *chan, u32 flow)
54388139ed0SSantosh Shilimkar {
54488139ed0SSantosh Shilimkar struct knav_dma_device *dma = chan->dma;
54588139ed0SSantosh Shilimkar
54688139ed0SSantosh Shilimkar chan->flow = flow;
54788139ed0SSantosh Shilimkar chan->reg_rx_flow = dma->reg_rx_flow + flow;
54888139ed0SSantosh Shilimkar chan->channel = DMA_INVALID_ID;
54988139ed0SSantosh Shilimkar dev_dbg(kdev->dev, "rx flow(%d) (%p)\n", chan->flow, chan->reg_rx_flow);
55088139ed0SSantosh Shilimkar
55188139ed0SSantosh Shilimkar return 0;
55288139ed0SSantosh Shilimkar }
55388139ed0SSantosh Shilimkar
pktdma_init_tx_chan(struct knav_dma_chan * chan,u32 channel)55488139ed0SSantosh Shilimkar static int pktdma_init_tx_chan(struct knav_dma_chan *chan, u32 channel)
55588139ed0SSantosh Shilimkar {
55688139ed0SSantosh Shilimkar struct knav_dma_device *dma = chan->dma;
55788139ed0SSantosh Shilimkar
55888139ed0SSantosh Shilimkar chan->channel = channel;
55988139ed0SSantosh Shilimkar chan->reg_chan = dma->reg_tx_chan + channel;
56088139ed0SSantosh Shilimkar chan->reg_tx_sched = dma->reg_tx_sched + channel;
56188139ed0SSantosh Shilimkar chan->flow = DMA_INVALID_ID;
56288139ed0SSantosh Shilimkar dev_dbg(kdev->dev, "tx channel(%d) (%p)\n", chan->channel, chan->reg_chan);
56388139ed0SSantosh Shilimkar
56488139ed0SSantosh Shilimkar return 0;
56588139ed0SSantosh Shilimkar }
56688139ed0SSantosh Shilimkar
pktdma_init_chan(struct knav_dma_device * dma,enum dma_transfer_direction dir,unsigned chan_num)56788139ed0SSantosh Shilimkar static int pktdma_init_chan(struct knav_dma_device *dma,
56888139ed0SSantosh Shilimkar enum dma_transfer_direction dir,
56988139ed0SSantosh Shilimkar unsigned chan_num)
57088139ed0SSantosh Shilimkar {
57188139ed0SSantosh Shilimkar struct device *dev = kdev->dev;
57288139ed0SSantosh Shilimkar struct knav_dma_chan *chan;
57388139ed0SSantosh Shilimkar int ret = -EINVAL;
57488139ed0SSantosh Shilimkar
57588139ed0SSantosh Shilimkar chan = devm_kzalloc(dev, sizeof(*chan), GFP_KERNEL);
57688139ed0SSantosh Shilimkar if (!chan)
57788139ed0SSantosh Shilimkar return -ENOMEM;
57888139ed0SSantosh Shilimkar
57988139ed0SSantosh Shilimkar INIT_LIST_HEAD(&chan->list);
58088139ed0SSantosh Shilimkar chan->dma = dma;
5812b13ef1fSNathan Chancellor chan->direction = DMA_TRANS_NONE;
58288139ed0SSantosh Shilimkar atomic_set(&chan->ref_count, 0);
58388139ed0SSantosh Shilimkar spin_lock_init(&chan->lock);
58488139ed0SSantosh Shilimkar
58588139ed0SSantosh Shilimkar if (dir == DMA_MEM_TO_DEV) {
58688139ed0SSantosh Shilimkar chan->direction = dir;
58788139ed0SSantosh Shilimkar ret = pktdma_init_tx_chan(chan, chan_num);
58888139ed0SSantosh Shilimkar } else if (dir == DMA_DEV_TO_MEM) {
58988139ed0SSantosh Shilimkar chan->direction = dir;
59088139ed0SSantosh Shilimkar ret = pktdma_init_rx_chan(chan, chan_num);
59188139ed0SSantosh Shilimkar } else {
59288139ed0SSantosh Shilimkar dev_err(dev, "channel(%d) direction unknown\n", chan_num);
59388139ed0SSantosh Shilimkar }
59488139ed0SSantosh Shilimkar
59588139ed0SSantosh Shilimkar list_add_tail(&chan->list, &dma->chan_list);
59688139ed0SSantosh Shilimkar
59788139ed0SSantosh Shilimkar return ret;
59888139ed0SSantosh Shilimkar }
59988139ed0SSantosh Shilimkar
dma_init(struct device_node * cloud,struct device_node * dma_node)60088139ed0SSantosh Shilimkar static int dma_init(struct device_node *cloud, struct device_node *dma_node)
60188139ed0SSantosh Shilimkar {
60288139ed0SSantosh Shilimkar unsigned max_tx_chan, max_rx_chan, max_rx_flow, max_tx_sched;
60388139ed0SSantosh Shilimkar struct device_node *node = dma_node;
60488139ed0SSantosh Shilimkar struct knav_dma_device *dma;
60588139ed0SSantosh Shilimkar int ret, len, num_chan = 0;
60688139ed0SSantosh Shilimkar resource_size_t size;
60788139ed0SSantosh Shilimkar u32 timeout;
60888139ed0SSantosh Shilimkar u32 i;
60988139ed0SSantosh Shilimkar
61088139ed0SSantosh Shilimkar dma = devm_kzalloc(kdev->dev, sizeof(*dma), GFP_KERNEL);
61188139ed0SSantosh Shilimkar if (!dma) {
61288139ed0SSantosh Shilimkar dev_err(kdev->dev, "could not allocate driver mem\n");
61388139ed0SSantosh Shilimkar return -ENOMEM;
61488139ed0SSantosh Shilimkar }
61588139ed0SSantosh Shilimkar INIT_LIST_HEAD(&dma->list);
61688139ed0SSantosh Shilimkar INIT_LIST_HEAD(&dma->chan_list);
61788139ed0SSantosh Shilimkar
61888139ed0SSantosh Shilimkar if (!of_find_property(cloud, "ti,navigator-cloud-address", &len)) {
61988139ed0SSantosh Shilimkar dev_err(kdev->dev, "unspecified navigator cloud addresses\n");
62088139ed0SSantosh Shilimkar return -ENODEV;
62188139ed0SSantosh Shilimkar }
62288139ed0SSantosh Shilimkar
62388139ed0SSantosh Shilimkar dma->logical_queue_managers = len / sizeof(u32);
62488139ed0SSantosh Shilimkar if (dma->logical_queue_managers > DMA_MAX_QMS) {
62588139ed0SSantosh Shilimkar dev_warn(kdev->dev, "too many queue mgrs(>%d) rest ignored\n",
62688139ed0SSantosh Shilimkar dma->logical_queue_managers);
62788139ed0SSantosh Shilimkar dma->logical_queue_managers = DMA_MAX_QMS;
62888139ed0SSantosh Shilimkar }
62988139ed0SSantosh Shilimkar
63088139ed0SSantosh Shilimkar ret = of_property_read_u32_array(cloud, "ti,navigator-cloud-address",
63188139ed0SSantosh Shilimkar dma->qm_base_address,
63288139ed0SSantosh Shilimkar dma->logical_queue_managers);
63388139ed0SSantosh Shilimkar if (ret) {
63488139ed0SSantosh Shilimkar dev_err(kdev->dev, "invalid navigator cloud addresses\n");
63588139ed0SSantosh Shilimkar return -ENODEV;
63688139ed0SSantosh Shilimkar }
63788139ed0SSantosh Shilimkar
63888139ed0SSantosh Shilimkar dma->reg_global = pktdma_get_regs(dma, node, 0, &size);
6391bb0b8b1SMiaoqian Lin if (IS_ERR(dma->reg_global))
6401bb0b8b1SMiaoqian Lin return PTR_ERR(dma->reg_global);
64188139ed0SSantosh Shilimkar if (size < sizeof(struct reg_global)) {
64288139ed0SSantosh Shilimkar dev_err(kdev->dev, "bad size %pa for global regs\n", &size);
64388139ed0SSantosh Shilimkar return -ENODEV;
64488139ed0SSantosh Shilimkar }
64588139ed0SSantosh Shilimkar
64688139ed0SSantosh Shilimkar dma->reg_tx_chan = pktdma_get_regs(dma, node, 1, &size);
6471bb0b8b1SMiaoqian Lin if (IS_ERR(dma->reg_tx_chan))
6481bb0b8b1SMiaoqian Lin return PTR_ERR(dma->reg_tx_chan);
64988139ed0SSantosh Shilimkar
65088139ed0SSantosh Shilimkar max_tx_chan = size / sizeof(struct reg_chan);
65188139ed0SSantosh Shilimkar dma->reg_rx_chan = pktdma_get_regs(dma, node, 2, &size);
6521bb0b8b1SMiaoqian Lin if (IS_ERR(dma->reg_rx_chan))
6531bb0b8b1SMiaoqian Lin return PTR_ERR(dma->reg_rx_chan);
65488139ed0SSantosh Shilimkar
65588139ed0SSantosh Shilimkar max_rx_chan = size / sizeof(struct reg_chan);
65688139ed0SSantosh Shilimkar dma->reg_tx_sched = pktdma_get_regs(dma, node, 3, &size);
6571bb0b8b1SMiaoqian Lin if (IS_ERR(dma->reg_tx_sched))
6581bb0b8b1SMiaoqian Lin return PTR_ERR(dma->reg_tx_sched);
65988139ed0SSantosh Shilimkar
66088139ed0SSantosh Shilimkar max_tx_sched = size / sizeof(struct reg_tx_sched);
66188139ed0SSantosh Shilimkar dma->reg_rx_flow = pktdma_get_regs(dma, node, 4, &size);
6621bb0b8b1SMiaoqian Lin if (IS_ERR(dma->reg_rx_flow))
6631bb0b8b1SMiaoqian Lin return PTR_ERR(dma->reg_rx_flow);
66488139ed0SSantosh Shilimkar
66588139ed0SSantosh Shilimkar max_rx_flow = size / sizeof(struct reg_rx_flow);
66688139ed0SSantosh Shilimkar dma->rx_priority = DMA_PRIO_DEFAULT;
66788139ed0SSantosh Shilimkar dma->tx_priority = DMA_PRIO_DEFAULT;
66888139ed0SSantosh Shilimkar
669*82e46bf7SRob Herring dma->enable_all = of_property_read_bool(node, "ti,enable-all");
670*82e46bf7SRob Herring dma->loopback = of_property_read_bool(node, "ti,loop-back");
67188139ed0SSantosh Shilimkar
67288139ed0SSantosh Shilimkar ret = of_property_read_u32(node, "ti,rx-retry-timeout", &timeout);
67388139ed0SSantosh Shilimkar if (ret < 0) {
67488139ed0SSantosh Shilimkar dev_dbg(kdev->dev, "unspecified rx timeout using value %d\n",
67588139ed0SSantosh Shilimkar DMA_RX_TIMEOUT_DEFAULT);
67688139ed0SSantosh Shilimkar timeout = DMA_RX_TIMEOUT_DEFAULT;
67788139ed0SSantosh Shilimkar }
67888139ed0SSantosh Shilimkar
67988139ed0SSantosh Shilimkar dma->rx_timeout = timeout;
68088139ed0SSantosh Shilimkar dma->max_rx_chan = max_rx_chan;
68188139ed0SSantosh Shilimkar dma->max_rx_flow = max_rx_flow;
68288139ed0SSantosh Shilimkar dma->max_tx_chan = min(max_tx_chan, max_tx_sched);
68388139ed0SSantosh Shilimkar atomic_set(&dma->ref_count, 0);
68488139ed0SSantosh Shilimkar strcpy(dma->name, node->name);
68588139ed0SSantosh Shilimkar spin_lock_init(&dma->lock);
68688139ed0SSantosh Shilimkar
68788139ed0SSantosh Shilimkar for (i = 0; i < dma->max_tx_chan; i++) {
68888139ed0SSantosh Shilimkar if (pktdma_init_chan(dma, DMA_MEM_TO_DEV, i) >= 0)
68988139ed0SSantosh Shilimkar num_chan++;
69088139ed0SSantosh Shilimkar }
69188139ed0SSantosh Shilimkar
69288139ed0SSantosh Shilimkar for (i = 0; i < dma->max_rx_flow; i++) {
69388139ed0SSantosh Shilimkar if (pktdma_init_chan(dma, DMA_DEV_TO_MEM, i) >= 0)
69488139ed0SSantosh Shilimkar num_chan++;
69588139ed0SSantosh Shilimkar }
69688139ed0SSantosh Shilimkar
69788139ed0SSantosh Shilimkar list_add_tail(&dma->list, &kdev->list);
69888139ed0SSantosh Shilimkar
69988139ed0SSantosh Shilimkar /*
70088139ed0SSantosh Shilimkar * For DSP software usecases or userpace transport software, setup all
70188139ed0SSantosh Shilimkar * the DMA hardware resources.
70288139ed0SSantosh Shilimkar */
70388139ed0SSantosh Shilimkar if (dma->enable_all) {
70488139ed0SSantosh Shilimkar atomic_inc(&dma->ref_count);
70588139ed0SSantosh Shilimkar knav_dma_hw_init(dma);
70688139ed0SSantosh Shilimkar dma_hw_enable_all(dma);
70788139ed0SSantosh Shilimkar }
70888139ed0SSantosh Shilimkar
70988139ed0SSantosh Shilimkar dev_info(kdev->dev, "DMA %s registered %d logical channels, flows %d, tx chans: %d, rx chans: %d%s\n",
71088139ed0SSantosh Shilimkar dma->name, num_chan, dma->max_rx_flow,
71188139ed0SSantosh Shilimkar dma->max_tx_chan, dma->max_rx_chan,
71288139ed0SSantosh Shilimkar dma->loopback ? ", loopback" : "");
71388139ed0SSantosh Shilimkar
71488139ed0SSantosh Shilimkar return 0;
71588139ed0SSantosh Shilimkar }
71688139ed0SSantosh Shilimkar
knav_dma_probe(struct platform_device * pdev)71788139ed0SSantosh Shilimkar static int knav_dma_probe(struct platform_device *pdev)
71888139ed0SSantosh Shilimkar {
71988139ed0SSantosh Shilimkar struct device *dev = &pdev->dev;
72088139ed0SSantosh Shilimkar struct device_node *node = pdev->dev.of_node;
72188139ed0SSantosh Shilimkar struct device_node *child;
72288139ed0SSantosh Shilimkar int ret = 0;
72388139ed0SSantosh Shilimkar
72488139ed0SSantosh Shilimkar if (!node) {
72588139ed0SSantosh Shilimkar dev_err(&pdev->dev, "could not find device info\n");
72688139ed0SSantosh Shilimkar return -EINVAL;
72788139ed0SSantosh Shilimkar }
72888139ed0SSantosh Shilimkar
72988139ed0SSantosh Shilimkar kdev = devm_kzalloc(dev,
73088139ed0SSantosh Shilimkar sizeof(struct knav_dma_pool_device), GFP_KERNEL);
73188139ed0SSantosh Shilimkar if (!kdev) {
73288139ed0SSantosh Shilimkar dev_err(dev, "could not allocate driver mem\n");
73388139ed0SSantosh Shilimkar return -ENOMEM;
73488139ed0SSantosh Shilimkar }
73588139ed0SSantosh Shilimkar
73688139ed0SSantosh Shilimkar kdev->dev = dev;
73788139ed0SSantosh Shilimkar INIT_LIST_HEAD(&kdev->list);
73888139ed0SSantosh Shilimkar
73988139ed0SSantosh Shilimkar pm_runtime_enable(kdev->dev);
740d3e3116fSMinghao Chi ret = pm_runtime_resume_and_get(kdev->dev);
74188139ed0SSantosh Shilimkar if (ret < 0) {
74288139ed0SSantosh Shilimkar dev_err(kdev->dev, "unable to enable pktdma, err %d\n", ret);
743b4fa7335SZhang Qilong goto err_pm_disable;
74488139ed0SSantosh Shilimkar }
74588139ed0SSantosh Shilimkar
74688139ed0SSantosh Shilimkar /* Initialise all packet dmas */
74788139ed0SSantosh Shilimkar for_each_child_of_node(node, child) {
74888139ed0SSantosh Shilimkar ret = dma_init(node, child);
74988139ed0SSantosh Shilimkar if (ret) {
750a88f66d4SVasyl Gomonovych of_node_put(child);
75188139ed0SSantosh Shilimkar dev_err(&pdev->dev, "init failed with %d\n", ret);
75288139ed0SSantosh Shilimkar break;
75388139ed0SSantosh Shilimkar }
75488139ed0SSantosh Shilimkar }
75588139ed0SSantosh Shilimkar
75688139ed0SSantosh Shilimkar if (list_empty(&kdev->list)) {
75788139ed0SSantosh Shilimkar dev_err(dev, "no valid dma instance\n");
758b4fa7335SZhang Qilong ret = -ENODEV;
759b4fa7335SZhang Qilong goto err_put_sync;
76088139ed0SSantosh Shilimkar }
76188139ed0SSantosh Shilimkar
76288139ed0SSantosh Shilimkar debugfs_create_file("knav_dma", S_IFREG | S_IRUGO, NULL, NULL,
76374e0e43aSQinglang Miao &knav_dma_debug_fops);
76488139ed0SSantosh Shilimkar
765a2dd6877SMurali Karicheri device_ready = true;
76688139ed0SSantosh Shilimkar return ret;
767b4fa7335SZhang Qilong
768b4fa7335SZhang Qilong err_put_sync:
769b4fa7335SZhang Qilong pm_runtime_put_sync(kdev->dev);
770b4fa7335SZhang Qilong err_pm_disable:
771b4fa7335SZhang Qilong pm_runtime_disable(kdev->dev);
772b4fa7335SZhang Qilong
773b4fa7335SZhang Qilong return ret;
77488139ed0SSantosh Shilimkar }
77588139ed0SSantosh Shilimkar
knav_dma_remove(struct platform_device * pdev)77688139ed0SSantosh Shilimkar static int knav_dma_remove(struct platform_device *pdev)
77788139ed0SSantosh Shilimkar {
77888139ed0SSantosh Shilimkar struct knav_dma_device *dma;
77988139ed0SSantosh Shilimkar
78088139ed0SSantosh Shilimkar list_for_each_entry(dma, &kdev->list, list) {
78188139ed0SSantosh Shilimkar if (atomic_dec_return(&dma->ref_count) == 0)
78288139ed0SSantosh Shilimkar knav_dma_hw_destroy(dma);
78388139ed0SSantosh Shilimkar }
78488139ed0SSantosh Shilimkar
78588139ed0SSantosh Shilimkar pm_runtime_put_sync(&pdev->dev);
78688139ed0SSantosh Shilimkar pm_runtime_disable(&pdev->dev);
78788139ed0SSantosh Shilimkar
78888139ed0SSantosh Shilimkar return 0;
78988139ed0SSantosh Shilimkar }
79088139ed0SSantosh Shilimkar
79188139ed0SSantosh Shilimkar static struct of_device_id of_match[] = {
79288139ed0SSantosh Shilimkar { .compatible = "ti,keystone-navigator-dma", },
79388139ed0SSantosh Shilimkar {},
79488139ed0SSantosh Shilimkar };
79588139ed0SSantosh Shilimkar
79688139ed0SSantosh Shilimkar MODULE_DEVICE_TABLE(of, of_match);
79788139ed0SSantosh Shilimkar
79888139ed0SSantosh Shilimkar static struct platform_driver knav_dma_driver = {
79988139ed0SSantosh Shilimkar .probe = knav_dma_probe,
80088139ed0SSantosh Shilimkar .remove = knav_dma_remove,
80188139ed0SSantosh Shilimkar .driver = {
80288139ed0SSantosh Shilimkar .name = "keystone-navigator-dma",
80388139ed0SSantosh Shilimkar .of_match_table = of_match,
80488139ed0SSantosh Shilimkar },
80588139ed0SSantosh Shilimkar };
80688139ed0SSantosh Shilimkar module_platform_driver(knav_dma_driver);
80788139ed0SSantosh Shilimkar
80888139ed0SSantosh Shilimkar MODULE_LICENSE("GPL v2");
80988139ed0SSantosh Shilimkar MODULE_DESCRIPTION("TI Keystone Navigator Packet DMA driver");
81088139ed0SSantosh Shilimkar MODULE_AUTHOR("Sandeep Nair <sandeep_n@ti.com>");
81188139ed0SSantosh Shilimkar MODULE_AUTHOR("Santosh Shilimkar <santosh.shilimkar@ti.com>");
812