1a869b7b3SNishanth Menon# 64-bit ARM SoCs from TI 2a869b7b3SNishanth Menonif ARM64 3a869b7b3SNishanth Menon 4a869b7b3SNishanth Menonif ARCH_K3 5a869b7b3SNishanth Menon 6a869b7b3SNishanth Menonconfig ARCH_K3_AM6_SOC 7a869b7b3SNishanth Menon bool "K3 AM6 SoC" 8a869b7b3SNishanth Menon help 9a869b7b3SNishanth Menon Enable support for TI's AM6 SoC Family support 10a869b7b3SNishanth Menon 11a869b7b3SNishanth Menonendif 12a869b7b3SNishanth Menon 13a869b7b3SNishanth Menonendif 14a869b7b3SNishanth Menon 1541f93af9SSandeep Nair# 1641f93af9SSandeep Nair# TI SOC drivers 1741f93af9SSandeep Nair# 1841f93af9SSandeep Nairmenuconfig SOC_TI 1941f93af9SSandeep Nair bool "TI SOC drivers support" 2041f93af9SSandeep Nair 2141f93af9SSandeep Nairif SOC_TI 2241f93af9SSandeep Nair 2341f93af9SSandeep Nairconfig KEYSTONE_NAVIGATOR_QMSS 2441f93af9SSandeep Nair tristate "Keystone Queue Manager Sub System" 2541f93af9SSandeep Nair depends on ARCH_KEYSTONE 2641f93af9SSandeep Nair help 2741f93af9SSandeep Nair Say y here to support the Keystone multicore Navigator Queue 2841f93af9SSandeep Nair Manager support. The Queue Manager is a hardware module that 2941f93af9SSandeep Nair is responsible for accelerating management of the packet queues. 3041f93af9SSandeep Nair Packets are queued/de-queued by writing/reading descriptor address 3141f93af9SSandeep Nair to a particular memory mapped location in the Queue Manager module. 3241f93af9SSandeep Nair 3341f93af9SSandeep Nair If unsure, say N. 3441f93af9SSandeep Nair 3588139ed0SSantosh Shilimkarconfig KEYSTONE_NAVIGATOR_DMA 3688139ed0SSantosh Shilimkar tristate "TI Keystone Navigator Packet DMA support" 3788139ed0SSantosh Shilimkar depends on ARCH_KEYSTONE 3888139ed0SSantosh Shilimkar help 3988139ed0SSantosh Shilimkar Say y tp enable support for the Keystone Navigator Packet DMA on 4088139ed0SSantosh Shilimkar on Keystone family of devices. It sets up the dma channels for the 4188139ed0SSantosh Shilimkar Queue Manager Sub System. 4288139ed0SSantosh Shilimkar 4388139ed0SSantosh Shilimkar If unsure, say N. 4488139ed0SSantosh Shilimkar 45afe761f8SDave Gerlachconfig AMX3_PM 46afe761f8SDave Gerlach tristate "AMx3 Power Management" 47afe761f8SDave Gerlach depends on SOC_AM33XX || SOC_AM43XX 485a99ae00SKeerthy depends on WKUP_M3_IPC && TI_EMIF_SRAM && SRAM && RTC_DRV_OMAP 49afe761f8SDave Gerlach help 50afe761f8SDave Gerlach Enable power management on AM335x and AM437x. Required for suspend to mem 51afe761f8SDave Gerlach and standby states on both AM335x and AM437x platforms and for deeper cpuidle 525a99ae00SKeerthy c-states on AM335x. Also required for rtc and ddr in self-refresh low 535a99ae00SKeerthy power mode on AM437x platforms. 54afe761f8SDave Gerlach 55cdd5de50SDave Gerlachconfig WKUP_M3_IPC 56cdd5de50SDave Gerlach tristate "TI AMx3 Wkup-M3 IPC Driver" 57cdd5de50SDave Gerlach depends on WKUP_M3_RPROC 58cdd5de50SDave Gerlach depends on OMAP2PLUS_MBOX 59cdd5de50SDave Gerlach help 60cdd5de50SDave Gerlach TI AM33XX and AM43XX have a Cortex M3, the Wakeup M3, to handle 61cdd5de50SDave Gerlach low power transitions. This IPC driver provides the necessary API 62cdd5de50SDave Gerlach to communicate and use the Wakeup M3 for PM features like suspend 63cdd5de50SDave Gerlach resume and boots it using wkup_m3_rproc driver. 64cdd5de50SDave Gerlach 6552835d59SDave Gerlachconfig TI_SCI_PM_DOMAINS 6652835d59SDave Gerlach tristate "TI SCI PM Domains Driver" 6752835d59SDave Gerlach depends on TI_SCI_PROTOCOL 6852835d59SDave Gerlach depends on PM_GENERIC_DOMAINS 6952835d59SDave Gerlach help 7052835d59SDave Gerlach Generic power domain implementation for TI device implementing 7152835d59SDave Gerlach the TI SCI protocol. 7252835d59SDave Gerlach 7352835d59SDave Gerlach To compile this as a module, choose M here. The module will be 7452835d59SDave Gerlach called ti_sci_pm_domains. Note this is needed early in boot before 7552835d59SDave Gerlach rootfs may be available. 7652835d59SDave Gerlach 7741f93af9SSandeep Nairendif # SOC_TI 78