1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/clk.h> 22 #include <linux/clk/tegra.h> 23 #include <linux/debugfs.h> 24 #include <linux/delay.h> 25 #include <linux/err.h> 26 #include <linux/export.h> 27 #include <linux/init.h> 28 #include <linux/io.h> 29 #include <linux/of.h> 30 #include <linux/of_address.h> 31 #include <linux/platform_device.h> 32 #include <linux/reboot.h> 33 #include <linux/reset.h> 34 #include <linux/seq_file.h> 35 #include <linux/spinlock.h> 36 37 #include <soc/tegra/common.h> 38 #include <soc/tegra/fuse.h> 39 #include <soc/tegra/pmc.h> 40 41 #define PMC_CNTRL 0x0 42 #define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ 43 #define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */ 44 #define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ 45 #define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ 46 #define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ 47 #define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */ 48 49 #define DPD_SAMPLE 0x020 50 #define DPD_SAMPLE_ENABLE (1 << 0) 51 #define DPD_SAMPLE_DISABLE (0 << 0) 52 53 #define PWRGATE_TOGGLE 0x30 54 #define PWRGATE_TOGGLE_START (1 << 8) 55 56 #define REMOVE_CLAMPING 0x34 57 58 #define PWRGATE_STATUS 0x38 59 60 #define PMC_SCRATCH0 0x50 61 #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) 62 #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) 63 #define PMC_SCRATCH0_MODE_RCM (1 << 1) 64 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 65 PMC_SCRATCH0_MODE_BOOTLOADER | \ 66 PMC_SCRATCH0_MODE_RCM) 67 68 #define PMC_CPUPWRGOOD_TIMER 0xc8 69 #define PMC_CPUPWROFF_TIMER 0xcc 70 71 #define PMC_SCRATCH41 0x140 72 73 #define PMC_SENSOR_CTRL 0x1b0 74 #define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2) 75 #define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1) 76 77 #define IO_DPD_REQ 0x1b8 78 #define IO_DPD_REQ_CODE_IDLE (0 << 30) 79 #define IO_DPD_REQ_CODE_OFF (1 << 30) 80 #define IO_DPD_REQ_CODE_ON (2 << 30) 81 #define IO_DPD_REQ_CODE_MASK (3 << 30) 82 83 #define IO_DPD_STATUS 0x1bc 84 #define IO_DPD2_REQ 0x1c0 85 #define IO_DPD2_STATUS 0x1c4 86 #define SEL_DPD_TIM 0x1c8 87 88 #define PMC_SCRATCH54 0x258 89 #define PMC_SCRATCH54_DATA_SHIFT 8 90 #define PMC_SCRATCH54_ADDR_SHIFT 0 91 92 #define PMC_SCRATCH55 0x25c 93 #define PMC_SCRATCH55_RESET_TEGRA (1 << 31) 94 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 95 #define PMC_SCRATCH55_PINMUX_SHIFT 24 96 #define PMC_SCRATCH55_16BITOP (1 << 15) 97 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 98 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 99 100 #define GPU_RG_CNTRL 0x2d4 101 102 struct tegra_pmc_soc { 103 unsigned int num_powergates; 104 const char *const *powergates; 105 unsigned int num_cpu_powergates; 106 const u8 *cpu_powergates; 107 108 bool has_tsense_reset; 109 bool has_gpu_clamps; 110 }; 111 112 /** 113 * struct tegra_pmc - NVIDIA Tegra PMC 114 * @base: pointer to I/O remapped register region 115 * @clk: pointer to pclk clock 116 * @rate: currently configured rate of pclk 117 * @suspend_mode: lowest suspend mode available 118 * @cpu_good_time: CPU power good time (in microseconds) 119 * @cpu_off_time: CPU power off time (in microsecends) 120 * @core_osc_time: core power good OSC time (in microseconds) 121 * @core_pmu_time: core power good PMU time (in microseconds) 122 * @core_off_time: core power off time (in microseconds) 123 * @corereq_high: core power request is active-high 124 * @sysclkreq_high: system clock request is active-high 125 * @combined_req: combined power request for CPU & core 126 * @cpu_pwr_good_en: CPU power good signal is enabled 127 * @lp0_vec_phys: physical base address of the LP0 warm boot code 128 * @lp0_vec_size: size of the LP0 warm boot code 129 * @powergates_lock: mutex for power gate register access 130 */ 131 struct tegra_pmc { 132 struct device *dev; 133 void __iomem *base; 134 struct clk *clk; 135 136 const struct tegra_pmc_soc *soc; 137 138 unsigned long rate; 139 140 enum tegra_suspend_mode suspend_mode; 141 u32 cpu_good_time; 142 u32 cpu_off_time; 143 u32 core_osc_time; 144 u32 core_pmu_time; 145 u32 core_off_time; 146 bool corereq_high; 147 bool sysclkreq_high; 148 bool combined_req; 149 bool cpu_pwr_good_en; 150 u32 lp0_vec_phys; 151 u32 lp0_vec_size; 152 153 struct mutex powergates_lock; 154 }; 155 156 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 157 .base = NULL, 158 .suspend_mode = TEGRA_SUSPEND_NONE, 159 }; 160 161 static u32 tegra_pmc_readl(unsigned long offset) 162 { 163 return readl(pmc->base + offset); 164 } 165 166 static void tegra_pmc_writel(u32 value, unsigned long offset) 167 { 168 writel(value, pmc->base + offset); 169 } 170 171 /** 172 * tegra_powergate_set() - set the state of a partition 173 * @id: partition ID 174 * @new_state: new state of the partition 175 */ 176 static int tegra_powergate_set(int id, bool new_state) 177 { 178 bool status; 179 180 mutex_lock(&pmc->powergates_lock); 181 182 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id); 183 184 if (status == new_state) { 185 mutex_unlock(&pmc->powergates_lock); 186 return 0; 187 } 188 189 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 190 191 mutex_unlock(&pmc->powergates_lock); 192 193 return 0; 194 } 195 196 /** 197 * tegra_powergate_power_on() - power on partition 198 * @id: partition ID 199 */ 200 int tegra_powergate_power_on(int id) 201 { 202 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) 203 return -EINVAL; 204 205 return tegra_powergate_set(id, true); 206 } 207 208 /** 209 * tegra_powergate_power_off() - power off partition 210 * @id: partition ID 211 */ 212 int tegra_powergate_power_off(int id) 213 { 214 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) 215 return -EINVAL; 216 217 return tegra_powergate_set(id, false); 218 } 219 EXPORT_SYMBOL(tegra_powergate_power_off); 220 221 /** 222 * tegra_powergate_is_powered() - check if partition is powered 223 * @id: partition ID 224 */ 225 int tegra_powergate_is_powered(int id) 226 { 227 u32 status; 228 229 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) 230 return -EINVAL; 231 232 status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id); 233 return !!status; 234 } 235 236 /** 237 * tegra_powergate_remove_clamping() - remove power clamps for partition 238 * @id: partition ID 239 */ 240 int tegra_powergate_remove_clamping(int id) 241 { 242 u32 mask; 243 244 if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) 245 return -EINVAL; 246 247 /* 248 * On Tegra124 and later, the clamps for the GPU are controlled by a 249 * separate register (with different semantics). 250 */ 251 if (id == TEGRA_POWERGATE_3D) { 252 if (pmc->soc->has_gpu_clamps) { 253 tegra_pmc_writel(0, GPU_RG_CNTRL); 254 return 0; 255 } 256 } 257 258 /* 259 * Tegra 2 has a bug where PCIE and VDE clamping masks are 260 * swapped relatively to the partition ids 261 */ 262 if (id == TEGRA_POWERGATE_VDEC) 263 mask = (1 << TEGRA_POWERGATE_PCIE); 264 else if (id == TEGRA_POWERGATE_PCIE) 265 mask = (1 << TEGRA_POWERGATE_VDEC); 266 else 267 mask = (1 << id); 268 269 tegra_pmc_writel(mask, REMOVE_CLAMPING); 270 271 return 0; 272 } 273 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 274 275 /** 276 * tegra_powergate_sequence_power_up() - power up partition 277 * @id: partition ID 278 * @clk: clock for partition 279 * @rst: reset for partition 280 * 281 * Must be called with clk disabled, and returns with clk enabled. 282 */ 283 int tegra_powergate_sequence_power_up(int id, struct clk *clk, 284 struct reset_control *rst) 285 { 286 int ret; 287 288 reset_control_assert(rst); 289 290 ret = tegra_powergate_power_on(id); 291 if (ret) 292 goto err_power; 293 294 ret = clk_prepare_enable(clk); 295 if (ret) 296 goto err_clk; 297 298 usleep_range(10, 20); 299 300 ret = tegra_powergate_remove_clamping(id); 301 if (ret) 302 goto err_clamp; 303 304 usleep_range(10, 20); 305 reset_control_deassert(rst); 306 307 return 0; 308 309 err_clamp: 310 clk_disable_unprepare(clk); 311 err_clk: 312 tegra_powergate_power_off(id); 313 err_power: 314 return ret; 315 } 316 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 317 318 #ifdef CONFIG_SMP 319 /** 320 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 321 * @cpuid: CPU partition ID 322 * 323 * Returns the partition ID corresponding to the CPU partition ID or a 324 * negative error code on failure. 325 */ 326 static int tegra_get_cpu_powergate_id(int cpuid) 327 { 328 if (pmc->soc && cpuid > 0 && cpuid < pmc->soc->num_cpu_powergates) 329 return pmc->soc->cpu_powergates[cpuid]; 330 331 return -EINVAL; 332 } 333 334 /** 335 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 336 * @cpuid: CPU partition ID 337 */ 338 bool tegra_pmc_cpu_is_powered(int cpuid) 339 { 340 int id; 341 342 id = tegra_get_cpu_powergate_id(cpuid); 343 if (id < 0) 344 return false; 345 346 return tegra_powergate_is_powered(id); 347 } 348 349 /** 350 * tegra_pmc_cpu_power_on() - power on CPU partition 351 * @cpuid: CPU partition ID 352 */ 353 int tegra_pmc_cpu_power_on(int cpuid) 354 { 355 int id; 356 357 id = tegra_get_cpu_powergate_id(cpuid); 358 if (id < 0) 359 return id; 360 361 return tegra_powergate_set(id, true); 362 } 363 364 /** 365 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 366 * @cpuid: CPU partition ID 367 */ 368 int tegra_pmc_cpu_remove_clamping(int cpuid) 369 { 370 int id; 371 372 id = tegra_get_cpu_powergate_id(cpuid); 373 if (id < 0) 374 return id; 375 376 return tegra_powergate_remove_clamping(id); 377 } 378 #endif /* CONFIG_SMP */ 379 380 static int tegra_pmc_restart_notify(struct notifier_block *this, 381 unsigned long action, void *data) 382 { 383 const char *cmd = data; 384 u32 value; 385 386 value = tegra_pmc_readl(PMC_SCRATCH0); 387 value &= ~PMC_SCRATCH0_MODE_MASK; 388 389 if (cmd) { 390 if (strcmp(cmd, "recovery") == 0) 391 value |= PMC_SCRATCH0_MODE_RECOVERY; 392 393 if (strcmp(cmd, "bootloader") == 0) 394 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 395 396 if (strcmp(cmd, "forced-recovery") == 0) 397 value |= PMC_SCRATCH0_MODE_RCM; 398 } 399 400 tegra_pmc_writel(value, PMC_SCRATCH0); 401 402 value = tegra_pmc_readl(0); 403 value |= 0x10; 404 tegra_pmc_writel(value, 0); 405 406 return NOTIFY_DONE; 407 } 408 409 static struct notifier_block tegra_pmc_restart_handler = { 410 .notifier_call = tegra_pmc_restart_notify, 411 .priority = 128, 412 }; 413 414 static int powergate_show(struct seq_file *s, void *data) 415 { 416 unsigned int i; 417 418 seq_printf(s, " powergate powered\n"); 419 seq_printf(s, "------------------\n"); 420 421 for (i = 0; i < pmc->soc->num_powergates; i++) { 422 if (!pmc->soc->powergates[i]) 423 continue; 424 425 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 426 tegra_powergate_is_powered(i) ? "yes" : "no"); 427 } 428 429 return 0; 430 } 431 432 static int powergate_open(struct inode *inode, struct file *file) 433 { 434 return single_open(file, powergate_show, inode->i_private); 435 } 436 437 static const struct file_operations powergate_fops = { 438 .open = powergate_open, 439 .read = seq_read, 440 .llseek = seq_lseek, 441 .release = single_release, 442 }; 443 444 static int tegra_powergate_debugfs_init(void) 445 { 446 struct dentry *d; 447 448 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 449 &powergate_fops); 450 if (!d) 451 return -ENOMEM; 452 453 return 0; 454 } 455 456 static int tegra_io_rail_prepare(int id, unsigned long *request, 457 unsigned long *status, unsigned int *bit) 458 { 459 unsigned long rate, value; 460 struct clk *clk; 461 462 *bit = id % 32; 463 464 /* 465 * There are two sets of 30 bits to select IO rails, but bits 30 and 466 * 31 are control bits rather than IO rail selection bits. 467 */ 468 if (id > 63 || *bit == 30 || *bit == 31) 469 return -EINVAL; 470 471 if (id < 32) { 472 *status = IO_DPD_STATUS; 473 *request = IO_DPD_REQ; 474 } else { 475 *status = IO_DPD2_STATUS; 476 *request = IO_DPD2_REQ; 477 } 478 479 clk = clk_get_sys(NULL, "pclk"); 480 if (IS_ERR(clk)) 481 return PTR_ERR(clk); 482 483 rate = clk_get_rate(clk); 484 clk_put(clk); 485 486 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 487 488 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 489 value = DIV_ROUND_UP(1000000000, rate); 490 value = DIV_ROUND_UP(200, value); 491 tegra_pmc_writel(value, SEL_DPD_TIM); 492 493 return 0; 494 } 495 496 static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, 497 unsigned long val, unsigned long timeout) 498 { 499 unsigned long value; 500 501 timeout = jiffies + msecs_to_jiffies(timeout); 502 503 while (time_after(timeout, jiffies)) { 504 value = tegra_pmc_readl(offset); 505 if ((value & mask) == val) 506 return 0; 507 508 usleep_range(250, 1000); 509 } 510 511 return -ETIMEDOUT; 512 } 513 514 static void tegra_io_rail_unprepare(void) 515 { 516 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 517 } 518 519 int tegra_io_rail_power_on(int id) 520 { 521 unsigned long request, status, value; 522 unsigned int bit, mask; 523 int err; 524 525 err = tegra_io_rail_prepare(id, &request, &status, &bit); 526 if (err < 0) 527 return err; 528 529 mask = 1 << bit; 530 531 value = tegra_pmc_readl(request); 532 value |= mask; 533 value &= ~IO_DPD_REQ_CODE_MASK; 534 value |= IO_DPD_REQ_CODE_OFF; 535 tegra_pmc_writel(value, request); 536 537 err = tegra_io_rail_poll(status, mask, 0, 250); 538 if (err < 0) 539 return err; 540 541 tegra_io_rail_unprepare(); 542 543 return 0; 544 } 545 EXPORT_SYMBOL(tegra_io_rail_power_on); 546 547 int tegra_io_rail_power_off(int id) 548 { 549 unsigned long request, status, value; 550 unsigned int bit, mask; 551 int err; 552 553 err = tegra_io_rail_prepare(id, &request, &status, &bit); 554 if (err < 0) 555 return err; 556 557 mask = 1 << bit; 558 559 value = tegra_pmc_readl(request); 560 value |= mask; 561 value &= ~IO_DPD_REQ_CODE_MASK; 562 value |= IO_DPD_REQ_CODE_ON; 563 tegra_pmc_writel(value, request); 564 565 err = tegra_io_rail_poll(status, mask, mask, 250); 566 if (err < 0) 567 return err; 568 569 tegra_io_rail_unprepare(); 570 571 return 0; 572 } 573 EXPORT_SYMBOL(tegra_io_rail_power_off); 574 575 #ifdef CONFIG_PM_SLEEP 576 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 577 { 578 return pmc->suspend_mode; 579 } 580 581 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 582 { 583 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 584 return; 585 586 pmc->suspend_mode = mode; 587 } 588 589 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 590 { 591 unsigned long long rate = 0; 592 u32 value; 593 594 switch (mode) { 595 case TEGRA_SUSPEND_LP1: 596 rate = 32768; 597 break; 598 599 case TEGRA_SUSPEND_LP2: 600 rate = clk_get_rate(pmc->clk); 601 break; 602 603 default: 604 break; 605 } 606 607 if (WARN_ON_ONCE(rate == 0)) 608 rate = 100000000; 609 610 if (rate != pmc->rate) { 611 u64 ticks; 612 613 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 614 do_div(ticks, USEC_PER_SEC); 615 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 616 617 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 618 do_div(ticks, USEC_PER_SEC); 619 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 620 621 wmb(); 622 623 pmc->rate = rate; 624 } 625 626 value = tegra_pmc_readl(PMC_CNTRL); 627 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 628 value |= PMC_CNTRL_CPU_PWRREQ_OE; 629 tegra_pmc_writel(value, PMC_CNTRL); 630 } 631 #endif 632 633 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 634 { 635 u32 value, values[2]; 636 637 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 638 } else { 639 switch (value) { 640 case 0: 641 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 642 break; 643 644 case 1: 645 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 646 break; 647 648 case 2: 649 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 650 break; 651 652 default: 653 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 654 break; 655 } 656 } 657 658 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 659 660 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 661 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 662 663 pmc->cpu_good_time = value; 664 665 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 666 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 667 668 pmc->cpu_off_time = value; 669 670 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 671 values, ARRAY_SIZE(values))) 672 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 673 674 pmc->core_osc_time = values[0]; 675 pmc->core_pmu_time = values[1]; 676 677 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 678 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 679 680 pmc->core_off_time = value; 681 682 pmc->corereq_high = of_property_read_bool(np, 683 "nvidia,core-power-req-active-high"); 684 685 pmc->sysclkreq_high = of_property_read_bool(np, 686 "nvidia,sys-clock-req-active-high"); 687 688 pmc->combined_req = of_property_read_bool(np, 689 "nvidia,combined-power-req"); 690 691 pmc->cpu_pwr_good_en = of_property_read_bool(np, 692 "nvidia,cpu-pwr-good-en"); 693 694 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 695 ARRAY_SIZE(values))) 696 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 697 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 698 699 pmc->lp0_vec_phys = values[0]; 700 pmc->lp0_vec_size = values[1]; 701 702 return 0; 703 } 704 705 static void tegra_pmc_init(struct tegra_pmc *pmc) 706 { 707 u32 value; 708 709 /* Always enable CPU power request */ 710 value = tegra_pmc_readl(PMC_CNTRL); 711 value |= PMC_CNTRL_CPU_PWRREQ_OE; 712 tegra_pmc_writel(value, PMC_CNTRL); 713 714 value = tegra_pmc_readl(PMC_CNTRL); 715 716 if (pmc->sysclkreq_high) 717 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 718 else 719 value |= PMC_CNTRL_SYSCLK_POLARITY; 720 721 /* configure the output polarity while the request is tristated */ 722 tegra_pmc_writel(value, PMC_CNTRL); 723 724 /* now enable the request */ 725 value = tegra_pmc_readl(PMC_CNTRL); 726 value |= PMC_CNTRL_SYSCLK_OE; 727 tegra_pmc_writel(value, PMC_CNTRL); 728 } 729 730 void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 731 { 732 static const char disabled[] = "emergency thermal reset disabled"; 733 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 734 struct device *dev = pmc->dev; 735 struct device_node *np; 736 u32 value, checksum; 737 738 if (!pmc->soc->has_tsense_reset) 739 goto out; 740 741 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); 742 if (!np) { 743 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 744 goto out; 745 } 746 747 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 748 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 749 goto out; 750 } 751 752 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 753 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 754 goto out; 755 } 756 757 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 758 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 759 goto out; 760 } 761 762 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 763 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 764 goto out; 765 } 766 767 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 768 pinmux = 0; 769 770 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 771 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 772 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 773 774 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 775 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 776 tegra_pmc_writel(value, PMC_SCRATCH54); 777 778 value = PMC_SCRATCH55_RESET_TEGRA; 779 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 780 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 781 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 782 783 /* 784 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 785 * contain the checksum and are currently zero, so they are not added. 786 */ 787 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 788 + ((value >> 24) & 0xff); 789 checksum &= 0xff; 790 checksum = 0x100 - checksum; 791 792 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 793 794 tegra_pmc_writel(value, PMC_SCRATCH55); 795 796 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 797 value |= PMC_SENSOR_CTRL_ENABLE_RST; 798 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 799 800 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 801 802 out: 803 of_node_put(np); 804 return; 805 } 806 807 static int tegra_pmc_probe(struct platform_device *pdev) 808 { 809 void __iomem *base = pmc->base; 810 struct resource *res; 811 int err; 812 813 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 814 if (err < 0) 815 return err; 816 817 /* take over the memory region from the early initialization */ 818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 819 pmc->base = devm_ioremap_resource(&pdev->dev, res); 820 if (IS_ERR(pmc->base)) 821 return PTR_ERR(pmc->base); 822 823 iounmap(base); 824 825 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 826 if (IS_ERR(pmc->clk)) { 827 err = PTR_ERR(pmc->clk); 828 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 829 return err; 830 } 831 832 pmc->dev = &pdev->dev; 833 834 tegra_pmc_init(pmc); 835 836 tegra_pmc_init_tsense_reset(pmc); 837 838 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 839 err = tegra_powergate_debugfs_init(); 840 if (err < 0) 841 return err; 842 } 843 844 err = register_restart_handler(&tegra_pmc_restart_handler); 845 if (err) { 846 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 847 err); 848 return err; 849 } 850 851 return 0; 852 } 853 854 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 855 static int tegra_pmc_suspend(struct device *dev) 856 { 857 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 858 859 return 0; 860 } 861 862 static int tegra_pmc_resume(struct device *dev) 863 { 864 tegra_pmc_writel(0x0, PMC_SCRATCH41); 865 866 return 0; 867 } 868 869 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 870 871 #endif 872 873 static const char * const tegra20_powergates[] = { 874 [TEGRA_POWERGATE_CPU] = "cpu", 875 [TEGRA_POWERGATE_3D] = "3d", 876 [TEGRA_POWERGATE_VENC] = "venc", 877 [TEGRA_POWERGATE_VDEC] = "vdec", 878 [TEGRA_POWERGATE_PCIE] = "pcie", 879 [TEGRA_POWERGATE_L2] = "l2", 880 [TEGRA_POWERGATE_MPE] = "mpe", 881 }; 882 883 static const struct tegra_pmc_soc tegra20_pmc_soc = { 884 .num_powergates = ARRAY_SIZE(tegra20_powergates), 885 .powergates = tegra20_powergates, 886 .num_cpu_powergates = 0, 887 .cpu_powergates = NULL, 888 .has_tsense_reset = false, 889 .has_gpu_clamps = false, 890 }; 891 892 static const char * const tegra30_powergates[] = { 893 [TEGRA_POWERGATE_CPU] = "cpu0", 894 [TEGRA_POWERGATE_3D] = "3d0", 895 [TEGRA_POWERGATE_VENC] = "venc", 896 [TEGRA_POWERGATE_VDEC] = "vdec", 897 [TEGRA_POWERGATE_PCIE] = "pcie", 898 [TEGRA_POWERGATE_L2] = "l2", 899 [TEGRA_POWERGATE_MPE] = "mpe", 900 [TEGRA_POWERGATE_HEG] = "heg", 901 [TEGRA_POWERGATE_SATA] = "sata", 902 [TEGRA_POWERGATE_CPU1] = "cpu1", 903 [TEGRA_POWERGATE_CPU2] = "cpu2", 904 [TEGRA_POWERGATE_CPU3] = "cpu3", 905 [TEGRA_POWERGATE_CELP] = "celp", 906 [TEGRA_POWERGATE_3D1] = "3d1", 907 }; 908 909 static const u8 tegra30_cpu_powergates[] = { 910 TEGRA_POWERGATE_CPU, 911 TEGRA_POWERGATE_CPU1, 912 TEGRA_POWERGATE_CPU2, 913 TEGRA_POWERGATE_CPU3, 914 }; 915 916 static const struct tegra_pmc_soc tegra30_pmc_soc = { 917 .num_powergates = ARRAY_SIZE(tegra30_powergates), 918 .powergates = tegra30_powergates, 919 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 920 .cpu_powergates = tegra30_cpu_powergates, 921 .has_tsense_reset = true, 922 .has_gpu_clamps = false, 923 }; 924 925 static const char * const tegra114_powergates[] = { 926 [TEGRA_POWERGATE_CPU] = "crail", 927 [TEGRA_POWERGATE_3D] = "3d", 928 [TEGRA_POWERGATE_VENC] = "venc", 929 [TEGRA_POWERGATE_VDEC] = "vdec", 930 [TEGRA_POWERGATE_MPE] = "mpe", 931 [TEGRA_POWERGATE_HEG] = "heg", 932 [TEGRA_POWERGATE_CPU1] = "cpu1", 933 [TEGRA_POWERGATE_CPU2] = "cpu2", 934 [TEGRA_POWERGATE_CPU3] = "cpu3", 935 [TEGRA_POWERGATE_CELP] = "celp", 936 [TEGRA_POWERGATE_CPU0] = "cpu0", 937 [TEGRA_POWERGATE_C0NC] = "c0nc", 938 [TEGRA_POWERGATE_C1NC] = "c1nc", 939 [TEGRA_POWERGATE_DIS] = "dis", 940 [TEGRA_POWERGATE_DISB] = "disb", 941 [TEGRA_POWERGATE_XUSBA] = "xusba", 942 [TEGRA_POWERGATE_XUSBB] = "xusbb", 943 [TEGRA_POWERGATE_XUSBC] = "xusbc", 944 }; 945 946 static const u8 tegra114_cpu_powergates[] = { 947 TEGRA_POWERGATE_CPU0, 948 TEGRA_POWERGATE_CPU1, 949 TEGRA_POWERGATE_CPU2, 950 TEGRA_POWERGATE_CPU3, 951 }; 952 953 static const struct tegra_pmc_soc tegra114_pmc_soc = { 954 .num_powergates = ARRAY_SIZE(tegra114_powergates), 955 .powergates = tegra114_powergates, 956 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 957 .cpu_powergates = tegra114_cpu_powergates, 958 .has_tsense_reset = true, 959 .has_gpu_clamps = false, 960 }; 961 962 static const char * const tegra124_powergates[] = { 963 [TEGRA_POWERGATE_CPU] = "crail", 964 [TEGRA_POWERGATE_3D] = "3d", 965 [TEGRA_POWERGATE_VENC] = "venc", 966 [TEGRA_POWERGATE_PCIE] = "pcie", 967 [TEGRA_POWERGATE_VDEC] = "vdec", 968 [TEGRA_POWERGATE_L2] = "l2", 969 [TEGRA_POWERGATE_MPE] = "mpe", 970 [TEGRA_POWERGATE_HEG] = "heg", 971 [TEGRA_POWERGATE_SATA] = "sata", 972 [TEGRA_POWERGATE_CPU1] = "cpu1", 973 [TEGRA_POWERGATE_CPU2] = "cpu2", 974 [TEGRA_POWERGATE_CPU3] = "cpu3", 975 [TEGRA_POWERGATE_CELP] = "celp", 976 [TEGRA_POWERGATE_CPU0] = "cpu0", 977 [TEGRA_POWERGATE_C0NC] = "c0nc", 978 [TEGRA_POWERGATE_C1NC] = "c1nc", 979 [TEGRA_POWERGATE_SOR] = "sor", 980 [TEGRA_POWERGATE_DIS] = "dis", 981 [TEGRA_POWERGATE_DISB] = "disb", 982 [TEGRA_POWERGATE_XUSBA] = "xusba", 983 [TEGRA_POWERGATE_XUSBB] = "xusbb", 984 [TEGRA_POWERGATE_XUSBC] = "xusbc", 985 [TEGRA_POWERGATE_VIC] = "vic", 986 [TEGRA_POWERGATE_IRAM] = "iram", 987 }; 988 989 static const u8 tegra124_cpu_powergates[] = { 990 TEGRA_POWERGATE_CPU0, 991 TEGRA_POWERGATE_CPU1, 992 TEGRA_POWERGATE_CPU2, 993 TEGRA_POWERGATE_CPU3, 994 }; 995 996 static const struct tegra_pmc_soc tegra124_pmc_soc = { 997 .num_powergates = ARRAY_SIZE(tegra124_powergates), 998 .powergates = tegra124_powergates, 999 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1000 .cpu_powergates = tegra124_cpu_powergates, 1001 .has_tsense_reset = true, 1002 .has_gpu_clamps = true, 1003 }; 1004 1005 static const struct of_device_id tegra_pmc_match[] = { 1006 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 1007 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 1008 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 1009 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 1010 { } 1011 }; 1012 1013 static struct platform_driver tegra_pmc_driver = { 1014 .driver = { 1015 .name = "tegra-pmc", 1016 .suppress_bind_attrs = true, 1017 .of_match_table = tegra_pmc_match, 1018 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1019 .pm = &tegra_pmc_pm_ops, 1020 #endif 1021 }, 1022 .probe = tegra_pmc_probe, 1023 }; 1024 builtin_platform_driver(tegra_pmc_driver); 1025 1026 /* 1027 * Early initialization to allow access to registers in the very early boot 1028 * process. 1029 */ 1030 static int __init tegra_pmc_early_init(void) 1031 { 1032 const struct of_device_id *match; 1033 struct device_node *np; 1034 struct resource regs; 1035 bool invert; 1036 u32 value; 1037 1038 if (!soc_is_tegra()) 1039 return 0; 1040 1041 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 1042 if (!np) { 1043 pr_warn("PMC device node not found, disabling powergating\n"); 1044 1045 regs.start = 0x7000e400; 1046 regs.end = 0x7000e7ff; 1047 regs.flags = IORESOURCE_MEM; 1048 1049 pr_warn("Using memory region %pR\n", ®s); 1050 } else { 1051 pmc->soc = match->data; 1052 } 1053 1054 if (of_address_to_resource(np, 0, ®s) < 0) { 1055 pr_err("failed to get PMC registers\n"); 1056 return -ENXIO; 1057 } 1058 1059 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 1060 if (!pmc->base) { 1061 pr_err("failed to map PMC registers\n"); 1062 return -ENXIO; 1063 } 1064 1065 mutex_init(&pmc->powergates_lock); 1066 1067 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 1068 1069 value = tegra_pmc_readl(PMC_CNTRL); 1070 1071 if (invert) 1072 value |= PMC_CNTRL_INTR_POLARITY; 1073 else 1074 value &= ~PMC_CNTRL_INTR_POLARITY; 1075 1076 tegra_pmc_writel(value, PMC_CNTRL); 1077 1078 return 0; 1079 } 1080 early_initcall(tegra_pmc_early_init); 1081