1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Author: 8 * Colin Cross <ccross@google.com> 9 * 10 * This software is licensed under the terms of the GNU General Public 11 * License version 2, as published by the Free Software Foundation, and 12 * may be copied, distributed, and modified under those terms. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21 #define pr_fmt(fmt) "tegra-pmc: " fmt 22 23 #include <linux/arm-smccc.h> 24 #include <linux/clk.h> 25 #include <linux/clk/tegra.h> 26 #include <linux/debugfs.h> 27 #include <linux/delay.h> 28 #include <linux/err.h> 29 #include <linux/export.h> 30 #include <linux/init.h> 31 #include <linux/io.h> 32 #include <linux/iopoll.h> 33 #include <linux/irqdomain.h> 34 #include <linux/irq.h> 35 #include <linux/kernel.h> 36 #include <linux/of_address.h> 37 #include <linux/of_clk.h> 38 #include <linux/of.h> 39 #include <linux/of_irq.h> 40 #include <linux/of_platform.h> 41 #include <linux/pinctrl/pinconf-generic.h> 42 #include <linux/pinctrl/pinconf.h> 43 #include <linux/pinctrl/pinctrl.h> 44 #include <linux/platform_device.h> 45 #include <linux/pm_domain.h> 46 #include <linux/reboot.h> 47 #include <linux/reset.h> 48 #include <linux/seq_file.h> 49 #include <linux/slab.h> 50 #include <linux/spinlock.h> 51 52 #include <soc/tegra/common.h> 53 #include <soc/tegra/fuse.h> 54 #include <soc/tegra/pmc.h> 55 56 #include <dt-bindings/interrupt-controller/arm-gic.h> 57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 58 #include <dt-bindings/gpio/tegra186-gpio.h> 59 #include <dt-bindings/gpio/tegra194-gpio.h> 60 61 #define PMC_CNTRL 0x0 62 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 63 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 64 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 65 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 66 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 67 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 68 #define PMC_CNTRL_MAIN_RST BIT(4) 69 70 #define DPD_SAMPLE 0x020 71 #define DPD_SAMPLE_ENABLE BIT(0) 72 #define DPD_SAMPLE_DISABLE (0 << 0) 73 74 #define PWRGATE_TOGGLE 0x30 75 #define PWRGATE_TOGGLE_START BIT(8) 76 77 #define REMOVE_CLAMPING 0x34 78 79 #define PWRGATE_STATUS 0x38 80 81 #define PMC_IMPL_E_33V_PWR 0x40 82 83 #define PMC_PWR_DET 0x48 84 85 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 86 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 87 #define PMC_SCRATCH0_MODE_RCM BIT(1) 88 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 89 PMC_SCRATCH0_MODE_BOOTLOADER | \ 90 PMC_SCRATCH0_MODE_RCM) 91 92 #define PMC_CPUPWRGOOD_TIMER 0xc8 93 #define PMC_CPUPWROFF_TIMER 0xcc 94 95 #define PMC_PWR_DET_VALUE 0xe4 96 97 #define PMC_SCRATCH41 0x140 98 99 #define PMC_SENSOR_CTRL 0x1b0 100 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 101 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 102 103 #define PMC_RST_STATUS_POR 0 104 #define PMC_RST_STATUS_WATCHDOG 1 105 #define PMC_RST_STATUS_SENSOR 2 106 #define PMC_RST_STATUS_SW_MAIN 3 107 #define PMC_RST_STATUS_LP0 4 108 #define PMC_RST_STATUS_AOTAG 5 109 110 #define IO_DPD_REQ 0x1b8 111 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 112 #define IO_DPD_REQ_CODE_OFF (1U << 30) 113 #define IO_DPD_REQ_CODE_ON (2U << 30) 114 #define IO_DPD_REQ_CODE_MASK (3U << 30) 115 116 #define IO_DPD_STATUS 0x1bc 117 #define IO_DPD2_REQ 0x1c0 118 #define IO_DPD2_STATUS 0x1c4 119 #define SEL_DPD_TIM 0x1c8 120 121 #define PMC_SCRATCH54 0x258 122 #define PMC_SCRATCH54_DATA_SHIFT 8 123 #define PMC_SCRATCH54_ADDR_SHIFT 0 124 125 #define PMC_SCRATCH55 0x25c 126 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 127 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 128 #define PMC_SCRATCH55_PINMUX_SHIFT 24 129 #define PMC_SCRATCH55_16BITOP BIT(15) 130 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 131 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 132 133 #define GPU_RG_CNTRL 0x2d4 134 135 /* Tegra186 and later */ 136 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 137 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 138 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 139 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 140 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 141 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 142 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 143 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 144 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 145 146 #define WAKE_AOWAKE_CTRL 0x4f4 147 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 148 149 /* for secure PMC */ 150 #define TEGRA_SMC_PMC 0xc2fffe00 151 #define TEGRA_SMC_PMC_READ 0xaa 152 #define TEGRA_SMC_PMC_WRITE 0xbb 153 154 struct tegra_powergate { 155 struct generic_pm_domain genpd; 156 struct tegra_pmc *pmc; 157 unsigned int id; 158 struct clk **clks; 159 unsigned int num_clks; 160 struct reset_control *reset; 161 }; 162 163 struct tegra_io_pad_soc { 164 enum tegra_io_pad id; 165 unsigned int dpd; 166 unsigned int voltage; 167 const char *name; 168 }; 169 170 struct tegra_pmc_regs { 171 unsigned int scratch0; 172 unsigned int dpd_req; 173 unsigned int dpd_status; 174 unsigned int dpd2_req; 175 unsigned int dpd2_status; 176 unsigned int rst_status; 177 unsigned int rst_source_shift; 178 unsigned int rst_source_mask; 179 unsigned int rst_level_shift; 180 unsigned int rst_level_mask; 181 }; 182 183 struct tegra_wake_event { 184 const char *name; 185 unsigned int id; 186 unsigned int irq; 187 struct { 188 unsigned int instance; 189 unsigned int pin; 190 } gpio; 191 }; 192 193 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 194 { \ 195 .name = _name, \ 196 .id = _id, \ 197 .irq = _irq, \ 198 .gpio = { \ 199 .instance = UINT_MAX, \ 200 .pin = UINT_MAX, \ 201 }, \ 202 } 203 204 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 205 { \ 206 .name = _name, \ 207 .id = _id, \ 208 .irq = 0, \ 209 .gpio = { \ 210 .instance = _instance, \ 211 .pin = _pin, \ 212 }, \ 213 } 214 215 struct tegra_pmc_soc { 216 unsigned int num_powergates; 217 const char *const *powergates; 218 unsigned int num_cpu_powergates; 219 const u8 *cpu_powergates; 220 221 bool has_tsense_reset; 222 bool has_gpu_clamps; 223 bool needs_mbist_war; 224 bool has_impl_33v_pwr; 225 bool maybe_tz_only; 226 227 const struct tegra_io_pad_soc *io_pads; 228 unsigned int num_io_pads; 229 230 const struct pinctrl_pin_desc *pin_descs; 231 unsigned int num_pin_descs; 232 233 const struct tegra_pmc_regs *regs; 234 void (*init)(struct tegra_pmc *pmc); 235 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 236 struct device_node *np, 237 bool invert); 238 239 const char * const *reset_sources; 240 unsigned int num_reset_sources; 241 const char * const *reset_levels; 242 unsigned int num_reset_levels; 243 244 const struct tegra_wake_event *wake_events; 245 unsigned int num_wake_events; 246 }; 247 248 static const char * const tegra186_reset_sources[] = { 249 "SYS_RESET", 250 "AOWDT", 251 "MCCPLEXWDT", 252 "BPMPWDT", 253 "SCEWDT", 254 "SPEWDT", 255 "APEWDT", 256 "BCCPLEXWDT", 257 "SENSOR", 258 "AOTAG", 259 "VFSENSOR", 260 "SWREST", 261 "SC7", 262 "HSM", 263 "CORESIGHT" 264 }; 265 266 static const char * const tegra186_reset_levels[] = { 267 "L0", "L1", "L2", "WARM" 268 }; 269 270 static const char * const tegra30_reset_sources[] = { 271 "POWER_ON_RESET", 272 "WATCHDOG", 273 "SENSOR", 274 "SW_MAIN", 275 "LP0", 276 "AOTAG" 277 }; 278 279 /** 280 * struct tegra_pmc - NVIDIA Tegra PMC 281 * @dev: pointer to PMC device structure 282 * @base: pointer to I/O remapped register region 283 * @wake: pointer to I/O remapped region for WAKE registers 284 * @aotag: pointer to I/O remapped region for AOTAG registers 285 * @scratch: pointer to I/O remapped region for scratch registers 286 * @clk: pointer to pclk clock 287 * @soc: pointer to SoC data structure 288 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 289 * @debugfs: pointer to debugfs entry 290 * @rate: currently configured rate of pclk 291 * @suspend_mode: lowest suspend mode available 292 * @cpu_good_time: CPU power good time (in microseconds) 293 * @cpu_off_time: CPU power off time (in microsecends) 294 * @core_osc_time: core power good OSC time (in microseconds) 295 * @core_pmu_time: core power good PMU time (in microseconds) 296 * @core_off_time: core power off time (in microseconds) 297 * @corereq_high: core power request is active-high 298 * @sysclkreq_high: system clock request is active-high 299 * @combined_req: combined power request for CPU & core 300 * @cpu_pwr_good_en: CPU power good signal is enabled 301 * @lp0_vec_phys: physical base address of the LP0 warm boot code 302 * @lp0_vec_size: size of the LP0 warm boot code 303 * @powergates_available: Bitmap of available power gates 304 * @powergates_lock: mutex for power gate register access 305 * @pctl_dev: pin controller exposed by the PMC 306 * @domain: IRQ domain provided by the PMC 307 * @irq: chip implementation for the IRQ domain 308 */ 309 struct tegra_pmc { 310 struct device *dev; 311 void __iomem *base; 312 void __iomem *wake; 313 void __iomem *aotag; 314 void __iomem *scratch; 315 struct clk *clk; 316 struct dentry *debugfs; 317 318 const struct tegra_pmc_soc *soc; 319 bool tz_only; 320 321 unsigned long rate; 322 323 enum tegra_suspend_mode suspend_mode; 324 u32 cpu_good_time; 325 u32 cpu_off_time; 326 u32 core_osc_time; 327 u32 core_pmu_time; 328 u32 core_off_time; 329 bool corereq_high; 330 bool sysclkreq_high; 331 bool combined_req; 332 bool cpu_pwr_good_en; 333 u32 lp0_vec_phys; 334 u32 lp0_vec_size; 335 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 336 337 struct mutex powergates_lock; 338 339 struct pinctrl_dev *pctl_dev; 340 341 struct irq_domain *domain; 342 struct irq_chip irq; 343 }; 344 345 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 346 .base = NULL, 347 .suspend_mode = TEGRA_SUSPEND_NONE, 348 }; 349 350 static inline struct tegra_powergate * 351 to_powergate(struct generic_pm_domain *domain) 352 { 353 return container_of(domain, struct tegra_powergate, genpd); 354 } 355 356 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 357 { 358 struct arm_smccc_res res; 359 360 if (pmc->tz_only) { 361 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 362 0, 0, 0, &res); 363 if (res.a0) { 364 if (pmc->dev) 365 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 366 __func__, res.a0); 367 else 368 pr_warn("%s(): SMC failed: %lu\n", __func__, 369 res.a0); 370 } 371 372 return res.a1; 373 } 374 375 return readl(pmc->base + offset); 376 } 377 378 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 379 unsigned long offset) 380 { 381 struct arm_smccc_res res; 382 383 if (pmc->tz_only) { 384 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 385 value, 0, 0, 0, 0, &res); 386 if (res.a0) { 387 if (pmc->dev) 388 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 389 __func__, res.a0); 390 else 391 pr_warn("%s(): SMC failed: %lu\n", __func__, 392 res.a0); 393 } 394 } else { 395 writel(value, pmc->base + offset); 396 } 397 } 398 399 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 400 { 401 if (pmc->tz_only) 402 return tegra_pmc_readl(pmc, offset); 403 404 return readl(pmc->scratch + offset); 405 } 406 407 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 408 unsigned long offset) 409 { 410 if (pmc->tz_only) 411 tegra_pmc_writel(pmc, value, offset); 412 else 413 writel(value, pmc->scratch + offset); 414 } 415 416 /* 417 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 418 * This currently doesn't work because readx_poll_timeout() can only operate 419 * on functions that take a single argument. 420 */ 421 static inline bool tegra_powergate_state(int id) 422 { 423 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 424 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 425 else 426 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 427 } 428 429 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 430 { 431 return (pmc->soc && pmc->soc->powergates[id]); 432 } 433 434 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 435 { 436 return test_bit(id, pmc->powergates_available); 437 } 438 439 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 440 { 441 unsigned int i; 442 443 if (!pmc || !pmc->soc || !name) 444 return -EINVAL; 445 446 for (i = 0; i < pmc->soc->num_powergates; i++) { 447 if (!tegra_powergate_is_valid(pmc, i)) 448 continue; 449 450 if (!strcmp(name, pmc->soc->powergates[i])) 451 return i; 452 } 453 454 return -ENODEV; 455 } 456 457 /** 458 * tegra_powergate_set() - set the state of a partition 459 * @pmc: power management controller 460 * @id: partition ID 461 * @new_state: new state of the partition 462 */ 463 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 464 bool new_state) 465 { 466 bool status; 467 int err; 468 469 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 470 return -EINVAL; 471 472 mutex_lock(&pmc->powergates_lock); 473 474 if (tegra_powergate_state(id) == new_state) { 475 mutex_unlock(&pmc->powergates_lock); 476 return 0; 477 } 478 479 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 480 481 err = readx_poll_timeout(tegra_powergate_state, id, status, 482 status == new_state, 10, 100000); 483 484 mutex_unlock(&pmc->powergates_lock); 485 486 return err; 487 } 488 489 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 490 unsigned int id) 491 { 492 u32 mask; 493 494 mutex_lock(&pmc->powergates_lock); 495 496 /* 497 * On Tegra124 and later, the clamps for the GPU are controlled by a 498 * separate register (with different semantics). 499 */ 500 if (id == TEGRA_POWERGATE_3D) { 501 if (pmc->soc->has_gpu_clamps) { 502 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 503 goto out; 504 } 505 } 506 507 /* 508 * Tegra 2 has a bug where PCIE and VDE clamping masks are 509 * swapped relatively to the partition ids 510 */ 511 if (id == TEGRA_POWERGATE_VDEC) 512 mask = (1 << TEGRA_POWERGATE_PCIE); 513 else if (id == TEGRA_POWERGATE_PCIE) 514 mask = (1 << TEGRA_POWERGATE_VDEC); 515 else 516 mask = (1 << id); 517 518 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 519 520 out: 521 mutex_unlock(&pmc->powergates_lock); 522 523 return 0; 524 } 525 526 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 527 { 528 unsigned int i; 529 530 for (i = 0; i < pg->num_clks; i++) 531 clk_disable_unprepare(pg->clks[i]); 532 } 533 534 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 535 { 536 unsigned int i; 537 int err; 538 539 for (i = 0; i < pg->num_clks; i++) { 540 err = clk_prepare_enable(pg->clks[i]); 541 if (err) 542 goto out; 543 } 544 545 return 0; 546 547 out: 548 while (i--) 549 clk_disable_unprepare(pg->clks[i]); 550 551 return err; 552 } 553 554 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 555 { 556 return 0; 557 } 558 559 static int tegra_powergate_power_up(struct tegra_powergate *pg, 560 bool disable_clocks) 561 { 562 int err; 563 564 err = reset_control_assert(pg->reset); 565 if (err) 566 return err; 567 568 usleep_range(10, 20); 569 570 err = tegra_powergate_set(pg->pmc, pg->id, true); 571 if (err < 0) 572 return err; 573 574 usleep_range(10, 20); 575 576 err = tegra_powergate_enable_clocks(pg); 577 if (err) 578 goto disable_clks; 579 580 usleep_range(10, 20); 581 582 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 583 if (err) 584 goto disable_clks; 585 586 usleep_range(10, 20); 587 588 err = reset_control_deassert(pg->reset); 589 if (err) 590 goto powergate_off; 591 592 usleep_range(10, 20); 593 594 if (pg->pmc->soc->needs_mbist_war) 595 err = tegra210_clk_handle_mbist_war(pg->id); 596 if (err) 597 goto disable_clks; 598 599 if (disable_clocks) 600 tegra_powergate_disable_clocks(pg); 601 602 return 0; 603 604 disable_clks: 605 tegra_powergate_disable_clocks(pg); 606 usleep_range(10, 20); 607 608 powergate_off: 609 tegra_powergate_set(pg->pmc, pg->id, false); 610 611 return err; 612 } 613 614 static int tegra_powergate_power_down(struct tegra_powergate *pg) 615 { 616 int err; 617 618 err = tegra_powergate_enable_clocks(pg); 619 if (err) 620 return err; 621 622 usleep_range(10, 20); 623 624 err = reset_control_assert(pg->reset); 625 if (err) 626 goto disable_clks; 627 628 usleep_range(10, 20); 629 630 tegra_powergate_disable_clocks(pg); 631 632 usleep_range(10, 20); 633 634 err = tegra_powergate_set(pg->pmc, pg->id, false); 635 if (err) 636 goto assert_resets; 637 638 return 0; 639 640 assert_resets: 641 tegra_powergate_enable_clocks(pg); 642 usleep_range(10, 20); 643 reset_control_deassert(pg->reset); 644 usleep_range(10, 20); 645 646 disable_clks: 647 tegra_powergate_disable_clocks(pg); 648 649 return err; 650 } 651 652 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 653 { 654 struct tegra_powergate *pg = to_powergate(domain); 655 struct device *dev = pg->pmc->dev; 656 int err; 657 658 err = tegra_powergate_power_up(pg, true); 659 if (err) 660 dev_err(dev, "failed to turn on PM domain %s: %d\n", 661 pg->genpd.name, err); 662 663 return err; 664 } 665 666 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 667 { 668 struct tegra_powergate *pg = to_powergate(domain); 669 struct device *dev = pg->pmc->dev; 670 int err; 671 672 err = tegra_powergate_power_down(pg); 673 if (err) 674 dev_err(dev, "failed to turn off PM domain %s: %d\n", 675 pg->genpd.name, err); 676 677 return err; 678 } 679 680 /** 681 * tegra_powergate_power_on() - power on partition 682 * @id: partition ID 683 */ 684 int tegra_powergate_power_on(unsigned int id) 685 { 686 if (!tegra_powergate_is_available(pmc, id)) 687 return -EINVAL; 688 689 return tegra_powergate_set(pmc, id, true); 690 } 691 692 /** 693 * tegra_powergate_power_off() - power off partition 694 * @id: partition ID 695 */ 696 int tegra_powergate_power_off(unsigned int id) 697 { 698 if (!tegra_powergate_is_available(pmc, id)) 699 return -EINVAL; 700 701 return tegra_powergate_set(pmc, id, false); 702 } 703 EXPORT_SYMBOL(tegra_powergate_power_off); 704 705 /** 706 * tegra_powergate_is_powered() - check if partition is powered 707 * @pmc: power management controller 708 * @id: partition ID 709 */ 710 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 711 { 712 if (!tegra_powergate_is_valid(pmc, id)) 713 return -EINVAL; 714 715 return tegra_powergate_state(id); 716 } 717 718 /** 719 * tegra_powergate_remove_clamping() - remove power clamps for partition 720 * @id: partition ID 721 */ 722 int tegra_powergate_remove_clamping(unsigned int id) 723 { 724 if (!tegra_powergate_is_available(pmc, id)) 725 return -EINVAL; 726 727 return __tegra_powergate_remove_clamping(pmc, id); 728 } 729 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 730 731 /** 732 * tegra_powergate_sequence_power_up() - power up partition 733 * @id: partition ID 734 * @clk: clock for partition 735 * @rst: reset for partition 736 * 737 * Must be called with clk disabled, and returns with clk enabled. 738 */ 739 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 740 struct reset_control *rst) 741 { 742 struct tegra_powergate *pg; 743 int err; 744 745 if (!tegra_powergate_is_available(pmc, id)) 746 return -EINVAL; 747 748 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 749 if (!pg) 750 return -ENOMEM; 751 752 pg->id = id; 753 pg->clks = &clk; 754 pg->num_clks = 1; 755 pg->reset = rst; 756 pg->pmc = pmc; 757 758 err = tegra_powergate_power_up(pg, false); 759 if (err) 760 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 761 err); 762 763 kfree(pg); 764 765 return err; 766 } 767 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 768 769 /** 770 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 771 * @pmc: power management controller 772 * @cpuid: CPU partition ID 773 * 774 * Returns the partition ID corresponding to the CPU partition ID or a 775 * negative error code on failure. 776 */ 777 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 778 unsigned int cpuid) 779 { 780 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 781 return pmc->soc->cpu_powergates[cpuid]; 782 783 return -EINVAL; 784 } 785 786 /** 787 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 788 * @cpuid: CPU partition ID 789 */ 790 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 791 { 792 int id; 793 794 id = tegra_get_cpu_powergate_id(pmc, cpuid); 795 if (id < 0) 796 return false; 797 798 return tegra_powergate_is_powered(pmc, id); 799 } 800 801 /** 802 * tegra_pmc_cpu_power_on() - power on CPU partition 803 * @cpuid: CPU partition ID 804 */ 805 int tegra_pmc_cpu_power_on(unsigned int cpuid) 806 { 807 int id; 808 809 id = tegra_get_cpu_powergate_id(pmc, cpuid); 810 if (id < 0) 811 return id; 812 813 return tegra_powergate_set(pmc, id, true); 814 } 815 816 /** 817 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 818 * @cpuid: CPU partition ID 819 */ 820 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 821 { 822 int id; 823 824 id = tegra_get_cpu_powergate_id(pmc, cpuid); 825 if (id < 0) 826 return id; 827 828 return tegra_powergate_remove_clamping(id); 829 } 830 831 static int tegra_pmc_restart_notify(struct notifier_block *this, 832 unsigned long action, void *data) 833 { 834 const char *cmd = data; 835 u32 value; 836 837 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 838 value &= ~PMC_SCRATCH0_MODE_MASK; 839 840 if (cmd) { 841 if (strcmp(cmd, "recovery") == 0) 842 value |= PMC_SCRATCH0_MODE_RECOVERY; 843 844 if (strcmp(cmd, "bootloader") == 0) 845 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 846 847 if (strcmp(cmd, "forced-recovery") == 0) 848 value |= PMC_SCRATCH0_MODE_RCM; 849 } 850 851 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 852 853 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 854 value = tegra_pmc_readl(pmc, PMC_CNTRL); 855 value |= PMC_CNTRL_MAIN_RST; 856 tegra_pmc_writel(pmc, value, PMC_CNTRL); 857 858 return NOTIFY_DONE; 859 } 860 861 static struct notifier_block tegra_pmc_restart_handler = { 862 .notifier_call = tegra_pmc_restart_notify, 863 .priority = 128, 864 }; 865 866 static int powergate_show(struct seq_file *s, void *data) 867 { 868 unsigned int i; 869 int status; 870 871 seq_printf(s, " powergate powered\n"); 872 seq_printf(s, "------------------\n"); 873 874 for (i = 0; i < pmc->soc->num_powergates; i++) { 875 status = tegra_powergate_is_powered(pmc, i); 876 if (status < 0) 877 continue; 878 879 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 880 status ? "yes" : "no"); 881 } 882 883 return 0; 884 } 885 886 DEFINE_SHOW_ATTRIBUTE(powergate); 887 888 static int tegra_powergate_debugfs_init(void) 889 { 890 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 891 &powergate_fops); 892 if (!pmc->debugfs) 893 return -ENOMEM; 894 895 return 0; 896 } 897 898 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 899 struct device_node *np) 900 { 901 struct clk *clk; 902 unsigned int i, count; 903 int err; 904 905 count = of_clk_get_parent_count(np); 906 if (count == 0) 907 return -ENODEV; 908 909 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 910 if (!pg->clks) 911 return -ENOMEM; 912 913 for (i = 0; i < count; i++) { 914 pg->clks[i] = of_clk_get(np, i); 915 if (IS_ERR(pg->clks[i])) { 916 err = PTR_ERR(pg->clks[i]); 917 goto err; 918 } 919 } 920 921 pg->num_clks = count; 922 923 return 0; 924 925 err: 926 while (i--) 927 clk_put(pg->clks[i]); 928 929 kfree(pg->clks); 930 931 return err; 932 } 933 934 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 935 struct device_node *np, bool off) 936 { 937 struct device *dev = pg->pmc->dev; 938 int err; 939 940 pg->reset = of_reset_control_array_get_exclusive(np); 941 if (IS_ERR(pg->reset)) { 942 err = PTR_ERR(pg->reset); 943 dev_err(dev, "failed to get device resets: %d\n", err); 944 return err; 945 } 946 947 if (off) 948 err = reset_control_assert(pg->reset); 949 else 950 err = reset_control_deassert(pg->reset); 951 952 if (err) 953 reset_control_put(pg->reset); 954 955 return err; 956 } 957 958 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 959 { 960 struct device *dev = pmc->dev; 961 struct tegra_powergate *pg; 962 int id, err; 963 bool off; 964 965 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 966 if (!pg) 967 return; 968 969 id = tegra_powergate_lookup(pmc, np->name); 970 if (id < 0) { 971 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 972 goto free_mem; 973 } 974 975 /* 976 * Clear the bit for this powergate so it cannot be managed 977 * directly via the legacy APIs for controlling powergates. 978 */ 979 clear_bit(id, pmc->powergates_available); 980 981 pg->id = id; 982 pg->genpd.name = np->name; 983 pg->genpd.power_off = tegra_genpd_power_off; 984 pg->genpd.power_on = tegra_genpd_power_on; 985 pg->pmc = pmc; 986 987 off = !tegra_powergate_is_powered(pmc, pg->id); 988 989 err = tegra_powergate_of_get_clks(pg, np); 990 if (err < 0) { 991 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 992 goto set_available; 993 } 994 995 err = tegra_powergate_of_get_resets(pg, np, off); 996 if (err < 0) { 997 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 998 goto remove_clks; 999 } 1000 1001 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1002 if (off) 1003 WARN_ON(tegra_powergate_power_up(pg, true)); 1004 1005 goto remove_resets; 1006 } 1007 1008 err = pm_genpd_init(&pg->genpd, NULL, off); 1009 if (err < 0) { 1010 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1011 err); 1012 goto remove_resets; 1013 } 1014 1015 err = of_genpd_add_provider_simple(np, &pg->genpd); 1016 if (err < 0) { 1017 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1018 np, err); 1019 goto remove_genpd; 1020 } 1021 1022 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1023 1024 return; 1025 1026 remove_genpd: 1027 pm_genpd_remove(&pg->genpd); 1028 1029 remove_resets: 1030 reset_control_put(pg->reset); 1031 1032 remove_clks: 1033 while (pg->num_clks--) 1034 clk_put(pg->clks[pg->num_clks]); 1035 1036 kfree(pg->clks); 1037 1038 set_available: 1039 set_bit(id, pmc->powergates_available); 1040 1041 free_mem: 1042 kfree(pg); 1043 } 1044 1045 static void tegra_powergate_init(struct tegra_pmc *pmc, 1046 struct device_node *parent) 1047 { 1048 struct device_node *np, *child; 1049 unsigned int i; 1050 1051 /* Create a bitmap of the available and valid partitions */ 1052 for (i = 0; i < pmc->soc->num_powergates; i++) 1053 if (pmc->soc->powergates[i]) 1054 set_bit(i, pmc->powergates_available); 1055 1056 np = of_get_child_by_name(parent, "powergates"); 1057 if (!np) 1058 return; 1059 1060 for_each_child_of_node(np, child) 1061 tegra_powergate_add(pmc, child); 1062 1063 of_node_put(np); 1064 } 1065 1066 static const struct tegra_io_pad_soc * 1067 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1068 { 1069 unsigned int i; 1070 1071 for (i = 0; i < pmc->soc->num_io_pads; i++) 1072 if (pmc->soc->io_pads[i].id == id) 1073 return &pmc->soc->io_pads[i]; 1074 1075 return NULL; 1076 } 1077 1078 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, 1079 enum tegra_io_pad id, 1080 unsigned long *request, 1081 unsigned long *status, 1082 u32 *mask) 1083 { 1084 const struct tegra_io_pad_soc *pad; 1085 1086 pad = tegra_io_pad_find(pmc, id); 1087 if (!pad) { 1088 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1089 return -ENOENT; 1090 } 1091 1092 if (pad->dpd == UINT_MAX) 1093 return -ENOTSUPP; 1094 1095 *mask = BIT(pad->dpd % 32); 1096 1097 if (pad->dpd < 32) { 1098 *status = pmc->soc->regs->dpd_status; 1099 *request = pmc->soc->regs->dpd_req; 1100 } else { 1101 *status = pmc->soc->regs->dpd2_status; 1102 *request = pmc->soc->regs->dpd2_req; 1103 } 1104 1105 return 0; 1106 } 1107 1108 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, 1109 unsigned long *request, unsigned long *status, 1110 u32 *mask) 1111 { 1112 unsigned long rate, value; 1113 int err; 1114 1115 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); 1116 if (err) 1117 return err; 1118 1119 if (pmc->clk) { 1120 rate = clk_get_rate(pmc->clk); 1121 if (!rate) { 1122 dev_err(pmc->dev, "failed to get clock rate\n"); 1123 return -ENODEV; 1124 } 1125 1126 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1127 1128 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1129 value = DIV_ROUND_UP(1000000000, rate); 1130 value = DIV_ROUND_UP(200, value); 1131 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1138 u32 mask, u32 val, unsigned long timeout) 1139 { 1140 u32 value; 1141 1142 timeout = jiffies + msecs_to_jiffies(timeout); 1143 1144 while (time_after(timeout, jiffies)) { 1145 value = tegra_pmc_readl(pmc, offset); 1146 if ((value & mask) == val) 1147 return 0; 1148 1149 usleep_range(250, 1000); 1150 } 1151 1152 return -ETIMEDOUT; 1153 } 1154 1155 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1156 { 1157 if (pmc->clk) 1158 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1159 } 1160 1161 /** 1162 * tegra_io_pad_power_enable() - enable power to I/O pad 1163 * @id: Tegra I/O pad ID for which to enable power 1164 * 1165 * Returns: 0 on success or a negative error code on failure. 1166 */ 1167 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1168 { 1169 unsigned long request, status; 1170 u32 mask; 1171 int err; 1172 1173 mutex_lock(&pmc->powergates_lock); 1174 1175 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1176 if (err < 0) { 1177 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1178 goto unlock; 1179 } 1180 1181 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1182 1183 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1184 if (err < 0) { 1185 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1186 goto unlock; 1187 } 1188 1189 tegra_io_pad_unprepare(pmc); 1190 1191 unlock: 1192 mutex_unlock(&pmc->powergates_lock); 1193 return err; 1194 } 1195 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1196 1197 /** 1198 * tegra_io_pad_power_disable() - disable power to I/O pad 1199 * @id: Tegra I/O pad ID for which to disable power 1200 * 1201 * Returns: 0 on success or a negative error code on failure. 1202 */ 1203 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1204 { 1205 unsigned long request, status; 1206 u32 mask; 1207 int err; 1208 1209 mutex_lock(&pmc->powergates_lock); 1210 1211 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1212 if (err < 0) { 1213 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1214 goto unlock; 1215 } 1216 1217 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1218 1219 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1220 if (err < 0) { 1221 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1222 goto unlock; 1223 } 1224 1225 tegra_io_pad_unprepare(pmc); 1226 1227 unlock: 1228 mutex_unlock(&pmc->powergates_lock); 1229 return err; 1230 } 1231 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1232 1233 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1234 { 1235 unsigned long request, status; 1236 u32 mask, value; 1237 int err; 1238 1239 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, 1240 &mask); 1241 if (err) 1242 return err; 1243 1244 value = tegra_pmc_readl(pmc, status); 1245 1246 return !(value & mask); 1247 } 1248 1249 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1250 int voltage) 1251 { 1252 const struct tegra_io_pad_soc *pad; 1253 u32 value; 1254 1255 pad = tegra_io_pad_find(pmc, id); 1256 if (!pad) 1257 return -ENOENT; 1258 1259 if (pad->voltage == UINT_MAX) 1260 return -ENOTSUPP; 1261 1262 mutex_lock(&pmc->powergates_lock); 1263 1264 if (pmc->soc->has_impl_33v_pwr) { 1265 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1266 1267 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1268 value &= ~BIT(pad->voltage); 1269 else 1270 value |= BIT(pad->voltage); 1271 1272 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1273 } else { 1274 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1275 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1276 value |= BIT(pad->voltage); 1277 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1278 1279 /* update I/O voltage */ 1280 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1281 1282 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1283 value &= ~BIT(pad->voltage); 1284 else 1285 value |= BIT(pad->voltage); 1286 1287 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1288 } 1289 1290 mutex_unlock(&pmc->powergates_lock); 1291 1292 usleep_range(100, 250); 1293 1294 return 0; 1295 } 1296 1297 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1298 { 1299 const struct tegra_io_pad_soc *pad; 1300 u32 value; 1301 1302 pad = tegra_io_pad_find(pmc, id); 1303 if (!pad) 1304 return -ENOENT; 1305 1306 if (pad->voltage == UINT_MAX) 1307 return -ENOTSUPP; 1308 1309 if (pmc->soc->has_impl_33v_pwr) 1310 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1311 else 1312 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1313 1314 if ((value & BIT(pad->voltage)) == 0) 1315 return TEGRA_IO_PAD_VOLTAGE_1V8; 1316 1317 return TEGRA_IO_PAD_VOLTAGE_3V3; 1318 } 1319 1320 /** 1321 * tegra_io_rail_power_on() - enable power to I/O rail 1322 * @id: Tegra I/O pad ID for which to enable power 1323 * 1324 * See also: tegra_io_pad_power_enable() 1325 */ 1326 int tegra_io_rail_power_on(unsigned int id) 1327 { 1328 return tegra_io_pad_power_enable(id); 1329 } 1330 EXPORT_SYMBOL(tegra_io_rail_power_on); 1331 1332 /** 1333 * tegra_io_rail_power_off() - disable power to I/O rail 1334 * @id: Tegra I/O pad ID for which to disable power 1335 * 1336 * See also: tegra_io_pad_power_disable() 1337 */ 1338 int tegra_io_rail_power_off(unsigned int id) 1339 { 1340 return tegra_io_pad_power_disable(id); 1341 } 1342 EXPORT_SYMBOL(tegra_io_rail_power_off); 1343 1344 #ifdef CONFIG_PM_SLEEP 1345 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1346 { 1347 return pmc->suspend_mode; 1348 } 1349 1350 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1351 { 1352 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1353 return; 1354 1355 pmc->suspend_mode = mode; 1356 } 1357 1358 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1359 { 1360 unsigned long long rate = 0; 1361 u32 value; 1362 1363 switch (mode) { 1364 case TEGRA_SUSPEND_LP1: 1365 rate = 32768; 1366 break; 1367 1368 case TEGRA_SUSPEND_LP2: 1369 rate = clk_get_rate(pmc->clk); 1370 break; 1371 1372 default: 1373 break; 1374 } 1375 1376 if (WARN_ON_ONCE(rate == 0)) 1377 rate = 100000000; 1378 1379 if (rate != pmc->rate) { 1380 u64 ticks; 1381 1382 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1383 do_div(ticks, USEC_PER_SEC); 1384 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1385 1386 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1387 do_div(ticks, USEC_PER_SEC); 1388 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1389 1390 wmb(); 1391 1392 pmc->rate = rate; 1393 } 1394 1395 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1396 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1397 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1398 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1399 } 1400 #endif 1401 1402 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1403 { 1404 u32 value, values[2]; 1405 1406 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1407 } else { 1408 switch (value) { 1409 case 0: 1410 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1411 break; 1412 1413 case 1: 1414 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1415 break; 1416 1417 case 2: 1418 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1419 break; 1420 1421 default: 1422 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1423 break; 1424 } 1425 } 1426 1427 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1428 1429 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1430 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1431 1432 pmc->cpu_good_time = value; 1433 1434 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1435 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1436 1437 pmc->cpu_off_time = value; 1438 1439 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1440 values, ARRAY_SIZE(values))) 1441 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1442 1443 pmc->core_osc_time = values[0]; 1444 pmc->core_pmu_time = values[1]; 1445 1446 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1447 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1448 1449 pmc->core_off_time = value; 1450 1451 pmc->corereq_high = of_property_read_bool(np, 1452 "nvidia,core-power-req-active-high"); 1453 1454 pmc->sysclkreq_high = of_property_read_bool(np, 1455 "nvidia,sys-clock-req-active-high"); 1456 1457 pmc->combined_req = of_property_read_bool(np, 1458 "nvidia,combined-power-req"); 1459 1460 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1461 "nvidia,cpu-pwr-good-en"); 1462 1463 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1464 ARRAY_SIZE(values))) 1465 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1466 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1467 1468 pmc->lp0_vec_phys = values[0]; 1469 pmc->lp0_vec_size = values[1]; 1470 1471 return 0; 1472 } 1473 1474 static void tegra_pmc_init(struct tegra_pmc *pmc) 1475 { 1476 if (pmc->soc->init) 1477 pmc->soc->init(pmc); 1478 } 1479 1480 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1481 { 1482 static const char disabled[] = "emergency thermal reset disabled"; 1483 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1484 struct device *dev = pmc->dev; 1485 struct device_node *np; 1486 u32 value, checksum; 1487 1488 if (!pmc->soc->has_tsense_reset) 1489 return; 1490 1491 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1492 if (!np) { 1493 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1494 return; 1495 } 1496 1497 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1498 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1499 goto out; 1500 } 1501 1502 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1503 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1504 goto out; 1505 } 1506 1507 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1508 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1509 goto out; 1510 } 1511 1512 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1513 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1514 goto out; 1515 } 1516 1517 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1518 pinmux = 0; 1519 1520 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1521 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1522 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1523 1524 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1525 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1526 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1527 1528 value = PMC_SCRATCH55_RESET_TEGRA; 1529 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1530 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1531 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1532 1533 /* 1534 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1535 * contain the checksum and are currently zero, so they are not added. 1536 */ 1537 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1538 + ((value >> 24) & 0xff); 1539 checksum &= 0xff; 1540 checksum = 0x100 - checksum; 1541 1542 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1543 1544 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1545 1546 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1547 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1548 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1549 1550 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1551 1552 out: 1553 of_node_put(np); 1554 } 1555 1556 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1557 { 1558 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1559 1560 return pmc->soc->num_io_pads; 1561 } 1562 1563 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 1564 unsigned int group) 1565 { 1566 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 1567 1568 return pmc->soc->io_pads[group].name; 1569 } 1570 1571 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 1572 unsigned int group, 1573 const unsigned int **pins, 1574 unsigned int *num_pins) 1575 { 1576 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1577 1578 *pins = &pmc->soc->io_pads[group].id; 1579 *num_pins = 1; 1580 1581 return 0; 1582 } 1583 1584 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 1585 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 1586 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 1587 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 1588 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1589 .dt_free_map = pinconf_generic_dt_free_map, 1590 }; 1591 1592 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 1593 unsigned int pin, unsigned long *config) 1594 { 1595 enum pin_config_param param = pinconf_to_config_param(*config); 1596 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1597 const struct tegra_io_pad_soc *pad; 1598 int ret; 1599 u32 arg; 1600 1601 pad = tegra_io_pad_find(pmc, pin); 1602 if (!pad) 1603 return -EINVAL; 1604 1605 switch (param) { 1606 case PIN_CONFIG_POWER_SOURCE: 1607 ret = tegra_io_pad_get_voltage(pmc, pad->id); 1608 if (ret < 0) 1609 return ret; 1610 1611 arg = ret; 1612 break; 1613 1614 case PIN_CONFIG_LOW_POWER_MODE: 1615 ret = tegra_io_pad_is_powered(pmc, pad->id); 1616 if (ret < 0) 1617 return ret; 1618 1619 arg = !ret; 1620 break; 1621 1622 default: 1623 return -EINVAL; 1624 } 1625 1626 *config = pinconf_to_config_packed(param, arg); 1627 1628 return 0; 1629 } 1630 1631 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 1632 unsigned int pin, unsigned long *configs, 1633 unsigned int num_configs) 1634 { 1635 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1636 const struct tegra_io_pad_soc *pad; 1637 enum pin_config_param param; 1638 unsigned int i; 1639 int err; 1640 u32 arg; 1641 1642 pad = tegra_io_pad_find(pmc, pin); 1643 if (!pad) 1644 return -EINVAL; 1645 1646 for (i = 0; i < num_configs; ++i) { 1647 param = pinconf_to_config_param(configs[i]); 1648 arg = pinconf_to_config_argument(configs[i]); 1649 1650 switch (param) { 1651 case PIN_CONFIG_LOW_POWER_MODE: 1652 if (arg) 1653 err = tegra_io_pad_power_disable(pad->id); 1654 else 1655 err = tegra_io_pad_power_enable(pad->id); 1656 if (err) 1657 return err; 1658 break; 1659 case PIN_CONFIG_POWER_SOURCE: 1660 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 1661 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 1662 return -EINVAL; 1663 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 1664 if (err) 1665 return err; 1666 break; 1667 default: 1668 return -EINVAL; 1669 } 1670 } 1671 1672 return 0; 1673 } 1674 1675 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 1676 .pin_config_get = tegra_io_pad_pinconf_get, 1677 .pin_config_set = tegra_io_pad_pinconf_set, 1678 .is_generic = true, 1679 }; 1680 1681 static struct pinctrl_desc tegra_pmc_pctl_desc = { 1682 .pctlops = &tegra_io_pad_pinctrl_ops, 1683 .confops = &tegra_io_pad_pinconf_ops, 1684 }; 1685 1686 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 1687 { 1688 int err; 1689 1690 if (!pmc->soc->num_pin_descs) 1691 return 0; 1692 1693 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 1694 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 1695 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 1696 1697 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 1698 pmc); 1699 if (IS_ERR(pmc->pctl_dev)) { 1700 err = PTR_ERR(pmc->pctl_dev); 1701 dev_err(pmc->dev, "failed to register pin controller: %d\n", 1702 err); 1703 return err; 1704 } 1705 1706 return 0; 1707 } 1708 1709 static ssize_t reset_reason_show(struct device *dev, 1710 struct device_attribute *attr, char *buf) 1711 { 1712 u32 value, rst_src; 1713 1714 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 1715 rst_src = (value & pmc->soc->regs->rst_source_mask) >> 1716 pmc->soc->regs->rst_source_shift; 1717 1718 return sprintf(buf, "%s\n", pmc->soc->reset_sources[rst_src]); 1719 } 1720 1721 static DEVICE_ATTR_RO(reset_reason); 1722 1723 static ssize_t reset_level_show(struct device *dev, 1724 struct device_attribute *attr, char *buf) 1725 { 1726 u32 value, rst_lvl; 1727 1728 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 1729 rst_lvl = (value & pmc->soc->regs->rst_level_mask) >> 1730 pmc->soc->regs->rst_level_shift; 1731 1732 return sprintf(buf, "%s\n", pmc->soc->reset_levels[rst_lvl]); 1733 } 1734 1735 static DEVICE_ATTR_RO(reset_level); 1736 1737 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 1738 { 1739 struct device *dev = pmc->dev; 1740 int err = 0; 1741 1742 if (pmc->soc->reset_sources) { 1743 err = device_create_file(dev, &dev_attr_reset_reason); 1744 if (err < 0) 1745 dev_warn(dev, 1746 "failed to create attr \"reset_reason\": %d\n", 1747 err); 1748 } 1749 1750 if (pmc->soc->reset_levels) { 1751 err = device_create_file(dev, &dev_attr_reset_level); 1752 if (err < 0) 1753 dev_warn(dev, 1754 "failed to create attr \"reset_level\": %d\n", 1755 err); 1756 } 1757 } 1758 1759 static int tegra_pmc_irq_translate(struct irq_domain *domain, 1760 struct irq_fwspec *fwspec, 1761 unsigned long *hwirq, 1762 unsigned int *type) 1763 { 1764 if (WARN_ON(fwspec->param_count < 2)) 1765 return -EINVAL; 1766 1767 *hwirq = fwspec->param[0]; 1768 *type = fwspec->param[1]; 1769 1770 return 0; 1771 } 1772 1773 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 1774 unsigned int num_irqs, void *data) 1775 { 1776 struct tegra_pmc *pmc = domain->host_data; 1777 const struct tegra_pmc_soc *soc = pmc->soc; 1778 struct irq_fwspec *fwspec = data; 1779 unsigned int i; 1780 int err = 0; 1781 1782 for (i = 0; i < soc->num_wake_events; i++) { 1783 const struct tegra_wake_event *event = &soc->wake_events[i]; 1784 1785 if (fwspec->param_count == 2) { 1786 struct irq_fwspec spec; 1787 1788 if (event->id != fwspec->param[0]) 1789 continue; 1790 1791 err = irq_domain_set_hwirq_and_chip(domain, virq, 1792 event->id, 1793 &pmc->irq, pmc); 1794 if (err < 0) 1795 break; 1796 1797 spec.fwnode = &pmc->dev->of_node->fwnode; 1798 spec.param_count = 3; 1799 spec.param[0] = GIC_SPI; 1800 spec.param[1] = event->irq; 1801 spec.param[2] = fwspec->param[1]; 1802 1803 err = irq_domain_alloc_irqs_parent(domain, virq, 1804 num_irqs, &spec); 1805 1806 break; 1807 } 1808 1809 if (fwspec->param_count == 3) { 1810 if (event->gpio.instance != fwspec->param[0] || 1811 event->gpio.pin != fwspec->param[1]) 1812 continue; 1813 1814 err = irq_domain_set_hwirq_and_chip(domain, virq, 1815 event->id, 1816 &pmc->irq, pmc); 1817 1818 break; 1819 } 1820 } 1821 1822 if (i == soc->num_wake_events) 1823 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX, 1824 &pmc->irq, pmc); 1825 1826 return err; 1827 } 1828 1829 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 1830 .translate = tegra_pmc_irq_translate, 1831 .alloc = tegra_pmc_irq_alloc, 1832 }; 1833 1834 static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 1835 { 1836 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 1837 unsigned int offset, bit; 1838 u32 value; 1839 1840 offset = data->hwirq / 32; 1841 bit = data->hwirq % 32; 1842 1843 /* clear wake status */ 1844 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 1845 1846 /* route wake to tier 2 */ 1847 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 1848 1849 if (!on) 1850 value &= ~(1 << bit); 1851 else 1852 value |= 1 << bit; 1853 1854 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 1855 1856 /* enable wakeup event */ 1857 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 1858 1859 return 0; 1860 } 1861 1862 static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) 1863 { 1864 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 1865 u32 value; 1866 1867 if (data->hwirq == ULONG_MAX) 1868 return 0; 1869 1870 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 1871 1872 switch (type) { 1873 case IRQ_TYPE_EDGE_RISING: 1874 case IRQ_TYPE_LEVEL_HIGH: 1875 value |= WAKE_AOWAKE_CNTRL_LEVEL; 1876 break; 1877 1878 case IRQ_TYPE_EDGE_FALLING: 1879 case IRQ_TYPE_LEVEL_LOW: 1880 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 1881 break; 1882 1883 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 1884 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 1885 break; 1886 1887 default: 1888 return -EINVAL; 1889 } 1890 1891 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 1892 1893 return 0; 1894 } 1895 1896 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 1897 { 1898 struct irq_domain *parent = NULL; 1899 struct device_node *np; 1900 1901 np = of_irq_find_parent(pmc->dev->of_node); 1902 if (np) { 1903 parent = irq_find_host(np); 1904 of_node_put(np); 1905 } 1906 1907 if (!parent) 1908 return 0; 1909 1910 pmc->irq.name = dev_name(pmc->dev); 1911 pmc->irq.irq_mask = irq_chip_mask_parent; 1912 pmc->irq.irq_unmask = irq_chip_unmask_parent; 1913 pmc->irq.irq_eoi = irq_chip_eoi_parent; 1914 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; 1915 pmc->irq.irq_set_type = tegra_pmc_irq_set_type; 1916 pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; 1917 1918 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, 1919 &tegra_pmc_irq_domain_ops, pmc); 1920 if (!pmc->domain) { 1921 dev_err(pmc->dev, "failed to allocate domain\n"); 1922 return -ENOMEM; 1923 } 1924 1925 return 0; 1926 } 1927 1928 static int tegra_pmc_probe(struct platform_device *pdev) 1929 { 1930 void __iomem *base; 1931 struct resource *res; 1932 int err; 1933 1934 /* 1935 * Early initialisation should have configured an initial 1936 * register mapping and setup the soc data pointer. If these 1937 * are not valid then something went badly wrong! 1938 */ 1939 if (WARN_ON(!pmc->base || !pmc->soc)) 1940 return -ENODEV; 1941 1942 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1943 if (err < 0) 1944 return err; 1945 1946 /* take over the memory region from the early initialization */ 1947 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1948 base = devm_ioremap_resource(&pdev->dev, res); 1949 if (IS_ERR(base)) 1950 return PTR_ERR(base); 1951 1952 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1953 if (res) { 1954 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1955 if (IS_ERR(pmc->wake)) 1956 return PTR_ERR(pmc->wake); 1957 } else { 1958 pmc->wake = base; 1959 } 1960 1961 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1962 if (res) { 1963 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1964 if (IS_ERR(pmc->aotag)) 1965 return PTR_ERR(pmc->aotag); 1966 } else { 1967 pmc->aotag = base; 1968 } 1969 1970 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1971 if (res) { 1972 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1973 if (IS_ERR(pmc->scratch)) 1974 return PTR_ERR(pmc->scratch); 1975 } else { 1976 pmc->scratch = base; 1977 } 1978 1979 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1980 if (IS_ERR(pmc->clk)) { 1981 err = PTR_ERR(pmc->clk); 1982 1983 if (err != -ENOENT) { 1984 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1985 return err; 1986 } 1987 1988 pmc->clk = NULL; 1989 } 1990 1991 pmc->dev = &pdev->dev; 1992 1993 tegra_pmc_init(pmc); 1994 1995 tegra_pmc_init_tsense_reset(pmc); 1996 1997 tegra_pmc_reset_sysfs_init(pmc); 1998 1999 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2000 err = tegra_powergate_debugfs_init(); 2001 if (err < 0) 2002 return err; 2003 } 2004 2005 err = register_restart_handler(&tegra_pmc_restart_handler); 2006 if (err) { 2007 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 2008 err); 2009 goto cleanup_debugfs; 2010 } 2011 2012 err = tegra_pmc_pinctrl_init(pmc); 2013 if (err) 2014 goto cleanup_restart_handler; 2015 2016 err = tegra_pmc_irq_init(pmc); 2017 if (err < 0) 2018 goto cleanup_restart_handler; 2019 2020 mutex_lock(&pmc->powergates_lock); 2021 iounmap(pmc->base); 2022 pmc->base = base; 2023 mutex_unlock(&pmc->powergates_lock); 2024 2025 platform_set_drvdata(pdev, pmc); 2026 2027 return 0; 2028 2029 cleanup_restart_handler: 2030 unregister_restart_handler(&tegra_pmc_restart_handler); 2031 cleanup_debugfs: 2032 debugfs_remove(pmc->debugfs); 2033 return err; 2034 } 2035 2036 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2037 static int tegra_pmc_suspend(struct device *dev) 2038 { 2039 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2040 2041 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 2042 2043 return 0; 2044 } 2045 2046 static int tegra_pmc_resume(struct device *dev) 2047 { 2048 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2049 2050 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 2051 2052 return 0; 2053 } 2054 2055 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 2056 2057 #endif 2058 2059 static const char * const tegra20_powergates[] = { 2060 [TEGRA_POWERGATE_CPU] = "cpu", 2061 [TEGRA_POWERGATE_3D] = "3d", 2062 [TEGRA_POWERGATE_VENC] = "venc", 2063 [TEGRA_POWERGATE_VDEC] = "vdec", 2064 [TEGRA_POWERGATE_PCIE] = "pcie", 2065 [TEGRA_POWERGATE_L2] = "l2", 2066 [TEGRA_POWERGATE_MPE] = "mpe", 2067 }; 2068 2069 static const struct tegra_pmc_regs tegra20_pmc_regs = { 2070 .scratch0 = 0x50, 2071 .dpd_req = 0x1b8, 2072 .dpd_status = 0x1bc, 2073 .dpd2_req = 0x1c0, 2074 .dpd2_status = 0x1c4, 2075 .rst_status = 0x1b4, 2076 .rst_source_shift = 0x0, 2077 .rst_source_mask = 0x7, 2078 .rst_level_shift = 0x0, 2079 .rst_level_mask = 0x0, 2080 }; 2081 2082 static void tegra20_pmc_init(struct tegra_pmc *pmc) 2083 { 2084 u32 value; 2085 2086 /* Always enable CPU power request */ 2087 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2088 value |= PMC_CNTRL_CPU_PWRREQ_OE; 2089 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2090 2091 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2092 2093 if (pmc->sysclkreq_high) 2094 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 2095 else 2096 value |= PMC_CNTRL_SYSCLK_POLARITY; 2097 2098 /* configure the output polarity while the request is tristated */ 2099 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2100 2101 /* now enable the request */ 2102 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2103 value |= PMC_CNTRL_SYSCLK_OE; 2104 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2105 } 2106 2107 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2108 struct device_node *np, 2109 bool invert) 2110 { 2111 u32 value; 2112 2113 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2114 2115 if (invert) 2116 value |= PMC_CNTRL_INTR_POLARITY; 2117 else 2118 value &= ~PMC_CNTRL_INTR_POLARITY; 2119 2120 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2121 } 2122 2123 static const struct tegra_pmc_soc tegra20_pmc_soc = { 2124 .num_powergates = ARRAY_SIZE(tegra20_powergates), 2125 .powergates = tegra20_powergates, 2126 .num_cpu_powergates = 0, 2127 .cpu_powergates = NULL, 2128 .has_tsense_reset = false, 2129 .has_gpu_clamps = false, 2130 .needs_mbist_war = false, 2131 .has_impl_33v_pwr = false, 2132 .maybe_tz_only = false, 2133 .num_io_pads = 0, 2134 .io_pads = NULL, 2135 .num_pin_descs = 0, 2136 .pin_descs = NULL, 2137 .regs = &tegra20_pmc_regs, 2138 .init = tegra20_pmc_init, 2139 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2140 .reset_sources = NULL, 2141 .num_reset_sources = 0, 2142 .reset_levels = NULL, 2143 .num_reset_levels = 0, 2144 }; 2145 2146 static const char * const tegra30_powergates[] = { 2147 [TEGRA_POWERGATE_CPU] = "cpu0", 2148 [TEGRA_POWERGATE_3D] = "3d0", 2149 [TEGRA_POWERGATE_VENC] = "venc", 2150 [TEGRA_POWERGATE_VDEC] = "vdec", 2151 [TEGRA_POWERGATE_PCIE] = "pcie", 2152 [TEGRA_POWERGATE_L2] = "l2", 2153 [TEGRA_POWERGATE_MPE] = "mpe", 2154 [TEGRA_POWERGATE_HEG] = "heg", 2155 [TEGRA_POWERGATE_SATA] = "sata", 2156 [TEGRA_POWERGATE_CPU1] = "cpu1", 2157 [TEGRA_POWERGATE_CPU2] = "cpu2", 2158 [TEGRA_POWERGATE_CPU3] = "cpu3", 2159 [TEGRA_POWERGATE_CELP] = "celp", 2160 [TEGRA_POWERGATE_3D1] = "3d1", 2161 }; 2162 2163 static const u8 tegra30_cpu_powergates[] = { 2164 TEGRA_POWERGATE_CPU, 2165 TEGRA_POWERGATE_CPU1, 2166 TEGRA_POWERGATE_CPU2, 2167 TEGRA_POWERGATE_CPU3, 2168 }; 2169 2170 static const struct tegra_pmc_soc tegra30_pmc_soc = { 2171 .num_powergates = ARRAY_SIZE(tegra30_powergates), 2172 .powergates = tegra30_powergates, 2173 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 2174 .cpu_powergates = tegra30_cpu_powergates, 2175 .has_tsense_reset = true, 2176 .has_gpu_clamps = false, 2177 .needs_mbist_war = false, 2178 .has_impl_33v_pwr = false, 2179 .maybe_tz_only = false, 2180 .num_io_pads = 0, 2181 .io_pads = NULL, 2182 .num_pin_descs = 0, 2183 .pin_descs = NULL, 2184 .regs = &tegra20_pmc_regs, 2185 .init = tegra20_pmc_init, 2186 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2187 .reset_sources = tegra30_reset_sources, 2188 .num_reset_sources = 5, 2189 .reset_levels = NULL, 2190 .num_reset_levels = 0, 2191 }; 2192 2193 static const char * const tegra114_powergates[] = { 2194 [TEGRA_POWERGATE_CPU] = "crail", 2195 [TEGRA_POWERGATE_3D] = "3d", 2196 [TEGRA_POWERGATE_VENC] = "venc", 2197 [TEGRA_POWERGATE_VDEC] = "vdec", 2198 [TEGRA_POWERGATE_MPE] = "mpe", 2199 [TEGRA_POWERGATE_HEG] = "heg", 2200 [TEGRA_POWERGATE_CPU1] = "cpu1", 2201 [TEGRA_POWERGATE_CPU2] = "cpu2", 2202 [TEGRA_POWERGATE_CPU3] = "cpu3", 2203 [TEGRA_POWERGATE_CELP] = "celp", 2204 [TEGRA_POWERGATE_CPU0] = "cpu0", 2205 [TEGRA_POWERGATE_C0NC] = "c0nc", 2206 [TEGRA_POWERGATE_C1NC] = "c1nc", 2207 [TEGRA_POWERGATE_DIS] = "dis", 2208 [TEGRA_POWERGATE_DISB] = "disb", 2209 [TEGRA_POWERGATE_XUSBA] = "xusba", 2210 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2211 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2212 }; 2213 2214 static const u8 tegra114_cpu_powergates[] = { 2215 TEGRA_POWERGATE_CPU0, 2216 TEGRA_POWERGATE_CPU1, 2217 TEGRA_POWERGATE_CPU2, 2218 TEGRA_POWERGATE_CPU3, 2219 }; 2220 2221 static const struct tegra_pmc_soc tegra114_pmc_soc = { 2222 .num_powergates = ARRAY_SIZE(tegra114_powergates), 2223 .powergates = tegra114_powergates, 2224 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 2225 .cpu_powergates = tegra114_cpu_powergates, 2226 .has_tsense_reset = true, 2227 .has_gpu_clamps = false, 2228 .needs_mbist_war = false, 2229 .has_impl_33v_pwr = false, 2230 .maybe_tz_only = false, 2231 .num_io_pads = 0, 2232 .io_pads = NULL, 2233 .num_pin_descs = 0, 2234 .pin_descs = NULL, 2235 .regs = &tegra20_pmc_regs, 2236 .init = tegra20_pmc_init, 2237 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2238 .reset_sources = tegra30_reset_sources, 2239 .num_reset_sources = 5, 2240 .reset_levels = NULL, 2241 .num_reset_levels = 0, 2242 }; 2243 2244 static const char * const tegra124_powergates[] = { 2245 [TEGRA_POWERGATE_CPU] = "crail", 2246 [TEGRA_POWERGATE_3D] = "3d", 2247 [TEGRA_POWERGATE_VENC] = "venc", 2248 [TEGRA_POWERGATE_PCIE] = "pcie", 2249 [TEGRA_POWERGATE_VDEC] = "vdec", 2250 [TEGRA_POWERGATE_MPE] = "mpe", 2251 [TEGRA_POWERGATE_HEG] = "heg", 2252 [TEGRA_POWERGATE_SATA] = "sata", 2253 [TEGRA_POWERGATE_CPU1] = "cpu1", 2254 [TEGRA_POWERGATE_CPU2] = "cpu2", 2255 [TEGRA_POWERGATE_CPU3] = "cpu3", 2256 [TEGRA_POWERGATE_CELP] = "celp", 2257 [TEGRA_POWERGATE_CPU0] = "cpu0", 2258 [TEGRA_POWERGATE_C0NC] = "c0nc", 2259 [TEGRA_POWERGATE_C1NC] = "c1nc", 2260 [TEGRA_POWERGATE_SOR] = "sor", 2261 [TEGRA_POWERGATE_DIS] = "dis", 2262 [TEGRA_POWERGATE_DISB] = "disb", 2263 [TEGRA_POWERGATE_XUSBA] = "xusba", 2264 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2265 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2266 [TEGRA_POWERGATE_VIC] = "vic", 2267 [TEGRA_POWERGATE_IRAM] = "iram", 2268 }; 2269 2270 static const u8 tegra124_cpu_powergates[] = { 2271 TEGRA_POWERGATE_CPU0, 2272 TEGRA_POWERGATE_CPU1, 2273 TEGRA_POWERGATE_CPU2, 2274 TEGRA_POWERGATE_CPU3, 2275 }; 2276 2277 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 2278 ((struct tegra_io_pad_soc) { \ 2279 .id = (_id), \ 2280 .dpd = (_dpd), \ 2281 .voltage = (_voltage), \ 2282 .name = (_name), \ 2283 }) 2284 2285 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 2286 ((struct pinctrl_pin_desc) { \ 2287 .number = (_id), \ 2288 .name = (_name) \ 2289 }) 2290 2291 #define TEGRA124_IO_PAD_TABLE(_pad) \ 2292 /* .id .dpd .voltage .name */ \ 2293 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2294 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 2295 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 2296 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 2297 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2298 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 2299 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 2300 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2301 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 2302 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 2303 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 2304 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 2305 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2306 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 2307 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 2308 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2309 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 2310 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 2311 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 2312 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2313 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2314 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 2315 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 2316 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 2317 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 2318 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2319 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2320 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2321 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2322 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 2323 2324 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 2325 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 2326 }; 2327 2328 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 2329 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2330 }; 2331 2332 static const struct tegra_pmc_soc tegra124_pmc_soc = { 2333 .num_powergates = ARRAY_SIZE(tegra124_powergates), 2334 .powergates = tegra124_powergates, 2335 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 2336 .cpu_powergates = tegra124_cpu_powergates, 2337 .has_tsense_reset = true, 2338 .has_gpu_clamps = true, 2339 .needs_mbist_war = false, 2340 .has_impl_33v_pwr = false, 2341 .maybe_tz_only = false, 2342 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 2343 .io_pads = tegra124_io_pads, 2344 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 2345 .pin_descs = tegra124_pin_descs, 2346 .regs = &tegra20_pmc_regs, 2347 .init = tegra20_pmc_init, 2348 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2349 .reset_sources = tegra30_reset_sources, 2350 .num_reset_sources = 5, 2351 .reset_levels = NULL, 2352 .num_reset_levels = 0, 2353 }; 2354 2355 static const char * const tegra210_powergates[] = { 2356 [TEGRA_POWERGATE_CPU] = "crail", 2357 [TEGRA_POWERGATE_3D] = "3d", 2358 [TEGRA_POWERGATE_VENC] = "venc", 2359 [TEGRA_POWERGATE_PCIE] = "pcie", 2360 [TEGRA_POWERGATE_MPE] = "mpe", 2361 [TEGRA_POWERGATE_SATA] = "sata", 2362 [TEGRA_POWERGATE_CPU1] = "cpu1", 2363 [TEGRA_POWERGATE_CPU2] = "cpu2", 2364 [TEGRA_POWERGATE_CPU3] = "cpu3", 2365 [TEGRA_POWERGATE_CPU0] = "cpu0", 2366 [TEGRA_POWERGATE_C0NC] = "c0nc", 2367 [TEGRA_POWERGATE_SOR] = "sor", 2368 [TEGRA_POWERGATE_DIS] = "dis", 2369 [TEGRA_POWERGATE_DISB] = "disb", 2370 [TEGRA_POWERGATE_XUSBA] = "xusba", 2371 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2372 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2373 [TEGRA_POWERGATE_VIC] = "vic", 2374 [TEGRA_POWERGATE_IRAM] = "iram", 2375 [TEGRA_POWERGATE_NVDEC] = "nvdec", 2376 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 2377 [TEGRA_POWERGATE_AUD] = "aud", 2378 [TEGRA_POWERGATE_DFD] = "dfd", 2379 [TEGRA_POWERGATE_VE2] = "ve2", 2380 }; 2381 2382 static const u8 tegra210_cpu_powergates[] = { 2383 TEGRA_POWERGATE_CPU0, 2384 TEGRA_POWERGATE_CPU1, 2385 TEGRA_POWERGATE_CPU2, 2386 TEGRA_POWERGATE_CPU3, 2387 }; 2388 2389 #define TEGRA210_IO_PAD_TABLE(_pad) \ 2390 /* .id .dpd .voltage .name */ \ 2391 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 2392 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 2393 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 2394 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2395 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2396 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 2397 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 2398 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 2399 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 2400 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 2401 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 2402 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 2403 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 2404 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2405 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 2406 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 2407 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 2408 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 2409 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 2410 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 2411 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 2412 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2413 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 2414 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2415 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 2416 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 2417 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2418 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 2419 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 2420 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 2421 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 2422 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 2423 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 2424 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2425 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2426 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2427 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 2428 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 2429 2430 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 2431 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 2432 }; 2433 2434 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 2435 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2436 }; 2437 2438 static const struct tegra_pmc_soc tegra210_pmc_soc = { 2439 .num_powergates = ARRAY_SIZE(tegra210_powergates), 2440 .powergates = tegra210_powergates, 2441 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 2442 .cpu_powergates = tegra210_cpu_powergates, 2443 .has_tsense_reset = true, 2444 .has_gpu_clamps = true, 2445 .needs_mbist_war = true, 2446 .has_impl_33v_pwr = false, 2447 .maybe_tz_only = true, 2448 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 2449 .io_pads = tegra210_io_pads, 2450 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 2451 .pin_descs = tegra210_pin_descs, 2452 .regs = &tegra20_pmc_regs, 2453 .init = tegra20_pmc_init, 2454 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2455 .reset_sources = tegra30_reset_sources, 2456 .num_reset_sources = 5, 2457 .reset_levels = NULL, 2458 .num_reset_levels = 0, 2459 }; 2460 2461 #define TEGRA186_IO_PAD_TABLE(_pad) \ 2462 /* .id .dpd .voltage .name */ \ 2463 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2464 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2465 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2466 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2467 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 2468 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 2469 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2470 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 2471 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2472 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2473 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2474 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 2475 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2476 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2477 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2478 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 2479 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 2480 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 2481 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2482 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 2483 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 2484 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 2485 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 2486 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 2487 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 2488 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 2489 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 2490 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 2491 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 2492 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 2493 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 2494 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 2495 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 2496 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 2497 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 2498 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 2499 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 2500 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 2501 2502 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 2503 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 2504 }; 2505 2506 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 2507 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2508 }; 2509 2510 static const struct tegra_pmc_regs tegra186_pmc_regs = { 2511 .scratch0 = 0x2000, 2512 .dpd_req = 0x74, 2513 .dpd_status = 0x78, 2514 .dpd2_req = 0x7c, 2515 .dpd2_status = 0x80, 2516 .rst_status = 0x70, 2517 .rst_source_shift = 0x2, 2518 .rst_source_mask = 0x3C, 2519 .rst_level_shift = 0x0, 2520 .rst_level_mask = 0x3, 2521 }; 2522 2523 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2524 struct device_node *np, 2525 bool invert) 2526 { 2527 struct resource regs; 2528 void __iomem *wake; 2529 u32 value; 2530 int index; 2531 2532 index = of_property_match_string(np, "reg-names", "wake"); 2533 if (index < 0) { 2534 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 2535 return; 2536 } 2537 2538 of_address_to_resource(np, index, ®s); 2539 2540 wake = ioremap_nocache(regs.start, resource_size(®s)); 2541 if (!wake) { 2542 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 2543 return; 2544 } 2545 2546 value = readl(wake + WAKE_AOWAKE_CTRL); 2547 2548 if (invert) 2549 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 2550 else 2551 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 2552 2553 writel(value, wake + WAKE_AOWAKE_CTRL); 2554 2555 iounmap(wake); 2556 } 2557 2558 static const struct tegra_wake_event tegra186_wake_events[] = { 2559 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 2560 TEGRA_WAKE_IRQ("rtc", 73, 10), 2561 }; 2562 2563 static const struct tegra_pmc_soc tegra186_pmc_soc = { 2564 .num_powergates = 0, 2565 .powergates = NULL, 2566 .num_cpu_powergates = 0, 2567 .cpu_powergates = NULL, 2568 .has_tsense_reset = false, 2569 .has_gpu_clamps = false, 2570 .needs_mbist_war = false, 2571 .has_impl_33v_pwr = true, 2572 .maybe_tz_only = false, 2573 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 2574 .io_pads = tegra186_io_pads, 2575 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 2576 .pin_descs = tegra186_pin_descs, 2577 .regs = &tegra186_pmc_regs, 2578 .init = NULL, 2579 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 2580 .reset_sources = tegra186_reset_sources, 2581 .num_reset_sources = 14, 2582 .reset_levels = tegra186_reset_levels, 2583 .num_reset_levels = 3, 2584 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 2585 .wake_events = tegra186_wake_events, 2586 }; 2587 2588 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 2589 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 2590 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 2591 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 2592 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, 2593 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, 2594 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 2595 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, 2596 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX }, 2597 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX }, 2598 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX }, 2599 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX }, 2600 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX }, 2601 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 2602 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX }, 2603 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX }, 2604 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 2605 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX }, 2606 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX }, 2607 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX }, 2608 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX }, 2609 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX }, 2610 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX }, 2611 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX }, 2612 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, 2613 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX }, 2614 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX }, 2615 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, 2616 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, 2617 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 2618 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX }, 2619 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX }, 2620 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX }, 2621 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, 2622 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX }, 2623 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, 2624 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, 2625 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, 2626 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, 2627 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, 2628 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, 2629 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX }, 2630 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX }, 2631 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, 2632 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, 2633 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, 2634 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, 2635 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, 2636 }; 2637 2638 static const struct tegra_wake_event tegra194_wake_events[] = { 2639 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 2640 TEGRA_WAKE_IRQ("rtc", 73, 10), 2641 }; 2642 2643 static const struct tegra_pmc_soc tegra194_pmc_soc = { 2644 .num_powergates = 0, 2645 .powergates = NULL, 2646 .num_cpu_powergates = 0, 2647 .cpu_powergates = NULL, 2648 .has_tsense_reset = false, 2649 .has_gpu_clamps = false, 2650 .needs_mbist_war = false, 2651 .has_impl_33v_pwr = false, 2652 .maybe_tz_only = false, 2653 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 2654 .io_pads = tegra194_io_pads, 2655 .regs = &tegra186_pmc_regs, 2656 .init = NULL, 2657 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 2658 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 2659 .wake_events = tegra194_wake_events, 2660 }; 2661 2662 static const struct of_device_id tegra_pmc_match[] = { 2663 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 2664 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 2665 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 2666 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 2667 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 2668 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 2669 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 2670 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 2671 { } 2672 }; 2673 2674 static struct platform_driver tegra_pmc_driver = { 2675 .driver = { 2676 .name = "tegra-pmc", 2677 .suppress_bind_attrs = true, 2678 .of_match_table = tegra_pmc_match, 2679 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2680 .pm = &tegra_pmc_pm_ops, 2681 #endif 2682 }, 2683 .probe = tegra_pmc_probe, 2684 }; 2685 builtin_platform_driver(tegra_pmc_driver); 2686 2687 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 2688 { 2689 u32 value, saved; 2690 2691 saved = readl(pmc->base + pmc->soc->regs->scratch0); 2692 value = saved ^ 0xffffffff; 2693 2694 if (value == 0xffffffff) 2695 value = 0xdeadbeef; 2696 2697 /* write pattern and read it back */ 2698 writel(value, pmc->base + pmc->soc->regs->scratch0); 2699 value = readl(pmc->base + pmc->soc->regs->scratch0); 2700 2701 /* if we read all-zeroes, access is restricted to TZ only */ 2702 if (value == 0) { 2703 pr_info("access to PMC is restricted to TZ\n"); 2704 return true; 2705 } 2706 2707 /* restore original value */ 2708 writel(saved, pmc->base + pmc->soc->regs->scratch0); 2709 2710 return false; 2711 } 2712 2713 /* 2714 * Early initialization to allow access to registers in the very early boot 2715 * process. 2716 */ 2717 static int __init tegra_pmc_early_init(void) 2718 { 2719 const struct of_device_id *match; 2720 struct device_node *np; 2721 struct resource regs; 2722 bool invert; 2723 2724 mutex_init(&pmc->powergates_lock); 2725 2726 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 2727 if (!np) { 2728 /* 2729 * Fall back to legacy initialization for 32-bit ARM only. All 2730 * 64-bit ARM device tree files for Tegra are required to have 2731 * a PMC node. 2732 * 2733 * This is for backwards-compatibility with old device trees 2734 * that didn't contain a PMC node. Note that in this case the 2735 * SoC data can't be matched and therefore powergating is 2736 * disabled. 2737 */ 2738 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2739 pr_warn("DT node not found, powergating disabled\n"); 2740 2741 regs.start = 0x7000e400; 2742 regs.end = 0x7000e7ff; 2743 regs.flags = IORESOURCE_MEM; 2744 2745 pr_warn("Using memory region %pR\n", ®s); 2746 } else { 2747 /* 2748 * At this point we're not running on Tegra, so play 2749 * nice with multi-platform kernels. 2750 */ 2751 return 0; 2752 } 2753 } else { 2754 /* 2755 * Extract information from the device tree if we've found a 2756 * matching node. 2757 */ 2758 if (of_address_to_resource(np, 0, ®s) < 0) { 2759 pr_err("failed to get PMC registers\n"); 2760 of_node_put(np); 2761 return -ENXIO; 2762 } 2763 } 2764 2765 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 2766 if (!pmc->base) { 2767 pr_err("failed to map PMC registers\n"); 2768 of_node_put(np); 2769 return -ENXIO; 2770 } 2771 2772 if (np) { 2773 pmc->soc = match->data; 2774 2775 if (pmc->soc->maybe_tz_only) 2776 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 2777 2778 tegra_powergate_init(pmc, np); 2779 2780 /* 2781 * Invert the interrupt polarity if a PMC device tree node 2782 * exists and contains the nvidia,invert-interrupt property. 2783 */ 2784 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 2785 2786 pmc->soc->setup_irq_polarity(pmc, np, invert); 2787 2788 of_node_put(np); 2789 } 2790 2791 return 0; 2792 } 2793 early_initcall(tegra_pmc_early_init); 2794