1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #define pr_fmt(fmt) "tegra-pmc: " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/clk/tegra.h> 25 #include <linux/debugfs.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/export.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_clk.h> 35 #include <linux/of_platform.h> 36 #include <linux/platform_device.h> 37 #include <linux/pm_domain.h> 38 #include <linux/reboot.h> 39 #include <linux/reset.h> 40 #include <linux/seq_file.h> 41 #include <linux/slab.h> 42 #include <linux/spinlock.h> 43 44 #include <soc/tegra/common.h> 45 #include <soc/tegra/fuse.h> 46 #include <soc/tegra/pmc.h> 47 48 #define PMC_CNTRL 0x0 49 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 50 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 51 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 52 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 53 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 54 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 55 #define PMC_CNTRL_MAIN_RST BIT(4) 56 57 #define DPD_SAMPLE 0x020 58 #define DPD_SAMPLE_ENABLE BIT(0) 59 #define DPD_SAMPLE_DISABLE (0 << 0) 60 61 #define PWRGATE_TOGGLE 0x30 62 #define PWRGATE_TOGGLE_START BIT(8) 63 64 #define REMOVE_CLAMPING 0x34 65 66 #define PWRGATE_STATUS 0x38 67 68 #define PMC_PWR_DET 0x48 69 70 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 71 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 72 #define PMC_SCRATCH0_MODE_RCM BIT(1) 73 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 74 PMC_SCRATCH0_MODE_BOOTLOADER | \ 75 PMC_SCRATCH0_MODE_RCM) 76 77 #define PMC_CPUPWRGOOD_TIMER 0xc8 78 #define PMC_CPUPWROFF_TIMER 0xcc 79 80 #define PMC_PWR_DET_VALUE 0xe4 81 82 #define PMC_SCRATCH41 0x140 83 84 #define PMC_SENSOR_CTRL 0x1b0 85 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 86 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 87 88 #define PMC_RST_STATUS 0x1b4 89 #define PMC_RST_STATUS_POR 0 90 #define PMC_RST_STATUS_WATCHDOG 1 91 #define PMC_RST_STATUS_SENSOR 2 92 #define PMC_RST_STATUS_SW_MAIN 3 93 #define PMC_RST_STATUS_LP0 4 94 #define PMC_RST_STATUS_AOTAG 5 95 96 #define IO_DPD_REQ 0x1b8 97 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 98 #define IO_DPD_REQ_CODE_OFF (1U << 30) 99 #define IO_DPD_REQ_CODE_ON (2U << 30) 100 #define IO_DPD_REQ_CODE_MASK (3U << 30) 101 102 #define IO_DPD_STATUS 0x1bc 103 #define IO_DPD2_REQ 0x1c0 104 #define IO_DPD2_STATUS 0x1c4 105 #define SEL_DPD_TIM 0x1c8 106 107 #define PMC_SCRATCH54 0x258 108 #define PMC_SCRATCH54_DATA_SHIFT 8 109 #define PMC_SCRATCH54_ADDR_SHIFT 0 110 111 #define PMC_SCRATCH55 0x25c 112 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 113 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 114 #define PMC_SCRATCH55_PINMUX_SHIFT 24 115 #define PMC_SCRATCH55_16BITOP BIT(15) 116 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 117 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 118 119 #define GPU_RG_CNTRL 0x2d4 120 121 /* Tegra186 and later */ 122 #define WAKE_AOWAKE_CTRL 0x4f4 123 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 124 125 struct tegra_powergate { 126 struct generic_pm_domain genpd; 127 struct tegra_pmc *pmc; 128 unsigned int id; 129 struct clk **clks; 130 unsigned int num_clks; 131 struct reset_control *reset; 132 }; 133 134 struct tegra_io_pad_soc { 135 enum tegra_io_pad id; 136 unsigned int dpd; 137 unsigned int voltage; 138 }; 139 140 struct tegra_pmc_regs { 141 unsigned int scratch0; 142 unsigned int dpd_req; 143 unsigned int dpd_status; 144 unsigned int dpd2_req; 145 unsigned int dpd2_status; 146 }; 147 148 struct tegra_pmc_soc { 149 unsigned int num_powergates; 150 const char *const *powergates; 151 unsigned int num_cpu_powergates; 152 const u8 *cpu_powergates; 153 154 bool has_tsense_reset; 155 bool has_gpu_clamps; 156 bool needs_mbist_war; 157 158 const struct tegra_io_pad_soc *io_pads; 159 unsigned int num_io_pads; 160 161 const struct tegra_pmc_regs *regs; 162 void (*init)(struct tegra_pmc *pmc); 163 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 164 struct device_node *np, 165 bool invert); 166 }; 167 168 /** 169 * struct tegra_pmc - NVIDIA Tegra PMC 170 * @dev: pointer to PMC device structure 171 * @base: pointer to I/O remapped register region 172 * @clk: pointer to pclk clock 173 * @soc: pointer to SoC data structure 174 * @debugfs: pointer to debugfs entry 175 * @rate: currently configured rate of pclk 176 * @suspend_mode: lowest suspend mode available 177 * @cpu_good_time: CPU power good time (in microseconds) 178 * @cpu_off_time: CPU power off time (in microsecends) 179 * @core_osc_time: core power good OSC time (in microseconds) 180 * @core_pmu_time: core power good PMU time (in microseconds) 181 * @core_off_time: core power off time (in microseconds) 182 * @corereq_high: core power request is active-high 183 * @sysclkreq_high: system clock request is active-high 184 * @combined_req: combined power request for CPU & core 185 * @cpu_pwr_good_en: CPU power good signal is enabled 186 * @lp0_vec_phys: physical base address of the LP0 warm boot code 187 * @lp0_vec_size: size of the LP0 warm boot code 188 * @powergates_available: Bitmap of available power gates 189 * @powergates_lock: mutex for power gate register access 190 */ 191 struct tegra_pmc { 192 struct device *dev; 193 void __iomem *base; 194 void __iomem *wake; 195 void __iomem *aotag; 196 void __iomem *scratch; 197 struct clk *clk; 198 struct dentry *debugfs; 199 200 const struct tegra_pmc_soc *soc; 201 202 unsigned long rate; 203 204 enum tegra_suspend_mode suspend_mode; 205 u32 cpu_good_time; 206 u32 cpu_off_time; 207 u32 core_osc_time; 208 u32 core_pmu_time; 209 u32 core_off_time; 210 bool corereq_high; 211 bool sysclkreq_high; 212 bool combined_req; 213 bool cpu_pwr_good_en; 214 u32 lp0_vec_phys; 215 u32 lp0_vec_size; 216 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 217 218 struct mutex powergates_lock; 219 }; 220 221 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 222 .base = NULL, 223 .suspend_mode = TEGRA_SUSPEND_NONE, 224 }; 225 226 static inline struct tegra_powergate * 227 to_powergate(struct generic_pm_domain *domain) 228 { 229 return container_of(domain, struct tegra_powergate, genpd); 230 } 231 232 static u32 tegra_pmc_readl(unsigned long offset) 233 { 234 return readl(pmc->base + offset); 235 } 236 237 static void tegra_pmc_writel(u32 value, unsigned long offset) 238 { 239 writel(value, pmc->base + offset); 240 } 241 242 static inline bool tegra_powergate_state(int id) 243 { 244 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 245 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 246 else 247 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 248 } 249 250 static inline bool tegra_powergate_is_valid(int id) 251 { 252 return (pmc->soc && pmc->soc->powergates[id]); 253 } 254 255 static inline bool tegra_powergate_is_available(int id) 256 { 257 return test_bit(id, pmc->powergates_available); 258 } 259 260 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 261 { 262 unsigned int i; 263 264 if (!pmc || !pmc->soc || !name) 265 return -EINVAL; 266 267 for (i = 0; i < pmc->soc->num_powergates; i++) { 268 if (!tegra_powergate_is_valid(i)) 269 continue; 270 271 if (!strcmp(name, pmc->soc->powergates[i])) 272 return i; 273 } 274 275 return -ENODEV; 276 } 277 278 /** 279 * tegra_powergate_set() - set the state of a partition 280 * @id: partition ID 281 * @new_state: new state of the partition 282 */ 283 static int tegra_powergate_set(unsigned int id, bool new_state) 284 { 285 bool status; 286 int err; 287 288 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 289 return -EINVAL; 290 291 mutex_lock(&pmc->powergates_lock); 292 293 if (tegra_powergate_state(id) == new_state) { 294 mutex_unlock(&pmc->powergates_lock); 295 return 0; 296 } 297 298 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 299 300 err = readx_poll_timeout(tegra_powergate_state, id, status, 301 status == new_state, 10, 100000); 302 303 mutex_unlock(&pmc->powergates_lock); 304 305 return err; 306 } 307 308 static int __tegra_powergate_remove_clamping(unsigned int id) 309 { 310 u32 mask; 311 312 mutex_lock(&pmc->powergates_lock); 313 314 /* 315 * On Tegra124 and later, the clamps for the GPU are controlled by a 316 * separate register (with different semantics). 317 */ 318 if (id == TEGRA_POWERGATE_3D) { 319 if (pmc->soc->has_gpu_clamps) { 320 tegra_pmc_writel(0, GPU_RG_CNTRL); 321 goto out; 322 } 323 } 324 325 /* 326 * Tegra 2 has a bug where PCIE and VDE clamping masks are 327 * swapped relatively to the partition ids 328 */ 329 if (id == TEGRA_POWERGATE_VDEC) 330 mask = (1 << TEGRA_POWERGATE_PCIE); 331 else if (id == TEGRA_POWERGATE_PCIE) 332 mask = (1 << TEGRA_POWERGATE_VDEC); 333 else 334 mask = (1 << id); 335 336 tegra_pmc_writel(mask, REMOVE_CLAMPING); 337 338 out: 339 mutex_unlock(&pmc->powergates_lock); 340 341 return 0; 342 } 343 344 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 345 { 346 unsigned int i; 347 348 for (i = 0; i < pg->num_clks; i++) 349 clk_disable_unprepare(pg->clks[i]); 350 } 351 352 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 353 { 354 unsigned int i; 355 int err; 356 357 for (i = 0; i < pg->num_clks; i++) { 358 err = clk_prepare_enable(pg->clks[i]); 359 if (err) 360 goto out; 361 } 362 363 return 0; 364 365 out: 366 while (i--) 367 clk_disable_unprepare(pg->clks[i]); 368 369 return err; 370 } 371 372 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 373 { 374 return 0; 375 } 376 377 static int tegra_powergate_power_up(struct tegra_powergate *pg, 378 bool disable_clocks) 379 { 380 int err; 381 382 err = reset_control_assert(pg->reset); 383 if (err) 384 return err; 385 386 usleep_range(10, 20); 387 388 err = tegra_powergate_set(pg->id, true); 389 if (err < 0) 390 return err; 391 392 usleep_range(10, 20); 393 394 err = tegra_powergate_enable_clocks(pg); 395 if (err) 396 goto disable_clks; 397 398 usleep_range(10, 20); 399 400 err = __tegra_powergate_remove_clamping(pg->id); 401 if (err) 402 goto disable_clks; 403 404 usleep_range(10, 20); 405 406 err = reset_control_deassert(pg->reset); 407 if (err) 408 goto powergate_off; 409 410 usleep_range(10, 20); 411 412 if (pg->pmc->soc->needs_mbist_war) 413 err = tegra210_clk_handle_mbist_war(pg->id); 414 if (err) 415 goto disable_clks; 416 417 if (disable_clocks) 418 tegra_powergate_disable_clocks(pg); 419 420 return 0; 421 422 disable_clks: 423 tegra_powergate_disable_clocks(pg); 424 usleep_range(10, 20); 425 426 powergate_off: 427 tegra_powergate_set(pg->id, false); 428 429 return err; 430 } 431 432 static int tegra_powergate_power_down(struct tegra_powergate *pg) 433 { 434 int err; 435 436 err = tegra_powergate_enable_clocks(pg); 437 if (err) 438 return err; 439 440 usleep_range(10, 20); 441 442 err = reset_control_assert(pg->reset); 443 if (err) 444 goto disable_clks; 445 446 usleep_range(10, 20); 447 448 tegra_powergate_disable_clocks(pg); 449 450 usleep_range(10, 20); 451 452 err = tegra_powergate_set(pg->id, false); 453 if (err) 454 goto assert_resets; 455 456 return 0; 457 458 assert_resets: 459 tegra_powergate_enable_clocks(pg); 460 usleep_range(10, 20); 461 reset_control_deassert(pg->reset); 462 usleep_range(10, 20); 463 464 disable_clks: 465 tegra_powergate_disable_clocks(pg); 466 467 return err; 468 } 469 470 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 471 { 472 struct tegra_powergate *pg = to_powergate(domain); 473 int err; 474 475 err = tegra_powergate_power_up(pg, true); 476 if (err) 477 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, 478 err); 479 480 return err; 481 } 482 483 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 484 { 485 struct tegra_powergate *pg = to_powergate(domain); 486 int err; 487 488 err = tegra_powergate_power_down(pg); 489 if (err) 490 pr_err("failed to turn off PM domain %s: %d\n", 491 pg->genpd.name, err); 492 493 return err; 494 } 495 496 /** 497 * tegra_powergate_power_on() - power on partition 498 * @id: partition ID 499 */ 500 int tegra_powergate_power_on(unsigned int id) 501 { 502 if (!tegra_powergate_is_available(id)) 503 return -EINVAL; 504 505 return tegra_powergate_set(id, true); 506 } 507 508 /** 509 * tegra_powergate_power_off() - power off partition 510 * @id: partition ID 511 */ 512 int tegra_powergate_power_off(unsigned int id) 513 { 514 if (!tegra_powergate_is_available(id)) 515 return -EINVAL; 516 517 return tegra_powergate_set(id, false); 518 } 519 EXPORT_SYMBOL(tegra_powergate_power_off); 520 521 /** 522 * tegra_powergate_is_powered() - check if partition is powered 523 * @id: partition ID 524 */ 525 int tegra_powergate_is_powered(unsigned int id) 526 { 527 int status; 528 529 if (!tegra_powergate_is_valid(id)) 530 return -EINVAL; 531 532 mutex_lock(&pmc->powergates_lock); 533 status = tegra_powergate_state(id); 534 mutex_unlock(&pmc->powergates_lock); 535 536 return status; 537 } 538 539 /** 540 * tegra_powergate_remove_clamping() - remove power clamps for partition 541 * @id: partition ID 542 */ 543 int tegra_powergate_remove_clamping(unsigned int id) 544 { 545 if (!tegra_powergate_is_available(id)) 546 return -EINVAL; 547 548 return __tegra_powergate_remove_clamping(id); 549 } 550 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 551 552 /** 553 * tegra_powergate_sequence_power_up() - power up partition 554 * @id: partition ID 555 * @clk: clock for partition 556 * @rst: reset for partition 557 * 558 * Must be called with clk disabled, and returns with clk enabled. 559 */ 560 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 561 struct reset_control *rst) 562 { 563 struct tegra_powergate *pg; 564 int err; 565 566 if (!tegra_powergate_is_available(id)) 567 return -EINVAL; 568 569 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 570 if (!pg) 571 return -ENOMEM; 572 573 pg->id = id; 574 pg->clks = &clk; 575 pg->num_clks = 1; 576 pg->reset = rst; 577 pg->pmc = pmc; 578 579 err = tegra_powergate_power_up(pg, false); 580 if (err) 581 pr_err("failed to turn on partition %d: %d\n", id, err); 582 583 kfree(pg); 584 585 return err; 586 } 587 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 588 589 #ifdef CONFIG_SMP 590 /** 591 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 592 * @cpuid: CPU partition ID 593 * 594 * Returns the partition ID corresponding to the CPU partition ID or a 595 * negative error code on failure. 596 */ 597 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 598 { 599 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 600 return pmc->soc->cpu_powergates[cpuid]; 601 602 return -EINVAL; 603 } 604 605 /** 606 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 607 * @cpuid: CPU partition ID 608 */ 609 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 610 { 611 int id; 612 613 id = tegra_get_cpu_powergate_id(cpuid); 614 if (id < 0) 615 return false; 616 617 return tegra_powergate_is_powered(id); 618 } 619 620 /** 621 * tegra_pmc_cpu_power_on() - power on CPU partition 622 * @cpuid: CPU partition ID 623 */ 624 int tegra_pmc_cpu_power_on(unsigned int cpuid) 625 { 626 int id; 627 628 id = tegra_get_cpu_powergate_id(cpuid); 629 if (id < 0) 630 return id; 631 632 return tegra_powergate_set(id, true); 633 } 634 635 /** 636 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 637 * @cpuid: CPU partition ID 638 */ 639 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 640 { 641 int id; 642 643 id = tegra_get_cpu_powergate_id(cpuid); 644 if (id < 0) 645 return id; 646 647 return tegra_powergate_remove_clamping(id); 648 } 649 #endif /* CONFIG_SMP */ 650 651 static int tegra_pmc_restart_notify(struct notifier_block *this, 652 unsigned long action, void *data) 653 { 654 const char *cmd = data; 655 u32 value; 656 657 value = readl(pmc->scratch + pmc->soc->regs->scratch0); 658 value &= ~PMC_SCRATCH0_MODE_MASK; 659 660 if (cmd) { 661 if (strcmp(cmd, "recovery") == 0) 662 value |= PMC_SCRATCH0_MODE_RECOVERY; 663 664 if (strcmp(cmd, "bootloader") == 0) 665 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 666 667 if (strcmp(cmd, "forced-recovery") == 0) 668 value |= PMC_SCRATCH0_MODE_RCM; 669 } 670 671 writel(value, pmc->scratch + pmc->soc->regs->scratch0); 672 673 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 674 value = tegra_pmc_readl(PMC_CNTRL); 675 value |= PMC_CNTRL_MAIN_RST; 676 tegra_pmc_writel(value, PMC_CNTRL); 677 678 return NOTIFY_DONE; 679 } 680 681 static struct notifier_block tegra_pmc_restart_handler = { 682 .notifier_call = tegra_pmc_restart_notify, 683 .priority = 128, 684 }; 685 686 static int powergate_show(struct seq_file *s, void *data) 687 { 688 unsigned int i; 689 int status; 690 691 seq_printf(s, " powergate powered\n"); 692 seq_printf(s, "------------------\n"); 693 694 for (i = 0; i < pmc->soc->num_powergates; i++) { 695 status = tegra_powergate_is_powered(i); 696 if (status < 0) 697 continue; 698 699 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 700 status ? "yes" : "no"); 701 } 702 703 return 0; 704 } 705 706 static int powergate_open(struct inode *inode, struct file *file) 707 { 708 return single_open(file, powergate_show, inode->i_private); 709 } 710 711 static const struct file_operations powergate_fops = { 712 .open = powergate_open, 713 .read = seq_read, 714 .llseek = seq_lseek, 715 .release = single_release, 716 }; 717 718 static int tegra_powergate_debugfs_init(void) 719 { 720 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 721 &powergate_fops); 722 if (!pmc->debugfs) 723 return -ENOMEM; 724 725 return 0; 726 } 727 728 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 729 struct device_node *np) 730 { 731 struct clk *clk; 732 unsigned int i, count; 733 int err; 734 735 count = of_clk_get_parent_count(np); 736 if (count == 0) 737 return -ENODEV; 738 739 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 740 if (!pg->clks) 741 return -ENOMEM; 742 743 for (i = 0; i < count; i++) { 744 pg->clks[i] = of_clk_get(np, i); 745 if (IS_ERR(pg->clks[i])) { 746 err = PTR_ERR(pg->clks[i]); 747 goto err; 748 } 749 } 750 751 pg->num_clks = count; 752 753 return 0; 754 755 err: 756 while (i--) 757 clk_put(pg->clks[i]); 758 759 kfree(pg->clks); 760 761 return err; 762 } 763 764 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 765 struct device_node *np, bool off) 766 { 767 int err; 768 769 pg->reset = of_reset_control_array_get_exclusive(np); 770 if (IS_ERR(pg->reset)) { 771 err = PTR_ERR(pg->reset); 772 pr_err("failed to get device resets: %d\n", err); 773 return err; 774 } 775 776 if (off) 777 err = reset_control_assert(pg->reset); 778 else 779 err = reset_control_deassert(pg->reset); 780 781 if (err) 782 reset_control_put(pg->reset); 783 784 return err; 785 } 786 787 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 788 { 789 struct tegra_powergate *pg; 790 int id, err; 791 bool off; 792 793 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 794 if (!pg) 795 return; 796 797 id = tegra_powergate_lookup(pmc, np->name); 798 if (id < 0) { 799 pr_err("powergate lookup failed for %s: %d\n", np->name, id); 800 goto free_mem; 801 } 802 803 /* 804 * Clear the bit for this powergate so it cannot be managed 805 * directly via the legacy APIs for controlling powergates. 806 */ 807 clear_bit(id, pmc->powergates_available); 808 809 pg->id = id; 810 pg->genpd.name = np->name; 811 pg->genpd.power_off = tegra_genpd_power_off; 812 pg->genpd.power_on = tegra_genpd_power_on; 813 pg->pmc = pmc; 814 815 off = !tegra_powergate_is_powered(pg->id); 816 817 err = tegra_powergate_of_get_clks(pg, np); 818 if (err < 0) { 819 pr_err("failed to get clocks for %s: %d\n", np->name, err); 820 goto set_available; 821 } 822 823 err = tegra_powergate_of_get_resets(pg, np, off); 824 if (err < 0) { 825 pr_err("failed to get resets for %s: %d\n", np->name, err); 826 goto remove_clks; 827 } 828 829 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 830 if (off) 831 WARN_ON(tegra_powergate_power_up(pg, true)); 832 833 goto remove_resets; 834 } 835 836 /* 837 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB 838 * host and super-speed partitions. Once the XHCI driver 839 * manages the partitions itself this code can be removed. Note 840 * that we don't register these partitions with the genpd core 841 * to avoid it from powering down the partitions as they appear 842 * to be unused. 843 */ 844 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && 845 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) { 846 if (off) 847 WARN_ON(tegra_powergate_power_up(pg, true)); 848 849 goto remove_resets; 850 } 851 852 err = pm_genpd_init(&pg->genpd, NULL, off); 853 if (err < 0) { 854 pr_err("failed to initialise PM domain %s: %d\n", np->name, 855 err); 856 goto remove_resets; 857 } 858 859 err = of_genpd_add_provider_simple(np, &pg->genpd); 860 if (err < 0) { 861 pr_err("failed to add PM domain provider for %s: %d\n", 862 np->name, err); 863 goto remove_genpd; 864 } 865 866 pr_debug("added PM domain %s\n", pg->genpd.name); 867 868 return; 869 870 remove_genpd: 871 pm_genpd_remove(&pg->genpd); 872 873 remove_resets: 874 reset_control_put(pg->reset); 875 876 remove_clks: 877 while (pg->num_clks--) 878 clk_put(pg->clks[pg->num_clks]); 879 880 kfree(pg->clks); 881 882 set_available: 883 set_bit(id, pmc->powergates_available); 884 885 free_mem: 886 kfree(pg); 887 } 888 889 static void tegra_powergate_init(struct tegra_pmc *pmc, 890 struct device_node *parent) 891 { 892 struct device_node *np, *child; 893 unsigned int i; 894 895 /* Create a bitmap of the available and valid partitions */ 896 for (i = 0; i < pmc->soc->num_powergates; i++) 897 if (pmc->soc->powergates[i]) 898 set_bit(i, pmc->powergates_available); 899 900 np = of_get_child_by_name(parent, "powergates"); 901 if (!np) 902 return; 903 904 for_each_child_of_node(np, child) 905 tegra_powergate_add(pmc, child); 906 907 of_node_put(np); 908 } 909 910 static const struct tegra_io_pad_soc * 911 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 912 { 913 unsigned int i; 914 915 for (i = 0; i < pmc->soc->num_io_pads; i++) 916 if (pmc->soc->io_pads[i].id == id) 917 return &pmc->soc->io_pads[i]; 918 919 return NULL; 920 } 921 922 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 923 unsigned long *status, u32 *mask) 924 { 925 const struct tegra_io_pad_soc *pad; 926 unsigned long rate, value; 927 928 pad = tegra_io_pad_find(pmc, id); 929 if (!pad) { 930 pr_err("invalid I/O pad ID %u\n", id); 931 return -ENOENT; 932 } 933 934 if (pad->dpd == UINT_MAX) 935 return -ENOTSUPP; 936 937 *mask = BIT(pad->dpd % 32); 938 939 if (pad->dpd < 32) { 940 *status = pmc->soc->regs->dpd_status; 941 *request = pmc->soc->regs->dpd_req; 942 } else { 943 *status = pmc->soc->regs->dpd2_status; 944 *request = pmc->soc->regs->dpd2_req; 945 } 946 947 if (pmc->clk) { 948 rate = clk_get_rate(pmc->clk); 949 if (!rate) { 950 pr_err("failed to get clock rate\n"); 951 return -ENODEV; 952 } 953 954 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 955 956 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 957 value = DIV_ROUND_UP(1000000000, rate); 958 value = DIV_ROUND_UP(200, value); 959 tegra_pmc_writel(value, SEL_DPD_TIM); 960 } 961 962 return 0; 963 } 964 965 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 966 u32 val, unsigned long timeout) 967 { 968 u32 value; 969 970 timeout = jiffies + msecs_to_jiffies(timeout); 971 972 while (time_after(timeout, jiffies)) { 973 value = tegra_pmc_readl(offset); 974 if ((value & mask) == val) 975 return 0; 976 977 usleep_range(250, 1000); 978 } 979 980 return -ETIMEDOUT; 981 } 982 983 static void tegra_io_pad_unprepare(void) 984 { 985 if (pmc->clk) 986 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 987 } 988 989 /** 990 * tegra_io_pad_power_enable() - enable power to I/O pad 991 * @id: Tegra I/O pad ID for which to enable power 992 * 993 * Returns: 0 on success or a negative error code on failure. 994 */ 995 int tegra_io_pad_power_enable(enum tegra_io_pad id) 996 { 997 unsigned long request, status; 998 u32 mask; 999 int err; 1000 1001 mutex_lock(&pmc->powergates_lock); 1002 1003 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1004 if (err < 0) { 1005 pr_err("failed to prepare I/O pad: %d\n", err); 1006 goto unlock; 1007 } 1008 1009 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); 1010 1011 err = tegra_io_pad_poll(status, mask, 0, 250); 1012 if (err < 0) { 1013 pr_err("failed to enable I/O pad: %d\n", err); 1014 goto unlock; 1015 } 1016 1017 tegra_io_pad_unprepare(); 1018 1019 unlock: 1020 mutex_unlock(&pmc->powergates_lock); 1021 return err; 1022 } 1023 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1024 1025 /** 1026 * tegra_io_pad_power_disable() - disable power to I/O pad 1027 * @id: Tegra I/O pad ID for which to disable power 1028 * 1029 * Returns: 0 on success or a negative error code on failure. 1030 */ 1031 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1032 { 1033 unsigned long request, status; 1034 u32 mask; 1035 int err; 1036 1037 mutex_lock(&pmc->powergates_lock); 1038 1039 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1040 if (err < 0) { 1041 pr_err("failed to prepare I/O pad: %d\n", err); 1042 goto unlock; 1043 } 1044 1045 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); 1046 1047 err = tegra_io_pad_poll(status, mask, mask, 250); 1048 if (err < 0) { 1049 pr_err("failed to disable I/O pad: %d\n", err); 1050 goto unlock; 1051 } 1052 1053 tegra_io_pad_unprepare(); 1054 1055 unlock: 1056 mutex_unlock(&pmc->powergates_lock); 1057 return err; 1058 } 1059 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1060 1061 int tegra_io_pad_set_voltage(enum tegra_io_pad id, 1062 enum tegra_io_pad_voltage voltage) 1063 { 1064 const struct tegra_io_pad_soc *pad; 1065 u32 value; 1066 1067 pad = tegra_io_pad_find(pmc, id); 1068 if (!pad) 1069 return -ENOENT; 1070 1071 if (pad->voltage == UINT_MAX) 1072 return -ENOTSUPP; 1073 1074 mutex_lock(&pmc->powergates_lock); 1075 1076 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1077 value = tegra_pmc_readl(PMC_PWR_DET); 1078 value |= BIT(pad->voltage); 1079 tegra_pmc_writel(value, PMC_PWR_DET); 1080 1081 /* update I/O voltage */ 1082 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1083 1084 if (voltage == TEGRA_IO_PAD_1800000UV) 1085 value &= ~BIT(pad->voltage); 1086 else 1087 value |= BIT(pad->voltage); 1088 1089 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1090 1091 mutex_unlock(&pmc->powergates_lock); 1092 1093 usleep_range(100, 250); 1094 1095 return 0; 1096 } 1097 EXPORT_SYMBOL(tegra_io_pad_set_voltage); 1098 1099 int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1100 { 1101 const struct tegra_io_pad_soc *pad; 1102 u32 value; 1103 1104 pad = tegra_io_pad_find(pmc, id); 1105 if (!pad) 1106 return -ENOENT; 1107 1108 if (pad->voltage == UINT_MAX) 1109 return -ENOTSUPP; 1110 1111 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1112 1113 if ((value & BIT(pad->voltage)) == 0) 1114 return TEGRA_IO_PAD_1800000UV; 1115 1116 return TEGRA_IO_PAD_3300000UV; 1117 } 1118 EXPORT_SYMBOL(tegra_io_pad_get_voltage); 1119 1120 /** 1121 * tegra_io_rail_power_on() - enable power to I/O rail 1122 * @id: Tegra I/O pad ID for which to enable power 1123 * 1124 * See also: tegra_io_pad_power_enable() 1125 */ 1126 int tegra_io_rail_power_on(unsigned int id) 1127 { 1128 return tegra_io_pad_power_enable(id); 1129 } 1130 EXPORT_SYMBOL(tegra_io_rail_power_on); 1131 1132 /** 1133 * tegra_io_rail_power_off() - disable power to I/O rail 1134 * @id: Tegra I/O pad ID for which to disable power 1135 * 1136 * See also: tegra_io_pad_power_disable() 1137 */ 1138 int tegra_io_rail_power_off(unsigned int id) 1139 { 1140 return tegra_io_pad_power_disable(id); 1141 } 1142 EXPORT_SYMBOL(tegra_io_rail_power_off); 1143 1144 #ifdef CONFIG_PM_SLEEP 1145 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1146 { 1147 return pmc->suspend_mode; 1148 } 1149 1150 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1151 { 1152 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1153 return; 1154 1155 pmc->suspend_mode = mode; 1156 } 1157 1158 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1159 { 1160 unsigned long long rate = 0; 1161 u32 value; 1162 1163 switch (mode) { 1164 case TEGRA_SUSPEND_LP1: 1165 rate = 32768; 1166 break; 1167 1168 case TEGRA_SUSPEND_LP2: 1169 rate = clk_get_rate(pmc->clk); 1170 break; 1171 1172 default: 1173 break; 1174 } 1175 1176 if (WARN_ON_ONCE(rate == 0)) 1177 rate = 100000000; 1178 1179 if (rate != pmc->rate) { 1180 u64 ticks; 1181 1182 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1183 do_div(ticks, USEC_PER_SEC); 1184 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1185 1186 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1187 do_div(ticks, USEC_PER_SEC); 1188 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1189 1190 wmb(); 1191 1192 pmc->rate = rate; 1193 } 1194 1195 value = tegra_pmc_readl(PMC_CNTRL); 1196 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1197 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1198 tegra_pmc_writel(value, PMC_CNTRL); 1199 } 1200 #endif 1201 1202 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1203 { 1204 u32 value, values[2]; 1205 1206 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1207 } else { 1208 switch (value) { 1209 case 0: 1210 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1211 break; 1212 1213 case 1: 1214 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1215 break; 1216 1217 case 2: 1218 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1219 break; 1220 1221 default: 1222 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1223 break; 1224 } 1225 } 1226 1227 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1228 1229 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1230 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1231 1232 pmc->cpu_good_time = value; 1233 1234 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1235 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1236 1237 pmc->cpu_off_time = value; 1238 1239 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1240 values, ARRAY_SIZE(values))) 1241 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1242 1243 pmc->core_osc_time = values[0]; 1244 pmc->core_pmu_time = values[1]; 1245 1246 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1247 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1248 1249 pmc->core_off_time = value; 1250 1251 pmc->corereq_high = of_property_read_bool(np, 1252 "nvidia,core-power-req-active-high"); 1253 1254 pmc->sysclkreq_high = of_property_read_bool(np, 1255 "nvidia,sys-clock-req-active-high"); 1256 1257 pmc->combined_req = of_property_read_bool(np, 1258 "nvidia,combined-power-req"); 1259 1260 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1261 "nvidia,cpu-pwr-good-en"); 1262 1263 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1264 ARRAY_SIZE(values))) 1265 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1266 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1267 1268 pmc->lp0_vec_phys = values[0]; 1269 pmc->lp0_vec_size = values[1]; 1270 1271 return 0; 1272 } 1273 1274 static void tegra_pmc_init(struct tegra_pmc *pmc) 1275 { 1276 if (pmc->soc->init) 1277 pmc->soc->init(pmc); 1278 } 1279 1280 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1281 { 1282 static const char disabled[] = "emergency thermal reset disabled"; 1283 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1284 struct device *dev = pmc->dev; 1285 struct device_node *np; 1286 u32 value, checksum; 1287 1288 if (!pmc->soc->has_tsense_reset) 1289 return; 1290 1291 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1292 if (!np) { 1293 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1294 return; 1295 } 1296 1297 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1298 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1299 goto out; 1300 } 1301 1302 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1303 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1304 goto out; 1305 } 1306 1307 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1308 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1309 goto out; 1310 } 1311 1312 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1313 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1314 goto out; 1315 } 1316 1317 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1318 pinmux = 0; 1319 1320 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1321 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1322 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1323 1324 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1325 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1326 tegra_pmc_writel(value, PMC_SCRATCH54); 1327 1328 value = PMC_SCRATCH55_RESET_TEGRA; 1329 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1330 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1331 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1332 1333 /* 1334 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1335 * contain the checksum and are currently zero, so they are not added. 1336 */ 1337 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1338 + ((value >> 24) & 0xff); 1339 checksum &= 0xff; 1340 checksum = 0x100 - checksum; 1341 1342 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1343 1344 tegra_pmc_writel(value, PMC_SCRATCH55); 1345 1346 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1347 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1348 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1349 1350 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1351 1352 out: 1353 of_node_put(np); 1354 } 1355 1356 static int tegra_pmc_probe(struct platform_device *pdev) 1357 { 1358 void __iomem *base; 1359 struct resource *res; 1360 int err; 1361 1362 /* 1363 * Early initialisation should have configured an initial 1364 * register mapping and setup the soc data pointer. If these 1365 * are not valid then something went badly wrong! 1366 */ 1367 if (WARN_ON(!pmc->base || !pmc->soc)) 1368 return -ENODEV; 1369 1370 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1371 if (err < 0) 1372 return err; 1373 1374 /* take over the memory region from the early initialization */ 1375 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1376 base = devm_ioremap_resource(&pdev->dev, res); 1377 if (IS_ERR(base)) 1378 return PTR_ERR(base); 1379 1380 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1381 if (res) { 1382 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1383 if (IS_ERR(pmc->wake)) 1384 return PTR_ERR(pmc->wake); 1385 } else { 1386 pmc->wake = base; 1387 } 1388 1389 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1390 if (res) { 1391 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1392 if (IS_ERR(pmc->aotag)) 1393 return PTR_ERR(pmc->aotag); 1394 } else { 1395 pmc->aotag = base; 1396 } 1397 1398 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1399 if (res) { 1400 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1401 if (IS_ERR(pmc->scratch)) 1402 return PTR_ERR(pmc->scratch); 1403 } else { 1404 pmc->scratch = base; 1405 } 1406 1407 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1408 if (IS_ERR(pmc->clk)) { 1409 err = PTR_ERR(pmc->clk); 1410 1411 if (err != -ENOENT) { 1412 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1413 return err; 1414 } 1415 1416 pmc->clk = NULL; 1417 } 1418 1419 pmc->dev = &pdev->dev; 1420 1421 tegra_pmc_init(pmc); 1422 1423 tegra_pmc_init_tsense_reset(pmc); 1424 1425 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1426 err = tegra_powergate_debugfs_init(); 1427 if (err < 0) 1428 return err; 1429 } 1430 1431 err = register_restart_handler(&tegra_pmc_restart_handler); 1432 if (err) { 1433 debugfs_remove(pmc->debugfs); 1434 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1435 err); 1436 return err; 1437 } 1438 1439 mutex_lock(&pmc->powergates_lock); 1440 iounmap(pmc->base); 1441 pmc->base = base; 1442 mutex_unlock(&pmc->powergates_lock); 1443 1444 return 0; 1445 } 1446 1447 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1448 static int tegra_pmc_suspend(struct device *dev) 1449 { 1450 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1451 1452 return 0; 1453 } 1454 1455 static int tegra_pmc_resume(struct device *dev) 1456 { 1457 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1458 1459 return 0; 1460 } 1461 1462 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1463 1464 #endif 1465 1466 static const char * const tegra20_powergates[] = { 1467 [TEGRA_POWERGATE_CPU] = "cpu", 1468 [TEGRA_POWERGATE_3D] = "3d", 1469 [TEGRA_POWERGATE_VENC] = "venc", 1470 [TEGRA_POWERGATE_VDEC] = "vdec", 1471 [TEGRA_POWERGATE_PCIE] = "pcie", 1472 [TEGRA_POWERGATE_L2] = "l2", 1473 [TEGRA_POWERGATE_MPE] = "mpe", 1474 }; 1475 1476 static const struct tegra_pmc_regs tegra20_pmc_regs = { 1477 .scratch0 = 0x50, 1478 .dpd_req = 0x1b8, 1479 .dpd_status = 0x1bc, 1480 .dpd2_req = 0x1c0, 1481 .dpd2_status = 0x1c4, 1482 }; 1483 1484 static void tegra20_pmc_init(struct tegra_pmc *pmc) 1485 { 1486 u32 value; 1487 1488 /* Always enable CPU power request */ 1489 value = tegra_pmc_readl(PMC_CNTRL); 1490 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1491 tegra_pmc_writel(value, PMC_CNTRL); 1492 1493 value = tegra_pmc_readl(PMC_CNTRL); 1494 1495 if (pmc->sysclkreq_high) 1496 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1497 else 1498 value |= PMC_CNTRL_SYSCLK_POLARITY; 1499 1500 /* configure the output polarity while the request is tristated */ 1501 tegra_pmc_writel(value, PMC_CNTRL); 1502 1503 /* now enable the request */ 1504 value = tegra_pmc_readl(PMC_CNTRL); 1505 value |= PMC_CNTRL_SYSCLK_OE; 1506 tegra_pmc_writel(value, PMC_CNTRL); 1507 } 1508 1509 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1510 struct device_node *np, 1511 bool invert) 1512 { 1513 u32 value; 1514 1515 value = tegra_pmc_readl(PMC_CNTRL); 1516 1517 if (invert) 1518 value |= PMC_CNTRL_INTR_POLARITY; 1519 else 1520 value &= ~PMC_CNTRL_INTR_POLARITY; 1521 1522 tegra_pmc_writel(value, PMC_CNTRL); 1523 } 1524 1525 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1526 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1527 .powergates = tegra20_powergates, 1528 .num_cpu_powergates = 0, 1529 .cpu_powergates = NULL, 1530 .has_tsense_reset = false, 1531 .has_gpu_clamps = false, 1532 .num_io_pads = 0, 1533 .io_pads = NULL, 1534 .regs = &tegra20_pmc_regs, 1535 .init = tegra20_pmc_init, 1536 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1537 }; 1538 1539 static const char * const tegra30_powergates[] = { 1540 [TEGRA_POWERGATE_CPU] = "cpu0", 1541 [TEGRA_POWERGATE_3D] = "3d0", 1542 [TEGRA_POWERGATE_VENC] = "venc", 1543 [TEGRA_POWERGATE_VDEC] = "vdec", 1544 [TEGRA_POWERGATE_PCIE] = "pcie", 1545 [TEGRA_POWERGATE_L2] = "l2", 1546 [TEGRA_POWERGATE_MPE] = "mpe", 1547 [TEGRA_POWERGATE_HEG] = "heg", 1548 [TEGRA_POWERGATE_SATA] = "sata", 1549 [TEGRA_POWERGATE_CPU1] = "cpu1", 1550 [TEGRA_POWERGATE_CPU2] = "cpu2", 1551 [TEGRA_POWERGATE_CPU3] = "cpu3", 1552 [TEGRA_POWERGATE_CELP] = "celp", 1553 [TEGRA_POWERGATE_3D1] = "3d1", 1554 }; 1555 1556 static const u8 tegra30_cpu_powergates[] = { 1557 TEGRA_POWERGATE_CPU, 1558 TEGRA_POWERGATE_CPU1, 1559 TEGRA_POWERGATE_CPU2, 1560 TEGRA_POWERGATE_CPU3, 1561 }; 1562 1563 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1564 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1565 .powergates = tegra30_powergates, 1566 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1567 .cpu_powergates = tegra30_cpu_powergates, 1568 .has_tsense_reset = true, 1569 .has_gpu_clamps = false, 1570 .num_io_pads = 0, 1571 .io_pads = NULL, 1572 .regs = &tegra20_pmc_regs, 1573 .init = tegra20_pmc_init, 1574 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1575 }; 1576 1577 static const char * const tegra114_powergates[] = { 1578 [TEGRA_POWERGATE_CPU] = "crail", 1579 [TEGRA_POWERGATE_3D] = "3d", 1580 [TEGRA_POWERGATE_VENC] = "venc", 1581 [TEGRA_POWERGATE_VDEC] = "vdec", 1582 [TEGRA_POWERGATE_MPE] = "mpe", 1583 [TEGRA_POWERGATE_HEG] = "heg", 1584 [TEGRA_POWERGATE_CPU1] = "cpu1", 1585 [TEGRA_POWERGATE_CPU2] = "cpu2", 1586 [TEGRA_POWERGATE_CPU3] = "cpu3", 1587 [TEGRA_POWERGATE_CELP] = "celp", 1588 [TEGRA_POWERGATE_CPU0] = "cpu0", 1589 [TEGRA_POWERGATE_C0NC] = "c0nc", 1590 [TEGRA_POWERGATE_C1NC] = "c1nc", 1591 [TEGRA_POWERGATE_DIS] = "dis", 1592 [TEGRA_POWERGATE_DISB] = "disb", 1593 [TEGRA_POWERGATE_XUSBA] = "xusba", 1594 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1595 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1596 }; 1597 1598 static const u8 tegra114_cpu_powergates[] = { 1599 TEGRA_POWERGATE_CPU0, 1600 TEGRA_POWERGATE_CPU1, 1601 TEGRA_POWERGATE_CPU2, 1602 TEGRA_POWERGATE_CPU3, 1603 }; 1604 1605 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1606 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1607 .powergates = tegra114_powergates, 1608 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1609 .cpu_powergates = tegra114_cpu_powergates, 1610 .has_tsense_reset = true, 1611 .has_gpu_clamps = false, 1612 .num_io_pads = 0, 1613 .io_pads = NULL, 1614 .regs = &tegra20_pmc_regs, 1615 .init = tegra20_pmc_init, 1616 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1617 }; 1618 1619 static const char * const tegra124_powergates[] = { 1620 [TEGRA_POWERGATE_CPU] = "crail", 1621 [TEGRA_POWERGATE_3D] = "3d", 1622 [TEGRA_POWERGATE_VENC] = "venc", 1623 [TEGRA_POWERGATE_PCIE] = "pcie", 1624 [TEGRA_POWERGATE_VDEC] = "vdec", 1625 [TEGRA_POWERGATE_MPE] = "mpe", 1626 [TEGRA_POWERGATE_HEG] = "heg", 1627 [TEGRA_POWERGATE_SATA] = "sata", 1628 [TEGRA_POWERGATE_CPU1] = "cpu1", 1629 [TEGRA_POWERGATE_CPU2] = "cpu2", 1630 [TEGRA_POWERGATE_CPU3] = "cpu3", 1631 [TEGRA_POWERGATE_CELP] = "celp", 1632 [TEGRA_POWERGATE_CPU0] = "cpu0", 1633 [TEGRA_POWERGATE_C0NC] = "c0nc", 1634 [TEGRA_POWERGATE_C1NC] = "c1nc", 1635 [TEGRA_POWERGATE_SOR] = "sor", 1636 [TEGRA_POWERGATE_DIS] = "dis", 1637 [TEGRA_POWERGATE_DISB] = "disb", 1638 [TEGRA_POWERGATE_XUSBA] = "xusba", 1639 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1640 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1641 [TEGRA_POWERGATE_VIC] = "vic", 1642 [TEGRA_POWERGATE_IRAM] = "iram", 1643 }; 1644 1645 static const u8 tegra124_cpu_powergates[] = { 1646 TEGRA_POWERGATE_CPU0, 1647 TEGRA_POWERGATE_CPU1, 1648 TEGRA_POWERGATE_CPU2, 1649 TEGRA_POWERGATE_CPU3, 1650 }; 1651 1652 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 1653 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1654 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX }, 1655 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX }, 1656 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX }, 1657 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1658 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1659 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1660 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1661 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1662 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1663 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1664 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1665 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1666 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX }, 1667 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1668 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1669 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX }, 1670 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1671 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1672 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1673 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1674 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX }, 1675 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX }, 1676 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX }, 1677 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX }, 1678 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1679 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1680 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1681 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1682 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1683 }; 1684 1685 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1686 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1687 .powergates = tegra124_powergates, 1688 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1689 .cpu_powergates = tegra124_cpu_powergates, 1690 .has_tsense_reset = true, 1691 .has_gpu_clamps = true, 1692 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 1693 .io_pads = tegra124_io_pads, 1694 .regs = &tegra20_pmc_regs, 1695 .init = tegra20_pmc_init, 1696 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1697 }; 1698 1699 static const char * const tegra210_powergates[] = { 1700 [TEGRA_POWERGATE_CPU] = "crail", 1701 [TEGRA_POWERGATE_3D] = "3d", 1702 [TEGRA_POWERGATE_VENC] = "venc", 1703 [TEGRA_POWERGATE_PCIE] = "pcie", 1704 [TEGRA_POWERGATE_MPE] = "mpe", 1705 [TEGRA_POWERGATE_SATA] = "sata", 1706 [TEGRA_POWERGATE_CPU1] = "cpu1", 1707 [TEGRA_POWERGATE_CPU2] = "cpu2", 1708 [TEGRA_POWERGATE_CPU3] = "cpu3", 1709 [TEGRA_POWERGATE_CPU0] = "cpu0", 1710 [TEGRA_POWERGATE_C0NC] = "c0nc", 1711 [TEGRA_POWERGATE_SOR] = "sor", 1712 [TEGRA_POWERGATE_DIS] = "dis", 1713 [TEGRA_POWERGATE_DISB] = "disb", 1714 [TEGRA_POWERGATE_XUSBA] = "xusba", 1715 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1716 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1717 [TEGRA_POWERGATE_VIC] = "vic", 1718 [TEGRA_POWERGATE_IRAM] = "iram", 1719 [TEGRA_POWERGATE_NVDEC] = "nvdec", 1720 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 1721 [TEGRA_POWERGATE_AUD] = "aud", 1722 [TEGRA_POWERGATE_DFD] = "dfd", 1723 [TEGRA_POWERGATE_VE2] = "ve2", 1724 }; 1725 1726 static const u8 tegra210_cpu_powergates[] = { 1727 TEGRA_POWERGATE_CPU0, 1728 TEGRA_POWERGATE_CPU1, 1729 TEGRA_POWERGATE_CPU2, 1730 TEGRA_POWERGATE_CPU3, 1731 }; 1732 1733 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 1734 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 }, 1735 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 }, 1736 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 }, 1737 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1738 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1739 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX }, 1740 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX }, 1741 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1742 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX }, 1743 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 }, 1744 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX }, 1745 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 }, 1746 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX }, 1747 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1748 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1749 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1750 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1751 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX }, 1752 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX }, 1753 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 }, 1754 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1755 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1756 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1757 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1758 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1759 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1760 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1761 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 }, 1762 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 }, 1763 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 }, 1764 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 }, 1765 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 }, 1766 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 }, 1767 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1768 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1769 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1770 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX }, 1771 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1772 }; 1773 1774 static const struct tegra_pmc_soc tegra210_pmc_soc = { 1775 .num_powergates = ARRAY_SIZE(tegra210_powergates), 1776 .powergates = tegra210_powergates, 1777 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 1778 .cpu_powergates = tegra210_cpu_powergates, 1779 .has_tsense_reset = true, 1780 .has_gpu_clamps = true, 1781 .needs_mbist_war = true, 1782 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 1783 .io_pads = tegra210_io_pads, 1784 .regs = &tegra20_pmc_regs, 1785 .init = tegra20_pmc_init, 1786 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1787 }; 1788 1789 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 1790 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1791 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1792 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1793 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1794 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1795 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, 1796 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1797 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, 1798 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1799 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1800 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1801 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1802 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1803 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1804 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1805 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, 1806 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, 1807 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, 1808 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1809 { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = UINT_MAX }, 1810 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, 1811 { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX }, 1812 { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX }, 1813 { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX }, 1814 { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX }, 1815 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, 1816 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, 1817 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, 1818 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, 1819 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, 1820 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, 1821 { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = UINT_MAX }, 1822 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, 1823 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, 1824 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, 1825 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, 1826 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, 1827 }; 1828 1829 static const struct tegra_pmc_regs tegra186_pmc_regs = { 1830 .scratch0 = 0x2000, 1831 .dpd_req = 0x74, 1832 .dpd_status = 0x78, 1833 .dpd2_req = 0x7c, 1834 .dpd2_status = 0x80, 1835 }; 1836 1837 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1838 struct device_node *np, 1839 bool invert) 1840 { 1841 struct resource regs; 1842 void __iomem *wake; 1843 u32 value; 1844 int index; 1845 1846 index = of_property_match_string(np, "reg-names", "wake"); 1847 if (index < 0) { 1848 pr_err("failed to find PMC wake registers\n"); 1849 return; 1850 } 1851 1852 of_address_to_resource(np, index, ®s); 1853 1854 wake = ioremap_nocache(regs.start, resource_size(®s)); 1855 if (!wake) { 1856 pr_err("failed to map PMC wake registers\n"); 1857 return; 1858 } 1859 1860 value = readl(wake + WAKE_AOWAKE_CTRL); 1861 1862 if (invert) 1863 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 1864 else 1865 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 1866 1867 writel(value, wake + WAKE_AOWAKE_CTRL); 1868 1869 iounmap(wake); 1870 } 1871 1872 static const struct tegra_pmc_soc tegra186_pmc_soc = { 1873 .num_powergates = 0, 1874 .powergates = NULL, 1875 .num_cpu_powergates = 0, 1876 .cpu_powergates = NULL, 1877 .has_tsense_reset = false, 1878 .has_gpu_clamps = false, 1879 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 1880 .io_pads = tegra186_io_pads, 1881 .regs = &tegra186_pmc_regs, 1882 .init = NULL, 1883 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 1884 }; 1885 1886 static const struct of_device_id tegra_pmc_match[] = { 1887 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc }, 1888 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 1889 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 1890 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 1891 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 1892 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 1893 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 1894 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 1895 { } 1896 }; 1897 1898 static struct platform_driver tegra_pmc_driver = { 1899 .driver = { 1900 .name = "tegra-pmc", 1901 .suppress_bind_attrs = true, 1902 .of_match_table = tegra_pmc_match, 1903 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1904 .pm = &tegra_pmc_pm_ops, 1905 #endif 1906 }, 1907 .probe = tegra_pmc_probe, 1908 }; 1909 builtin_platform_driver(tegra_pmc_driver); 1910 1911 /* 1912 * Early initialization to allow access to registers in the very early boot 1913 * process. 1914 */ 1915 static int __init tegra_pmc_early_init(void) 1916 { 1917 const struct of_device_id *match; 1918 struct device_node *np; 1919 struct resource regs; 1920 bool invert; 1921 1922 mutex_init(&pmc->powergates_lock); 1923 1924 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 1925 if (!np) { 1926 /* 1927 * Fall back to legacy initialization for 32-bit ARM only. All 1928 * 64-bit ARM device tree files for Tegra are required to have 1929 * a PMC node. 1930 * 1931 * This is for backwards-compatibility with old device trees 1932 * that didn't contain a PMC node. Note that in this case the 1933 * SoC data can't be matched and therefore powergating is 1934 * disabled. 1935 */ 1936 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 1937 pr_warn("DT node not found, powergating disabled\n"); 1938 1939 regs.start = 0x7000e400; 1940 regs.end = 0x7000e7ff; 1941 regs.flags = IORESOURCE_MEM; 1942 1943 pr_warn("Using memory region %pR\n", ®s); 1944 } else { 1945 /* 1946 * At this point we're not running on Tegra, so play 1947 * nice with multi-platform kernels. 1948 */ 1949 return 0; 1950 } 1951 } else { 1952 /* 1953 * Extract information from the device tree if we've found a 1954 * matching node. 1955 */ 1956 if (of_address_to_resource(np, 0, ®s) < 0) { 1957 pr_err("failed to get PMC registers\n"); 1958 of_node_put(np); 1959 return -ENXIO; 1960 } 1961 } 1962 1963 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 1964 if (!pmc->base) { 1965 pr_err("failed to map PMC registers\n"); 1966 of_node_put(np); 1967 return -ENXIO; 1968 } 1969 1970 if (np) { 1971 pmc->soc = match->data; 1972 1973 tegra_powergate_init(pmc, np); 1974 1975 /* 1976 * Invert the interrupt polarity if a PMC device tree node 1977 * exists and contains the nvidia,invert-interrupt property. 1978 */ 1979 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 1980 1981 pmc->soc->setup_irq_polarity(pmc, np, invert); 1982 1983 of_node_put(np); 1984 } 1985 1986 return 0; 1987 } 1988 early_initcall(tegra_pmc_early_init); 1989