1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/io.h> 27 #include <linux/iopoll.h> 28 #include <linux/irqdomain.h> 29 #include <linux/irq.h> 30 #include <linux/kernel.h> 31 #include <linux/of_address.h> 32 #include <linux/of_clk.h> 33 #include <linux/of.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_platform.h> 36 #include <linux/pinctrl/pinconf-generic.h> 37 #include <linux/pinctrl/pinconf.h> 38 #include <linux/pinctrl/pinctrl.h> 39 #include <linux/platform_device.h> 40 #include <linux/pm_domain.h> 41 #include <linux/pm_opp.h> 42 #include <linux/reboot.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <linux/seq_file.h> 46 #include <linux/slab.h> 47 #include <linux/spinlock.h> 48 49 #include <soc/tegra/common.h> 50 #include <soc/tegra/fuse.h> 51 #include <soc/tegra/pmc.h> 52 53 #include <dt-bindings/interrupt-controller/arm-gic.h> 54 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 55 #include <dt-bindings/gpio/tegra186-gpio.h> 56 #include <dt-bindings/gpio/tegra194-gpio.h> 57 #include <dt-bindings/gpio/tegra234-gpio.h> 58 #include <dt-bindings/soc/tegra-pmc.h> 59 60 #define PMC_CNTRL 0x0 61 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 62 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 63 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 64 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 65 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 66 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 67 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 68 #define PMC_CNTRL_BLINK_EN 7 69 #define PMC_CNTRL_MAIN_RST BIT(4) 70 71 #define PMC_WAKE_MASK 0x0c 72 #define PMC_WAKE_LEVEL 0x10 73 #define PMC_WAKE_STATUS 0x14 74 #define PMC_SW_WAKE_STATUS 0x18 75 #define PMC_DPD_PADS_ORIDE 0x1c 76 #define PMC_DPD_PADS_ORIDE_BLINK 20 77 78 #define DPD_SAMPLE 0x020 79 #define DPD_SAMPLE_ENABLE BIT(0) 80 #define DPD_SAMPLE_DISABLE (0 << 0) 81 82 #define PWRGATE_TOGGLE 0x30 83 #define PWRGATE_TOGGLE_START BIT(8) 84 85 #define REMOVE_CLAMPING 0x34 86 87 #define PWRGATE_STATUS 0x38 88 89 #define PMC_BLINK_TIMER 0x40 90 #define PMC_IMPL_E_33V_PWR 0x40 91 92 #define PMC_PWR_DET 0x48 93 94 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 95 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 96 #define PMC_SCRATCH0_MODE_RCM BIT(1) 97 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 98 PMC_SCRATCH0_MODE_BOOTLOADER | \ 99 PMC_SCRATCH0_MODE_RCM) 100 101 #define PMC_CPUPWRGOOD_TIMER 0xc8 102 #define PMC_CPUPWROFF_TIMER 0xcc 103 #define PMC_COREPWRGOOD_TIMER 0x3c 104 #define PMC_COREPWROFF_TIMER 0xe0 105 106 #define PMC_PWR_DET_VALUE 0xe4 107 108 #define PMC_USB_DEBOUNCE_DEL 0xec 109 #define PMC_USB_AO 0xf0 110 111 #define PMC_SCRATCH41 0x140 112 113 #define PMC_WAKE2_MASK 0x160 114 #define PMC_WAKE2_LEVEL 0x164 115 #define PMC_WAKE2_STATUS 0x168 116 #define PMC_SW_WAKE2_STATUS 0x16c 117 118 #define PMC_CLK_OUT_CNTRL 0x1a8 119 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 120 #define PMC_SENSOR_CTRL 0x1b0 121 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 122 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 123 124 #define PMC_RST_STATUS_POR 0 125 #define PMC_RST_STATUS_WATCHDOG 1 126 #define PMC_RST_STATUS_SENSOR 2 127 #define PMC_RST_STATUS_SW_MAIN 3 128 #define PMC_RST_STATUS_LP0 4 129 #define PMC_RST_STATUS_AOTAG 5 130 131 #define IO_DPD_REQ 0x1b8 132 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 133 #define IO_DPD_REQ_CODE_OFF (1U << 30) 134 #define IO_DPD_REQ_CODE_ON (2U << 30) 135 #define IO_DPD_REQ_CODE_MASK (3U << 30) 136 137 #define IO_DPD_STATUS 0x1bc 138 #define IO_DPD2_REQ 0x1c0 139 #define IO_DPD2_STATUS 0x1c4 140 #define SEL_DPD_TIM 0x1c8 141 142 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 143 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 144 145 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 146 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 147 #define PMC_UTMIP_UHSIC_FAKE 0x218 148 149 #define PMC_SCRATCH54 0x258 150 #define PMC_SCRATCH54_DATA_SHIFT 8 151 #define PMC_SCRATCH54_ADDR_SHIFT 0 152 153 #define PMC_SCRATCH55 0x25c 154 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 155 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 156 #define PMC_SCRATCH55_PINMUX_SHIFT 24 157 #define PMC_SCRATCH55_16BITOP BIT(15) 158 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 159 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 160 161 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 162 163 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 164 #define PMC_UTMIP_MASTER_CONFIG 0x274 165 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 166 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 167 168 #define GPU_RG_CNTRL 0x2d4 169 170 #define PMC_UTMIP_PAD_CFG0 0x4c0 171 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 172 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 173 /* Tegra186 and later */ 174 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 175 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 176 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 177 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 178 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 179 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 180 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 181 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 182 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 183 184 #define WAKE_AOWAKE_CTRL 0x4f4 185 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 186 187 /* for secure PMC */ 188 #define TEGRA_SMC_PMC 0xc2fffe00 189 #define TEGRA_SMC_PMC_READ 0xaa 190 #define TEGRA_SMC_PMC_WRITE 0xbb 191 192 struct pmc_clk { 193 struct clk_hw hw; 194 unsigned long offs; 195 u32 mux_shift; 196 u32 force_en_shift; 197 }; 198 199 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 200 201 struct pmc_clk_gate { 202 struct clk_hw hw; 203 unsigned long offs; 204 u32 shift; 205 }; 206 207 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 208 209 struct pmc_clk_init_data { 210 char *name; 211 const char *const *parents; 212 int num_parents; 213 int clk_id; 214 u8 mux_shift; 215 u8 force_en_shift; 216 }; 217 218 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 219 "osc_div4", "extern1", 220 }; 221 222 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 223 "osc_div4", "extern2", 224 }; 225 226 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 227 "osc_div4", "extern3", 228 }; 229 230 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 231 { 232 .name = "pmc_clk_out_1", 233 .parents = clk_out1_parents, 234 .num_parents = ARRAY_SIZE(clk_out1_parents), 235 .clk_id = TEGRA_PMC_CLK_OUT_1, 236 .mux_shift = 6, 237 .force_en_shift = 2, 238 }, 239 { 240 .name = "pmc_clk_out_2", 241 .parents = clk_out2_parents, 242 .num_parents = ARRAY_SIZE(clk_out2_parents), 243 .clk_id = TEGRA_PMC_CLK_OUT_2, 244 .mux_shift = 14, 245 .force_en_shift = 10, 246 }, 247 { 248 .name = "pmc_clk_out_3", 249 .parents = clk_out3_parents, 250 .num_parents = ARRAY_SIZE(clk_out3_parents), 251 .clk_id = TEGRA_PMC_CLK_OUT_3, 252 .mux_shift = 22, 253 .force_en_shift = 18, 254 }, 255 }; 256 257 struct tegra_powergate { 258 struct generic_pm_domain genpd; 259 struct tegra_pmc *pmc; 260 unsigned int id; 261 struct clk **clks; 262 unsigned int num_clks; 263 unsigned long *clk_rates; 264 struct reset_control *reset; 265 }; 266 267 struct tegra_io_pad_soc { 268 enum tegra_io_pad id; 269 unsigned int dpd; 270 unsigned int voltage; 271 const char *name; 272 }; 273 274 struct tegra_pmc_regs { 275 unsigned int scratch0; 276 unsigned int dpd_req; 277 unsigned int dpd_status; 278 unsigned int dpd2_req; 279 unsigned int dpd2_status; 280 unsigned int rst_status; 281 unsigned int rst_source_shift; 282 unsigned int rst_source_mask; 283 unsigned int rst_level_shift; 284 unsigned int rst_level_mask; 285 }; 286 287 struct tegra_wake_event { 288 const char *name; 289 unsigned int id; 290 unsigned int irq; 291 struct { 292 unsigned int instance; 293 unsigned int pin; 294 } gpio; 295 }; 296 297 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 298 { \ 299 .name = _name, \ 300 .id = _id, \ 301 .irq = _irq, \ 302 .gpio = { \ 303 .instance = UINT_MAX, \ 304 .pin = UINT_MAX, \ 305 }, \ 306 } 307 308 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 309 { \ 310 .name = _name, \ 311 .id = _id, \ 312 .irq = 0, \ 313 .gpio = { \ 314 .instance = _instance, \ 315 .pin = _pin, \ 316 }, \ 317 } 318 319 struct tegra_pmc_soc { 320 unsigned int num_powergates; 321 const char *const *powergates; 322 unsigned int num_cpu_powergates; 323 const u8 *cpu_powergates; 324 325 bool has_tsense_reset; 326 bool has_gpu_clamps; 327 bool needs_mbist_war; 328 bool has_impl_33v_pwr; 329 bool maybe_tz_only; 330 331 const struct tegra_io_pad_soc *io_pads; 332 unsigned int num_io_pads; 333 334 const struct pinctrl_pin_desc *pin_descs; 335 unsigned int num_pin_descs; 336 337 const struct tegra_pmc_regs *regs; 338 void (*init)(struct tegra_pmc *pmc); 339 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 340 struct device_node *np, 341 bool invert); 342 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 343 int (*irq_set_type)(struct irq_data *data, unsigned int type); 344 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 345 bool new_state); 346 347 const char * const *reset_sources; 348 unsigned int num_reset_sources; 349 const char * const *reset_levels; 350 unsigned int num_reset_levels; 351 352 /* 353 * These describe events that can wake the system from sleep (i.e. 354 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 355 * are dealt with in the LIC. 356 */ 357 const struct tegra_wake_event *wake_events; 358 unsigned int num_wake_events; 359 360 const struct pmc_clk_init_data *pmc_clks_data; 361 unsigned int num_pmc_clks; 362 bool has_blink_output; 363 bool has_usb_sleepwalk; 364 bool supports_core_domain; 365 }; 366 367 /** 368 * struct tegra_pmc - NVIDIA Tegra PMC 369 * @dev: pointer to PMC device structure 370 * @base: pointer to I/O remapped register region 371 * @wake: pointer to I/O remapped region for WAKE registers 372 * @aotag: pointer to I/O remapped region for AOTAG registers 373 * @scratch: pointer to I/O remapped region for scratch registers 374 * @clk: pointer to pclk clock 375 * @soc: pointer to SoC data structure 376 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 377 * @debugfs: pointer to debugfs entry 378 * @rate: currently configured rate of pclk 379 * @suspend_mode: lowest suspend mode available 380 * @cpu_good_time: CPU power good time (in microseconds) 381 * @cpu_off_time: CPU power off time (in microsecends) 382 * @core_osc_time: core power good OSC time (in microseconds) 383 * @core_pmu_time: core power good PMU time (in microseconds) 384 * @core_off_time: core power off time (in microseconds) 385 * @corereq_high: core power request is active-high 386 * @sysclkreq_high: system clock request is active-high 387 * @combined_req: combined power request for CPU & core 388 * @cpu_pwr_good_en: CPU power good signal is enabled 389 * @lp0_vec_phys: physical base address of the LP0 warm boot code 390 * @lp0_vec_size: size of the LP0 warm boot code 391 * @powergates_available: Bitmap of available power gates 392 * @powergates_lock: mutex for power gate register access 393 * @pctl_dev: pin controller exposed by the PMC 394 * @domain: IRQ domain provided by the PMC 395 * @irq: chip implementation for the IRQ domain 396 * @clk_nb: pclk clock changes handler 397 * @core_domain_state_synced: flag marking the core domain's state as synced 398 * @core_domain_registered: flag marking the core domain as registered 399 */ 400 struct tegra_pmc { 401 struct device *dev; 402 void __iomem *base; 403 void __iomem *wake; 404 void __iomem *aotag; 405 void __iomem *scratch; 406 struct clk *clk; 407 struct dentry *debugfs; 408 409 const struct tegra_pmc_soc *soc; 410 bool tz_only; 411 412 unsigned long rate; 413 414 enum tegra_suspend_mode suspend_mode; 415 u32 cpu_good_time; 416 u32 cpu_off_time; 417 u32 core_osc_time; 418 u32 core_pmu_time; 419 u32 core_off_time; 420 bool corereq_high; 421 bool sysclkreq_high; 422 bool combined_req; 423 bool cpu_pwr_good_en; 424 u32 lp0_vec_phys; 425 u32 lp0_vec_size; 426 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 427 428 struct mutex powergates_lock; 429 430 struct pinctrl_dev *pctl_dev; 431 432 struct irq_domain *domain; 433 struct irq_chip irq; 434 435 struct notifier_block clk_nb; 436 437 bool core_domain_state_synced; 438 bool core_domain_registered; 439 }; 440 441 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 442 .base = NULL, 443 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 444 }; 445 446 static inline struct tegra_powergate * 447 to_powergate(struct generic_pm_domain *domain) 448 { 449 return container_of(domain, struct tegra_powergate, genpd); 450 } 451 452 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 453 { 454 struct arm_smccc_res res; 455 456 if (pmc->tz_only) { 457 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 458 0, 0, 0, &res); 459 if (res.a0) { 460 if (pmc->dev) 461 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 462 __func__, res.a0); 463 else 464 pr_warn("%s(): SMC failed: %lu\n", __func__, 465 res.a0); 466 } 467 468 return res.a1; 469 } 470 471 return readl(pmc->base + offset); 472 } 473 474 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 475 unsigned long offset) 476 { 477 struct arm_smccc_res res; 478 479 if (pmc->tz_only) { 480 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 481 value, 0, 0, 0, 0, &res); 482 if (res.a0) { 483 if (pmc->dev) 484 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 485 __func__, res.a0); 486 else 487 pr_warn("%s(): SMC failed: %lu\n", __func__, 488 res.a0); 489 } 490 } else { 491 writel(value, pmc->base + offset); 492 } 493 } 494 495 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 496 { 497 if (pmc->tz_only) 498 return tegra_pmc_readl(pmc, offset); 499 500 return readl(pmc->scratch + offset); 501 } 502 503 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 504 unsigned long offset) 505 { 506 if (pmc->tz_only) 507 tegra_pmc_writel(pmc, value, offset); 508 else 509 writel(value, pmc->scratch + offset); 510 } 511 512 /* 513 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 514 * This currently doesn't work because readx_poll_timeout() can only operate 515 * on functions that take a single argument. 516 */ 517 static inline bool tegra_powergate_state(int id) 518 { 519 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 520 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 521 else 522 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 523 } 524 525 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 526 { 527 return (pmc->soc && pmc->soc->powergates[id]); 528 } 529 530 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 531 { 532 return test_bit(id, pmc->powergates_available); 533 } 534 535 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 536 { 537 unsigned int i; 538 539 if (!pmc || !pmc->soc || !name) 540 return -EINVAL; 541 542 for (i = 0; i < pmc->soc->num_powergates; i++) { 543 if (!tegra_powergate_is_valid(pmc, i)) 544 continue; 545 546 if (!strcmp(name, pmc->soc->powergates[i])) 547 return i; 548 } 549 550 return -ENODEV; 551 } 552 553 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 554 bool new_state) 555 { 556 unsigned int retries = 100; 557 bool status; 558 int ret; 559 560 /* 561 * As per TRM documentation, the toggle command will be dropped by PMC 562 * if there is contention with a HW-initiated toggling (i.e. CPU core 563 * power-gated), the command should be retried in that case. 564 */ 565 do { 566 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 567 568 /* wait for PMC to execute the command */ 569 ret = readx_poll_timeout(tegra_powergate_state, id, status, 570 status == new_state, 1, 10); 571 } while (ret == -ETIMEDOUT && retries--); 572 573 return ret; 574 } 575 576 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 577 { 578 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 579 } 580 581 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 582 bool new_state) 583 { 584 bool status; 585 int err; 586 587 /* wait while PMC power gating is contended */ 588 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 589 status == true, 1, 100); 590 if (err) 591 return err; 592 593 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 594 595 /* wait for PMC to accept the command */ 596 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 597 status == true, 1, 100); 598 if (err) 599 return err; 600 601 /* wait for PMC to execute the command */ 602 err = readx_poll_timeout(tegra_powergate_state, id, status, 603 status == new_state, 10, 100000); 604 if (err) 605 return err; 606 607 return 0; 608 } 609 610 /** 611 * tegra_powergate_set() - set the state of a partition 612 * @pmc: power management controller 613 * @id: partition ID 614 * @new_state: new state of the partition 615 */ 616 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 617 bool new_state) 618 { 619 int err; 620 621 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 622 return -EINVAL; 623 624 mutex_lock(&pmc->powergates_lock); 625 626 if (tegra_powergate_state(id) == new_state) { 627 mutex_unlock(&pmc->powergates_lock); 628 return 0; 629 } 630 631 err = pmc->soc->powergate_set(pmc, id, new_state); 632 633 mutex_unlock(&pmc->powergates_lock); 634 635 return err; 636 } 637 638 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 639 unsigned int id) 640 { 641 u32 mask; 642 643 mutex_lock(&pmc->powergates_lock); 644 645 /* 646 * On Tegra124 and later, the clamps for the GPU are controlled by a 647 * separate register (with different semantics). 648 */ 649 if (id == TEGRA_POWERGATE_3D) { 650 if (pmc->soc->has_gpu_clamps) { 651 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 652 goto out; 653 } 654 } 655 656 /* 657 * Tegra 2 has a bug where PCIE and VDE clamping masks are 658 * swapped relatively to the partition ids 659 */ 660 if (id == TEGRA_POWERGATE_VDEC) 661 mask = (1 << TEGRA_POWERGATE_PCIE); 662 else if (id == TEGRA_POWERGATE_PCIE) 663 mask = (1 << TEGRA_POWERGATE_VDEC); 664 else 665 mask = (1 << id); 666 667 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 668 669 out: 670 mutex_unlock(&pmc->powergates_lock); 671 672 return 0; 673 } 674 675 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 676 { 677 unsigned long safe_rate = 100 * 1000 * 1000; 678 unsigned int i; 679 int err; 680 681 for (i = 0; i < pg->num_clks; i++) { 682 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 683 684 if (!pg->clk_rates[i]) { 685 err = -EINVAL; 686 goto out; 687 } 688 689 if (pg->clk_rates[i] <= safe_rate) 690 continue; 691 692 /* 693 * We don't know whether voltage state is okay for the 694 * current clock rate, hence it's better to temporally 695 * switch clock to a safe rate which is suitable for 696 * all voltages, before enabling the clock. 697 */ 698 err = clk_set_rate(pg->clks[i], safe_rate); 699 if (err) 700 goto out; 701 } 702 703 return 0; 704 705 out: 706 while (i--) 707 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 708 709 return err; 710 } 711 712 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 713 { 714 unsigned int i; 715 int err; 716 717 for (i = 0; i < pg->num_clks; i++) { 718 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 719 if (err) 720 return err; 721 } 722 723 return 0; 724 } 725 726 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 727 { 728 unsigned int i; 729 730 for (i = 0; i < pg->num_clks; i++) 731 clk_disable_unprepare(pg->clks[i]); 732 } 733 734 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 735 { 736 unsigned int i; 737 int err; 738 739 for (i = 0; i < pg->num_clks; i++) { 740 err = clk_prepare_enable(pg->clks[i]); 741 if (err) 742 goto out; 743 } 744 745 return 0; 746 747 out: 748 while (i--) 749 clk_disable_unprepare(pg->clks[i]); 750 751 return err; 752 } 753 754 static int tegra_powergate_power_up(struct tegra_powergate *pg, 755 bool disable_clocks) 756 { 757 int err; 758 759 err = reset_control_assert(pg->reset); 760 if (err) 761 return err; 762 763 usleep_range(10, 20); 764 765 err = tegra_powergate_set(pg->pmc, pg->id, true); 766 if (err < 0) 767 return err; 768 769 usleep_range(10, 20); 770 771 err = tegra_powergate_prepare_clocks(pg); 772 if (err) 773 goto powergate_off; 774 775 err = tegra_powergate_enable_clocks(pg); 776 if (err) 777 goto unprepare_clks; 778 779 usleep_range(10, 20); 780 781 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 782 if (err) 783 goto disable_clks; 784 785 usleep_range(10, 20); 786 787 err = reset_control_deassert(pg->reset); 788 if (err) 789 goto disable_clks; 790 791 usleep_range(10, 20); 792 793 if (pg->pmc->soc->needs_mbist_war) 794 err = tegra210_clk_handle_mbist_war(pg->id); 795 if (err) 796 goto disable_clks; 797 798 if (disable_clocks) 799 tegra_powergate_disable_clocks(pg); 800 801 err = tegra_powergate_unprepare_clocks(pg); 802 if (err) 803 return err; 804 805 return 0; 806 807 disable_clks: 808 tegra_powergate_disable_clocks(pg); 809 usleep_range(10, 20); 810 811 unprepare_clks: 812 tegra_powergate_unprepare_clocks(pg); 813 814 powergate_off: 815 tegra_powergate_set(pg->pmc, pg->id, false); 816 817 return err; 818 } 819 820 static int tegra_powergate_power_down(struct tegra_powergate *pg) 821 { 822 int err; 823 824 err = tegra_powergate_prepare_clocks(pg); 825 if (err) 826 return err; 827 828 err = tegra_powergate_enable_clocks(pg); 829 if (err) 830 goto unprepare_clks; 831 832 usleep_range(10, 20); 833 834 err = reset_control_assert(pg->reset); 835 if (err) 836 goto disable_clks; 837 838 usleep_range(10, 20); 839 840 tegra_powergate_disable_clocks(pg); 841 842 usleep_range(10, 20); 843 844 err = tegra_powergate_set(pg->pmc, pg->id, false); 845 if (err) 846 goto assert_resets; 847 848 err = tegra_powergate_unprepare_clocks(pg); 849 if (err) 850 return err; 851 852 return 0; 853 854 assert_resets: 855 tegra_powergate_enable_clocks(pg); 856 usleep_range(10, 20); 857 reset_control_deassert(pg->reset); 858 usleep_range(10, 20); 859 860 disable_clks: 861 tegra_powergate_disable_clocks(pg); 862 863 unprepare_clks: 864 tegra_powergate_unprepare_clocks(pg); 865 866 return err; 867 } 868 869 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 870 { 871 struct tegra_powergate *pg = to_powergate(domain); 872 struct device *dev = pg->pmc->dev; 873 int err; 874 875 err = tegra_powergate_power_up(pg, true); 876 if (err) { 877 dev_err(dev, "failed to turn on PM domain %s: %d\n", 878 pg->genpd.name, err); 879 goto out; 880 } 881 882 reset_control_release(pg->reset); 883 884 out: 885 return err; 886 } 887 888 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 889 { 890 struct tegra_powergate *pg = to_powergate(domain); 891 struct device *dev = pg->pmc->dev; 892 int err; 893 894 err = reset_control_acquire(pg->reset); 895 if (err < 0) { 896 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 897 pg->genpd.name, err); 898 return err; 899 } 900 901 err = tegra_powergate_power_down(pg); 902 if (err) { 903 dev_err(dev, "failed to turn off PM domain %s: %d\n", 904 pg->genpd.name, err); 905 reset_control_release(pg->reset); 906 } 907 908 return err; 909 } 910 911 /** 912 * tegra_powergate_power_on() - power on partition 913 * @id: partition ID 914 */ 915 int tegra_powergate_power_on(unsigned int id) 916 { 917 if (!tegra_powergate_is_available(pmc, id)) 918 return -EINVAL; 919 920 return tegra_powergate_set(pmc, id, true); 921 } 922 EXPORT_SYMBOL(tegra_powergate_power_on); 923 924 /** 925 * tegra_powergate_power_off() - power off partition 926 * @id: partition ID 927 */ 928 int tegra_powergate_power_off(unsigned int id) 929 { 930 if (!tegra_powergate_is_available(pmc, id)) 931 return -EINVAL; 932 933 return tegra_powergate_set(pmc, id, false); 934 } 935 EXPORT_SYMBOL(tegra_powergate_power_off); 936 937 /** 938 * tegra_powergate_is_powered() - check if partition is powered 939 * @pmc: power management controller 940 * @id: partition ID 941 */ 942 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 943 { 944 if (!tegra_powergate_is_valid(pmc, id)) 945 return -EINVAL; 946 947 return tegra_powergate_state(id); 948 } 949 950 /** 951 * tegra_powergate_remove_clamping() - remove power clamps for partition 952 * @id: partition ID 953 */ 954 int tegra_powergate_remove_clamping(unsigned int id) 955 { 956 if (!tegra_powergate_is_available(pmc, id)) 957 return -EINVAL; 958 959 return __tegra_powergate_remove_clamping(pmc, id); 960 } 961 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 962 963 /** 964 * tegra_powergate_sequence_power_up() - power up partition 965 * @id: partition ID 966 * @clk: clock for partition 967 * @rst: reset for partition 968 * 969 * Must be called with clk disabled, and returns with clk enabled. 970 */ 971 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 972 struct reset_control *rst) 973 { 974 struct tegra_powergate *pg; 975 int err; 976 977 if (!tegra_powergate_is_available(pmc, id)) 978 return -EINVAL; 979 980 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 981 if (!pg) 982 return -ENOMEM; 983 984 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); 985 if (!pg->clk_rates) { 986 kfree(pg->clks); 987 return -ENOMEM; 988 } 989 990 pg->id = id; 991 pg->clks = &clk; 992 pg->num_clks = 1; 993 pg->reset = rst; 994 pg->pmc = pmc; 995 996 err = tegra_powergate_power_up(pg, false); 997 if (err) 998 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 999 err); 1000 1001 kfree(pg->clk_rates); 1002 kfree(pg); 1003 1004 return err; 1005 } 1006 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1007 1008 /** 1009 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1010 * @pmc: power management controller 1011 * @cpuid: CPU partition ID 1012 * 1013 * Returns the partition ID corresponding to the CPU partition ID or a 1014 * negative error code on failure. 1015 */ 1016 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1017 unsigned int cpuid) 1018 { 1019 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1020 return pmc->soc->cpu_powergates[cpuid]; 1021 1022 return -EINVAL; 1023 } 1024 1025 /** 1026 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1027 * @cpuid: CPU partition ID 1028 */ 1029 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1030 { 1031 int id; 1032 1033 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1034 if (id < 0) 1035 return false; 1036 1037 return tegra_powergate_is_powered(pmc, id); 1038 } 1039 1040 /** 1041 * tegra_pmc_cpu_power_on() - power on CPU partition 1042 * @cpuid: CPU partition ID 1043 */ 1044 int tegra_pmc_cpu_power_on(unsigned int cpuid) 1045 { 1046 int id; 1047 1048 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1049 if (id < 0) 1050 return id; 1051 1052 return tegra_powergate_set(pmc, id, true); 1053 } 1054 1055 /** 1056 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1057 * @cpuid: CPU partition ID 1058 */ 1059 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1060 { 1061 int id; 1062 1063 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1064 if (id < 0) 1065 return id; 1066 1067 return tegra_powergate_remove_clamping(id); 1068 } 1069 1070 static void tegra_pmc_program_reboot_reason(const char *cmd) 1071 { 1072 u32 value; 1073 1074 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1075 value &= ~PMC_SCRATCH0_MODE_MASK; 1076 1077 if (cmd) { 1078 if (strcmp(cmd, "recovery") == 0) 1079 value |= PMC_SCRATCH0_MODE_RECOVERY; 1080 1081 if (strcmp(cmd, "bootloader") == 0) 1082 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1083 1084 if (strcmp(cmd, "forced-recovery") == 0) 1085 value |= PMC_SCRATCH0_MODE_RCM; 1086 } 1087 1088 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1089 } 1090 1091 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1092 unsigned long action, void *data) 1093 { 1094 if (action == SYS_RESTART) 1095 tegra_pmc_program_reboot_reason(data); 1096 1097 return NOTIFY_DONE; 1098 } 1099 1100 static struct notifier_block tegra_pmc_reboot_notifier = { 1101 .notifier_call = tegra_pmc_reboot_notify, 1102 }; 1103 1104 static int tegra_pmc_restart_notify(struct notifier_block *this, 1105 unsigned long action, void *data) 1106 { 1107 u32 value; 1108 1109 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1110 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1111 value |= PMC_CNTRL_MAIN_RST; 1112 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1113 1114 return NOTIFY_DONE; 1115 } 1116 1117 static struct notifier_block tegra_pmc_restart_handler = { 1118 .notifier_call = tegra_pmc_restart_notify, 1119 .priority = 128, 1120 }; 1121 1122 static int powergate_show(struct seq_file *s, void *data) 1123 { 1124 unsigned int i; 1125 int status; 1126 1127 seq_printf(s, " powergate powered\n"); 1128 seq_printf(s, "------------------\n"); 1129 1130 for (i = 0; i < pmc->soc->num_powergates; i++) { 1131 status = tegra_powergate_is_powered(pmc, i); 1132 if (status < 0) 1133 continue; 1134 1135 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1136 status ? "yes" : "no"); 1137 } 1138 1139 return 0; 1140 } 1141 1142 DEFINE_SHOW_ATTRIBUTE(powergate); 1143 1144 static int tegra_powergate_debugfs_init(void) 1145 { 1146 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 1147 &powergate_fops); 1148 if (!pmc->debugfs) 1149 return -ENOMEM; 1150 1151 return 0; 1152 } 1153 1154 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1155 struct device_node *np) 1156 { 1157 struct clk *clk; 1158 unsigned int i, count; 1159 int err; 1160 1161 count = of_clk_get_parent_count(np); 1162 if (count == 0) 1163 return -ENODEV; 1164 1165 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1166 if (!pg->clks) 1167 return -ENOMEM; 1168 1169 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1170 if (!pg->clk_rates) { 1171 kfree(pg->clks); 1172 return -ENOMEM; 1173 } 1174 1175 for (i = 0; i < count; i++) { 1176 pg->clks[i] = of_clk_get(np, i); 1177 if (IS_ERR(pg->clks[i])) { 1178 err = PTR_ERR(pg->clks[i]); 1179 goto err; 1180 } 1181 } 1182 1183 pg->num_clks = count; 1184 1185 return 0; 1186 1187 err: 1188 while (i--) 1189 clk_put(pg->clks[i]); 1190 1191 kfree(pg->clk_rates); 1192 kfree(pg->clks); 1193 1194 return err; 1195 } 1196 1197 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1198 struct device_node *np, bool off) 1199 { 1200 struct device *dev = pg->pmc->dev; 1201 int err; 1202 1203 pg->reset = of_reset_control_array_get_exclusive_released(np); 1204 if (IS_ERR(pg->reset)) { 1205 err = PTR_ERR(pg->reset); 1206 dev_err(dev, "failed to get device resets: %d\n", err); 1207 return err; 1208 } 1209 1210 err = reset_control_acquire(pg->reset); 1211 if (err < 0) { 1212 pr_err("failed to acquire resets: %d\n", err); 1213 goto out; 1214 } 1215 1216 if (off) { 1217 err = reset_control_assert(pg->reset); 1218 } else { 1219 err = reset_control_deassert(pg->reset); 1220 if (err < 0) 1221 goto out; 1222 1223 reset_control_release(pg->reset); 1224 } 1225 1226 out: 1227 if (err) { 1228 reset_control_release(pg->reset); 1229 reset_control_put(pg->reset); 1230 } 1231 1232 return err; 1233 } 1234 1235 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1236 { 1237 struct device *dev = pmc->dev; 1238 struct tegra_powergate *pg; 1239 int id, err = 0; 1240 bool off; 1241 1242 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1243 if (!pg) 1244 return -ENOMEM; 1245 1246 id = tegra_powergate_lookup(pmc, np->name); 1247 if (id < 0) { 1248 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1249 err = -ENODEV; 1250 goto free_mem; 1251 } 1252 1253 /* 1254 * Clear the bit for this powergate so it cannot be managed 1255 * directly via the legacy APIs for controlling powergates. 1256 */ 1257 clear_bit(id, pmc->powergates_available); 1258 1259 pg->id = id; 1260 pg->genpd.name = np->name; 1261 pg->genpd.power_off = tegra_genpd_power_off; 1262 pg->genpd.power_on = tegra_genpd_power_on; 1263 pg->pmc = pmc; 1264 1265 off = !tegra_powergate_is_powered(pmc, pg->id); 1266 1267 err = tegra_powergate_of_get_clks(pg, np); 1268 if (err < 0) { 1269 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1270 goto set_available; 1271 } 1272 1273 err = tegra_powergate_of_get_resets(pg, np, off); 1274 if (err < 0) { 1275 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1276 goto remove_clks; 1277 } 1278 1279 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1280 if (off) 1281 WARN_ON(tegra_powergate_power_up(pg, true)); 1282 1283 goto remove_resets; 1284 } 1285 1286 err = pm_genpd_init(&pg->genpd, NULL, off); 1287 if (err < 0) { 1288 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1289 err); 1290 goto remove_resets; 1291 } 1292 1293 err = of_genpd_add_provider_simple(np, &pg->genpd); 1294 if (err < 0) { 1295 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1296 np, err); 1297 goto remove_genpd; 1298 } 1299 1300 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1301 1302 return 0; 1303 1304 remove_genpd: 1305 pm_genpd_remove(&pg->genpd); 1306 1307 remove_resets: 1308 reset_control_put(pg->reset); 1309 1310 remove_clks: 1311 while (pg->num_clks--) 1312 clk_put(pg->clks[pg->num_clks]); 1313 1314 kfree(pg->clks); 1315 1316 set_available: 1317 set_bit(id, pmc->powergates_available); 1318 1319 free_mem: 1320 kfree(pg); 1321 1322 return err; 1323 } 1324 1325 bool tegra_pmc_core_domain_state_synced(void) 1326 { 1327 return pmc->core_domain_state_synced; 1328 } 1329 1330 static int 1331 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1332 unsigned int level) 1333 { 1334 struct dev_pm_opp *opp; 1335 int err; 1336 1337 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1338 if (IS_ERR(opp)) { 1339 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1340 level, opp); 1341 return PTR_ERR(opp); 1342 } 1343 1344 mutex_lock(&pmc->powergates_lock); 1345 err = dev_pm_opp_set_opp(pmc->dev, opp); 1346 mutex_unlock(&pmc->powergates_lock); 1347 1348 dev_pm_opp_put(opp); 1349 1350 if (err) { 1351 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1352 level, err); 1353 return err; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static unsigned int 1360 tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd, 1361 struct dev_pm_opp *opp) 1362 { 1363 return dev_pm_opp_get_level(opp); 1364 } 1365 1366 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1367 { 1368 struct generic_pm_domain *genpd; 1369 const char *rname = "core"; 1370 int err; 1371 1372 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); 1373 if (!genpd) 1374 return -ENOMEM; 1375 1376 genpd->name = "core"; 1377 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; 1378 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; 1379 1380 err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1); 1381 if (err) 1382 return dev_err_probe(pmc->dev, err, 1383 "failed to set core OPP regulator\n"); 1384 1385 err = pm_genpd_init(genpd, NULL, false); 1386 if (err) { 1387 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1388 return err; 1389 } 1390 1391 err = of_genpd_add_provider_simple(np, genpd); 1392 if (err) { 1393 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1394 goto remove_genpd; 1395 } 1396 1397 pmc->core_domain_registered = true; 1398 1399 return 0; 1400 1401 remove_genpd: 1402 pm_genpd_remove(genpd); 1403 1404 return err; 1405 } 1406 1407 static int tegra_powergate_init(struct tegra_pmc *pmc, 1408 struct device_node *parent) 1409 { 1410 struct of_phandle_args child_args, parent_args; 1411 struct device_node *np, *child; 1412 int err = 0; 1413 1414 /* 1415 * Core power domain is the parent of powergate domains, hence it 1416 * should be registered first. 1417 */ 1418 np = of_get_child_by_name(parent, "core-domain"); 1419 if (np) { 1420 err = tegra_pmc_core_pd_add(pmc, np); 1421 of_node_put(np); 1422 if (err) 1423 return err; 1424 } 1425 1426 np = of_get_child_by_name(parent, "powergates"); 1427 if (!np) 1428 return 0; 1429 1430 for_each_child_of_node(np, child) { 1431 err = tegra_powergate_add(pmc, child); 1432 if (err < 0) { 1433 of_node_put(child); 1434 break; 1435 } 1436 1437 if (of_parse_phandle_with_args(child, "power-domains", 1438 "#power-domain-cells", 1439 0, &parent_args)) 1440 continue; 1441 1442 child_args.np = child; 1443 child_args.args_count = 0; 1444 1445 err = of_genpd_add_subdomain(&parent_args, &child_args); 1446 of_node_put(parent_args.np); 1447 if (err) { 1448 of_node_put(child); 1449 break; 1450 } 1451 } 1452 1453 of_node_put(np); 1454 1455 return err; 1456 } 1457 1458 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1459 { 1460 struct tegra_powergate *pg = to_powergate(genpd); 1461 1462 reset_control_put(pg->reset); 1463 1464 while (pg->num_clks--) 1465 clk_put(pg->clks[pg->num_clks]); 1466 1467 kfree(pg->clks); 1468 1469 set_bit(pg->id, pmc->powergates_available); 1470 1471 kfree(pg); 1472 } 1473 1474 static void tegra_powergate_remove_all(struct device_node *parent) 1475 { 1476 struct generic_pm_domain *genpd; 1477 struct device_node *np, *child; 1478 1479 np = of_get_child_by_name(parent, "powergates"); 1480 if (!np) 1481 return; 1482 1483 for_each_child_of_node(np, child) { 1484 of_genpd_del_provider(child); 1485 1486 genpd = of_genpd_remove_last(child); 1487 if (IS_ERR(genpd)) 1488 continue; 1489 1490 tegra_powergate_remove(genpd); 1491 } 1492 1493 of_node_put(np); 1494 1495 np = of_get_child_by_name(parent, "core-domain"); 1496 if (np) { 1497 of_genpd_del_provider(np); 1498 of_genpd_remove_last(np); 1499 } 1500 } 1501 1502 static const struct tegra_io_pad_soc * 1503 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1504 { 1505 unsigned int i; 1506 1507 for (i = 0; i < pmc->soc->num_io_pads; i++) 1508 if (pmc->soc->io_pads[i].id == id) 1509 return &pmc->soc->io_pads[i]; 1510 1511 return NULL; 1512 } 1513 1514 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, 1515 enum tegra_io_pad id, 1516 unsigned long *request, 1517 unsigned long *status, 1518 u32 *mask) 1519 { 1520 const struct tegra_io_pad_soc *pad; 1521 1522 pad = tegra_io_pad_find(pmc, id); 1523 if (!pad) { 1524 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1525 return -ENOENT; 1526 } 1527 1528 if (pad->dpd == UINT_MAX) 1529 return -ENOTSUPP; 1530 1531 *mask = BIT(pad->dpd % 32); 1532 1533 if (pad->dpd < 32) { 1534 *status = pmc->soc->regs->dpd_status; 1535 *request = pmc->soc->regs->dpd_req; 1536 } else { 1537 *status = pmc->soc->regs->dpd2_status; 1538 *request = pmc->soc->regs->dpd2_req; 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, 1545 unsigned long *request, unsigned long *status, 1546 u32 *mask) 1547 { 1548 unsigned long rate, value; 1549 int err; 1550 1551 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); 1552 if (err) 1553 return err; 1554 1555 if (pmc->clk) { 1556 rate = pmc->rate; 1557 if (!rate) { 1558 dev_err(pmc->dev, "failed to get clock rate\n"); 1559 return -ENODEV; 1560 } 1561 1562 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1563 1564 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1565 value = DIV_ROUND_UP(1000000000, rate); 1566 value = DIV_ROUND_UP(200, value); 1567 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1568 } 1569 1570 return 0; 1571 } 1572 1573 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1574 u32 mask, u32 val, unsigned long timeout) 1575 { 1576 u32 value; 1577 1578 timeout = jiffies + msecs_to_jiffies(timeout); 1579 1580 while (time_after(timeout, jiffies)) { 1581 value = tegra_pmc_readl(pmc, offset); 1582 if ((value & mask) == val) 1583 return 0; 1584 1585 usleep_range(250, 1000); 1586 } 1587 1588 return -ETIMEDOUT; 1589 } 1590 1591 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1592 { 1593 if (pmc->clk) 1594 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1595 } 1596 1597 /** 1598 * tegra_io_pad_power_enable() - enable power to I/O pad 1599 * @id: Tegra I/O pad ID for which to enable power 1600 * 1601 * Returns: 0 on success or a negative error code on failure. 1602 */ 1603 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1604 { 1605 unsigned long request, status; 1606 u32 mask; 1607 int err; 1608 1609 mutex_lock(&pmc->powergates_lock); 1610 1611 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1612 if (err < 0) { 1613 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1614 goto unlock; 1615 } 1616 1617 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1618 1619 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1620 if (err < 0) { 1621 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1622 goto unlock; 1623 } 1624 1625 tegra_io_pad_unprepare(pmc); 1626 1627 unlock: 1628 mutex_unlock(&pmc->powergates_lock); 1629 return err; 1630 } 1631 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1632 1633 /** 1634 * tegra_io_pad_power_disable() - disable power to I/O pad 1635 * @id: Tegra I/O pad ID for which to disable power 1636 * 1637 * Returns: 0 on success or a negative error code on failure. 1638 */ 1639 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1640 { 1641 unsigned long request, status; 1642 u32 mask; 1643 int err; 1644 1645 mutex_lock(&pmc->powergates_lock); 1646 1647 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1648 if (err < 0) { 1649 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1650 goto unlock; 1651 } 1652 1653 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1654 1655 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1656 if (err < 0) { 1657 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1658 goto unlock; 1659 } 1660 1661 tegra_io_pad_unprepare(pmc); 1662 1663 unlock: 1664 mutex_unlock(&pmc->powergates_lock); 1665 return err; 1666 } 1667 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1668 1669 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1670 { 1671 unsigned long request, status; 1672 u32 mask, value; 1673 int err; 1674 1675 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, 1676 &mask); 1677 if (err) 1678 return err; 1679 1680 value = tegra_pmc_readl(pmc, status); 1681 1682 return !(value & mask); 1683 } 1684 1685 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1686 int voltage) 1687 { 1688 const struct tegra_io_pad_soc *pad; 1689 u32 value; 1690 1691 pad = tegra_io_pad_find(pmc, id); 1692 if (!pad) 1693 return -ENOENT; 1694 1695 if (pad->voltage == UINT_MAX) 1696 return -ENOTSUPP; 1697 1698 mutex_lock(&pmc->powergates_lock); 1699 1700 if (pmc->soc->has_impl_33v_pwr) { 1701 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1702 1703 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1704 value &= ~BIT(pad->voltage); 1705 else 1706 value |= BIT(pad->voltage); 1707 1708 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1709 } else { 1710 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1711 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1712 value |= BIT(pad->voltage); 1713 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1714 1715 /* update I/O voltage */ 1716 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1717 1718 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1719 value &= ~BIT(pad->voltage); 1720 else 1721 value |= BIT(pad->voltage); 1722 1723 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1724 } 1725 1726 mutex_unlock(&pmc->powergates_lock); 1727 1728 usleep_range(100, 250); 1729 1730 return 0; 1731 } 1732 1733 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1734 { 1735 const struct tegra_io_pad_soc *pad; 1736 u32 value; 1737 1738 pad = tegra_io_pad_find(pmc, id); 1739 if (!pad) 1740 return -ENOENT; 1741 1742 if (pad->voltage == UINT_MAX) 1743 return -ENOTSUPP; 1744 1745 if (pmc->soc->has_impl_33v_pwr) 1746 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1747 else 1748 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1749 1750 if ((value & BIT(pad->voltage)) == 0) 1751 return TEGRA_IO_PAD_VOLTAGE_1V8; 1752 1753 return TEGRA_IO_PAD_VOLTAGE_3V3; 1754 } 1755 1756 /** 1757 * tegra_io_rail_power_on() - enable power to I/O rail 1758 * @id: Tegra I/O pad ID for which to enable power 1759 * 1760 * See also: tegra_io_pad_power_enable() 1761 */ 1762 int tegra_io_rail_power_on(unsigned int id) 1763 { 1764 return tegra_io_pad_power_enable(id); 1765 } 1766 EXPORT_SYMBOL(tegra_io_rail_power_on); 1767 1768 /** 1769 * tegra_io_rail_power_off() - disable power to I/O rail 1770 * @id: Tegra I/O pad ID for which to disable power 1771 * 1772 * See also: tegra_io_pad_power_disable() 1773 */ 1774 int tegra_io_rail_power_off(unsigned int id) 1775 { 1776 return tegra_io_pad_power_disable(id); 1777 } 1778 EXPORT_SYMBOL(tegra_io_rail_power_off); 1779 1780 #ifdef CONFIG_PM_SLEEP 1781 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1782 { 1783 return pmc->suspend_mode; 1784 } 1785 1786 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1787 { 1788 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1789 return; 1790 1791 pmc->suspend_mode = mode; 1792 } 1793 1794 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1795 { 1796 unsigned long long rate = 0; 1797 u64 ticks; 1798 u32 value; 1799 1800 switch (mode) { 1801 case TEGRA_SUSPEND_LP1: 1802 rate = 32768; 1803 break; 1804 1805 case TEGRA_SUSPEND_LP2: 1806 rate = pmc->rate; 1807 break; 1808 1809 default: 1810 break; 1811 } 1812 1813 if (WARN_ON_ONCE(rate == 0)) 1814 rate = 100000000; 1815 1816 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1817 do_div(ticks, USEC_PER_SEC); 1818 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1819 1820 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1821 do_div(ticks, USEC_PER_SEC); 1822 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1823 1824 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1825 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1826 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1827 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1828 } 1829 #endif 1830 1831 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1832 { 1833 u32 value, values[2]; 1834 1835 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1836 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1837 } else { 1838 switch (value) { 1839 case 0: 1840 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1841 break; 1842 1843 case 1: 1844 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1845 break; 1846 1847 case 2: 1848 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1849 break; 1850 1851 default: 1852 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1853 break; 1854 } 1855 } 1856 1857 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1858 1859 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1860 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1861 1862 pmc->cpu_good_time = value; 1863 1864 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1865 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1866 1867 pmc->cpu_off_time = value; 1868 1869 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1870 values, ARRAY_SIZE(values))) 1871 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1872 1873 pmc->core_osc_time = values[0]; 1874 pmc->core_pmu_time = values[1]; 1875 1876 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1877 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1878 1879 pmc->core_off_time = value; 1880 1881 pmc->corereq_high = of_property_read_bool(np, 1882 "nvidia,core-power-req-active-high"); 1883 1884 pmc->sysclkreq_high = of_property_read_bool(np, 1885 "nvidia,sys-clock-req-active-high"); 1886 1887 pmc->combined_req = of_property_read_bool(np, 1888 "nvidia,combined-power-req"); 1889 1890 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1891 "nvidia,cpu-pwr-good-en"); 1892 1893 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1894 ARRAY_SIZE(values))) 1895 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1896 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1897 1898 pmc->lp0_vec_phys = values[0]; 1899 pmc->lp0_vec_size = values[1]; 1900 1901 return 0; 1902 } 1903 1904 static void tegra_pmc_init(struct tegra_pmc *pmc) 1905 { 1906 if (pmc->soc->init) 1907 pmc->soc->init(pmc); 1908 } 1909 1910 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1911 { 1912 static const char disabled[] = "emergency thermal reset disabled"; 1913 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1914 struct device *dev = pmc->dev; 1915 struct device_node *np; 1916 u32 value, checksum; 1917 1918 if (!pmc->soc->has_tsense_reset) 1919 return; 1920 1921 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1922 if (!np) { 1923 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1924 return; 1925 } 1926 1927 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1928 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1929 goto out; 1930 } 1931 1932 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1933 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1934 goto out; 1935 } 1936 1937 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1938 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1939 goto out; 1940 } 1941 1942 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1943 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1944 goto out; 1945 } 1946 1947 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1948 pinmux = 0; 1949 1950 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1951 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1952 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1953 1954 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1955 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1956 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1957 1958 value = PMC_SCRATCH55_RESET_TEGRA; 1959 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1960 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1961 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1962 1963 /* 1964 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1965 * contain the checksum and are currently zero, so they are not added. 1966 */ 1967 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1968 + ((value >> 24) & 0xff); 1969 checksum &= 0xff; 1970 checksum = 0x100 - checksum; 1971 1972 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1973 1974 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1975 1976 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1977 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1978 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1979 1980 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1981 1982 out: 1983 of_node_put(np); 1984 } 1985 1986 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1987 { 1988 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1989 1990 return pmc->soc->num_io_pads; 1991 } 1992 1993 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 1994 unsigned int group) 1995 { 1996 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 1997 1998 return pmc->soc->io_pads[group].name; 1999 } 2000 2001 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2002 unsigned int group, 2003 const unsigned int **pins, 2004 unsigned int *num_pins) 2005 { 2006 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2007 2008 *pins = &pmc->soc->io_pads[group].id; 2009 *num_pins = 1; 2010 2011 return 0; 2012 } 2013 2014 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2015 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2016 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2017 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2018 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2019 .dt_free_map = pinconf_generic_dt_free_map, 2020 }; 2021 2022 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2023 unsigned int pin, unsigned long *config) 2024 { 2025 enum pin_config_param param = pinconf_to_config_param(*config); 2026 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2027 const struct tegra_io_pad_soc *pad; 2028 int ret; 2029 u32 arg; 2030 2031 pad = tegra_io_pad_find(pmc, pin); 2032 if (!pad) 2033 return -EINVAL; 2034 2035 switch (param) { 2036 case PIN_CONFIG_POWER_SOURCE: 2037 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2038 if (ret < 0) 2039 return ret; 2040 2041 arg = ret; 2042 break; 2043 2044 case PIN_CONFIG_MODE_LOW_POWER: 2045 ret = tegra_io_pad_is_powered(pmc, pad->id); 2046 if (ret < 0) 2047 return ret; 2048 2049 arg = !ret; 2050 break; 2051 2052 default: 2053 return -EINVAL; 2054 } 2055 2056 *config = pinconf_to_config_packed(param, arg); 2057 2058 return 0; 2059 } 2060 2061 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2062 unsigned int pin, unsigned long *configs, 2063 unsigned int num_configs) 2064 { 2065 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2066 const struct tegra_io_pad_soc *pad; 2067 enum pin_config_param param; 2068 unsigned int i; 2069 int err; 2070 u32 arg; 2071 2072 pad = tegra_io_pad_find(pmc, pin); 2073 if (!pad) 2074 return -EINVAL; 2075 2076 for (i = 0; i < num_configs; ++i) { 2077 param = pinconf_to_config_param(configs[i]); 2078 arg = pinconf_to_config_argument(configs[i]); 2079 2080 switch (param) { 2081 case PIN_CONFIG_MODE_LOW_POWER: 2082 if (arg) 2083 err = tegra_io_pad_power_disable(pad->id); 2084 else 2085 err = tegra_io_pad_power_enable(pad->id); 2086 if (err) 2087 return err; 2088 break; 2089 case PIN_CONFIG_POWER_SOURCE: 2090 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2091 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2092 return -EINVAL; 2093 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2094 if (err) 2095 return err; 2096 break; 2097 default: 2098 return -EINVAL; 2099 } 2100 } 2101 2102 return 0; 2103 } 2104 2105 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2106 .pin_config_get = tegra_io_pad_pinconf_get, 2107 .pin_config_set = tegra_io_pad_pinconf_set, 2108 .is_generic = true, 2109 }; 2110 2111 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2112 .pctlops = &tegra_io_pad_pinctrl_ops, 2113 .confops = &tegra_io_pad_pinconf_ops, 2114 }; 2115 2116 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2117 { 2118 int err; 2119 2120 if (!pmc->soc->num_pin_descs) 2121 return 0; 2122 2123 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2124 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2125 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2126 2127 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2128 pmc); 2129 if (IS_ERR(pmc->pctl_dev)) { 2130 err = PTR_ERR(pmc->pctl_dev); 2131 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2132 err); 2133 return err; 2134 } 2135 2136 return 0; 2137 } 2138 2139 static ssize_t reset_reason_show(struct device *dev, 2140 struct device_attribute *attr, char *buf) 2141 { 2142 u32 value; 2143 2144 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2145 value &= pmc->soc->regs->rst_source_mask; 2146 value >>= pmc->soc->regs->rst_source_shift; 2147 2148 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2149 return sprintf(buf, "%s\n", "UNKNOWN"); 2150 2151 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2152 } 2153 2154 static DEVICE_ATTR_RO(reset_reason); 2155 2156 static ssize_t reset_level_show(struct device *dev, 2157 struct device_attribute *attr, char *buf) 2158 { 2159 u32 value; 2160 2161 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2162 value &= pmc->soc->regs->rst_level_mask; 2163 value >>= pmc->soc->regs->rst_level_shift; 2164 2165 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2166 return sprintf(buf, "%s\n", "UNKNOWN"); 2167 2168 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2169 } 2170 2171 static DEVICE_ATTR_RO(reset_level); 2172 2173 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2174 { 2175 struct device *dev = pmc->dev; 2176 int err = 0; 2177 2178 if (pmc->soc->reset_sources) { 2179 err = device_create_file(dev, &dev_attr_reset_reason); 2180 if (err < 0) 2181 dev_warn(dev, 2182 "failed to create attr \"reset_reason\": %d\n", 2183 err); 2184 } 2185 2186 if (pmc->soc->reset_levels) { 2187 err = device_create_file(dev, &dev_attr_reset_level); 2188 if (err < 0) 2189 dev_warn(dev, 2190 "failed to create attr \"reset_level\": %d\n", 2191 err); 2192 } 2193 } 2194 2195 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2196 struct irq_fwspec *fwspec, 2197 unsigned long *hwirq, 2198 unsigned int *type) 2199 { 2200 if (WARN_ON(fwspec->param_count < 2)) 2201 return -EINVAL; 2202 2203 *hwirq = fwspec->param[0]; 2204 *type = fwspec->param[1]; 2205 2206 return 0; 2207 } 2208 2209 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2210 unsigned int num_irqs, void *data) 2211 { 2212 struct tegra_pmc *pmc = domain->host_data; 2213 const struct tegra_pmc_soc *soc = pmc->soc; 2214 struct irq_fwspec *fwspec = data; 2215 unsigned int i; 2216 int err = 0; 2217 2218 if (WARN_ON(num_irqs > 1)) 2219 return -EINVAL; 2220 2221 for (i = 0; i < soc->num_wake_events; i++) { 2222 const struct tegra_wake_event *event = &soc->wake_events[i]; 2223 2224 if (fwspec->param_count == 2) { 2225 struct irq_fwspec spec; 2226 2227 if (event->id != fwspec->param[0]) 2228 continue; 2229 2230 err = irq_domain_set_hwirq_and_chip(domain, virq, 2231 event->id, 2232 &pmc->irq, pmc); 2233 if (err < 0) 2234 break; 2235 2236 spec.fwnode = &pmc->dev->of_node->fwnode; 2237 spec.param_count = 3; 2238 spec.param[0] = GIC_SPI; 2239 spec.param[1] = event->irq; 2240 spec.param[2] = fwspec->param[1]; 2241 2242 err = irq_domain_alloc_irqs_parent(domain, virq, 2243 num_irqs, &spec); 2244 2245 break; 2246 } 2247 2248 if (fwspec->param_count == 3) { 2249 if (event->gpio.instance != fwspec->param[0] || 2250 event->gpio.pin != fwspec->param[1]) 2251 continue; 2252 2253 err = irq_domain_set_hwirq_and_chip(domain, virq, 2254 event->id, 2255 &pmc->irq, pmc); 2256 2257 /* GPIO hierarchies stop at the PMC level */ 2258 if (!err && domain->parent) 2259 err = irq_domain_disconnect_hierarchy(domain->parent, 2260 virq); 2261 break; 2262 } 2263 } 2264 2265 /* If there is no wake-up event, there is no PMC mapping */ 2266 if (i == soc->num_wake_events) 2267 err = irq_domain_disconnect_hierarchy(domain, virq); 2268 2269 return err; 2270 } 2271 2272 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2273 .translate = tegra_pmc_irq_translate, 2274 .alloc = tegra_pmc_irq_alloc, 2275 }; 2276 2277 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2278 { 2279 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2280 unsigned int offset, bit; 2281 u32 value; 2282 2283 offset = data->hwirq / 32; 2284 bit = data->hwirq % 32; 2285 2286 /* clear wake status */ 2287 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2288 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2289 2290 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2291 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2292 2293 /* enable PMC wake */ 2294 if (data->hwirq >= 32) 2295 offset = PMC_WAKE2_MASK; 2296 else 2297 offset = PMC_WAKE_MASK; 2298 2299 value = tegra_pmc_readl(pmc, offset); 2300 2301 if (on) 2302 value |= BIT(bit); 2303 else 2304 value &= ~BIT(bit); 2305 2306 tegra_pmc_writel(pmc, value, offset); 2307 2308 return 0; 2309 } 2310 2311 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2312 { 2313 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2314 unsigned int offset, bit; 2315 u32 value; 2316 2317 offset = data->hwirq / 32; 2318 bit = data->hwirq % 32; 2319 2320 if (data->hwirq >= 32) 2321 offset = PMC_WAKE2_LEVEL; 2322 else 2323 offset = PMC_WAKE_LEVEL; 2324 2325 value = tegra_pmc_readl(pmc, offset); 2326 2327 switch (type) { 2328 case IRQ_TYPE_EDGE_RISING: 2329 case IRQ_TYPE_LEVEL_HIGH: 2330 value |= BIT(bit); 2331 break; 2332 2333 case IRQ_TYPE_EDGE_FALLING: 2334 case IRQ_TYPE_LEVEL_LOW: 2335 value &= ~BIT(bit); 2336 break; 2337 2338 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2339 value ^= BIT(bit); 2340 break; 2341 2342 default: 2343 return -EINVAL; 2344 } 2345 2346 tegra_pmc_writel(pmc, value, offset); 2347 2348 return 0; 2349 } 2350 2351 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2352 { 2353 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2354 unsigned int offset, bit; 2355 u32 value; 2356 2357 offset = data->hwirq / 32; 2358 bit = data->hwirq % 32; 2359 2360 /* clear wake status */ 2361 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2362 2363 /* route wake to tier 2 */ 2364 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2365 2366 if (!on) 2367 value &= ~(1 << bit); 2368 else 2369 value |= 1 << bit; 2370 2371 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2372 2373 /* enable wakeup event */ 2374 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2375 2376 return 0; 2377 } 2378 2379 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2380 { 2381 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2382 u32 value; 2383 2384 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2385 2386 switch (type) { 2387 case IRQ_TYPE_EDGE_RISING: 2388 case IRQ_TYPE_LEVEL_HIGH: 2389 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2390 break; 2391 2392 case IRQ_TYPE_EDGE_FALLING: 2393 case IRQ_TYPE_LEVEL_LOW: 2394 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2395 break; 2396 2397 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2398 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2399 break; 2400 2401 default: 2402 return -EINVAL; 2403 } 2404 2405 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2406 2407 return 0; 2408 } 2409 2410 static void tegra_irq_mask_parent(struct irq_data *data) 2411 { 2412 if (data->parent_data) 2413 irq_chip_mask_parent(data); 2414 } 2415 2416 static void tegra_irq_unmask_parent(struct irq_data *data) 2417 { 2418 if (data->parent_data) 2419 irq_chip_unmask_parent(data); 2420 } 2421 2422 static void tegra_irq_eoi_parent(struct irq_data *data) 2423 { 2424 if (data->parent_data) 2425 irq_chip_eoi_parent(data); 2426 } 2427 2428 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2429 const struct cpumask *dest, 2430 bool force) 2431 { 2432 if (data->parent_data) 2433 return irq_chip_set_affinity_parent(data, dest, force); 2434 2435 return -EINVAL; 2436 } 2437 2438 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2439 { 2440 struct irq_domain *parent = NULL; 2441 struct device_node *np; 2442 2443 np = of_irq_find_parent(pmc->dev->of_node); 2444 if (np) { 2445 parent = irq_find_host(np); 2446 of_node_put(np); 2447 } 2448 2449 if (!parent) 2450 return 0; 2451 2452 pmc->irq.name = dev_name(pmc->dev); 2453 pmc->irq.irq_mask = tegra_irq_mask_parent; 2454 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2455 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2456 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2457 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2458 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2459 2460 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, 2461 &tegra_pmc_irq_domain_ops, pmc); 2462 if (!pmc->domain) { 2463 dev_err(pmc->dev, "failed to allocate domain\n"); 2464 return -ENOMEM; 2465 } 2466 2467 return 0; 2468 } 2469 2470 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2471 unsigned long action, void *ptr) 2472 { 2473 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2474 struct clk_notifier_data *data = ptr; 2475 2476 switch (action) { 2477 case PRE_RATE_CHANGE: 2478 mutex_lock(&pmc->powergates_lock); 2479 break; 2480 2481 case POST_RATE_CHANGE: 2482 pmc->rate = data->new_rate; 2483 fallthrough; 2484 2485 case ABORT_RATE_CHANGE: 2486 mutex_unlock(&pmc->powergates_lock); 2487 break; 2488 2489 default: 2490 WARN_ON_ONCE(1); 2491 return notifier_from_errno(-EINVAL); 2492 } 2493 2494 return NOTIFY_OK; 2495 } 2496 2497 static void pmc_clk_fence_udelay(u32 offset) 2498 { 2499 tegra_pmc_readl(pmc, offset); 2500 /* pmc clk propagation delay 2 us */ 2501 udelay(2); 2502 } 2503 2504 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2505 { 2506 struct pmc_clk *clk = to_pmc_clk(hw); 2507 u32 val; 2508 2509 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2510 val &= PMC_CLK_OUT_MUX_MASK; 2511 2512 return val; 2513 } 2514 2515 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2516 { 2517 struct pmc_clk *clk = to_pmc_clk(hw); 2518 u32 val; 2519 2520 val = tegra_pmc_readl(pmc, clk->offs); 2521 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2522 val |= index << clk->mux_shift; 2523 tegra_pmc_writel(pmc, val, clk->offs); 2524 pmc_clk_fence_udelay(clk->offs); 2525 2526 return 0; 2527 } 2528 2529 static int pmc_clk_is_enabled(struct clk_hw *hw) 2530 { 2531 struct pmc_clk *clk = to_pmc_clk(hw); 2532 u32 val; 2533 2534 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2535 2536 return val ? 1 : 0; 2537 } 2538 2539 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2540 { 2541 u32 val; 2542 2543 val = tegra_pmc_readl(pmc, offs); 2544 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2545 tegra_pmc_writel(pmc, val, offs); 2546 pmc_clk_fence_udelay(offs); 2547 } 2548 2549 static int pmc_clk_enable(struct clk_hw *hw) 2550 { 2551 struct pmc_clk *clk = to_pmc_clk(hw); 2552 2553 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2554 2555 return 0; 2556 } 2557 2558 static void pmc_clk_disable(struct clk_hw *hw) 2559 { 2560 struct pmc_clk *clk = to_pmc_clk(hw); 2561 2562 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2563 } 2564 2565 static const struct clk_ops pmc_clk_ops = { 2566 .get_parent = pmc_clk_mux_get_parent, 2567 .set_parent = pmc_clk_mux_set_parent, 2568 .determine_rate = __clk_mux_determine_rate, 2569 .is_enabled = pmc_clk_is_enabled, 2570 .enable = pmc_clk_enable, 2571 .disable = pmc_clk_disable, 2572 }; 2573 2574 static struct clk * 2575 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2576 const struct pmc_clk_init_data *data, 2577 unsigned long offset) 2578 { 2579 struct clk_init_data init; 2580 struct pmc_clk *pmc_clk; 2581 2582 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2583 if (!pmc_clk) 2584 return ERR_PTR(-ENOMEM); 2585 2586 init.name = data->name; 2587 init.ops = &pmc_clk_ops; 2588 init.parent_names = data->parents; 2589 init.num_parents = data->num_parents; 2590 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2591 CLK_SET_PARENT_GATE; 2592 2593 pmc_clk->hw.init = &init; 2594 pmc_clk->offs = offset; 2595 pmc_clk->mux_shift = data->mux_shift; 2596 pmc_clk->force_en_shift = data->force_en_shift; 2597 2598 return clk_register(NULL, &pmc_clk->hw); 2599 } 2600 2601 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2602 { 2603 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2604 2605 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2606 } 2607 2608 static int pmc_clk_gate_enable(struct clk_hw *hw) 2609 { 2610 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2611 2612 pmc_clk_set_state(gate->offs, gate->shift, 1); 2613 2614 return 0; 2615 } 2616 2617 static void pmc_clk_gate_disable(struct clk_hw *hw) 2618 { 2619 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2620 2621 pmc_clk_set_state(gate->offs, gate->shift, 0); 2622 } 2623 2624 static const struct clk_ops pmc_clk_gate_ops = { 2625 .is_enabled = pmc_clk_gate_is_enabled, 2626 .enable = pmc_clk_gate_enable, 2627 .disable = pmc_clk_gate_disable, 2628 }; 2629 2630 static struct clk * 2631 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2632 const char *parent_name, unsigned long offset, 2633 u32 shift) 2634 { 2635 struct clk_init_data init; 2636 struct pmc_clk_gate *gate; 2637 2638 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2639 if (!gate) 2640 return ERR_PTR(-ENOMEM); 2641 2642 init.name = name; 2643 init.ops = &pmc_clk_gate_ops; 2644 init.parent_names = &parent_name; 2645 init.num_parents = 1; 2646 init.flags = 0; 2647 2648 gate->hw.init = &init; 2649 gate->offs = offset; 2650 gate->shift = shift; 2651 2652 return clk_register(NULL, &gate->hw); 2653 } 2654 2655 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2656 struct device_node *np) 2657 { 2658 struct clk *clk; 2659 struct clk_onecell_data *clk_data; 2660 unsigned int num_clks; 2661 int i, err; 2662 2663 num_clks = pmc->soc->num_pmc_clks; 2664 if (pmc->soc->has_blink_output) 2665 num_clks += 1; 2666 2667 if (!num_clks) 2668 return; 2669 2670 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2671 if (!clk_data) 2672 return; 2673 2674 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2675 sizeof(*clk_data->clks), GFP_KERNEL); 2676 if (!clk_data->clks) 2677 return; 2678 2679 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2680 2681 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2682 clk_data->clks[i] = ERR_PTR(-ENOENT); 2683 2684 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2685 const struct pmc_clk_init_data *data; 2686 2687 data = pmc->soc->pmc_clks_data + i; 2688 2689 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2690 if (IS_ERR(clk)) { 2691 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2692 data->name, PTR_ERR_OR_ZERO(clk)); 2693 return; 2694 } 2695 2696 err = clk_register_clkdev(clk, data->name, NULL); 2697 if (err) { 2698 dev_warn(pmc->dev, 2699 "unable to register %s clock lookup: %d\n", 2700 data->name, err); 2701 return; 2702 } 2703 2704 clk_data->clks[data->clk_id] = clk; 2705 } 2706 2707 if (pmc->soc->has_blink_output) { 2708 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2709 clk = tegra_pmc_clk_gate_register(pmc, 2710 "pmc_blink_override", 2711 "clk_32k", 2712 PMC_DPD_PADS_ORIDE, 2713 PMC_DPD_PADS_ORIDE_BLINK); 2714 if (IS_ERR(clk)) { 2715 dev_warn(pmc->dev, 2716 "unable to register pmc_blink_override: %d\n", 2717 PTR_ERR_OR_ZERO(clk)); 2718 return; 2719 } 2720 2721 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2722 "pmc_blink_override", 2723 PMC_CNTRL, 2724 PMC_CNTRL_BLINK_EN); 2725 if (IS_ERR(clk)) { 2726 dev_warn(pmc->dev, 2727 "unable to register pmc_blink: %d\n", 2728 PTR_ERR_OR_ZERO(clk)); 2729 return; 2730 } 2731 2732 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2733 if (err) { 2734 dev_warn(pmc->dev, 2735 "unable to register pmc_blink lookup: %d\n", 2736 err); 2737 return; 2738 } 2739 2740 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2741 } 2742 2743 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2744 if (err) 2745 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2746 err); 2747 } 2748 2749 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 2750 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 2751 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 2752 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 2753 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 2754 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 2755 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 2756 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 2757 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 2758 }; 2759 2760 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 2761 .yes_ranges = pmc_usb_sleepwalk_ranges, 2762 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 2763 }; 2764 2765 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 2766 { 2767 struct tegra_pmc *pmc = context; 2768 2769 *value = tegra_pmc_readl(pmc, offset); 2770 return 0; 2771 } 2772 2773 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 2774 { 2775 struct tegra_pmc *pmc = context; 2776 2777 tegra_pmc_writel(pmc, value, offset); 2778 return 0; 2779 } 2780 2781 static const struct regmap_config usb_sleepwalk_regmap_config = { 2782 .name = "usb_sleepwalk", 2783 .reg_bits = 32, 2784 .val_bits = 32, 2785 .reg_stride = 4, 2786 .fast_io = true, 2787 .rd_table = &pmc_usb_sleepwalk_table, 2788 .wr_table = &pmc_usb_sleepwalk_table, 2789 .reg_read = tegra_pmc_regmap_readl, 2790 .reg_write = tegra_pmc_regmap_writel, 2791 }; 2792 2793 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 2794 { 2795 struct regmap *regmap; 2796 int err; 2797 2798 if (pmc->soc->has_usb_sleepwalk) { 2799 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 2800 if (IS_ERR(regmap)) { 2801 err = PTR_ERR(regmap); 2802 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 2803 return err; 2804 } 2805 } 2806 2807 return 0; 2808 } 2809 2810 static void tegra_pmc_reset_suspend_mode(void *data) 2811 { 2812 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 2813 } 2814 2815 static int tegra_pmc_probe(struct platform_device *pdev) 2816 { 2817 void __iomem *base; 2818 struct resource *res; 2819 int err; 2820 2821 /* 2822 * Early initialisation should have configured an initial 2823 * register mapping and setup the soc data pointer. If these 2824 * are not valid then something went badly wrong! 2825 */ 2826 if (WARN_ON(!pmc->base || !pmc->soc)) 2827 return -ENODEV; 2828 2829 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2830 if (err < 0) 2831 return err; 2832 2833 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 2834 NULL); 2835 if (err) 2836 return err; 2837 2838 /* take over the memory region from the early initialization */ 2839 base = devm_platform_ioremap_resource(pdev, 0); 2840 if (IS_ERR(base)) 2841 return PTR_ERR(base); 2842 2843 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 2844 if (res) { 2845 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 2846 if (IS_ERR(pmc->wake)) 2847 return PTR_ERR(pmc->wake); 2848 } else { 2849 pmc->wake = base; 2850 } 2851 2852 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 2853 if (res) { 2854 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 2855 if (IS_ERR(pmc->aotag)) 2856 return PTR_ERR(pmc->aotag); 2857 } else { 2858 pmc->aotag = base; 2859 } 2860 2861 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 2862 if (res) { 2863 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2864 if (IS_ERR(pmc->scratch)) 2865 return PTR_ERR(pmc->scratch); 2866 } else { 2867 pmc->scratch = base; 2868 } 2869 2870 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 2871 if (IS_ERR(pmc->clk)) { 2872 err = PTR_ERR(pmc->clk); 2873 2874 if (err != -ENOENT) { 2875 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 2876 return err; 2877 } 2878 2879 pmc->clk = NULL; 2880 } 2881 2882 /* 2883 * PCLK clock rate can't be retrieved using CLK API because it 2884 * causes lockup if CPU enters LP2 idle state from some other 2885 * CLK notifier, hence we're caching the rate's value locally. 2886 */ 2887 if (pmc->clk) { 2888 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 2889 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); 2890 if (err) { 2891 dev_err(&pdev->dev, 2892 "failed to register clk notifier\n"); 2893 return err; 2894 } 2895 2896 pmc->rate = clk_get_rate(pmc->clk); 2897 } 2898 2899 pmc->dev = &pdev->dev; 2900 2901 tegra_pmc_init(pmc); 2902 2903 tegra_pmc_init_tsense_reset(pmc); 2904 2905 tegra_pmc_reset_sysfs_init(pmc); 2906 2907 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2908 err = tegra_powergate_debugfs_init(); 2909 if (err < 0) 2910 goto cleanup_sysfs; 2911 } 2912 2913 err = devm_register_reboot_notifier(&pdev->dev, 2914 &tegra_pmc_reboot_notifier); 2915 if (err) { 2916 dev_err(&pdev->dev, "unable to register reboot notifier, %d\n", 2917 err); 2918 goto cleanup_debugfs; 2919 } 2920 2921 err = register_restart_handler(&tegra_pmc_restart_handler); 2922 if (err) { 2923 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 2924 err); 2925 goto cleanup_debugfs; 2926 } 2927 2928 err = tegra_pmc_pinctrl_init(pmc); 2929 if (err) 2930 goto cleanup_restart_handler; 2931 2932 err = tegra_pmc_regmap_init(pmc); 2933 if (err < 0) 2934 goto cleanup_restart_handler; 2935 2936 err = tegra_powergate_init(pmc, pdev->dev.of_node); 2937 if (err < 0) 2938 goto cleanup_powergates; 2939 2940 err = tegra_pmc_irq_init(pmc); 2941 if (err < 0) 2942 goto cleanup_powergates; 2943 2944 mutex_lock(&pmc->powergates_lock); 2945 iounmap(pmc->base); 2946 pmc->base = base; 2947 mutex_unlock(&pmc->powergates_lock); 2948 2949 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 2950 platform_set_drvdata(pdev, pmc); 2951 tegra_pm_init_suspend(); 2952 2953 return 0; 2954 2955 cleanup_powergates: 2956 tegra_powergate_remove_all(pdev->dev.of_node); 2957 cleanup_restart_handler: 2958 unregister_restart_handler(&tegra_pmc_restart_handler); 2959 cleanup_debugfs: 2960 debugfs_remove(pmc->debugfs); 2961 cleanup_sysfs: 2962 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 2963 device_remove_file(&pdev->dev, &dev_attr_reset_level); 2964 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); 2965 2966 return err; 2967 } 2968 2969 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2970 static int tegra_pmc_suspend(struct device *dev) 2971 { 2972 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2973 2974 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 2975 2976 return 0; 2977 } 2978 2979 static int tegra_pmc_resume(struct device *dev) 2980 { 2981 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2982 2983 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 2984 2985 return 0; 2986 } 2987 2988 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 2989 2990 #endif 2991 2992 static const char * const tegra20_powergates[] = { 2993 [TEGRA_POWERGATE_CPU] = "cpu", 2994 [TEGRA_POWERGATE_3D] = "td", 2995 [TEGRA_POWERGATE_VENC] = "venc", 2996 [TEGRA_POWERGATE_VDEC] = "vdec", 2997 [TEGRA_POWERGATE_PCIE] = "pcie", 2998 [TEGRA_POWERGATE_L2] = "l2", 2999 [TEGRA_POWERGATE_MPE] = "mpe", 3000 }; 3001 3002 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3003 .scratch0 = 0x50, 3004 .dpd_req = 0x1b8, 3005 .dpd_status = 0x1bc, 3006 .dpd2_req = 0x1c0, 3007 .dpd2_status = 0x1c4, 3008 .rst_status = 0x1b4, 3009 .rst_source_shift = 0x0, 3010 .rst_source_mask = 0x7, 3011 .rst_level_shift = 0x0, 3012 .rst_level_mask = 0x0, 3013 }; 3014 3015 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3016 { 3017 u32 value, osc, pmu, off; 3018 3019 /* Always enable CPU power request */ 3020 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3021 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3022 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3023 3024 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3025 3026 if (pmc->sysclkreq_high) 3027 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3028 else 3029 value |= PMC_CNTRL_SYSCLK_POLARITY; 3030 3031 if (pmc->corereq_high) 3032 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3033 else 3034 value |= PMC_CNTRL_PWRREQ_POLARITY; 3035 3036 /* configure the output polarity while the request is tristated */ 3037 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3038 3039 /* now enable the request */ 3040 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3041 value |= PMC_CNTRL_SYSCLK_OE; 3042 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3043 3044 /* program core timings which are applicable only for suspend state */ 3045 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3046 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3047 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3048 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3049 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3050 PMC_COREPWRGOOD_TIMER); 3051 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3052 } 3053 } 3054 3055 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3056 struct device_node *np, 3057 bool invert) 3058 { 3059 u32 value; 3060 3061 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3062 3063 if (invert) 3064 value |= PMC_CNTRL_INTR_POLARITY; 3065 else 3066 value &= ~PMC_CNTRL_INTR_POLARITY; 3067 3068 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3069 } 3070 3071 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3072 .supports_core_domain = true, 3073 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3074 .powergates = tegra20_powergates, 3075 .num_cpu_powergates = 0, 3076 .cpu_powergates = NULL, 3077 .has_tsense_reset = false, 3078 .has_gpu_clamps = false, 3079 .needs_mbist_war = false, 3080 .has_impl_33v_pwr = false, 3081 .maybe_tz_only = false, 3082 .num_io_pads = 0, 3083 .io_pads = NULL, 3084 .num_pin_descs = 0, 3085 .pin_descs = NULL, 3086 .regs = &tegra20_pmc_regs, 3087 .init = tegra20_pmc_init, 3088 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3089 .powergate_set = tegra20_powergate_set, 3090 .reset_sources = NULL, 3091 .num_reset_sources = 0, 3092 .reset_levels = NULL, 3093 .num_reset_levels = 0, 3094 .pmc_clks_data = NULL, 3095 .num_pmc_clks = 0, 3096 .has_blink_output = true, 3097 .has_usb_sleepwalk = true, 3098 }; 3099 3100 static const char * const tegra30_powergates[] = { 3101 [TEGRA_POWERGATE_CPU] = "cpu0", 3102 [TEGRA_POWERGATE_3D] = "td", 3103 [TEGRA_POWERGATE_VENC] = "venc", 3104 [TEGRA_POWERGATE_VDEC] = "vdec", 3105 [TEGRA_POWERGATE_PCIE] = "pcie", 3106 [TEGRA_POWERGATE_L2] = "l2", 3107 [TEGRA_POWERGATE_MPE] = "mpe", 3108 [TEGRA_POWERGATE_HEG] = "heg", 3109 [TEGRA_POWERGATE_SATA] = "sata", 3110 [TEGRA_POWERGATE_CPU1] = "cpu1", 3111 [TEGRA_POWERGATE_CPU2] = "cpu2", 3112 [TEGRA_POWERGATE_CPU3] = "cpu3", 3113 [TEGRA_POWERGATE_CELP] = "celp", 3114 [TEGRA_POWERGATE_3D1] = "td2", 3115 }; 3116 3117 static const u8 tegra30_cpu_powergates[] = { 3118 TEGRA_POWERGATE_CPU, 3119 TEGRA_POWERGATE_CPU1, 3120 TEGRA_POWERGATE_CPU2, 3121 TEGRA_POWERGATE_CPU3, 3122 }; 3123 3124 static const char * const tegra30_reset_sources[] = { 3125 "POWER_ON_RESET", 3126 "WATCHDOG", 3127 "SENSOR", 3128 "SW_MAIN", 3129 "LP0" 3130 }; 3131 3132 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3133 .supports_core_domain = true, 3134 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3135 .powergates = tegra30_powergates, 3136 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3137 .cpu_powergates = tegra30_cpu_powergates, 3138 .has_tsense_reset = true, 3139 .has_gpu_clamps = false, 3140 .needs_mbist_war = false, 3141 .has_impl_33v_pwr = false, 3142 .maybe_tz_only = false, 3143 .num_io_pads = 0, 3144 .io_pads = NULL, 3145 .num_pin_descs = 0, 3146 .pin_descs = NULL, 3147 .regs = &tegra20_pmc_regs, 3148 .init = tegra20_pmc_init, 3149 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3150 .powergate_set = tegra20_powergate_set, 3151 .reset_sources = tegra30_reset_sources, 3152 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3153 .reset_levels = NULL, 3154 .num_reset_levels = 0, 3155 .pmc_clks_data = tegra_pmc_clks_data, 3156 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3157 .has_blink_output = true, 3158 .has_usb_sleepwalk = true, 3159 }; 3160 3161 static const char * const tegra114_powergates[] = { 3162 [TEGRA_POWERGATE_CPU] = "crail", 3163 [TEGRA_POWERGATE_3D] = "td", 3164 [TEGRA_POWERGATE_VENC] = "venc", 3165 [TEGRA_POWERGATE_VDEC] = "vdec", 3166 [TEGRA_POWERGATE_MPE] = "mpe", 3167 [TEGRA_POWERGATE_HEG] = "heg", 3168 [TEGRA_POWERGATE_CPU1] = "cpu1", 3169 [TEGRA_POWERGATE_CPU2] = "cpu2", 3170 [TEGRA_POWERGATE_CPU3] = "cpu3", 3171 [TEGRA_POWERGATE_CELP] = "celp", 3172 [TEGRA_POWERGATE_CPU0] = "cpu0", 3173 [TEGRA_POWERGATE_C0NC] = "c0nc", 3174 [TEGRA_POWERGATE_C1NC] = "c1nc", 3175 [TEGRA_POWERGATE_DIS] = "dis", 3176 [TEGRA_POWERGATE_DISB] = "disb", 3177 [TEGRA_POWERGATE_XUSBA] = "xusba", 3178 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3179 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3180 }; 3181 3182 static const u8 tegra114_cpu_powergates[] = { 3183 TEGRA_POWERGATE_CPU0, 3184 TEGRA_POWERGATE_CPU1, 3185 TEGRA_POWERGATE_CPU2, 3186 TEGRA_POWERGATE_CPU3, 3187 }; 3188 3189 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3190 .supports_core_domain = false, 3191 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3192 .powergates = tegra114_powergates, 3193 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3194 .cpu_powergates = tegra114_cpu_powergates, 3195 .has_tsense_reset = true, 3196 .has_gpu_clamps = false, 3197 .needs_mbist_war = false, 3198 .has_impl_33v_pwr = false, 3199 .maybe_tz_only = false, 3200 .num_io_pads = 0, 3201 .io_pads = NULL, 3202 .num_pin_descs = 0, 3203 .pin_descs = NULL, 3204 .regs = &tegra20_pmc_regs, 3205 .init = tegra20_pmc_init, 3206 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3207 .powergate_set = tegra114_powergate_set, 3208 .reset_sources = tegra30_reset_sources, 3209 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3210 .reset_levels = NULL, 3211 .num_reset_levels = 0, 3212 .pmc_clks_data = tegra_pmc_clks_data, 3213 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3214 .has_blink_output = true, 3215 .has_usb_sleepwalk = true, 3216 }; 3217 3218 static const char * const tegra124_powergates[] = { 3219 [TEGRA_POWERGATE_CPU] = "crail", 3220 [TEGRA_POWERGATE_3D] = "3d", 3221 [TEGRA_POWERGATE_VENC] = "venc", 3222 [TEGRA_POWERGATE_PCIE] = "pcie", 3223 [TEGRA_POWERGATE_VDEC] = "vdec", 3224 [TEGRA_POWERGATE_MPE] = "mpe", 3225 [TEGRA_POWERGATE_HEG] = "heg", 3226 [TEGRA_POWERGATE_SATA] = "sata", 3227 [TEGRA_POWERGATE_CPU1] = "cpu1", 3228 [TEGRA_POWERGATE_CPU2] = "cpu2", 3229 [TEGRA_POWERGATE_CPU3] = "cpu3", 3230 [TEGRA_POWERGATE_CELP] = "celp", 3231 [TEGRA_POWERGATE_CPU0] = "cpu0", 3232 [TEGRA_POWERGATE_C0NC] = "c0nc", 3233 [TEGRA_POWERGATE_C1NC] = "c1nc", 3234 [TEGRA_POWERGATE_SOR] = "sor", 3235 [TEGRA_POWERGATE_DIS] = "dis", 3236 [TEGRA_POWERGATE_DISB] = "disb", 3237 [TEGRA_POWERGATE_XUSBA] = "xusba", 3238 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3239 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3240 [TEGRA_POWERGATE_VIC] = "vic", 3241 [TEGRA_POWERGATE_IRAM] = "iram", 3242 }; 3243 3244 static const u8 tegra124_cpu_powergates[] = { 3245 TEGRA_POWERGATE_CPU0, 3246 TEGRA_POWERGATE_CPU1, 3247 TEGRA_POWERGATE_CPU2, 3248 TEGRA_POWERGATE_CPU3, 3249 }; 3250 3251 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 3252 ((struct tegra_io_pad_soc) { \ 3253 .id = (_id), \ 3254 .dpd = (_dpd), \ 3255 .voltage = (_voltage), \ 3256 .name = (_name), \ 3257 }) 3258 3259 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 3260 ((struct pinctrl_pin_desc) { \ 3261 .number = (_id), \ 3262 .name = (_name) \ 3263 }) 3264 3265 #define TEGRA124_IO_PAD_TABLE(_pad) \ 3266 /* .id .dpd .voltage .name */ \ 3267 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3268 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 3269 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 3270 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 3271 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3272 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 3273 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 3274 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3275 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 3276 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 3277 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 3278 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 3279 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3280 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 3281 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 3282 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3283 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 3284 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 3285 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 3286 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3287 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3288 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 3289 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 3290 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 3291 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 3292 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3293 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3294 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3295 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3296 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 3297 3298 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3299 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 3300 }; 3301 3302 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3303 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3304 }; 3305 3306 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3307 .supports_core_domain = false, 3308 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3309 .powergates = tegra124_powergates, 3310 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3311 .cpu_powergates = tegra124_cpu_powergates, 3312 .has_tsense_reset = true, 3313 .has_gpu_clamps = true, 3314 .needs_mbist_war = false, 3315 .has_impl_33v_pwr = false, 3316 .maybe_tz_only = false, 3317 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3318 .io_pads = tegra124_io_pads, 3319 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3320 .pin_descs = tegra124_pin_descs, 3321 .regs = &tegra20_pmc_regs, 3322 .init = tegra20_pmc_init, 3323 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3324 .powergate_set = tegra114_powergate_set, 3325 .reset_sources = tegra30_reset_sources, 3326 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3327 .reset_levels = NULL, 3328 .num_reset_levels = 0, 3329 .pmc_clks_data = tegra_pmc_clks_data, 3330 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3331 .has_blink_output = true, 3332 .has_usb_sleepwalk = true, 3333 }; 3334 3335 static const char * const tegra210_powergates[] = { 3336 [TEGRA_POWERGATE_CPU] = "crail", 3337 [TEGRA_POWERGATE_3D] = "3d", 3338 [TEGRA_POWERGATE_VENC] = "venc", 3339 [TEGRA_POWERGATE_PCIE] = "pcie", 3340 [TEGRA_POWERGATE_MPE] = "mpe", 3341 [TEGRA_POWERGATE_SATA] = "sata", 3342 [TEGRA_POWERGATE_CPU1] = "cpu1", 3343 [TEGRA_POWERGATE_CPU2] = "cpu2", 3344 [TEGRA_POWERGATE_CPU3] = "cpu3", 3345 [TEGRA_POWERGATE_CPU0] = "cpu0", 3346 [TEGRA_POWERGATE_C0NC] = "c0nc", 3347 [TEGRA_POWERGATE_SOR] = "sor", 3348 [TEGRA_POWERGATE_DIS] = "dis", 3349 [TEGRA_POWERGATE_DISB] = "disb", 3350 [TEGRA_POWERGATE_XUSBA] = "xusba", 3351 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3352 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3353 [TEGRA_POWERGATE_VIC] = "vic", 3354 [TEGRA_POWERGATE_IRAM] = "iram", 3355 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3356 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3357 [TEGRA_POWERGATE_AUD] = "aud", 3358 [TEGRA_POWERGATE_DFD] = "dfd", 3359 [TEGRA_POWERGATE_VE2] = "ve2", 3360 }; 3361 3362 static const u8 tegra210_cpu_powergates[] = { 3363 TEGRA_POWERGATE_CPU0, 3364 TEGRA_POWERGATE_CPU1, 3365 TEGRA_POWERGATE_CPU2, 3366 TEGRA_POWERGATE_CPU3, 3367 }; 3368 3369 #define TEGRA210_IO_PAD_TABLE(_pad) \ 3370 /* .id .dpd .voltage .name */ \ 3371 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 3372 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 3373 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 3374 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3375 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3376 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 3377 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 3378 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 3379 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 3380 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 3381 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 3382 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 3383 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 3384 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3385 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 3386 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 3387 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 3388 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 3389 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 3390 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 3391 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 3392 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3393 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 3394 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3395 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 3396 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 3397 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3398 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 3399 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 3400 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 3401 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 3402 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 3403 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 3404 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3405 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3406 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3407 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 3408 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 3409 3410 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3411 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 3412 }; 3413 3414 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3415 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3416 }; 3417 3418 static const char * const tegra210_reset_sources[] = { 3419 "POWER_ON_RESET", 3420 "WATCHDOG", 3421 "SENSOR", 3422 "SW_MAIN", 3423 "LP0", 3424 "AOTAG" 3425 }; 3426 3427 static const struct tegra_wake_event tegra210_wake_events[] = { 3428 TEGRA_WAKE_IRQ("rtc", 16, 2), 3429 TEGRA_WAKE_IRQ("pmu", 51, 86), 3430 }; 3431 3432 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3433 .supports_core_domain = false, 3434 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3435 .powergates = tegra210_powergates, 3436 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3437 .cpu_powergates = tegra210_cpu_powergates, 3438 .has_tsense_reset = true, 3439 .has_gpu_clamps = true, 3440 .needs_mbist_war = true, 3441 .has_impl_33v_pwr = false, 3442 .maybe_tz_only = true, 3443 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3444 .io_pads = tegra210_io_pads, 3445 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3446 .pin_descs = tegra210_pin_descs, 3447 .regs = &tegra20_pmc_regs, 3448 .init = tegra20_pmc_init, 3449 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3450 .powergate_set = tegra114_powergate_set, 3451 .irq_set_wake = tegra210_pmc_irq_set_wake, 3452 .irq_set_type = tegra210_pmc_irq_set_type, 3453 .reset_sources = tegra210_reset_sources, 3454 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3455 .reset_levels = NULL, 3456 .num_reset_levels = 0, 3457 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3458 .wake_events = tegra210_wake_events, 3459 .pmc_clks_data = tegra_pmc_clks_data, 3460 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3461 .has_blink_output = true, 3462 .has_usb_sleepwalk = true, 3463 }; 3464 3465 #define TEGRA186_IO_PAD_TABLE(_pad) \ 3466 /* .id .dpd .voltage .name */ \ 3467 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3468 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3469 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3470 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3471 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3472 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3473 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3474 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3475 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3476 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3477 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3478 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 3479 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3480 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3481 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3482 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3483 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3484 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3485 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3486 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 3487 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3488 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3489 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 3490 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 3491 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 3492 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3493 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3494 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3495 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3496 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3497 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3498 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 3499 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3500 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3501 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3502 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3503 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3504 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3505 3506 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3507 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 3508 }; 3509 3510 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3511 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3512 }; 3513 3514 static const struct tegra_pmc_regs tegra186_pmc_regs = { 3515 .scratch0 = 0x2000, 3516 .dpd_req = 0x74, 3517 .dpd_status = 0x78, 3518 .dpd2_req = 0x7c, 3519 .dpd2_status = 0x80, 3520 .rst_status = 0x70, 3521 .rst_source_shift = 0x2, 3522 .rst_source_mask = 0x3c, 3523 .rst_level_shift = 0x0, 3524 .rst_level_mask = 0x3, 3525 }; 3526 3527 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3528 struct device_node *np, 3529 bool invert) 3530 { 3531 struct resource regs; 3532 void __iomem *wake; 3533 u32 value; 3534 int index; 3535 3536 index = of_property_match_string(np, "reg-names", "wake"); 3537 if (index < 0) { 3538 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3539 return; 3540 } 3541 3542 of_address_to_resource(np, index, ®s); 3543 3544 wake = ioremap(regs.start, resource_size(®s)); 3545 if (!wake) { 3546 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3547 return; 3548 } 3549 3550 value = readl(wake + WAKE_AOWAKE_CTRL); 3551 3552 if (invert) 3553 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3554 else 3555 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3556 3557 writel(value, wake + WAKE_AOWAKE_CTRL); 3558 3559 iounmap(wake); 3560 } 3561 3562 static const char * const tegra186_reset_sources[] = { 3563 "SYS_RESET", 3564 "AOWDT", 3565 "MCCPLEXWDT", 3566 "BPMPWDT", 3567 "SCEWDT", 3568 "SPEWDT", 3569 "APEWDT", 3570 "BCCPLEXWDT", 3571 "SENSOR", 3572 "AOTAG", 3573 "VFSENSOR", 3574 "SWREST", 3575 "SC7", 3576 "HSM", 3577 "CORESIGHT" 3578 }; 3579 3580 static const char * const tegra186_reset_levels[] = { 3581 "L0", "L1", "L2", "WARM" 3582 }; 3583 3584 static const struct tegra_wake_event tegra186_wake_events[] = { 3585 TEGRA_WAKE_IRQ("pmu", 24, 209), 3586 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3587 TEGRA_WAKE_IRQ("rtc", 73, 10), 3588 }; 3589 3590 static const struct tegra_pmc_soc tegra186_pmc_soc = { 3591 .supports_core_domain = false, 3592 .num_powergates = 0, 3593 .powergates = NULL, 3594 .num_cpu_powergates = 0, 3595 .cpu_powergates = NULL, 3596 .has_tsense_reset = false, 3597 .has_gpu_clamps = false, 3598 .needs_mbist_war = false, 3599 .has_impl_33v_pwr = true, 3600 .maybe_tz_only = false, 3601 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3602 .io_pads = tegra186_io_pads, 3603 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3604 .pin_descs = tegra186_pin_descs, 3605 .regs = &tegra186_pmc_regs, 3606 .init = NULL, 3607 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3608 .irq_set_wake = tegra186_pmc_irq_set_wake, 3609 .irq_set_type = tegra186_pmc_irq_set_type, 3610 .reset_sources = tegra186_reset_sources, 3611 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3612 .reset_levels = tegra186_reset_levels, 3613 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3614 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3615 .wake_events = tegra186_wake_events, 3616 .pmc_clks_data = NULL, 3617 .num_pmc_clks = 0, 3618 .has_blink_output = false, 3619 .has_usb_sleepwalk = false, 3620 }; 3621 3622 #define TEGRA194_IO_PAD_TABLE(_pad) \ 3623 /* .id .dpd .voltage .name */ \ 3624 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3625 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3626 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3627 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3628 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3629 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3630 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3631 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \ 3632 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \ 3633 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \ 3634 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \ 3635 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \ 3636 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3637 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \ 3638 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \ 3639 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3640 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \ 3641 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \ 3642 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \ 3643 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \ 3644 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \ 3645 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \ 3646 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \ 3647 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3648 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \ 3649 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \ 3650 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3651 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3652 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3653 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \ 3654 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \ 3655 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \ 3656 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3657 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \ 3658 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3659 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3660 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3661 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3662 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3663 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3664 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3665 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \ 3666 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \ 3667 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3668 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3669 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3670 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3671 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3672 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3673 3674 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3675 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD) 3676 }; 3677 3678 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 3679 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3680 }; 3681 3682 static const struct tegra_pmc_regs tegra194_pmc_regs = { 3683 .scratch0 = 0x2000, 3684 .dpd_req = 0x74, 3685 .dpd_status = 0x78, 3686 .dpd2_req = 0x7c, 3687 .dpd2_status = 0x80, 3688 .rst_status = 0x70, 3689 .rst_source_shift = 0x2, 3690 .rst_source_mask = 0x7c, 3691 .rst_level_shift = 0x0, 3692 .rst_level_mask = 0x3, 3693 }; 3694 3695 static const char * const tegra194_reset_sources[] = { 3696 "SYS_RESET_N", 3697 "AOWDT", 3698 "BCCPLEXWDT", 3699 "BPMPWDT", 3700 "SCEWDT", 3701 "SPEWDT", 3702 "APEWDT", 3703 "LCCPLEXWDT", 3704 "SENSOR", 3705 "AOTAG", 3706 "VFSENSOR", 3707 "MAINSWRST", 3708 "SC7", 3709 "HSM", 3710 "CSITE", 3711 "RCEWDT", 3712 "PVA0WDT", 3713 "PVA1WDT", 3714 "L1A_ASYNC", 3715 "BPMPBOOT", 3716 "FUSECRC", 3717 }; 3718 3719 static const struct tegra_wake_event tegra194_wake_events[] = { 3720 TEGRA_WAKE_IRQ("pmu", 24, 209), 3721 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 3722 TEGRA_WAKE_IRQ("rtc", 73, 10), 3723 }; 3724 3725 static const struct tegra_pmc_soc tegra194_pmc_soc = { 3726 .supports_core_domain = false, 3727 .num_powergates = 0, 3728 .powergates = NULL, 3729 .num_cpu_powergates = 0, 3730 .cpu_powergates = NULL, 3731 .has_tsense_reset = false, 3732 .has_gpu_clamps = false, 3733 .needs_mbist_war = false, 3734 .has_impl_33v_pwr = true, 3735 .maybe_tz_only = false, 3736 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 3737 .io_pads = tegra194_io_pads, 3738 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 3739 .pin_descs = tegra194_pin_descs, 3740 .regs = &tegra194_pmc_regs, 3741 .init = NULL, 3742 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3743 .irq_set_wake = tegra186_pmc_irq_set_wake, 3744 .irq_set_type = tegra186_pmc_irq_set_type, 3745 .reset_sources = tegra194_reset_sources, 3746 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 3747 .reset_levels = tegra186_reset_levels, 3748 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3749 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 3750 .wake_events = tegra194_wake_events, 3751 .pmc_clks_data = NULL, 3752 .num_pmc_clks = 0, 3753 .has_blink_output = false, 3754 .has_usb_sleepwalk = false, 3755 }; 3756 3757 static const struct tegra_pmc_regs tegra234_pmc_regs = { 3758 .scratch0 = 0x2000, 3759 .dpd_req = 0, 3760 .dpd_status = 0, 3761 .dpd2_req = 0, 3762 .dpd2_status = 0, 3763 .rst_status = 0x70, 3764 .rst_source_shift = 0x2, 3765 .rst_source_mask = 0xfc, 3766 .rst_level_shift = 0x0, 3767 .rst_level_mask = 0x3, 3768 }; 3769 3770 static const char * const tegra234_reset_sources[] = { 3771 "SYS_RESET_N", /* 0x0 */ 3772 "AOWDT", 3773 "BCCPLEXWDT", 3774 "BPMPWDT", 3775 "SCEWDT", 3776 "SPEWDT", 3777 "APEWDT", 3778 "LCCPLEXWDT", 3779 "SENSOR", /* 0x8 */ 3780 NULL, 3781 NULL, 3782 "MAINSWRST", 3783 "SC7", 3784 "HSM", 3785 NULL, 3786 "RCEWDT", 3787 NULL, /* 0x10 */ 3788 NULL, 3789 NULL, 3790 "BPMPBOOT", 3791 "FUSECRC", 3792 "DCEWDT", 3793 "PSCWDT", 3794 "PSC", 3795 "CSITE_SW", /* 0x18 */ 3796 "POD", 3797 "SCPM", 3798 "VREFRO_POWERBAD", 3799 "VMON", 3800 "FMON", 3801 "FSI_R5WDT", 3802 "FSI_THERM", 3803 "FSI_R52C0WDT", /* 0x20 */ 3804 "FSI_R52C1WDT", 3805 "FSI_R52C2WDT", 3806 "FSI_R52C3WDT", 3807 "FSI_FMON", 3808 "FSI_VMON", /* 0x25 */ 3809 }; 3810 3811 static const struct tegra_wake_event tegra234_wake_events[] = { 3812 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 3813 TEGRA_WAKE_IRQ("rtc", 73, 10), 3814 }; 3815 3816 static const struct tegra_pmc_soc tegra234_pmc_soc = { 3817 .supports_core_domain = false, 3818 .num_powergates = 0, 3819 .powergates = NULL, 3820 .num_cpu_powergates = 0, 3821 .cpu_powergates = NULL, 3822 .has_tsense_reset = false, 3823 .has_gpu_clamps = false, 3824 .needs_mbist_war = false, 3825 .has_impl_33v_pwr = true, 3826 .maybe_tz_only = false, 3827 .num_io_pads = 0, 3828 .io_pads = NULL, 3829 .num_pin_descs = 0, 3830 .pin_descs = NULL, 3831 .regs = &tegra234_pmc_regs, 3832 .init = NULL, 3833 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3834 .irq_set_wake = tegra186_pmc_irq_set_wake, 3835 .irq_set_type = tegra186_pmc_irq_set_type, 3836 .reset_sources = tegra234_reset_sources, 3837 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 3838 .reset_levels = tegra186_reset_levels, 3839 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3840 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 3841 .wake_events = tegra234_wake_events, 3842 .pmc_clks_data = NULL, 3843 .num_pmc_clks = 0, 3844 .has_blink_output = false, 3845 }; 3846 3847 static const struct of_device_id tegra_pmc_match[] = { 3848 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 3849 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 3850 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 3851 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 3852 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 3853 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 3854 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 3855 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 3856 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 3857 { } 3858 }; 3859 3860 static void tegra_pmc_sync_state(struct device *dev) 3861 { 3862 int err; 3863 3864 /* 3865 * Newer device-trees have power domains, but we need to prepare all 3866 * device drivers with runtime PM and OPP support first, otherwise 3867 * state syncing is unsafe. 3868 */ 3869 if (!pmc->soc->supports_core_domain) 3870 return; 3871 3872 /* 3873 * Older device-trees don't have core PD, and thus, there are 3874 * no dependencies that will block the state syncing. We shouldn't 3875 * mark the domain as synced in this case. 3876 */ 3877 if (!pmc->core_domain_registered) 3878 return; 3879 3880 pmc->core_domain_state_synced = true; 3881 3882 /* this is a no-op if core regulator isn't used */ 3883 mutex_lock(&pmc->powergates_lock); 3884 err = dev_pm_opp_sync_regulators(dev); 3885 mutex_unlock(&pmc->powergates_lock); 3886 3887 if (err) 3888 dev_err(dev, "failed to sync regulators: %d\n", err); 3889 } 3890 3891 static struct platform_driver tegra_pmc_driver = { 3892 .driver = { 3893 .name = "tegra-pmc", 3894 .suppress_bind_attrs = true, 3895 .of_match_table = tegra_pmc_match, 3896 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3897 .pm = &tegra_pmc_pm_ops, 3898 #endif 3899 .sync_state = tegra_pmc_sync_state, 3900 }, 3901 .probe = tegra_pmc_probe, 3902 }; 3903 builtin_platform_driver(tegra_pmc_driver); 3904 3905 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 3906 { 3907 u32 value, saved; 3908 3909 saved = readl(pmc->base + pmc->soc->regs->scratch0); 3910 value = saved ^ 0xffffffff; 3911 3912 if (value == 0xffffffff) 3913 value = 0xdeadbeef; 3914 3915 /* write pattern and read it back */ 3916 writel(value, pmc->base + pmc->soc->regs->scratch0); 3917 value = readl(pmc->base + pmc->soc->regs->scratch0); 3918 3919 /* if we read all-zeroes, access is restricted to TZ only */ 3920 if (value == 0) { 3921 pr_info("access to PMC is restricted to TZ\n"); 3922 return true; 3923 } 3924 3925 /* restore original value */ 3926 writel(saved, pmc->base + pmc->soc->regs->scratch0); 3927 3928 return false; 3929 } 3930 3931 /* 3932 * Early initialization to allow access to registers in the very early boot 3933 * process. 3934 */ 3935 static int __init tegra_pmc_early_init(void) 3936 { 3937 const struct of_device_id *match; 3938 struct device_node *np; 3939 struct resource regs; 3940 unsigned int i; 3941 bool invert; 3942 3943 mutex_init(&pmc->powergates_lock); 3944 3945 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 3946 if (!np) { 3947 /* 3948 * Fall back to legacy initialization for 32-bit ARM only. All 3949 * 64-bit ARM device tree files for Tegra are required to have 3950 * a PMC node. 3951 * 3952 * This is for backwards-compatibility with old device trees 3953 * that didn't contain a PMC node. Note that in this case the 3954 * SoC data can't be matched and therefore powergating is 3955 * disabled. 3956 */ 3957 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 3958 pr_warn("DT node not found, powergating disabled\n"); 3959 3960 regs.start = 0x7000e400; 3961 regs.end = 0x7000e7ff; 3962 regs.flags = IORESOURCE_MEM; 3963 3964 pr_warn("Using memory region %pR\n", ®s); 3965 } else { 3966 /* 3967 * At this point we're not running on Tegra, so play 3968 * nice with multi-platform kernels. 3969 */ 3970 return 0; 3971 } 3972 } else { 3973 /* 3974 * Extract information from the device tree if we've found a 3975 * matching node. 3976 */ 3977 if (of_address_to_resource(np, 0, ®s) < 0) { 3978 pr_err("failed to get PMC registers\n"); 3979 of_node_put(np); 3980 return -ENXIO; 3981 } 3982 } 3983 3984 pmc->base = ioremap(regs.start, resource_size(®s)); 3985 if (!pmc->base) { 3986 pr_err("failed to map PMC registers\n"); 3987 of_node_put(np); 3988 return -ENXIO; 3989 } 3990 3991 if (np) { 3992 pmc->soc = match->data; 3993 3994 if (pmc->soc->maybe_tz_only) 3995 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 3996 3997 /* Create a bitmap of the available and valid partitions */ 3998 for (i = 0; i < pmc->soc->num_powergates; i++) 3999 if (pmc->soc->powergates[i]) 4000 set_bit(i, pmc->powergates_available); 4001 4002 /* 4003 * Invert the interrupt polarity if a PMC device tree node 4004 * exists and contains the nvidia,invert-interrupt property. 4005 */ 4006 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 4007 4008 pmc->soc->setup_irq_polarity(pmc, np, invert); 4009 4010 of_node_put(np); 4011 } 4012 4013 return 0; 4014 } 4015 early_initcall(tegra_pmc_early_init); 4016