1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/io.h> 27 #include <linux/iopoll.h> 28 #include <linux/irqdomain.h> 29 #include <linux/irq.h> 30 #include <linux/kernel.h> 31 #include <linux/of_address.h> 32 #include <linux/of_clk.h> 33 #include <linux/of.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_platform.h> 36 #include <linux/pinctrl/pinconf-generic.h> 37 #include <linux/pinctrl/pinconf.h> 38 #include <linux/pinctrl/pinctrl.h> 39 #include <linux/platform_device.h> 40 #include <linux/pm_domain.h> 41 #include <linux/pm_opp.h> 42 #include <linux/power_supply.h> 43 #include <linux/reboot.h> 44 #include <linux/regmap.h> 45 #include <linux/reset.h> 46 #include <linux/seq_file.h> 47 #include <linux/slab.h> 48 #include <linux/spinlock.h> 49 50 #include <soc/tegra/common.h> 51 #include <soc/tegra/fuse.h> 52 #include <soc/tegra/pmc.h> 53 54 #include <dt-bindings/interrupt-controller/arm-gic.h> 55 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 56 #include <dt-bindings/gpio/tegra186-gpio.h> 57 #include <dt-bindings/gpio/tegra194-gpio.h> 58 #include <dt-bindings/gpio/tegra234-gpio.h> 59 #include <dt-bindings/soc/tegra-pmc.h> 60 61 #define PMC_CNTRL 0x0 62 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 63 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 64 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 65 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 66 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 67 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 68 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 69 #define PMC_CNTRL_BLINK_EN 7 70 #define PMC_CNTRL_MAIN_RST BIT(4) 71 72 #define PMC_WAKE_MASK 0x0c 73 #define PMC_WAKE_LEVEL 0x10 74 #define PMC_WAKE_STATUS 0x14 75 #define PMC_SW_WAKE_STATUS 0x18 76 #define PMC_DPD_PADS_ORIDE 0x1c 77 #define PMC_DPD_PADS_ORIDE_BLINK 20 78 79 #define DPD_SAMPLE 0x020 80 #define DPD_SAMPLE_ENABLE BIT(0) 81 #define DPD_SAMPLE_DISABLE (0 << 0) 82 83 #define PWRGATE_TOGGLE 0x30 84 #define PWRGATE_TOGGLE_START BIT(8) 85 86 #define REMOVE_CLAMPING 0x34 87 88 #define PWRGATE_STATUS 0x38 89 90 #define PMC_BLINK_TIMER 0x40 91 #define PMC_IMPL_E_33V_PWR 0x40 92 93 #define PMC_PWR_DET 0x48 94 95 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 96 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 97 #define PMC_SCRATCH0_MODE_RCM BIT(1) 98 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 99 PMC_SCRATCH0_MODE_BOOTLOADER | \ 100 PMC_SCRATCH0_MODE_RCM) 101 102 #define PMC_CPUPWRGOOD_TIMER 0xc8 103 #define PMC_CPUPWROFF_TIMER 0xcc 104 #define PMC_COREPWRGOOD_TIMER 0x3c 105 #define PMC_COREPWROFF_TIMER 0xe0 106 107 #define PMC_PWR_DET_VALUE 0xe4 108 109 #define PMC_USB_DEBOUNCE_DEL 0xec 110 #define PMC_USB_AO 0xf0 111 112 #define PMC_SCRATCH37 0x130 113 #define PMC_SCRATCH41 0x140 114 115 #define PMC_WAKE2_MASK 0x160 116 #define PMC_WAKE2_LEVEL 0x164 117 #define PMC_WAKE2_STATUS 0x168 118 #define PMC_SW_WAKE2_STATUS 0x16c 119 120 #define PMC_CLK_OUT_CNTRL 0x1a8 121 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 122 #define PMC_SENSOR_CTRL 0x1b0 123 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 124 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 125 126 #define PMC_RST_STATUS_POR 0 127 #define PMC_RST_STATUS_WATCHDOG 1 128 #define PMC_RST_STATUS_SENSOR 2 129 #define PMC_RST_STATUS_SW_MAIN 3 130 #define PMC_RST_STATUS_LP0 4 131 #define PMC_RST_STATUS_AOTAG 5 132 133 #define IO_DPD_REQ 0x1b8 134 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 135 #define IO_DPD_REQ_CODE_OFF (1U << 30) 136 #define IO_DPD_REQ_CODE_ON (2U << 30) 137 #define IO_DPD_REQ_CODE_MASK (3U << 30) 138 139 #define IO_DPD_STATUS 0x1bc 140 #define IO_DPD2_REQ 0x1c0 141 #define IO_DPD2_STATUS 0x1c4 142 #define SEL_DPD_TIM 0x1c8 143 144 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec 145 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0 146 147 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8 148 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc 149 #define PMC_UTMIP_UHSIC_FAKE 0x218 150 151 #define PMC_SCRATCH54 0x258 152 #define PMC_SCRATCH54_DATA_SHIFT 8 153 #define PMC_SCRATCH54_ADDR_SHIFT 0 154 155 #define PMC_SCRATCH55 0x25c 156 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 157 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 158 #define PMC_SCRATCH55_PINMUX_SHIFT 24 159 #define PMC_SCRATCH55_16BITOP BIT(15) 160 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 161 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 162 163 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c 164 165 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270 166 #define PMC_UTMIP_MASTER_CONFIG 0x274 167 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c 168 #define PMC_UTMIP_MASTER2_CONFIG 0x29c 169 170 #define GPU_RG_CNTRL 0x2d4 171 172 #define PMC_UTMIP_PAD_CFG0 0x4c0 173 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0 174 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0 175 /* Tegra186 and later */ 176 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 177 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 178 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 179 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 180 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 181 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 182 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 183 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 184 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 185 186 #define WAKE_AOWAKE_CTRL 0x4f4 187 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 188 189 /* for secure PMC */ 190 #define TEGRA_SMC_PMC 0xc2fffe00 191 #define TEGRA_SMC_PMC_READ 0xaa 192 #define TEGRA_SMC_PMC_WRITE 0xbb 193 194 struct pmc_clk { 195 struct clk_hw hw; 196 unsigned long offs; 197 u32 mux_shift; 198 u32 force_en_shift; 199 }; 200 201 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 202 203 struct pmc_clk_gate { 204 struct clk_hw hw; 205 unsigned long offs; 206 u32 shift; 207 }; 208 209 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 210 211 struct pmc_clk_init_data { 212 char *name; 213 const char *const *parents; 214 int num_parents; 215 int clk_id; 216 u8 mux_shift; 217 u8 force_en_shift; 218 }; 219 220 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 221 "osc_div4", "extern1", 222 }; 223 224 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 225 "osc_div4", "extern2", 226 }; 227 228 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 229 "osc_div4", "extern3", 230 }; 231 232 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 233 { 234 .name = "pmc_clk_out_1", 235 .parents = clk_out1_parents, 236 .num_parents = ARRAY_SIZE(clk_out1_parents), 237 .clk_id = TEGRA_PMC_CLK_OUT_1, 238 .mux_shift = 6, 239 .force_en_shift = 2, 240 }, 241 { 242 .name = "pmc_clk_out_2", 243 .parents = clk_out2_parents, 244 .num_parents = ARRAY_SIZE(clk_out2_parents), 245 .clk_id = TEGRA_PMC_CLK_OUT_2, 246 .mux_shift = 14, 247 .force_en_shift = 10, 248 }, 249 { 250 .name = "pmc_clk_out_3", 251 .parents = clk_out3_parents, 252 .num_parents = ARRAY_SIZE(clk_out3_parents), 253 .clk_id = TEGRA_PMC_CLK_OUT_3, 254 .mux_shift = 22, 255 .force_en_shift = 18, 256 }, 257 }; 258 259 struct tegra_powergate { 260 struct generic_pm_domain genpd; 261 struct tegra_pmc *pmc; 262 unsigned int id; 263 struct clk **clks; 264 unsigned int num_clks; 265 unsigned long *clk_rates; 266 struct reset_control *reset; 267 }; 268 269 struct tegra_io_pad_soc { 270 enum tegra_io_pad id; 271 unsigned int dpd; 272 unsigned int voltage; 273 const char *name; 274 }; 275 276 struct tegra_pmc_regs { 277 unsigned int scratch0; 278 unsigned int dpd_req; 279 unsigned int dpd_status; 280 unsigned int dpd2_req; 281 unsigned int dpd2_status; 282 unsigned int rst_status; 283 unsigned int rst_source_shift; 284 unsigned int rst_source_mask; 285 unsigned int rst_level_shift; 286 unsigned int rst_level_mask; 287 }; 288 289 struct tegra_wake_event { 290 const char *name; 291 unsigned int id; 292 unsigned int irq; 293 struct { 294 unsigned int instance; 295 unsigned int pin; 296 } gpio; 297 }; 298 299 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 300 { \ 301 .name = _name, \ 302 .id = _id, \ 303 .irq = _irq, \ 304 .gpio = { \ 305 .instance = UINT_MAX, \ 306 .pin = UINT_MAX, \ 307 }, \ 308 } 309 310 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 311 { \ 312 .name = _name, \ 313 .id = _id, \ 314 .irq = 0, \ 315 .gpio = { \ 316 .instance = _instance, \ 317 .pin = _pin, \ 318 }, \ 319 } 320 321 struct tegra_pmc_soc { 322 unsigned int num_powergates; 323 const char *const *powergates; 324 unsigned int num_cpu_powergates; 325 const u8 *cpu_powergates; 326 327 bool has_tsense_reset; 328 bool has_gpu_clamps; 329 bool needs_mbist_war; 330 bool has_impl_33v_pwr; 331 bool maybe_tz_only; 332 333 const struct tegra_io_pad_soc *io_pads; 334 unsigned int num_io_pads; 335 336 const struct pinctrl_pin_desc *pin_descs; 337 unsigned int num_pin_descs; 338 339 const struct tegra_pmc_regs *regs; 340 void (*init)(struct tegra_pmc *pmc); 341 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 342 struct device_node *np, 343 bool invert); 344 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 345 int (*irq_set_type)(struct irq_data *data, unsigned int type); 346 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, 347 bool new_state); 348 349 const char * const *reset_sources; 350 unsigned int num_reset_sources; 351 const char * const *reset_levels; 352 unsigned int num_reset_levels; 353 354 /* 355 * These describe events that can wake the system from sleep (i.e. 356 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 357 * are dealt with in the LIC. 358 */ 359 const struct tegra_wake_event *wake_events; 360 unsigned int num_wake_events; 361 362 const struct pmc_clk_init_data *pmc_clks_data; 363 unsigned int num_pmc_clks; 364 bool has_blink_output; 365 bool has_usb_sleepwalk; 366 bool supports_core_domain; 367 }; 368 369 /** 370 * struct tegra_pmc - NVIDIA Tegra PMC 371 * @dev: pointer to PMC device structure 372 * @base: pointer to I/O remapped register region 373 * @wake: pointer to I/O remapped region for WAKE registers 374 * @aotag: pointer to I/O remapped region for AOTAG registers 375 * @scratch: pointer to I/O remapped region for scratch registers 376 * @clk: pointer to pclk clock 377 * @soc: pointer to SoC data structure 378 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 379 * @debugfs: pointer to debugfs entry 380 * @rate: currently configured rate of pclk 381 * @suspend_mode: lowest suspend mode available 382 * @cpu_good_time: CPU power good time (in microseconds) 383 * @cpu_off_time: CPU power off time (in microsecends) 384 * @core_osc_time: core power good OSC time (in microseconds) 385 * @core_pmu_time: core power good PMU time (in microseconds) 386 * @core_off_time: core power off time (in microseconds) 387 * @corereq_high: core power request is active-high 388 * @sysclkreq_high: system clock request is active-high 389 * @combined_req: combined power request for CPU & core 390 * @cpu_pwr_good_en: CPU power good signal is enabled 391 * @lp0_vec_phys: physical base address of the LP0 warm boot code 392 * @lp0_vec_size: size of the LP0 warm boot code 393 * @powergates_available: Bitmap of available power gates 394 * @powergates_lock: mutex for power gate register access 395 * @pctl_dev: pin controller exposed by the PMC 396 * @domain: IRQ domain provided by the PMC 397 * @irq: chip implementation for the IRQ domain 398 * @clk_nb: pclk clock changes handler 399 * @core_domain_state_synced: flag marking the core domain's state as synced 400 * @core_domain_registered: flag marking the core domain as registered 401 */ 402 struct tegra_pmc { 403 struct device *dev; 404 void __iomem *base; 405 void __iomem *wake; 406 void __iomem *aotag; 407 void __iomem *scratch; 408 struct clk *clk; 409 struct dentry *debugfs; 410 411 const struct tegra_pmc_soc *soc; 412 bool tz_only; 413 414 unsigned long rate; 415 416 enum tegra_suspend_mode suspend_mode; 417 u32 cpu_good_time; 418 u32 cpu_off_time; 419 u32 core_osc_time; 420 u32 core_pmu_time; 421 u32 core_off_time; 422 bool corereq_high; 423 bool sysclkreq_high; 424 bool combined_req; 425 bool cpu_pwr_good_en; 426 u32 lp0_vec_phys; 427 u32 lp0_vec_size; 428 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 429 430 struct mutex powergates_lock; 431 432 struct pinctrl_dev *pctl_dev; 433 434 struct irq_domain *domain; 435 struct irq_chip irq; 436 437 struct notifier_block clk_nb; 438 439 bool core_domain_state_synced; 440 bool core_domain_registered; 441 }; 442 443 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 444 .base = NULL, 445 .suspend_mode = TEGRA_SUSPEND_NOT_READY, 446 }; 447 448 static inline struct tegra_powergate * 449 to_powergate(struct generic_pm_domain *domain) 450 { 451 return container_of(domain, struct tegra_powergate, genpd); 452 } 453 454 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 455 { 456 struct arm_smccc_res res; 457 458 if (pmc->tz_only) { 459 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 460 0, 0, 0, &res); 461 if (res.a0) { 462 if (pmc->dev) 463 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 464 __func__, res.a0); 465 else 466 pr_warn("%s(): SMC failed: %lu\n", __func__, 467 res.a0); 468 } 469 470 return res.a1; 471 } 472 473 return readl(pmc->base + offset); 474 } 475 476 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 477 unsigned long offset) 478 { 479 struct arm_smccc_res res; 480 481 if (pmc->tz_only) { 482 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 483 value, 0, 0, 0, 0, &res); 484 if (res.a0) { 485 if (pmc->dev) 486 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 487 __func__, res.a0); 488 else 489 pr_warn("%s(): SMC failed: %lu\n", __func__, 490 res.a0); 491 } 492 } else { 493 writel(value, pmc->base + offset); 494 } 495 } 496 497 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 498 { 499 if (pmc->tz_only) 500 return tegra_pmc_readl(pmc, offset); 501 502 return readl(pmc->scratch + offset); 503 } 504 505 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 506 unsigned long offset) 507 { 508 if (pmc->tz_only) 509 tegra_pmc_writel(pmc, value, offset); 510 else 511 writel(value, pmc->scratch + offset); 512 } 513 514 /* 515 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 516 * This currently doesn't work because readx_poll_timeout() can only operate 517 * on functions that take a single argument. 518 */ 519 static inline bool tegra_powergate_state(int id) 520 { 521 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 522 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 523 else 524 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 525 } 526 527 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 528 { 529 return (pmc->soc && pmc->soc->powergates[id]); 530 } 531 532 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 533 { 534 return test_bit(id, pmc->powergates_available); 535 } 536 537 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 538 { 539 unsigned int i; 540 541 if (!pmc || !pmc->soc || !name) 542 return -EINVAL; 543 544 for (i = 0; i < pmc->soc->num_powergates; i++) { 545 if (!tegra_powergate_is_valid(pmc, i)) 546 continue; 547 548 if (!strcmp(name, pmc->soc->powergates[i])) 549 return i; 550 } 551 552 return -ENODEV; 553 } 554 555 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, 556 bool new_state) 557 { 558 unsigned int retries = 100; 559 bool status; 560 int ret; 561 562 /* 563 * As per TRM documentation, the toggle command will be dropped by PMC 564 * if there is contention with a HW-initiated toggling (i.e. CPU core 565 * power-gated), the command should be retried in that case. 566 */ 567 do { 568 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 569 570 /* wait for PMC to execute the command */ 571 ret = readx_poll_timeout(tegra_powergate_state, id, status, 572 status == new_state, 1, 10); 573 } while (ret == -ETIMEDOUT && retries--); 574 575 return ret; 576 } 577 578 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) 579 { 580 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); 581 } 582 583 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, 584 bool new_state) 585 { 586 bool status; 587 int err; 588 589 /* wait while PMC power gating is contended */ 590 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 591 status == true, 1, 100); 592 if (err) 593 return err; 594 595 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 596 597 /* wait for PMC to accept the command */ 598 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, 599 status == true, 1, 100); 600 if (err) 601 return err; 602 603 /* wait for PMC to execute the command */ 604 err = readx_poll_timeout(tegra_powergate_state, id, status, 605 status == new_state, 10, 100000); 606 if (err) 607 return err; 608 609 return 0; 610 } 611 612 /** 613 * tegra_powergate_set() - set the state of a partition 614 * @pmc: power management controller 615 * @id: partition ID 616 * @new_state: new state of the partition 617 */ 618 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 619 bool new_state) 620 { 621 int err; 622 623 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 624 return -EINVAL; 625 626 mutex_lock(&pmc->powergates_lock); 627 628 if (tegra_powergate_state(id) == new_state) { 629 mutex_unlock(&pmc->powergates_lock); 630 return 0; 631 } 632 633 err = pmc->soc->powergate_set(pmc, id, new_state); 634 635 mutex_unlock(&pmc->powergates_lock); 636 637 return err; 638 } 639 640 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 641 unsigned int id) 642 { 643 u32 mask; 644 645 mutex_lock(&pmc->powergates_lock); 646 647 /* 648 * On Tegra124 and later, the clamps for the GPU are controlled by a 649 * separate register (with different semantics). 650 */ 651 if (id == TEGRA_POWERGATE_3D) { 652 if (pmc->soc->has_gpu_clamps) { 653 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 654 goto out; 655 } 656 } 657 658 /* 659 * Tegra 2 has a bug where PCIE and VDE clamping masks are 660 * swapped relatively to the partition ids 661 */ 662 if (id == TEGRA_POWERGATE_VDEC) 663 mask = (1 << TEGRA_POWERGATE_PCIE); 664 else if (id == TEGRA_POWERGATE_PCIE) 665 mask = (1 << TEGRA_POWERGATE_VDEC); 666 else 667 mask = (1 << id); 668 669 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 670 671 out: 672 mutex_unlock(&pmc->powergates_lock); 673 674 return 0; 675 } 676 677 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg) 678 { 679 unsigned long safe_rate = 100 * 1000 * 1000; 680 unsigned int i; 681 int err; 682 683 for (i = 0; i < pg->num_clks; i++) { 684 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); 685 686 if (!pg->clk_rates[i]) { 687 err = -EINVAL; 688 goto out; 689 } 690 691 if (pg->clk_rates[i] <= safe_rate) 692 continue; 693 694 /* 695 * We don't know whether voltage state is okay for the 696 * current clock rate, hence it's better to temporally 697 * switch clock to a safe rate which is suitable for 698 * all voltages, before enabling the clock. 699 */ 700 err = clk_set_rate(pg->clks[i], safe_rate); 701 if (err) 702 goto out; 703 } 704 705 return 0; 706 707 out: 708 while (i--) 709 clk_set_rate(pg->clks[i], pg->clk_rates[i]); 710 711 return err; 712 } 713 714 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg) 715 { 716 unsigned int i; 717 int err; 718 719 for (i = 0; i < pg->num_clks; i++) { 720 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); 721 if (err) 722 return err; 723 } 724 725 return 0; 726 } 727 728 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 729 { 730 unsigned int i; 731 732 for (i = 0; i < pg->num_clks; i++) 733 clk_disable_unprepare(pg->clks[i]); 734 } 735 736 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 737 { 738 unsigned int i; 739 int err; 740 741 for (i = 0; i < pg->num_clks; i++) { 742 err = clk_prepare_enable(pg->clks[i]); 743 if (err) 744 goto out; 745 } 746 747 return 0; 748 749 out: 750 while (i--) 751 clk_disable_unprepare(pg->clks[i]); 752 753 return err; 754 } 755 756 static int tegra_powergate_power_up(struct tegra_powergate *pg, 757 bool disable_clocks) 758 { 759 int err; 760 761 err = reset_control_assert(pg->reset); 762 if (err) 763 return err; 764 765 usleep_range(10, 20); 766 767 err = tegra_powergate_set(pg->pmc, pg->id, true); 768 if (err < 0) 769 return err; 770 771 usleep_range(10, 20); 772 773 err = tegra_powergate_prepare_clocks(pg); 774 if (err) 775 goto powergate_off; 776 777 err = tegra_powergate_enable_clocks(pg); 778 if (err) 779 goto unprepare_clks; 780 781 usleep_range(10, 20); 782 783 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 784 if (err) 785 goto disable_clks; 786 787 usleep_range(10, 20); 788 789 err = reset_control_deassert(pg->reset); 790 if (err) 791 goto disable_clks; 792 793 usleep_range(10, 20); 794 795 if (pg->pmc->soc->needs_mbist_war) 796 err = tegra210_clk_handle_mbist_war(pg->id); 797 if (err) 798 goto disable_clks; 799 800 if (disable_clocks) 801 tegra_powergate_disable_clocks(pg); 802 803 err = tegra_powergate_unprepare_clocks(pg); 804 if (err) 805 return err; 806 807 return 0; 808 809 disable_clks: 810 tegra_powergate_disable_clocks(pg); 811 usleep_range(10, 20); 812 813 unprepare_clks: 814 tegra_powergate_unprepare_clocks(pg); 815 816 powergate_off: 817 tegra_powergate_set(pg->pmc, pg->id, false); 818 819 return err; 820 } 821 822 static int tegra_powergate_power_down(struct tegra_powergate *pg) 823 { 824 int err; 825 826 err = tegra_powergate_prepare_clocks(pg); 827 if (err) 828 return err; 829 830 err = tegra_powergate_enable_clocks(pg); 831 if (err) 832 goto unprepare_clks; 833 834 usleep_range(10, 20); 835 836 err = reset_control_assert(pg->reset); 837 if (err) 838 goto disable_clks; 839 840 usleep_range(10, 20); 841 842 tegra_powergate_disable_clocks(pg); 843 844 usleep_range(10, 20); 845 846 err = tegra_powergate_set(pg->pmc, pg->id, false); 847 if (err) 848 goto assert_resets; 849 850 err = tegra_powergate_unprepare_clocks(pg); 851 if (err) 852 return err; 853 854 return 0; 855 856 assert_resets: 857 tegra_powergate_enable_clocks(pg); 858 usleep_range(10, 20); 859 reset_control_deassert(pg->reset); 860 usleep_range(10, 20); 861 862 disable_clks: 863 tegra_powergate_disable_clocks(pg); 864 865 unprepare_clks: 866 tegra_powergate_unprepare_clocks(pg); 867 868 return err; 869 } 870 871 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 872 { 873 struct tegra_powergate *pg = to_powergate(domain); 874 struct device *dev = pg->pmc->dev; 875 int err; 876 877 err = tegra_powergate_power_up(pg, true); 878 if (err) { 879 dev_err(dev, "failed to turn on PM domain %s: %d\n", 880 pg->genpd.name, err); 881 goto out; 882 } 883 884 reset_control_release(pg->reset); 885 886 out: 887 return err; 888 } 889 890 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 891 { 892 struct tegra_powergate *pg = to_powergate(domain); 893 struct device *dev = pg->pmc->dev; 894 int err; 895 896 err = reset_control_acquire(pg->reset); 897 if (err < 0) { 898 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n", 899 pg->genpd.name, err); 900 return err; 901 } 902 903 err = tegra_powergate_power_down(pg); 904 if (err) { 905 dev_err(dev, "failed to turn off PM domain %s: %d\n", 906 pg->genpd.name, err); 907 reset_control_release(pg->reset); 908 } 909 910 return err; 911 } 912 913 /** 914 * tegra_powergate_power_on() - power on partition 915 * @id: partition ID 916 */ 917 int tegra_powergate_power_on(unsigned int id) 918 { 919 if (!tegra_powergate_is_available(pmc, id)) 920 return -EINVAL; 921 922 return tegra_powergate_set(pmc, id, true); 923 } 924 EXPORT_SYMBOL(tegra_powergate_power_on); 925 926 /** 927 * tegra_powergate_power_off() - power off partition 928 * @id: partition ID 929 */ 930 int tegra_powergate_power_off(unsigned int id) 931 { 932 if (!tegra_powergate_is_available(pmc, id)) 933 return -EINVAL; 934 935 return tegra_powergate_set(pmc, id, false); 936 } 937 EXPORT_SYMBOL(tegra_powergate_power_off); 938 939 /** 940 * tegra_powergate_is_powered() - check if partition is powered 941 * @pmc: power management controller 942 * @id: partition ID 943 */ 944 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 945 { 946 if (!tegra_powergate_is_valid(pmc, id)) 947 return -EINVAL; 948 949 return tegra_powergate_state(id); 950 } 951 952 /** 953 * tegra_powergate_remove_clamping() - remove power clamps for partition 954 * @id: partition ID 955 */ 956 int tegra_powergate_remove_clamping(unsigned int id) 957 { 958 if (!tegra_powergate_is_available(pmc, id)) 959 return -EINVAL; 960 961 return __tegra_powergate_remove_clamping(pmc, id); 962 } 963 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 964 965 /** 966 * tegra_powergate_sequence_power_up() - power up partition 967 * @id: partition ID 968 * @clk: clock for partition 969 * @rst: reset for partition 970 * 971 * Must be called with clk disabled, and returns with clk enabled. 972 */ 973 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 974 struct reset_control *rst) 975 { 976 struct tegra_powergate *pg; 977 int err; 978 979 if (!tegra_powergate_is_available(pmc, id)) 980 return -EINVAL; 981 982 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 983 if (!pg) 984 return -ENOMEM; 985 986 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); 987 if (!pg->clk_rates) { 988 kfree(pg->clks); 989 return -ENOMEM; 990 } 991 992 pg->id = id; 993 pg->clks = &clk; 994 pg->num_clks = 1; 995 pg->reset = rst; 996 pg->pmc = pmc; 997 998 err = tegra_powergate_power_up(pg, false); 999 if (err) 1000 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 1001 err); 1002 1003 kfree(pg->clk_rates); 1004 kfree(pg); 1005 1006 return err; 1007 } 1008 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 1009 1010 /** 1011 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 1012 * @pmc: power management controller 1013 * @cpuid: CPU partition ID 1014 * 1015 * Returns the partition ID corresponding to the CPU partition ID or a 1016 * negative error code on failure. 1017 */ 1018 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 1019 unsigned int cpuid) 1020 { 1021 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 1022 return pmc->soc->cpu_powergates[cpuid]; 1023 1024 return -EINVAL; 1025 } 1026 1027 /** 1028 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 1029 * @cpuid: CPU partition ID 1030 */ 1031 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 1032 { 1033 int id; 1034 1035 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1036 if (id < 0) 1037 return false; 1038 1039 return tegra_powergate_is_powered(pmc, id); 1040 } 1041 1042 /** 1043 * tegra_pmc_cpu_power_on() - power on CPU partition 1044 * @cpuid: CPU partition ID 1045 */ 1046 int tegra_pmc_cpu_power_on(unsigned int cpuid) 1047 { 1048 int id; 1049 1050 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1051 if (id < 0) 1052 return id; 1053 1054 return tegra_powergate_set(pmc, id, true); 1055 } 1056 1057 /** 1058 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 1059 * @cpuid: CPU partition ID 1060 */ 1061 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 1062 { 1063 int id; 1064 1065 id = tegra_get_cpu_powergate_id(pmc, cpuid); 1066 if (id < 0) 1067 return id; 1068 1069 return tegra_powergate_remove_clamping(id); 1070 } 1071 1072 static void tegra_pmc_program_reboot_reason(const char *cmd) 1073 { 1074 u32 value; 1075 1076 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 1077 value &= ~PMC_SCRATCH0_MODE_MASK; 1078 1079 if (cmd) { 1080 if (strcmp(cmd, "recovery") == 0) 1081 value |= PMC_SCRATCH0_MODE_RECOVERY; 1082 1083 if (strcmp(cmd, "bootloader") == 0) 1084 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 1085 1086 if (strcmp(cmd, "forced-recovery") == 0) 1087 value |= PMC_SCRATCH0_MODE_RCM; 1088 } 1089 1090 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 1091 } 1092 1093 static int tegra_pmc_reboot_notify(struct notifier_block *this, 1094 unsigned long action, void *data) 1095 { 1096 if (action == SYS_RESTART) 1097 tegra_pmc_program_reboot_reason(data); 1098 1099 return NOTIFY_DONE; 1100 } 1101 1102 static struct notifier_block tegra_pmc_reboot_notifier = { 1103 .notifier_call = tegra_pmc_reboot_notify, 1104 }; 1105 1106 static void tegra_pmc_restart(void) 1107 { 1108 u32 value; 1109 1110 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 1111 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1112 value |= PMC_CNTRL_MAIN_RST; 1113 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1114 } 1115 1116 static int tegra_pmc_restart_handler(struct sys_off_data *data) 1117 { 1118 tegra_pmc_restart(); 1119 1120 return NOTIFY_DONE; 1121 } 1122 1123 static int tegra_pmc_power_off_handler(struct sys_off_data *data) 1124 { 1125 /* 1126 * Reboot Nexus 7 into special bootloader mode if USB cable is 1127 * connected in order to display battery status and power off. 1128 */ 1129 if (of_machine_is_compatible("asus,grouper") && 1130 power_supply_is_system_supplied()) { 1131 const u32 go_to_charger_mode = 0xa5a55a5a; 1132 1133 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37); 1134 tegra_pmc_restart(); 1135 } 1136 1137 return NOTIFY_DONE; 1138 } 1139 1140 static int powergate_show(struct seq_file *s, void *data) 1141 { 1142 unsigned int i; 1143 int status; 1144 1145 seq_printf(s, " powergate powered\n"); 1146 seq_printf(s, "------------------\n"); 1147 1148 for (i = 0; i < pmc->soc->num_powergates; i++) { 1149 status = tegra_powergate_is_powered(pmc, i); 1150 if (status < 0) 1151 continue; 1152 1153 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 1154 status ? "yes" : "no"); 1155 } 1156 1157 return 0; 1158 } 1159 1160 DEFINE_SHOW_ATTRIBUTE(powergate); 1161 1162 static int tegra_powergate_debugfs_init(void) 1163 { 1164 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 1165 &powergate_fops); 1166 if (!pmc->debugfs) 1167 return -ENOMEM; 1168 1169 return 0; 1170 } 1171 1172 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 1173 struct device_node *np) 1174 { 1175 struct clk *clk; 1176 unsigned int i, count; 1177 int err; 1178 1179 count = of_clk_get_parent_count(np); 1180 if (count == 0) 1181 return -ENODEV; 1182 1183 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 1184 if (!pg->clks) 1185 return -ENOMEM; 1186 1187 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); 1188 if (!pg->clk_rates) { 1189 kfree(pg->clks); 1190 return -ENOMEM; 1191 } 1192 1193 for (i = 0; i < count; i++) { 1194 pg->clks[i] = of_clk_get(np, i); 1195 if (IS_ERR(pg->clks[i])) { 1196 err = PTR_ERR(pg->clks[i]); 1197 goto err; 1198 } 1199 } 1200 1201 pg->num_clks = count; 1202 1203 return 0; 1204 1205 err: 1206 while (i--) 1207 clk_put(pg->clks[i]); 1208 1209 kfree(pg->clk_rates); 1210 kfree(pg->clks); 1211 1212 return err; 1213 } 1214 1215 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1216 struct device_node *np, bool off) 1217 { 1218 struct device *dev = pg->pmc->dev; 1219 int err; 1220 1221 pg->reset = of_reset_control_array_get_exclusive_released(np); 1222 if (IS_ERR(pg->reset)) { 1223 err = PTR_ERR(pg->reset); 1224 dev_err(dev, "failed to get device resets: %d\n", err); 1225 return err; 1226 } 1227 1228 err = reset_control_acquire(pg->reset); 1229 if (err < 0) { 1230 pr_err("failed to acquire resets: %d\n", err); 1231 goto out; 1232 } 1233 1234 if (off) { 1235 err = reset_control_assert(pg->reset); 1236 } else { 1237 err = reset_control_deassert(pg->reset); 1238 if (err < 0) 1239 goto out; 1240 1241 reset_control_release(pg->reset); 1242 } 1243 1244 out: 1245 if (err) { 1246 reset_control_release(pg->reset); 1247 reset_control_put(pg->reset); 1248 } 1249 1250 return err; 1251 } 1252 1253 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1254 { 1255 struct device *dev = pmc->dev; 1256 struct tegra_powergate *pg; 1257 int id, err = 0; 1258 bool off; 1259 1260 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1261 if (!pg) 1262 return -ENOMEM; 1263 1264 id = tegra_powergate_lookup(pmc, np->name); 1265 if (id < 0) { 1266 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1267 err = -ENODEV; 1268 goto free_mem; 1269 } 1270 1271 /* 1272 * Clear the bit for this powergate so it cannot be managed 1273 * directly via the legacy APIs for controlling powergates. 1274 */ 1275 clear_bit(id, pmc->powergates_available); 1276 1277 pg->id = id; 1278 pg->genpd.name = np->name; 1279 pg->genpd.power_off = tegra_genpd_power_off; 1280 pg->genpd.power_on = tegra_genpd_power_on; 1281 pg->pmc = pmc; 1282 1283 off = !tegra_powergate_is_powered(pmc, pg->id); 1284 1285 err = tegra_powergate_of_get_clks(pg, np); 1286 if (err < 0) { 1287 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1288 goto set_available; 1289 } 1290 1291 err = tegra_powergate_of_get_resets(pg, np, off); 1292 if (err < 0) { 1293 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1294 goto remove_clks; 1295 } 1296 1297 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1298 if (off) 1299 WARN_ON(tegra_powergate_power_up(pg, true)); 1300 1301 goto remove_resets; 1302 } 1303 1304 err = pm_genpd_init(&pg->genpd, NULL, off); 1305 if (err < 0) { 1306 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1307 err); 1308 goto remove_resets; 1309 } 1310 1311 err = of_genpd_add_provider_simple(np, &pg->genpd); 1312 if (err < 0) { 1313 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1314 np, err); 1315 goto remove_genpd; 1316 } 1317 1318 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1319 1320 return 0; 1321 1322 remove_genpd: 1323 pm_genpd_remove(&pg->genpd); 1324 1325 remove_resets: 1326 reset_control_put(pg->reset); 1327 1328 remove_clks: 1329 while (pg->num_clks--) 1330 clk_put(pg->clks[pg->num_clks]); 1331 1332 kfree(pg->clks); 1333 1334 set_available: 1335 set_bit(id, pmc->powergates_available); 1336 1337 free_mem: 1338 kfree(pg); 1339 1340 return err; 1341 } 1342 1343 bool tegra_pmc_core_domain_state_synced(void) 1344 { 1345 return pmc->core_domain_state_synced; 1346 } 1347 1348 static int 1349 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd, 1350 unsigned int level) 1351 { 1352 struct dev_pm_opp *opp; 1353 int err; 1354 1355 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); 1356 if (IS_ERR(opp)) { 1357 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", 1358 level, opp); 1359 return PTR_ERR(opp); 1360 } 1361 1362 mutex_lock(&pmc->powergates_lock); 1363 err = dev_pm_opp_set_opp(pmc->dev, opp); 1364 mutex_unlock(&pmc->powergates_lock); 1365 1366 dev_pm_opp_put(opp); 1367 1368 if (err) { 1369 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", 1370 level, err); 1371 return err; 1372 } 1373 1374 return 0; 1375 } 1376 1377 static unsigned int 1378 tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd, 1379 struct dev_pm_opp *opp) 1380 { 1381 return dev_pm_opp_get_level(opp); 1382 } 1383 1384 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) 1385 { 1386 struct generic_pm_domain *genpd; 1387 const char *rname[] = { "core", NULL}; 1388 int err; 1389 1390 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); 1391 if (!genpd) 1392 return -ENOMEM; 1393 1394 genpd->name = "core"; 1395 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; 1396 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; 1397 1398 err = devm_pm_opp_set_regulators(pmc->dev, rname); 1399 if (err) 1400 return dev_err_probe(pmc->dev, err, 1401 "failed to set core OPP regulator\n"); 1402 1403 err = pm_genpd_init(genpd, NULL, false); 1404 if (err) { 1405 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); 1406 return err; 1407 } 1408 1409 err = of_genpd_add_provider_simple(np, genpd); 1410 if (err) { 1411 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); 1412 goto remove_genpd; 1413 } 1414 1415 pmc->core_domain_registered = true; 1416 1417 return 0; 1418 1419 remove_genpd: 1420 pm_genpd_remove(genpd); 1421 1422 return err; 1423 } 1424 1425 static int tegra_powergate_init(struct tegra_pmc *pmc, 1426 struct device_node *parent) 1427 { 1428 struct of_phandle_args child_args, parent_args; 1429 struct device_node *np, *child; 1430 int err = 0; 1431 1432 /* 1433 * Core power domain is the parent of powergate domains, hence it 1434 * should be registered first. 1435 */ 1436 np = of_get_child_by_name(parent, "core-domain"); 1437 if (np) { 1438 err = tegra_pmc_core_pd_add(pmc, np); 1439 of_node_put(np); 1440 if (err) 1441 return err; 1442 } 1443 1444 np = of_get_child_by_name(parent, "powergates"); 1445 if (!np) 1446 return 0; 1447 1448 for_each_child_of_node(np, child) { 1449 err = tegra_powergate_add(pmc, child); 1450 if (err < 0) { 1451 of_node_put(child); 1452 break; 1453 } 1454 1455 if (of_parse_phandle_with_args(child, "power-domains", 1456 "#power-domain-cells", 1457 0, &parent_args)) 1458 continue; 1459 1460 child_args.np = child; 1461 child_args.args_count = 0; 1462 1463 err = of_genpd_add_subdomain(&parent_args, &child_args); 1464 of_node_put(parent_args.np); 1465 if (err) { 1466 of_node_put(child); 1467 break; 1468 } 1469 } 1470 1471 of_node_put(np); 1472 1473 return err; 1474 } 1475 1476 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1477 { 1478 struct tegra_powergate *pg = to_powergate(genpd); 1479 1480 reset_control_put(pg->reset); 1481 1482 while (pg->num_clks--) 1483 clk_put(pg->clks[pg->num_clks]); 1484 1485 kfree(pg->clks); 1486 1487 set_bit(pg->id, pmc->powergates_available); 1488 1489 kfree(pg); 1490 } 1491 1492 static void tegra_powergate_remove_all(struct device_node *parent) 1493 { 1494 struct generic_pm_domain *genpd; 1495 struct device_node *np, *child; 1496 1497 np = of_get_child_by_name(parent, "powergates"); 1498 if (!np) 1499 return; 1500 1501 for_each_child_of_node(np, child) { 1502 of_genpd_del_provider(child); 1503 1504 genpd = of_genpd_remove_last(child); 1505 if (IS_ERR(genpd)) 1506 continue; 1507 1508 tegra_powergate_remove(genpd); 1509 } 1510 1511 of_node_put(np); 1512 1513 np = of_get_child_by_name(parent, "core-domain"); 1514 if (np) { 1515 of_genpd_del_provider(np); 1516 of_genpd_remove_last(np); 1517 } 1518 } 1519 1520 static const struct tegra_io_pad_soc * 1521 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1522 { 1523 unsigned int i; 1524 1525 for (i = 0; i < pmc->soc->num_io_pads; i++) 1526 if (pmc->soc->io_pads[i].id == id) 1527 return &pmc->soc->io_pads[i]; 1528 1529 return NULL; 1530 } 1531 1532 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, 1533 enum tegra_io_pad id, 1534 unsigned long *request, 1535 unsigned long *status, 1536 u32 *mask) 1537 { 1538 const struct tegra_io_pad_soc *pad; 1539 1540 pad = tegra_io_pad_find(pmc, id); 1541 if (!pad) { 1542 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1543 return -ENOENT; 1544 } 1545 1546 if (pad->dpd == UINT_MAX) 1547 return -ENOTSUPP; 1548 1549 *mask = BIT(pad->dpd % 32); 1550 1551 if (pad->dpd < 32) { 1552 *status = pmc->soc->regs->dpd_status; 1553 *request = pmc->soc->regs->dpd_req; 1554 } else { 1555 *status = pmc->soc->regs->dpd2_status; 1556 *request = pmc->soc->regs->dpd2_req; 1557 } 1558 1559 return 0; 1560 } 1561 1562 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, 1563 unsigned long *request, unsigned long *status, 1564 u32 *mask) 1565 { 1566 unsigned long rate, value; 1567 int err; 1568 1569 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); 1570 if (err) 1571 return err; 1572 1573 if (pmc->clk) { 1574 rate = pmc->rate; 1575 if (!rate) { 1576 dev_err(pmc->dev, "failed to get clock rate\n"); 1577 return -ENODEV; 1578 } 1579 1580 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1581 1582 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1583 value = DIV_ROUND_UP(1000000000, rate); 1584 value = DIV_ROUND_UP(200, value); 1585 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1586 } 1587 1588 return 0; 1589 } 1590 1591 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1592 u32 mask, u32 val, unsigned long timeout) 1593 { 1594 u32 value; 1595 1596 timeout = jiffies + msecs_to_jiffies(timeout); 1597 1598 while (time_after(timeout, jiffies)) { 1599 value = tegra_pmc_readl(pmc, offset); 1600 if ((value & mask) == val) 1601 return 0; 1602 1603 usleep_range(250, 1000); 1604 } 1605 1606 return -ETIMEDOUT; 1607 } 1608 1609 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1610 { 1611 if (pmc->clk) 1612 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1613 } 1614 1615 /** 1616 * tegra_io_pad_power_enable() - enable power to I/O pad 1617 * @id: Tegra I/O pad ID for which to enable power 1618 * 1619 * Returns: 0 on success or a negative error code on failure. 1620 */ 1621 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1622 { 1623 unsigned long request, status; 1624 u32 mask; 1625 int err; 1626 1627 mutex_lock(&pmc->powergates_lock); 1628 1629 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1630 if (err < 0) { 1631 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1632 goto unlock; 1633 } 1634 1635 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1636 1637 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1638 if (err < 0) { 1639 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1640 goto unlock; 1641 } 1642 1643 tegra_io_pad_unprepare(pmc); 1644 1645 unlock: 1646 mutex_unlock(&pmc->powergates_lock); 1647 return err; 1648 } 1649 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1650 1651 /** 1652 * tegra_io_pad_power_disable() - disable power to I/O pad 1653 * @id: Tegra I/O pad ID for which to disable power 1654 * 1655 * Returns: 0 on success or a negative error code on failure. 1656 */ 1657 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1658 { 1659 unsigned long request, status; 1660 u32 mask; 1661 int err; 1662 1663 mutex_lock(&pmc->powergates_lock); 1664 1665 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1666 if (err < 0) { 1667 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1668 goto unlock; 1669 } 1670 1671 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1672 1673 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1674 if (err < 0) { 1675 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1676 goto unlock; 1677 } 1678 1679 tegra_io_pad_unprepare(pmc); 1680 1681 unlock: 1682 mutex_unlock(&pmc->powergates_lock); 1683 return err; 1684 } 1685 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1686 1687 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1688 { 1689 unsigned long request, status; 1690 u32 mask, value; 1691 int err; 1692 1693 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, 1694 &mask); 1695 if (err) 1696 return err; 1697 1698 value = tegra_pmc_readl(pmc, status); 1699 1700 return !(value & mask); 1701 } 1702 1703 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1704 int voltage) 1705 { 1706 const struct tegra_io_pad_soc *pad; 1707 u32 value; 1708 1709 pad = tegra_io_pad_find(pmc, id); 1710 if (!pad) 1711 return -ENOENT; 1712 1713 if (pad->voltage == UINT_MAX) 1714 return -ENOTSUPP; 1715 1716 mutex_lock(&pmc->powergates_lock); 1717 1718 if (pmc->soc->has_impl_33v_pwr) { 1719 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1720 1721 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1722 value &= ~BIT(pad->voltage); 1723 else 1724 value |= BIT(pad->voltage); 1725 1726 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1727 } else { 1728 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1729 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1730 value |= BIT(pad->voltage); 1731 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1732 1733 /* update I/O voltage */ 1734 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1735 1736 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1737 value &= ~BIT(pad->voltage); 1738 else 1739 value |= BIT(pad->voltage); 1740 1741 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1742 } 1743 1744 mutex_unlock(&pmc->powergates_lock); 1745 1746 usleep_range(100, 250); 1747 1748 return 0; 1749 } 1750 1751 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1752 { 1753 const struct tegra_io_pad_soc *pad; 1754 u32 value; 1755 1756 pad = tegra_io_pad_find(pmc, id); 1757 if (!pad) 1758 return -ENOENT; 1759 1760 if (pad->voltage == UINT_MAX) 1761 return -ENOTSUPP; 1762 1763 if (pmc->soc->has_impl_33v_pwr) 1764 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1765 else 1766 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1767 1768 if ((value & BIT(pad->voltage)) == 0) 1769 return TEGRA_IO_PAD_VOLTAGE_1V8; 1770 1771 return TEGRA_IO_PAD_VOLTAGE_3V3; 1772 } 1773 1774 /** 1775 * tegra_io_rail_power_on() - enable power to I/O rail 1776 * @id: Tegra I/O pad ID for which to enable power 1777 * 1778 * See also: tegra_io_pad_power_enable() 1779 */ 1780 int tegra_io_rail_power_on(unsigned int id) 1781 { 1782 return tegra_io_pad_power_enable(id); 1783 } 1784 EXPORT_SYMBOL(tegra_io_rail_power_on); 1785 1786 /** 1787 * tegra_io_rail_power_off() - disable power to I/O rail 1788 * @id: Tegra I/O pad ID for which to disable power 1789 * 1790 * See also: tegra_io_pad_power_disable() 1791 */ 1792 int tegra_io_rail_power_off(unsigned int id) 1793 { 1794 return tegra_io_pad_power_disable(id); 1795 } 1796 EXPORT_SYMBOL(tegra_io_rail_power_off); 1797 1798 #ifdef CONFIG_PM_SLEEP 1799 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1800 { 1801 return pmc->suspend_mode; 1802 } 1803 1804 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1805 { 1806 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1807 return; 1808 1809 pmc->suspend_mode = mode; 1810 } 1811 1812 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1813 { 1814 unsigned long long rate = 0; 1815 u64 ticks; 1816 u32 value; 1817 1818 switch (mode) { 1819 case TEGRA_SUSPEND_LP1: 1820 rate = 32768; 1821 break; 1822 1823 case TEGRA_SUSPEND_LP2: 1824 rate = pmc->rate; 1825 break; 1826 1827 default: 1828 break; 1829 } 1830 1831 if (WARN_ON_ONCE(rate == 0)) 1832 rate = 100000000; 1833 1834 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1835 do_div(ticks, USEC_PER_SEC); 1836 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1837 1838 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1839 do_div(ticks, USEC_PER_SEC); 1840 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1841 1842 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1843 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1844 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1845 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1846 } 1847 #endif 1848 1849 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1850 { 1851 u32 value, values[2]; 1852 1853 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1854 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1855 } else { 1856 switch (value) { 1857 case 0: 1858 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1859 break; 1860 1861 case 1: 1862 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1863 break; 1864 1865 case 2: 1866 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1867 break; 1868 1869 default: 1870 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1871 break; 1872 } 1873 } 1874 1875 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1876 1877 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1878 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1879 1880 pmc->cpu_good_time = value; 1881 1882 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1883 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1884 1885 pmc->cpu_off_time = value; 1886 1887 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1888 values, ARRAY_SIZE(values))) 1889 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1890 1891 pmc->core_osc_time = values[0]; 1892 pmc->core_pmu_time = values[1]; 1893 1894 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1895 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1896 1897 pmc->core_off_time = value; 1898 1899 pmc->corereq_high = of_property_read_bool(np, 1900 "nvidia,core-power-req-active-high"); 1901 1902 pmc->sysclkreq_high = of_property_read_bool(np, 1903 "nvidia,sys-clock-req-active-high"); 1904 1905 pmc->combined_req = of_property_read_bool(np, 1906 "nvidia,combined-power-req"); 1907 1908 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1909 "nvidia,cpu-pwr-good-en"); 1910 1911 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1912 ARRAY_SIZE(values))) 1913 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1914 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1915 1916 pmc->lp0_vec_phys = values[0]; 1917 pmc->lp0_vec_size = values[1]; 1918 1919 return 0; 1920 } 1921 1922 static void tegra_pmc_init(struct tegra_pmc *pmc) 1923 { 1924 if (pmc->soc->init) 1925 pmc->soc->init(pmc); 1926 } 1927 1928 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1929 { 1930 static const char disabled[] = "emergency thermal reset disabled"; 1931 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1932 struct device *dev = pmc->dev; 1933 struct device_node *np; 1934 u32 value, checksum; 1935 1936 if (!pmc->soc->has_tsense_reset) 1937 return; 1938 1939 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1940 if (!np) { 1941 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1942 return; 1943 } 1944 1945 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1946 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1947 goto out; 1948 } 1949 1950 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1951 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1952 goto out; 1953 } 1954 1955 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1956 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1957 goto out; 1958 } 1959 1960 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1961 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1962 goto out; 1963 } 1964 1965 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1966 pinmux = 0; 1967 1968 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1969 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1970 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1971 1972 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1973 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1974 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1975 1976 value = PMC_SCRATCH55_RESET_TEGRA; 1977 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1978 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1979 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1980 1981 /* 1982 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1983 * contain the checksum and are currently zero, so they are not added. 1984 */ 1985 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1986 + ((value >> 24) & 0xff); 1987 checksum &= 0xff; 1988 checksum = 0x100 - checksum; 1989 1990 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1991 1992 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1993 1994 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1995 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1996 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1997 1998 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1999 2000 out: 2001 of_node_put(np); 2002 } 2003 2004 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 2005 { 2006 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2007 2008 return pmc->soc->num_io_pads; 2009 } 2010 2011 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 2012 unsigned int group) 2013 { 2014 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 2015 2016 return pmc->soc->io_pads[group].name; 2017 } 2018 2019 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 2020 unsigned int group, 2021 const unsigned int **pins, 2022 unsigned int *num_pins) 2023 { 2024 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2025 2026 *pins = &pmc->soc->io_pads[group].id; 2027 *num_pins = 1; 2028 2029 return 0; 2030 } 2031 2032 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 2033 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 2034 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 2035 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 2036 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2037 .dt_free_map = pinconf_generic_dt_free_map, 2038 }; 2039 2040 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 2041 unsigned int pin, unsigned long *config) 2042 { 2043 enum pin_config_param param = pinconf_to_config_param(*config); 2044 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2045 const struct tegra_io_pad_soc *pad; 2046 int ret; 2047 u32 arg; 2048 2049 pad = tegra_io_pad_find(pmc, pin); 2050 if (!pad) 2051 return -EINVAL; 2052 2053 switch (param) { 2054 case PIN_CONFIG_POWER_SOURCE: 2055 ret = tegra_io_pad_get_voltage(pmc, pad->id); 2056 if (ret < 0) 2057 return ret; 2058 2059 arg = ret; 2060 break; 2061 2062 case PIN_CONFIG_MODE_LOW_POWER: 2063 ret = tegra_io_pad_is_powered(pmc, pad->id); 2064 if (ret < 0) 2065 return ret; 2066 2067 arg = !ret; 2068 break; 2069 2070 default: 2071 return -EINVAL; 2072 } 2073 2074 *config = pinconf_to_config_packed(param, arg); 2075 2076 return 0; 2077 } 2078 2079 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 2080 unsigned int pin, unsigned long *configs, 2081 unsigned int num_configs) 2082 { 2083 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 2084 const struct tegra_io_pad_soc *pad; 2085 enum pin_config_param param; 2086 unsigned int i; 2087 int err; 2088 u32 arg; 2089 2090 pad = tegra_io_pad_find(pmc, pin); 2091 if (!pad) 2092 return -EINVAL; 2093 2094 for (i = 0; i < num_configs; ++i) { 2095 param = pinconf_to_config_param(configs[i]); 2096 arg = pinconf_to_config_argument(configs[i]); 2097 2098 switch (param) { 2099 case PIN_CONFIG_MODE_LOW_POWER: 2100 if (arg) 2101 err = tegra_io_pad_power_disable(pad->id); 2102 else 2103 err = tegra_io_pad_power_enable(pad->id); 2104 if (err) 2105 return err; 2106 break; 2107 case PIN_CONFIG_POWER_SOURCE: 2108 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 2109 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 2110 return -EINVAL; 2111 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 2112 if (err) 2113 return err; 2114 break; 2115 default: 2116 return -EINVAL; 2117 } 2118 } 2119 2120 return 0; 2121 } 2122 2123 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 2124 .pin_config_get = tegra_io_pad_pinconf_get, 2125 .pin_config_set = tegra_io_pad_pinconf_set, 2126 .is_generic = true, 2127 }; 2128 2129 static struct pinctrl_desc tegra_pmc_pctl_desc = { 2130 .pctlops = &tegra_io_pad_pinctrl_ops, 2131 .confops = &tegra_io_pad_pinconf_ops, 2132 }; 2133 2134 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 2135 { 2136 int err; 2137 2138 if (!pmc->soc->num_pin_descs) 2139 return 0; 2140 2141 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 2142 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 2143 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 2144 2145 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 2146 pmc); 2147 if (IS_ERR(pmc->pctl_dev)) { 2148 err = PTR_ERR(pmc->pctl_dev); 2149 dev_err(pmc->dev, "failed to register pin controller: %d\n", 2150 err); 2151 return err; 2152 } 2153 2154 return 0; 2155 } 2156 2157 static ssize_t reset_reason_show(struct device *dev, 2158 struct device_attribute *attr, char *buf) 2159 { 2160 u32 value; 2161 2162 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2163 value &= pmc->soc->regs->rst_source_mask; 2164 value >>= pmc->soc->regs->rst_source_shift; 2165 2166 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 2167 return sprintf(buf, "%s\n", "UNKNOWN"); 2168 2169 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 2170 } 2171 2172 static DEVICE_ATTR_RO(reset_reason); 2173 2174 static ssize_t reset_level_show(struct device *dev, 2175 struct device_attribute *attr, char *buf) 2176 { 2177 u32 value; 2178 2179 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 2180 value &= pmc->soc->regs->rst_level_mask; 2181 value >>= pmc->soc->regs->rst_level_shift; 2182 2183 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 2184 return sprintf(buf, "%s\n", "UNKNOWN"); 2185 2186 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 2187 } 2188 2189 static DEVICE_ATTR_RO(reset_level); 2190 2191 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 2192 { 2193 struct device *dev = pmc->dev; 2194 int err = 0; 2195 2196 if (pmc->soc->reset_sources) { 2197 err = device_create_file(dev, &dev_attr_reset_reason); 2198 if (err < 0) 2199 dev_warn(dev, 2200 "failed to create attr \"reset_reason\": %d\n", 2201 err); 2202 } 2203 2204 if (pmc->soc->reset_levels) { 2205 err = device_create_file(dev, &dev_attr_reset_level); 2206 if (err < 0) 2207 dev_warn(dev, 2208 "failed to create attr \"reset_level\": %d\n", 2209 err); 2210 } 2211 } 2212 2213 static int tegra_pmc_irq_translate(struct irq_domain *domain, 2214 struct irq_fwspec *fwspec, 2215 unsigned long *hwirq, 2216 unsigned int *type) 2217 { 2218 if (WARN_ON(fwspec->param_count < 2)) 2219 return -EINVAL; 2220 2221 *hwirq = fwspec->param[0]; 2222 *type = fwspec->param[1]; 2223 2224 return 0; 2225 } 2226 2227 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 2228 unsigned int num_irqs, void *data) 2229 { 2230 struct tegra_pmc *pmc = domain->host_data; 2231 const struct tegra_pmc_soc *soc = pmc->soc; 2232 struct irq_fwspec *fwspec = data; 2233 unsigned int i; 2234 int err = 0; 2235 2236 if (WARN_ON(num_irqs > 1)) 2237 return -EINVAL; 2238 2239 for (i = 0; i < soc->num_wake_events; i++) { 2240 const struct tegra_wake_event *event = &soc->wake_events[i]; 2241 2242 if (fwspec->param_count == 2) { 2243 struct irq_fwspec spec; 2244 2245 if (event->id != fwspec->param[0]) 2246 continue; 2247 2248 err = irq_domain_set_hwirq_and_chip(domain, virq, 2249 event->id, 2250 &pmc->irq, pmc); 2251 if (err < 0) 2252 break; 2253 2254 spec.fwnode = &pmc->dev->of_node->fwnode; 2255 spec.param_count = 3; 2256 spec.param[0] = GIC_SPI; 2257 spec.param[1] = event->irq; 2258 spec.param[2] = fwspec->param[1]; 2259 2260 err = irq_domain_alloc_irqs_parent(domain, virq, 2261 num_irqs, &spec); 2262 2263 break; 2264 } 2265 2266 if (fwspec->param_count == 3) { 2267 if (event->gpio.instance != fwspec->param[0] || 2268 event->gpio.pin != fwspec->param[1]) 2269 continue; 2270 2271 err = irq_domain_set_hwirq_and_chip(domain, virq, 2272 event->id, 2273 &pmc->irq, pmc); 2274 2275 /* GPIO hierarchies stop at the PMC level */ 2276 if (!err && domain->parent) 2277 err = irq_domain_disconnect_hierarchy(domain->parent, 2278 virq); 2279 break; 2280 } 2281 } 2282 2283 /* If there is no wake-up event, there is no PMC mapping */ 2284 if (i == soc->num_wake_events) 2285 err = irq_domain_disconnect_hierarchy(domain, virq); 2286 2287 return err; 2288 } 2289 2290 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 2291 .translate = tegra_pmc_irq_translate, 2292 .alloc = tegra_pmc_irq_alloc, 2293 }; 2294 2295 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2296 { 2297 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2298 unsigned int offset, bit; 2299 u32 value; 2300 2301 offset = data->hwirq / 32; 2302 bit = data->hwirq % 32; 2303 2304 /* clear wake status */ 2305 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 2306 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 2307 2308 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 2309 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 2310 2311 /* enable PMC wake */ 2312 if (data->hwirq >= 32) 2313 offset = PMC_WAKE2_MASK; 2314 else 2315 offset = PMC_WAKE_MASK; 2316 2317 value = tegra_pmc_readl(pmc, offset); 2318 2319 if (on) 2320 value |= BIT(bit); 2321 else 2322 value &= ~BIT(bit); 2323 2324 tegra_pmc_writel(pmc, value, offset); 2325 2326 return 0; 2327 } 2328 2329 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2330 { 2331 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2332 unsigned int offset, bit; 2333 u32 value; 2334 2335 offset = data->hwirq / 32; 2336 bit = data->hwirq % 32; 2337 2338 if (data->hwirq >= 32) 2339 offset = PMC_WAKE2_LEVEL; 2340 else 2341 offset = PMC_WAKE_LEVEL; 2342 2343 value = tegra_pmc_readl(pmc, offset); 2344 2345 switch (type) { 2346 case IRQ_TYPE_EDGE_RISING: 2347 case IRQ_TYPE_LEVEL_HIGH: 2348 value |= BIT(bit); 2349 break; 2350 2351 case IRQ_TYPE_EDGE_FALLING: 2352 case IRQ_TYPE_LEVEL_LOW: 2353 value &= ~BIT(bit); 2354 break; 2355 2356 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2357 value ^= BIT(bit); 2358 break; 2359 2360 default: 2361 return -EINVAL; 2362 } 2363 2364 tegra_pmc_writel(pmc, value, offset); 2365 2366 return 0; 2367 } 2368 2369 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2370 { 2371 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2372 unsigned int offset, bit; 2373 u32 value; 2374 2375 offset = data->hwirq / 32; 2376 bit = data->hwirq % 32; 2377 2378 /* clear wake status */ 2379 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2380 2381 /* route wake to tier 2 */ 2382 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2383 2384 if (!on) 2385 value &= ~(1 << bit); 2386 else 2387 value |= 1 << bit; 2388 2389 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2390 2391 /* enable wakeup event */ 2392 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2393 2394 return 0; 2395 } 2396 2397 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2398 { 2399 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2400 u32 value; 2401 2402 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2403 2404 switch (type) { 2405 case IRQ_TYPE_EDGE_RISING: 2406 case IRQ_TYPE_LEVEL_HIGH: 2407 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2408 break; 2409 2410 case IRQ_TYPE_EDGE_FALLING: 2411 case IRQ_TYPE_LEVEL_LOW: 2412 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2413 break; 2414 2415 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2416 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2417 break; 2418 2419 default: 2420 return -EINVAL; 2421 } 2422 2423 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2424 2425 return 0; 2426 } 2427 2428 static void tegra_irq_mask_parent(struct irq_data *data) 2429 { 2430 if (data->parent_data) 2431 irq_chip_mask_parent(data); 2432 } 2433 2434 static void tegra_irq_unmask_parent(struct irq_data *data) 2435 { 2436 if (data->parent_data) 2437 irq_chip_unmask_parent(data); 2438 } 2439 2440 static void tegra_irq_eoi_parent(struct irq_data *data) 2441 { 2442 if (data->parent_data) 2443 irq_chip_eoi_parent(data); 2444 } 2445 2446 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2447 const struct cpumask *dest, 2448 bool force) 2449 { 2450 if (data->parent_data) 2451 return irq_chip_set_affinity_parent(data, dest, force); 2452 2453 return -EINVAL; 2454 } 2455 2456 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2457 { 2458 struct irq_domain *parent = NULL; 2459 struct device_node *np; 2460 2461 np = of_irq_find_parent(pmc->dev->of_node); 2462 if (np) { 2463 parent = irq_find_host(np); 2464 of_node_put(np); 2465 } 2466 2467 if (!parent) 2468 return 0; 2469 2470 pmc->irq.name = dev_name(pmc->dev); 2471 pmc->irq.irq_mask = tegra_irq_mask_parent; 2472 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2473 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2474 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2475 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2476 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2477 2478 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, 2479 &tegra_pmc_irq_domain_ops, pmc); 2480 if (!pmc->domain) { 2481 dev_err(pmc->dev, "failed to allocate domain\n"); 2482 return -ENOMEM; 2483 } 2484 2485 return 0; 2486 } 2487 2488 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2489 unsigned long action, void *ptr) 2490 { 2491 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2492 struct clk_notifier_data *data = ptr; 2493 2494 switch (action) { 2495 case PRE_RATE_CHANGE: 2496 mutex_lock(&pmc->powergates_lock); 2497 break; 2498 2499 case POST_RATE_CHANGE: 2500 pmc->rate = data->new_rate; 2501 fallthrough; 2502 2503 case ABORT_RATE_CHANGE: 2504 mutex_unlock(&pmc->powergates_lock); 2505 break; 2506 2507 default: 2508 WARN_ON_ONCE(1); 2509 return notifier_from_errno(-EINVAL); 2510 } 2511 2512 return NOTIFY_OK; 2513 } 2514 2515 static void pmc_clk_fence_udelay(u32 offset) 2516 { 2517 tegra_pmc_readl(pmc, offset); 2518 /* pmc clk propagation delay 2 us */ 2519 udelay(2); 2520 } 2521 2522 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2523 { 2524 struct pmc_clk *clk = to_pmc_clk(hw); 2525 u32 val; 2526 2527 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2528 val &= PMC_CLK_OUT_MUX_MASK; 2529 2530 return val; 2531 } 2532 2533 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2534 { 2535 struct pmc_clk *clk = to_pmc_clk(hw); 2536 u32 val; 2537 2538 val = tegra_pmc_readl(pmc, clk->offs); 2539 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2540 val |= index << clk->mux_shift; 2541 tegra_pmc_writel(pmc, val, clk->offs); 2542 pmc_clk_fence_udelay(clk->offs); 2543 2544 return 0; 2545 } 2546 2547 static int pmc_clk_is_enabled(struct clk_hw *hw) 2548 { 2549 struct pmc_clk *clk = to_pmc_clk(hw); 2550 u32 val; 2551 2552 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2553 2554 return val ? 1 : 0; 2555 } 2556 2557 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2558 { 2559 u32 val; 2560 2561 val = tegra_pmc_readl(pmc, offs); 2562 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2563 tegra_pmc_writel(pmc, val, offs); 2564 pmc_clk_fence_udelay(offs); 2565 } 2566 2567 static int pmc_clk_enable(struct clk_hw *hw) 2568 { 2569 struct pmc_clk *clk = to_pmc_clk(hw); 2570 2571 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2572 2573 return 0; 2574 } 2575 2576 static void pmc_clk_disable(struct clk_hw *hw) 2577 { 2578 struct pmc_clk *clk = to_pmc_clk(hw); 2579 2580 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2581 } 2582 2583 static const struct clk_ops pmc_clk_ops = { 2584 .get_parent = pmc_clk_mux_get_parent, 2585 .set_parent = pmc_clk_mux_set_parent, 2586 .determine_rate = __clk_mux_determine_rate, 2587 .is_enabled = pmc_clk_is_enabled, 2588 .enable = pmc_clk_enable, 2589 .disable = pmc_clk_disable, 2590 }; 2591 2592 static struct clk * 2593 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2594 const struct pmc_clk_init_data *data, 2595 unsigned long offset) 2596 { 2597 struct clk_init_data init; 2598 struct pmc_clk *pmc_clk; 2599 2600 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2601 if (!pmc_clk) 2602 return ERR_PTR(-ENOMEM); 2603 2604 init.name = data->name; 2605 init.ops = &pmc_clk_ops; 2606 init.parent_names = data->parents; 2607 init.num_parents = data->num_parents; 2608 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2609 CLK_SET_PARENT_GATE; 2610 2611 pmc_clk->hw.init = &init; 2612 pmc_clk->offs = offset; 2613 pmc_clk->mux_shift = data->mux_shift; 2614 pmc_clk->force_en_shift = data->force_en_shift; 2615 2616 return clk_register(NULL, &pmc_clk->hw); 2617 } 2618 2619 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2620 { 2621 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2622 2623 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2624 } 2625 2626 static int pmc_clk_gate_enable(struct clk_hw *hw) 2627 { 2628 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2629 2630 pmc_clk_set_state(gate->offs, gate->shift, 1); 2631 2632 return 0; 2633 } 2634 2635 static void pmc_clk_gate_disable(struct clk_hw *hw) 2636 { 2637 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2638 2639 pmc_clk_set_state(gate->offs, gate->shift, 0); 2640 } 2641 2642 static const struct clk_ops pmc_clk_gate_ops = { 2643 .is_enabled = pmc_clk_gate_is_enabled, 2644 .enable = pmc_clk_gate_enable, 2645 .disable = pmc_clk_gate_disable, 2646 }; 2647 2648 static struct clk * 2649 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2650 const char *parent_name, unsigned long offset, 2651 u32 shift) 2652 { 2653 struct clk_init_data init; 2654 struct pmc_clk_gate *gate; 2655 2656 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2657 if (!gate) 2658 return ERR_PTR(-ENOMEM); 2659 2660 init.name = name; 2661 init.ops = &pmc_clk_gate_ops; 2662 init.parent_names = &parent_name; 2663 init.num_parents = 1; 2664 init.flags = 0; 2665 2666 gate->hw.init = &init; 2667 gate->offs = offset; 2668 gate->shift = shift; 2669 2670 return clk_register(NULL, &gate->hw); 2671 } 2672 2673 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2674 struct device_node *np) 2675 { 2676 struct clk *clk; 2677 struct clk_onecell_data *clk_data; 2678 unsigned int num_clks; 2679 int i, err; 2680 2681 num_clks = pmc->soc->num_pmc_clks; 2682 if (pmc->soc->has_blink_output) 2683 num_clks += 1; 2684 2685 if (!num_clks) 2686 return; 2687 2688 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2689 if (!clk_data) 2690 return; 2691 2692 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2693 sizeof(*clk_data->clks), GFP_KERNEL); 2694 if (!clk_data->clks) 2695 return; 2696 2697 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2698 2699 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2700 clk_data->clks[i] = ERR_PTR(-ENOENT); 2701 2702 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2703 const struct pmc_clk_init_data *data; 2704 2705 data = pmc->soc->pmc_clks_data + i; 2706 2707 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2708 if (IS_ERR(clk)) { 2709 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2710 data->name, PTR_ERR_OR_ZERO(clk)); 2711 return; 2712 } 2713 2714 err = clk_register_clkdev(clk, data->name, NULL); 2715 if (err) { 2716 dev_warn(pmc->dev, 2717 "unable to register %s clock lookup: %d\n", 2718 data->name, err); 2719 return; 2720 } 2721 2722 clk_data->clks[data->clk_id] = clk; 2723 } 2724 2725 if (pmc->soc->has_blink_output) { 2726 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2727 clk = tegra_pmc_clk_gate_register(pmc, 2728 "pmc_blink_override", 2729 "clk_32k", 2730 PMC_DPD_PADS_ORIDE, 2731 PMC_DPD_PADS_ORIDE_BLINK); 2732 if (IS_ERR(clk)) { 2733 dev_warn(pmc->dev, 2734 "unable to register pmc_blink_override: %d\n", 2735 PTR_ERR_OR_ZERO(clk)); 2736 return; 2737 } 2738 2739 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2740 "pmc_blink_override", 2741 PMC_CNTRL, 2742 PMC_CNTRL_BLINK_EN); 2743 if (IS_ERR(clk)) { 2744 dev_warn(pmc->dev, 2745 "unable to register pmc_blink: %d\n", 2746 PTR_ERR_OR_ZERO(clk)); 2747 return; 2748 } 2749 2750 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2751 if (err) { 2752 dev_warn(pmc->dev, 2753 "unable to register pmc_blink lookup: %d\n", 2754 err); 2755 return; 2756 } 2757 2758 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2759 } 2760 2761 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2762 if (err) 2763 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2764 err); 2765 } 2766 2767 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = { 2768 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO), 2769 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE), 2770 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE), 2771 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP), 2772 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG), 2773 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG), 2774 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1), 2775 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3), 2776 }; 2777 2778 static const struct regmap_access_table pmc_usb_sleepwalk_table = { 2779 .yes_ranges = pmc_usb_sleepwalk_ranges, 2780 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges), 2781 }; 2782 2783 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value) 2784 { 2785 struct tegra_pmc *pmc = context; 2786 2787 *value = tegra_pmc_readl(pmc, offset); 2788 return 0; 2789 } 2790 2791 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value) 2792 { 2793 struct tegra_pmc *pmc = context; 2794 2795 tegra_pmc_writel(pmc, value, offset); 2796 return 0; 2797 } 2798 2799 static const struct regmap_config usb_sleepwalk_regmap_config = { 2800 .name = "usb_sleepwalk", 2801 .reg_bits = 32, 2802 .val_bits = 32, 2803 .reg_stride = 4, 2804 .fast_io = true, 2805 .rd_table = &pmc_usb_sleepwalk_table, 2806 .wr_table = &pmc_usb_sleepwalk_table, 2807 .reg_read = tegra_pmc_regmap_readl, 2808 .reg_write = tegra_pmc_regmap_writel, 2809 }; 2810 2811 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) 2812 { 2813 struct regmap *regmap; 2814 int err; 2815 2816 if (pmc->soc->has_usb_sleepwalk) { 2817 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); 2818 if (IS_ERR(regmap)) { 2819 err = PTR_ERR(regmap); 2820 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); 2821 return err; 2822 } 2823 } 2824 2825 return 0; 2826 } 2827 2828 static void tegra_pmc_reset_suspend_mode(void *data) 2829 { 2830 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; 2831 } 2832 2833 static int tegra_pmc_probe(struct platform_device *pdev) 2834 { 2835 void __iomem *base; 2836 struct resource *res; 2837 int err; 2838 2839 /* 2840 * Early initialisation should have configured an initial 2841 * register mapping and setup the soc data pointer. If these 2842 * are not valid then something went badly wrong! 2843 */ 2844 if (WARN_ON(!pmc->base || !pmc->soc)) 2845 return -ENODEV; 2846 2847 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2848 if (err < 0) 2849 return err; 2850 2851 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, 2852 NULL); 2853 if (err) 2854 return err; 2855 2856 /* take over the memory region from the early initialization */ 2857 base = devm_platform_ioremap_resource(pdev, 0); 2858 if (IS_ERR(base)) 2859 return PTR_ERR(base); 2860 2861 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 2862 if (res) { 2863 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 2864 if (IS_ERR(pmc->wake)) 2865 return PTR_ERR(pmc->wake); 2866 } else { 2867 pmc->wake = base; 2868 } 2869 2870 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 2871 if (res) { 2872 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 2873 if (IS_ERR(pmc->aotag)) 2874 return PTR_ERR(pmc->aotag); 2875 } else { 2876 pmc->aotag = base; 2877 } 2878 2879 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 2880 if (res) { 2881 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2882 if (IS_ERR(pmc->scratch)) 2883 return PTR_ERR(pmc->scratch); 2884 } else { 2885 pmc->scratch = base; 2886 } 2887 2888 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 2889 if (IS_ERR(pmc->clk)) { 2890 err = PTR_ERR(pmc->clk); 2891 2892 if (err != -ENOENT) { 2893 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 2894 return err; 2895 } 2896 2897 pmc->clk = NULL; 2898 } 2899 2900 /* 2901 * PMC should be last resort for restarting since it soft-resets 2902 * CPU without resetting everything else. 2903 */ 2904 err = devm_register_reboot_notifier(&pdev->dev, 2905 &tegra_pmc_reboot_notifier); 2906 if (err) { 2907 dev_err(&pdev->dev, "unable to register reboot notifier, %d\n", 2908 err); 2909 return err; 2910 } 2911 2912 err = devm_register_sys_off_handler(&pdev->dev, 2913 SYS_OFF_MODE_RESTART, 2914 SYS_OFF_PRIO_LOW, 2915 tegra_pmc_restart_handler, NULL); 2916 if (err) { 2917 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 2918 err); 2919 return err; 2920 } 2921 2922 /* 2923 * PMC should be primary power-off method if it soft-resets CPU, 2924 * asking bootloader to shutdown hardware. 2925 */ 2926 err = devm_register_sys_off_handler(&pdev->dev, 2927 SYS_OFF_MODE_POWER_OFF, 2928 SYS_OFF_PRIO_FIRMWARE, 2929 tegra_pmc_power_off_handler, NULL); 2930 if (err) { 2931 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", 2932 err); 2933 return err; 2934 } 2935 2936 /* 2937 * PCLK clock rate can't be retrieved using CLK API because it 2938 * causes lockup if CPU enters LP2 idle state from some other 2939 * CLK notifier, hence we're caching the rate's value locally. 2940 */ 2941 if (pmc->clk) { 2942 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 2943 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); 2944 if (err) { 2945 dev_err(&pdev->dev, 2946 "failed to register clk notifier\n"); 2947 return err; 2948 } 2949 2950 pmc->rate = clk_get_rate(pmc->clk); 2951 } 2952 2953 pmc->dev = &pdev->dev; 2954 2955 tegra_pmc_init(pmc); 2956 2957 tegra_pmc_init_tsense_reset(pmc); 2958 2959 tegra_pmc_reset_sysfs_init(pmc); 2960 2961 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2962 err = tegra_powergate_debugfs_init(); 2963 if (err < 0) 2964 goto cleanup_sysfs; 2965 } 2966 2967 err = tegra_pmc_pinctrl_init(pmc); 2968 if (err) 2969 goto cleanup_debugfs; 2970 2971 err = tegra_pmc_regmap_init(pmc); 2972 if (err < 0) 2973 goto cleanup_debugfs; 2974 2975 err = tegra_powergate_init(pmc, pdev->dev.of_node); 2976 if (err < 0) 2977 goto cleanup_powergates; 2978 2979 err = tegra_pmc_irq_init(pmc); 2980 if (err < 0) 2981 goto cleanup_powergates; 2982 2983 mutex_lock(&pmc->powergates_lock); 2984 iounmap(pmc->base); 2985 pmc->base = base; 2986 mutex_unlock(&pmc->powergates_lock); 2987 2988 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 2989 platform_set_drvdata(pdev, pmc); 2990 tegra_pm_init_suspend(); 2991 2992 return 0; 2993 2994 cleanup_powergates: 2995 tegra_powergate_remove_all(pdev->dev.of_node); 2996 cleanup_debugfs: 2997 debugfs_remove(pmc->debugfs); 2998 cleanup_sysfs: 2999 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 3000 device_remove_file(&pdev->dev, &dev_attr_reset_level); 3001 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); 3002 3003 return err; 3004 } 3005 3006 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3007 static int tegra_pmc_suspend(struct device *dev) 3008 { 3009 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3010 3011 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 3012 3013 return 0; 3014 } 3015 3016 static int tegra_pmc_resume(struct device *dev) 3017 { 3018 struct tegra_pmc *pmc = dev_get_drvdata(dev); 3019 3020 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 3021 3022 return 0; 3023 } 3024 3025 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 3026 3027 #endif 3028 3029 static const char * const tegra20_powergates[] = { 3030 [TEGRA_POWERGATE_CPU] = "cpu", 3031 [TEGRA_POWERGATE_3D] = "td", 3032 [TEGRA_POWERGATE_VENC] = "venc", 3033 [TEGRA_POWERGATE_VDEC] = "vdec", 3034 [TEGRA_POWERGATE_PCIE] = "pcie", 3035 [TEGRA_POWERGATE_L2] = "l2", 3036 [TEGRA_POWERGATE_MPE] = "mpe", 3037 }; 3038 3039 static const struct tegra_pmc_regs tegra20_pmc_regs = { 3040 .scratch0 = 0x50, 3041 .dpd_req = 0x1b8, 3042 .dpd_status = 0x1bc, 3043 .dpd2_req = 0x1c0, 3044 .dpd2_status = 0x1c4, 3045 .rst_status = 0x1b4, 3046 .rst_source_shift = 0x0, 3047 .rst_source_mask = 0x7, 3048 .rst_level_shift = 0x0, 3049 .rst_level_mask = 0x0, 3050 }; 3051 3052 static void tegra20_pmc_init(struct tegra_pmc *pmc) 3053 { 3054 u32 value, osc, pmu, off; 3055 3056 /* Always enable CPU power request */ 3057 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3058 value |= PMC_CNTRL_CPU_PWRREQ_OE; 3059 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3060 3061 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3062 3063 if (pmc->sysclkreq_high) 3064 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 3065 else 3066 value |= PMC_CNTRL_SYSCLK_POLARITY; 3067 3068 if (pmc->corereq_high) 3069 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 3070 else 3071 value |= PMC_CNTRL_PWRREQ_POLARITY; 3072 3073 /* configure the output polarity while the request is tristated */ 3074 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3075 3076 /* now enable the request */ 3077 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3078 value |= PMC_CNTRL_SYSCLK_OE; 3079 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3080 3081 /* program core timings which are applicable only for suspend state */ 3082 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 3083 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 3084 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 3085 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 3086 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 3087 PMC_COREPWRGOOD_TIMER); 3088 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 3089 } 3090 } 3091 3092 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3093 struct device_node *np, 3094 bool invert) 3095 { 3096 u32 value; 3097 3098 value = tegra_pmc_readl(pmc, PMC_CNTRL); 3099 3100 if (invert) 3101 value |= PMC_CNTRL_INTR_POLARITY; 3102 else 3103 value &= ~PMC_CNTRL_INTR_POLARITY; 3104 3105 tegra_pmc_writel(pmc, value, PMC_CNTRL); 3106 } 3107 3108 static const struct tegra_pmc_soc tegra20_pmc_soc = { 3109 .supports_core_domain = true, 3110 .num_powergates = ARRAY_SIZE(tegra20_powergates), 3111 .powergates = tegra20_powergates, 3112 .num_cpu_powergates = 0, 3113 .cpu_powergates = NULL, 3114 .has_tsense_reset = false, 3115 .has_gpu_clamps = false, 3116 .needs_mbist_war = false, 3117 .has_impl_33v_pwr = false, 3118 .maybe_tz_only = false, 3119 .num_io_pads = 0, 3120 .io_pads = NULL, 3121 .num_pin_descs = 0, 3122 .pin_descs = NULL, 3123 .regs = &tegra20_pmc_regs, 3124 .init = tegra20_pmc_init, 3125 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3126 .powergate_set = tegra20_powergate_set, 3127 .reset_sources = NULL, 3128 .num_reset_sources = 0, 3129 .reset_levels = NULL, 3130 .num_reset_levels = 0, 3131 .pmc_clks_data = NULL, 3132 .num_pmc_clks = 0, 3133 .has_blink_output = true, 3134 .has_usb_sleepwalk = true, 3135 }; 3136 3137 static const char * const tegra30_powergates[] = { 3138 [TEGRA_POWERGATE_CPU] = "cpu0", 3139 [TEGRA_POWERGATE_3D] = "td", 3140 [TEGRA_POWERGATE_VENC] = "venc", 3141 [TEGRA_POWERGATE_VDEC] = "vdec", 3142 [TEGRA_POWERGATE_PCIE] = "pcie", 3143 [TEGRA_POWERGATE_L2] = "l2", 3144 [TEGRA_POWERGATE_MPE] = "mpe", 3145 [TEGRA_POWERGATE_HEG] = "heg", 3146 [TEGRA_POWERGATE_SATA] = "sata", 3147 [TEGRA_POWERGATE_CPU1] = "cpu1", 3148 [TEGRA_POWERGATE_CPU2] = "cpu2", 3149 [TEGRA_POWERGATE_CPU3] = "cpu3", 3150 [TEGRA_POWERGATE_CELP] = "celp", 3151 [TEGRA_POWERGATE_3D1] = "td2", 3152 }; 3153 3154 static const u8 tegra30_cpu_powergates[] = { 3155 TEGRA_POWERGATE_CPU, 3156 TEGRA_POWERGATE_CPU1, 3157 TEGRA_POWERGATE_CPU2, 3158 TEGRA_POWERGATE_CPU3, 3159 }; 3160 3161 static const char * const tegra30_reset_sources[] = { 3162 "POWER_ON_RESET", 3163 "WATCHDOG", 3164 "SENSOR", 3165 "SW_MAIN", 3166 "LP0" 3167 }; 3168 3169 static const struct tegra_pmc_soc tegra30_pmc_soc = { 3170 .supports_core_domain = true, 3171 .num_powergates = ARRAY_SIZE(tegra30_powergates), 3172 .powergates = tegra30_powergates, 3173 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 3174 .cpu_powergates = tegra30_cpu_powergates, 3175 .has_tsense_reset = true, 3176 .has_gpu_clamps = false, 3177 .needs_mbist_war = false, 3178 .has_impl_33v_pwr = false, 3179 .maybe_tz_only = false, 3180 .num_io_pads = 0, 3181 .io_pads = NULL, 3182 .num_pin_descs = 0, 3183 .pin_descs = NULL, 3184 .regs = &tegra20_pmc_regs, 3185 .init = tegra20_pmc_init, 3186 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3187 .powergate_set = tegra20_powergate_set, 3188 .reset_sources = tegra30_reset_sources, 3189 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3190 .reset_levels = NULL, 3191 .num_reset_levels = 0, 3192 .pmc_clks_data = tegra_pmc_clks_data, 3193 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3194 .has_blink_output = true, 3195 .has_usb_sleepwalk = true, 3196 }; 3197 3198 static const char * const tegra114_powergates[] = { 3199 [TEGRA_POWERGATE_CPU] = "crail", 3200 [TEGRA_POWERGATE_3D] = "td", 3201 [TEGRA_POWERGATE_VENC] = "venc", 3202 [TEGRA_POWERGATE_VDEC] = "vdec", 3203 [TEGRA_POWERGATE_MPE] = "mpe", 3204 [TEGRA_POWERGATE_HEG] = "heg", 3205 [TEGRA_POWERGATE_CPU1] = "cpu1", 3206 [TEGRA_POWERGATE_CPU2] = "cpu2", 3207 [TEGRA_POWERGATE_CPU3] = "cpu3", 3208 [TEGRA_POWERGATE_CELP] = "celp", 3209 [TEGRA_POWERGATE_CPU0] = "cpu0", 3210 [TEGRA_POWERGATE_C0NC] = "c0nc", 3211 [TEGRA_POWERGATE_C1NC] = "c1nc", 3212 [TEGRA_POWERGATE_DIS] = "dis", 3213 [TEGRA_POWERGATE_DISB] = "disb", 3214 [TEGRA_POWERGATE_XUSBA] = "xusba", 3215 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3216 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3217 }; 3218 3219 static const u8 tegra114_cpu_powergates[] = { 3220 TEGRA_POWERGATE_CPU0, 3221 TEGRA_POWERGATE_CPU1, 3222 TEGRA_POWERGATE_CPU2, 3223 TEGRA_POWERGATE_CPU3, 3224 }; 3225 3226 static const struct tegra_pmc_soc tegra114_pmc_soc = { 3227 .supports_core_domain = false, 3228 .num_powergates = ARRAY_SIZE(tegra114_powergates), 3229 .powergates = tegra114_powergates, 3230 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 3231 .cpu_powergates = tegra114_cpu_powergates, 3232 .has_tsense_reset = true, 3233 .has_gpu_clamps = false, 3234 .needs_mbist_war = false, 3235 .has_impl_33v_pwr = false, 3236 .maybe_tz_only = false, 3237 .num_io_pads = 0, 3238 .io_pads = NULL, 3239 .num_pin_descs = 0, 3240 .pin_descs = NULL, 3241 .regs = &tegra20_pmc_regs, 3242 .init = tegra20_pmc_init, 3243 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3244 .powergate_set = tegra114_powergate_set, 3245 .reset_sources = tegra30_reset_sources, 3246 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3247 .reset_levels = NULL, 3248 .num_reset_levels = 0, 3249 .pmc_clks_data = tegra_pmc_clks_data, 3250 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3251 .has_blink_output = true, 3252 .has_usb_sleepwalk = true, 3253 }; 3254 3255 static const char * const tegra124_powergates[] = { 3256 [TEGRA_POWERGATE_CPU] = "crail", 3257 [TEGRA_POWERGATE_3D] = "3d", 3258 [TEGRA_POWERGATE_VENC] = "venc", 3259 [TEGRA_POWERGATE_PCIE] = "pcie", 3260 [TEGRA_POWERGATE_VDEC] = "vdec", 3261 [TEGRA_POWERGATE_MPE] = "mpe", 3262 [TEGRA_POWERGATE_HEG] = "heg", 3263 [TEGRA_POWERGATE_SATA] = "sata", 3264 [TEGRA_POWERGATE_CPU1] = "cpu1", 3265 [TEGRA_POWERGATE_CPU2] = "cpu2", 3266 [TEGRA_POWERGATE_CPU3] = "cpu3", 3267 [TEGRA_POWERGATE_CELP] = "celp", 3268 [TEGRA_POWERGATE_CPU0] = "cpu0", 3269 [TEGRA_POWERGATE_C0NC] = "c0nc", 3270 [TEGRA_POWERGATE_C1NC] = "c1nc", 3271 [TEGRA_POWERGATE_SOR] = "sor", 3272 [TEGRA_POWERGATE_DIS] = "dis", 3273 [TEGRA_POWERGATE_DISB] = "disb", 3274 [TEGRA_POWERGATE_XUSBA] = "xusba", 3275 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3276 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3277 [TEGRA_POWERGATE_VIC] = "vic", 3278 [TEGRA_POWERGATE_IRAM] = "iram", 3279 }; 3280 3281 static const u8 tegra124_cpu_powergates[] = { 3282 TEGRA_POWERGATE_CPU0, 3283 TEGRA_POWERGATE_CPU1, 3284 TEGRA_POWERGATE_CPU2, 3285 TEGRA_POWERGATE_CPU3, 3286 }; 3287 3288 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 3289 ((struct tegra_io_pad_soc) { \ 3290 .id = (_id), \ 3291 .dpd = (_dpd), \ 3292 .voltage = (_voltage), \ 3293 .name = (_name), \ 3294 }) 3295 3296 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 3297 ((struct pinctrl_pin_desc) { \ 3298 .number = (_id), \ 3299 .name = (_name) \ 3300 }) 3301 3302 #define TEGRA124_IO_PAD_TABLE(_pad) \ 3303 /* .id .dpd .voltage .name */ \ 3304 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3305 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 3306 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 3307 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 3308 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3309 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 3310 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 3311 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3312 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 3313 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 3314 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 3315 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 3316 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3317 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 3318 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 3319 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3320 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 3321 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 3322 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 3323 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3324 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3325 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 3326 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 3327 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 3328 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 3329 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3330 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3331 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3332 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3333 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 3334 3335 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 3336 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 3337 }; 3338 3339 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 3340 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3341 }; 3342 3343 static const struct tegra_pmc_soc tegra124_pmc_soc = { 3344 .supports_core_domain = false, 3345 .num_powergates = ARRAY_SIZE(tegra124_powergates), 3346 .powergates = tegra124_powergates, 3347 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 3348 .cpu_powergates = tegra124_cpu_powergates, 3349 .has_tsense_reset = true, 3350 .has_gpu_clamps = true, 3351 .needs_mbist_war = false, 3352 .has_impl_33v_pwr = false, 3353 .maybe_tz_only = false, 3354 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 3355 .io_pads = tegra124_io_pads, 3356 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 3357 .pin_descs = tegra124_pin_descs, 3358 .regs = &tegra20_pmc_regs, 3359 .init = tegra20_pmc_init, 3360 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3361 .powergate_set = tegra114_powergate_set, 3362 .reset_sources = tegra30_reset_sources, 3363 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 3364 .reset_levels = NULL, 3365 .num_reset_levels = 0, 3366 .pmc_clks_data = tegra_pmc_clks_data, 3367 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3368 .has_blink_output = true, 3369 .has_usb_sleepwalk = true, 3370 }; 3371 3372 static const char * const tegra210_powergates[] = { 3373 [TEGRA_POWERGATE_CPU] = "crail", 3374 [TEGRA_POWERGATE_3D] = "3d", 3375 [TEGRA_POWERGATE_VENC] = "venc", 3376 [TEGRA_POWERGATE_PCIE] = "pcie", 3377 [TEGRA_POWERGATE_MPE] = "mpe", 3378 [TEGRA_POWERGATE_SATA] = "sata", 3379 [TEGRA_POWERGATE_CPU1] = "cpu1", 3380 [TEGRA_POWERGATE_CPU2] = "cpu2", 3381 [TEGRA_POWERGATE_CPU3] = "cpu3", 3382 [TEGRA_POWERGATE_CPU0] = "cpu0", 3383 [TEGRA_POWERGATE_C0NC] = "c0nc", 3384 [TEGRA_POWERGATE_SOR] = "sor", 3385 [TEGRA_POWERGATE_DIS] = "dis", 3386 [TEGRA_POWERGATE_DISB] = "disb", 3387 [TEGRA_POWERGATE_XUSBA] = "xusba", 3388 [TEGRA_POWERGATE_XUSBB] = "xusbb", 3389 [TEGRA_POWERGATE_XUSBC] = "xusbc", 3390 [TEGRA_POWERGATE_VIC] = "vic", 3391 [TEGRA_POWERGATE_IRAM] = "iram", 3392 [TEGRA_POWERGATE_NVDEC] = "nvdec", 3393 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 3394 [TEGRA_POWERGATE_AUD] = "aud", 3395 [TEGRA_POWERGATE_DFD] = "dfd", 3396 [TEGRA_POWERGATE_VE2] = "ve2", 3397 }; 3398 3399 static const u8 tegra210_cpu_powergates[] = { 3400 TEGRA_POWERGATE_CPU0, 3401 TEGRA_POWERGATE_CPU1, 3402 TEGRA_POWERGATE_CPU2, 3403 TEGRA_POWERGATE_CPU3, 3404 }; 3405 3406 #define TEGRA210_IO_PAD_TABLE(_pad) \ 3407 /* .id .dpd .voltage .name */ \ 3408 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 3409 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 3410 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 3411 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3412 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3413 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 3414 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 3415 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 3416 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 3417 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 3418 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 3419 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 3420 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 3421 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3422 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 3423 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 3424 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 3425 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 3426 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 3427 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 3428 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 3429 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3430 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 3431 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3432 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 3433 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 3434 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3435 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 3436 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 3437 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 3438 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 3439 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 3440 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 3441 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3442 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3443 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3444 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 3445 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 3446 3447 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3448 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 3449 }; 3450 3451 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3452 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3453 }; 3454 3455 static const char * const tegra210_reset_sources[] = { 3456 "POWER_ON_RESET", 3457 "WATCHDOG", 3458 "SENSOR", 3459 "SW_MAIN", 3460 "LP0", 3461 "AOTAG" 3462 }; 3463 3464 static const struct tegra_wake_event tegra210_wake_events[] = { 3465 TEGRA_WAKE_IRQ("rtc", 16, 2), 3466 TEGRA_WAKE_IRQ("pmu", 51, 86), 3467 }; 3468 3469 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3470 .supports_core_domain = false, 3471 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3472 .powergates = tegra210_powergates, 3473 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3474 .cpu_powergates = tegra210_cpu_powergates, 3475 .has_tsense_reset = true, 3476 .has_gpu_clamps = true, 3477 .needs_mbist_war = true, 3478 .has_impl_33v_pwr = false, 3479 .maybe_tz_only = true, 3480 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3481 .io_pads = tegra210_io_pads, 3482 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3483 .pin_descs = tegra210_pin_descs, 3484 .regs = &tegra20_pmc_regs, 3485 .init = tegra20_pmc_init, 3486 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3487 .powergate_set = tegra114_powergate_set, 3488 .irq_set_wake = tegra210_pmc_irq_set_wake, 3489 .irq_set_type = tegra210_pmc_irq_set_type, 3490 .reset_sources = tegra210_reset_sources, 3491 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3492 .reset_levels = NULL, 3493 .num_reset_levels = 0, 3494 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3495 .wake_events = tegra210_wake_events, 3496 .pmc_clks_data = tegra_pmc_clks_data, 3497 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3498 .has_blink_output = true, 3499 .has_usb_sleepwalk = true, 3500 }; 3501 3502 #define TEGRA186_IO_PAD_TABLE(_pad) \ 3503 /* .id .dpd .voltage .name */ \ 3504 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3505 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3506 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3507 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3508 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3509 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3510 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3511 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3512 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3513 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3514 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3515 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 3516 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3517 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3518 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3519 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3520 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3521 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3522 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3523 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 3524 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3525 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3526 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 3527 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 3528 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 3529 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3530 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3531 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3532 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3533 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3534 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3535 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 3536 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3537 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3538 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3539 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3540 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3541 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3542 3543 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3544 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 3545 }; 3546 3547 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3548 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3549 }; 3550 3551 static const struct tegra_pmc_regs tegra186_pmc_regs = { 3552 .scratch0 = 0x2000, 3553 .dpd_req = 0x74, 3554 .dpd_status = 0x78, 3555 .dpd2_req = 0x7c, 3556 .dpd2_status = 0x80, 3557 .rst_status = 0x70, 3558 .rst_source_shift = 0x2, 3559 .rst_source_mask = 0x3c, 3560 .rst_level_shift = 0x0, 3561 .rst_level_mask = 0x3, 3562 }; 3563 3564 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3565 struct device_node *np, 3566 bool invert) 3567 { 3568 struct resource regs; 3569 void __iomem *wake; 3570 u32 value; 3571 int index; 3572 3573 index = of_property_match_string(np, "reg-names", "wake"); 3574 if (index < 0) { 3575 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3576 return; 3577 } 3578 3579 of_address_to_resource(np, index, ®s); 3580 3581 wake = ioremap(regs.start, resource_size(®s)); 3582 if (!wake) { 3583 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3584 return; 3585 } 3586 3587 value = readl(wake + WAKE_AOWAKE_CTRL); 3588 3589 if (invert) 3590 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3591 else 3592 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3593 3594 writel(value, wake + WAKE_AOWAKE_CTRL); 3595 3596 iounmap(wake); 3597 } 3598 3599 static const char * const tegra186_reset_sources[] = { 3600 "SYS_RESET", 3601 "AOWDT", 3602 "MCCPLEXWDT", 3603 "BPMPWDT", 3604 "SCEWDT", 3605 "SPEWDT", 3606 "APEWDT", 3607 "BCCPLEXWDT", 3608 "SENSOR", 3609 "AOTAG", 3610 "VFSENSOR", 3611 "SWREST", 3612 "SC7", 3613 "HSM", 3614 "CORESIGHT" 3615 }; 3616 3617 static const char * const tegra186_reset_levels[] = { 3618 "L0", "L1", "L2", "WARM" 3619 }; 3620 3621 static const struct tegra_wake_event tegra186_wake_events[] = { 3622 TEGRA_WAKE_IRQ("pmu", 24, 209), 3623 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3624 TEGRA_WAKE_IRQ("rtc", 73, 10), 3625 }; 3626 3627 static const struct tegra_pmc_soc tegra186_pmc_soc = { 3628 .supports_core_domain = false, 3629 .num_powergates = 0, 3630 .powergates = NULL, 3631 .num_cpu_powergates = 0, 3632 .cpu_powergates = NULL, 3633 .has_tsense_reset = false, 3634 .has_gpu_clamps = false, 3635 .needs_mbist_war = false, 3636 .has_impl_33v_pwr = true, 3637 .maybe_tz_only = false, 3638 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3639 .io_pads = tegra186_io_pads, 3640 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3641 .pin_descs = tegra186_pin_descs, 3642 .regs = &tegra186_pmc_regs, 3643 .init = NULL, 3644 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3645 .irq_set_wake = tegra186_pmc_irq_set_wake, 3646 .irq_set_type = tegra186_pmc_irq_set_type, 3647 .reset_sources = tegra186_reset_sources, 3648 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3649 .reset_levels = tegra186_reset_levels, 3650 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3651 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3652 .wake_events = tegra186_wake_events, 3653 .pmc_clks_data = NULL, 3654 .num_pmc_clks = 0, 3655 .has_blink_output = false, 3656 .has_usb_sleepwalk = false, 3657 }; 3658 3659 #define TEGRA194_IO_PAD_TABLE(_pad) \ 3660 /* .id .dpd .voltage .name */ \ 3661 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3662 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3663 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3664 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3665 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3666 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3667 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3668 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \ 3669 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \ 3670 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \ 3671 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \ 3672 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \ 3673 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3674 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \ 3675 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \ 3676 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3677 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \ 3678 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \ 3679 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \ 3680 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \ 3681 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \ 3682 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \ 3683 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \ 3684 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3685 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \ 3686 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \ 3687 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3688 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3689 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3690 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \ 3691 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \ 3692 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \ 3693 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3694 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \ 3695 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3696 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3697 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3698 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3699 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3700 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3701 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3702 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \ 3703 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \ 3704 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3705 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3706 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3707 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3708 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3709 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3710 3711 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3712 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD) 3713 }; 3714 3715 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 3716 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3717 }; 3718 3719 static const struct tegra_pmc_regs tegra194_pmc_regs = { 3720 .scratch0 = 0x2000, 3721 .dpd_req = 0x74, 3722 .dpd_status = 0x78, 3723 .dpd2_req = 0x7c, 3724 .dpd2_status = 0x80, 3725 .rst_status = 0x70, 3726 .rst_source_shift = 0x2, 3727 .rst_source_mask = 0x7c, 3728 .rst_level_shift = 0x0, 3729 .rst_level_mask = 0x3, 3730 }; 3731 3732 static const char * const tegra194_reset_sources[] = { 3733 "SYS_RESET_N", 3734 "AOWDT", 3735 "BCCPLEXWDT", 3736 "BPMPWDT", 3737 "SCEWDT", 3738 "SPEWDT", 3739 "APEWDT", 3740 "LCCPLEXWDT", 3741 "SENSOR", 3742 "AOTAG", 3743 "VFSENSOR", 3744 "MAINSWRST", 3745 "SC7", 3746 "HSM", 3747 "CSITE", 3748 "RCEWDT", 3749 "PVA0WDT", 3750 "PVA1WDT", 3751 "L1A_ASYNC", 3752 "BPMPBOOT", 3753 "FUSECRC", 3754 }; 3755 3756 static const struct tegra_wake_event tegra194_wake_events[] = { 3757 TEGRA_WAKE_IRQ("pmu", 24, 209), 3758 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 3759 TEGRA_WAKE_IRQ("rtc", 73, 10), 3760 }; 3761 3762 static const struct tegra_pmc_soc tegra194_pmc_soc = { 3763 .supports_core_domain = false, 3764 .num_powergates = 0, 3765 .powergates = NULL, 3766 .num_cpu_powergates = 0, 3767 .cpu_powergates = NULL, 3768 .has_tsense_reset = false, 3769 .has_gpu_clamps = false, 3770 .needs_mbist_war = false, 3771 .has_impl_33v_pwr = true, 3772 .maybe_tz_only = false, 3773 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 3774 .io_pads = tegra194_io_pads, 3775 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 3776 .pin_descs = tegra194_pin_descs, 3777 .regs = &tegra194_pmc_regs, 3778 .init = NULL, 3779 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3780 .irq_set_wake = tegra186_pmc_irq_set_wake, 3781 .irq_set_type = tegra186_pmc_irq_set_type, 3782 .reset_sources = tegra194_reset_sources, 3783 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 3784 .reset_levels = tegra186_reset_levels, 3785 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3786 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 3787 .wake_events = tegra194_wake_events, 3788 .pmc_clks_data = NULL, 3789 .num_pmc_clks = 0, 3790 .has_blink_output = false, 3791 .has_usb_sleepwalk = false, 3792 }; 3793 3794 static const struct tegra_pmc_regs tegra234_pmc_regs = { 3795 .scratch0 = 0x2000, 3796 .dpd_req = 0, 3797 .dpd_status = 0, 3798 .dpd2_req = 0, 3799 .dpd2_status = 0, 3800 .rst_status = 0x70, 3801 .rst_source_shift = 0x2, 3802 .rst_source_mask = 0xfc, 3803 .rst_level_shift = 0x0, 3804 .rst_level_mask = 0x3, 3805 }; 3806 3807 static const char * const tegra234_reset_sources[] = { 3808 "SYS_RESET_N", /* 0x0 */ 3809 "AOWDT", 3810 "BCCPLEXWDT", 3811 "BPMPWDT", 3812 "SCEWDT", 3813 "SPEWDT", 3814 "APEWDT", 3815 "LCCPLEXWDT", 3816 "SENSOR", /* 0x8 */ 3817 NULL, 3818 NULL, 3819 "MAINSWRST", 3820 "SC7", 3821 "HSM", 3822 NULL, 3823 "RCEWDT", 3824 NULL, /* 0x10 */ 3825 NULL, 3826 NULL, 3827 "BPMPBOOT", 3828 "FUSECRC", 3829 "DCEWDT", 3830 "PSCWDT", 3831 "PSC", 3832 "CSITE_SW", /* 0x18 */ 3833 "POD", 3834 "SCPM", 3835 "VREFRO_POWERBAD", 3836 "VMON", 3837 "FMON", 3838 "FSI_R5WDT", 3839 "FSI_THERM", 3840 "FSI_R52C0WDT", /* 0x20 */ 3841 "FSI_R52C1WDT", 3842 "FSI_R52C2WDT", 3843 "FSI_R52C3WDT", 3844 "FSI_FMON", 3845 "FSI_VMON", /* 0x25 */ 3846 }; 3847 3848 static const struct tegra_wake_event tegra234_wake_events[] = { 3849 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), 3850 TEGRA_WAKE_IRQ("rtc", 73, 10), 3851 }; 3852 3853 static const struct tegra_pmc_soc tegra234_pmc_soc = { 3854 .supports_core_domain = false, 3855 .num_powergates = 0, 3856 .powergates = NULL, 3857 .num_cpu_powergates = 0, 3858 .cpu_powergates = NULL, 3859 .has_tsense_reset = false, 3860 .has_gpu_clamps = false, 3861 .needs_mbist_war = false, 3862 .has_impl_33v_pwr = true, 3863 .maybe_tz_only = false, 3864 .num_io_pads = 0, 3865 .io_pads = NULL, 3866 .num_pin_descs = 0, 3867 .pin_descs = NULL, 3868 .regs = &tegra234_pmc_regs, 3869 .init = NULL, 3870 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3871 .irq_set_wake = tegra186_pmc_irq_set_wake, 3872 .irq_set_type = tegra186_pmc_irq_set_type, 3873 .reset_sources = tegra234_reset_sources, 3874 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 3875 .reset_levels = tegra186_reset_levels, 3876 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3877 .num_wake_events = ARRAY_SIZE(tegra234_wake_events), 3878 .wake_events = tegra234_wake_events, 3879 .pmc_clks_data = NULL, 3880 .num_pmc_clks = 0, 3881 .has_blink_output = false, 3882 }; 3883 3884 static const struct of_device_id tegra_pmc_match[] = { 3885 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 3886 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 3887 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 3888 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 3889 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 3890 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 3891 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 3892 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 3893 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 3894 { } 3895 }; 3896 3897 static void tegra_pmc_sync_state(struct device *dev) 3898 { 3899 int err; 3900 3901 /* 3902 * Newer device-trees have power domains, but we need to prepare all 3903 * device drivers with runtime PM and OPP support first, otherwise 3904 * state syncing is unsafe. 3905 */ 3906 if (!pmc->soc->supports_core_domain) 3907 return; 3908 3909 /* 3910 * Older device-trees don't have core PD, and thus, there are 3911 * no dependencies that will block the state syncing. We shouldn't 3912 * mark the domain as synced in this case. 3913 */ 3914 if (!pmc->core_domain_registered) 3915 return; 3916 3917 pmc->core_domain_state_synced = true; 3918 3919 /* this is a no-op if core regulator isn't used */ 3920 mutex_lock(&pmc->powergates_lock); 3921 err = dev_pm_opp_sync_regulators(dev); 3922 mutex_unlock(&pmc->powergates_lock); 3923 3924 if (err) 3925 dev_err(dev, "failed to sync regulators: %d\n", err); 3926 } 3927 3928 static struct platform_driver tegra_pmc_driver = { 3929 .driver = { 3930 .name = "tegra-pmc", 3931 .suppress_bind_attrs = true, 3932 .of_match_table = tegra_pmc_match, 3933 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3934 .pm = &tegra_pmc_pm_ops, 3935 #endif 3936 .sync_state = tegra_pmc_sync_state, 3937 }, 3938 .probe = tegra_pmc_probe, 3939 }; 3940 builtin_platform_driver(tegra_pmc_driver); 3941 3942 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 3943 { 3944 u32 value, saved; 3945 3946 saved = readl(pmc->base + pmc->soc->regs->scratch0); 3947 value = saved ^ 0xffffffff; 3948 3949 if (value == 0xffffffff) 3950 value = 0xdeadbeef; 3951 3952 /* write pattern and read it back */ 3953 writel(value, pmc->base + pmc->soc->regs->scratch0); 3954 value = readl(pmc->base + pmc->soc->regs->scratch0); 3955 3956 /* if we read all-zeroes, access is restricted to TZ only */ 3957 if (value == 0) { 3958 pr_info("access to PMC is restricted to TZ\n"); 3959 return true; 3960 } 3961 3962 /* restore original value */ 3963 writel(saved, pmc->base + pmc->soc->regs->scratch0); 3964 3965 return false; 3966 } 3967 3968 /* 3969 * Early initialization to allow access to registers in the very early boot 3970 * process. 3971 */ 3972 static int __init tegra_pmc_early_init(void) 3973 { 3974 const struct of_device_id *match; 3975 struct device_node *np; 3976 struct resource regs; 3977 unsigned int i; 3978 bool invert; 3979 3980 mutex_init(&pmc->powergates_lock); 3981 3982 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 3983 if (!np) { 3984 /* 3985 * Fall back to legacy initialization for 32-bit ARM only. All 3986 * 64-bit ARM device tree files for Tegra are required to have 3987 * a PMC node. 3988 * 3989 * This is for backwards-compatibility with old device trees 3990 * that didn't contain a PMC node. Note that in this case the 3991 * SoC data can't be matched and therefore powergating is 3992 * disabled. 3993 */ 3994 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 3995 pr_warn("DT node not found, powergating disabled\n"); 3996 3997 regs.start = 0x7000e400; 3998 regs.end = 0x7000e7ff; 3999 regs.flags = IORESOURCE_MEM; 4000 4001 pr_warn("Using memory region %pR\n", ®s); 4002 } else { 4003 /* 4004 * At this point we're not running on Tegra, so play 4005 * nice with multi-platform kernels. 4006 */ 4007 return 0; 4008 } 4009 } else { 4010 /* 4011 * Extract information from the device tree if we've found a 4012 * matching node. 4013 */ 4014 if (of_address_to_resource(np, 0, ®s) < 0) { 4015 pr_err("failed to get PMC registers\n"); 4016 of_node_put(np); 4017 return -ENXIO; 4018 } 4019 } 4020 4021 pmc->base = ioremap(regs.start, resource_size(®s)); 4022 if (!pmc->base) { 4023 pr_err("failed to map PMC registers\n"); 4024 of_node_put(np); 4025 return -ENXIO; 4026 } 4027 4028 if (np) { 4029 pmc->soc = match->data; 4030 4031 if (pmc->soc->maybe_tz_only) 4032 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 4033 4034 /* Create a bitmap of the available and valid partitions */ 4035 for (i = 0; i < pmc->soc->num_powergates; i++) 4036 if (pmc->soc->powergates[i]) 4037 set_bit(i, pmc->powergates_available); 4038 4039 /* 4040 * Invert the interrupt polarity if a PMC device tree node 4041 * exists and contains the nvidia,invert-interrupt property. 4042 */ 4043 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 4044 4045 pmc->soc->setup_irq_polarity(pmc, np, invert); 4046 4047 of_node_put(np); 4048 } 4049 4050 return 0; 4051 } 4052 early_initcall(tegra_pmc_early_init); 4053