1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #define pr_fmt(fmt) "tegra-pmc: " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/clk/tegra.h> 25 #include <linux/debugfs.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/export.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_clk.h> 35 #include <linux/of_platform.h> 36 #include <linux/pinctrl/pinctrl.h> 37 #include <linux/pinctrl/pinconf.h> 38 #include <linux/pinctrl/pinconf-generic.h> 39 #include <linux/platform_device.h> 40 #include <linux/pm_domain.h> 41 #include <linux/reboot.h> 42 #include <linux/reset.h> 43 #include <linux/seq_file.h> 44 #include <linux/slab.h> 45 #include <linux/spinlock.h> 46 47 #include <soc/tegra/common.h> 48 #include <soc/tegra/fuse.h> 49 #include <soc/tegra/pmc.h> 50 51 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 52 53 #define PMC_CNTRL 0x0 54 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 55 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 56 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 57 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 58 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 59 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 60 #define PMC_CNTRL_MAIN_RST BIT(4) 61 62 #define DPD_SAMPLE 0x020 63 #define DPD_SAMPLE_ENABLE BIT(0) 64 #define DPD_SAMPLE_DISABLE (0 << 0) 65 66 #define PWRGATE_TOGGLE 0x30 67 #define PWRGATE_TOGGLE_START BIT(8) 68 69 #define REMOVE_CLAMPING 0x34 70 71 #define PWRGATE_STATUS 0x38 72 73 #define PMC_IMPL_E_33V_PWR 0x40 74 75 #define PMC_PWR_DET 0x48 76 77 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 78 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 79 #define PMC_SCRATCH0_MODE_RCM BIT(1) 80 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 81 PMC_SCRATCH0_MODE_BOOTLOADER | \ 82 PMC_SCRATCH0_MODE_RCM) 83 84 #define PMC_CPUPWRGOOD_TIMER 0xc8 85 #define PMC_CPUPWROFF_TIMER 0xcc 86 87 #define PMC_PWR_DET_VALUE 0xe4 88 89 #define PMC_SCRATCH41 0x140 90 91 #define PMC_SENSOR_CTRL 0x1b0 92 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 93 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 94 95 #define PMC_RST_STATUS 0x1b4 96 #define PMC_RST_STATUS_POR 0 97 #define PMC_RST_STATUS_WATCHDOG 1 98 #define PMC_RST_STATUS_SENSOR 2 99 #define PMC_RST_STATUS_SW_MAIN 3 100 #define PMC_RST_STATUS_LP0 4 101 #define PMC_RST_STATUS_AOTAG 5 102 103 #define IO_DPD_REQ 0x1b8 104 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 105 #define IO_DPD_REQ_CODE_OFF (1U << 30) 106 #define IO_DPD_REQ_CODE_ON (2U << 30) 107 #define IO_DPD_REQ_CODE_MASK (3U << 30) 108 109 #define IO_DPD_STATUS 0x1bc 110 #define IO_DPD2_REQ 0x1c0 111 #define IO_DPD2_STATUS 0x1c4 112 #define SEL_DPD_TIM 0x1c8 113 114 #define PMC_SCRATCH54 0x258 115 #define PMC_SCRATCH54_DATA_SHIFT 8 116 #define PMC_SCRATCH54_ADDR_SHIFT 0 117 118 #define PMC_SCRATCH55 0x25c 119 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 120 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 121 #define PMC_SCRATCH55_PINMUX_SHIFT 24 122 #define PMC_SCRATCH55_16BITOP BIT(15) 123 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 124 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 125 126 #define GPU_RG_CNTRL 0x2d4 127 128 /* Tegra186 and later */ 129 #define WAKE_AOWAKE_CTRL 0x4f4 130 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 131 132 struct tegra_powergate { 133 struct generic_pm_domain genpd; 134 struct tegra_pmc *pmc; 135 unsigned int id; 136 struct clk **clks; 137 unsigned int num_clks; 138 struct reset_control *reset; 139 }; 140 141 struct tegra_io_pad_soc { 142 enum tegra_io_pad id; 143 unsigned int dpd; 144 unsigned int voltage; 145 const char *name; 146 }; 147 148 struct tegra_pmc_regs { 149 unsigned int scratch0; 150 unsigned int dpd_req; 151 unsigned int dpd_status; 152 unsigned int dpd2_req; 153 unsigned int dpd2_status; 154 }; 155 156 struct tegra_pmc_soc { 157 unsigned int num_powergates; 158 const char *const *powergates; 159 unsigned int num_cpu_powergates; 160 const u8 *cpu_powergates; 161 162 bool has_tsense_reset; 163 bool has_gpu_clamps; 164 bool needs_mbist_war; 165 bool has_impl_33v_pwr; 166 167 const struct tegra_io_pad_soc *io_pads; 168 unsigned int num_io_pads; 169 170 const struct pinctrl_pin_desc *pin_descs; 171 unsigned int num_pin_descs; 172 173 const struct tegra_pmc_regs *regs; 174 void (*init)(struct tegra_pmc *pmc); 175 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 176 struct device_node *np, 177 bool invert); 178 }; 179 180 /** 181 * struct tegra_pmc - NVIDIA Tegra PMC 182 * @dev: pointer to PMC device structure 183 * @base: pointer to I/O remapped register region 184 * @clk: pointer to pclk clock 185 * @soc: pointer to SoC data structure 186 * @debugfs: pointer to debugfs entry 187 * @rate: currently configured rate of pclk 188 * @suspend_mode: lowest suspend mode available 189 * @cpu_good_time: CPU power good time (in microseconds) 190 * @cpu_off_time: CPU power off time (in microsecends) 191 * @core_osc_time: core power good OSC time (in microseconds) 192 * @core_pmu_time: core power good PMU time (in microseconds) 193 * @core_off_time: core power off time (in microseconds) 194 * @corereq_high: core power request is active-high 195 * @sysclkreq_high: system clock request is active-high 196 * @combined_req: combined power request for CPU & core 197 * @cpu_pwr_good_en: CPU power good signal is enabled 198 * @lp0_vec_phys: physical base address of the LP0 warm boot code 199 * @lp0_vec_size: size of the LP0 warm boot code 200 * @powergates_available: Bitmap of available power gates 201 * @powergates_lock: mutex for power gate register access 202 */ 203 struct tegra_pmc { 204 struct device *dev; 205 void __iomem *base; 206 void __iomem *wake; 207 void __iomem *aotag; 208 void __iomem *scratch; 209 struct clk *clk; 210 struct dentry *debugfs; 211 212 const struct tegra_pmc_soc *soc; 213 214 unsigned long rate; 215 216 enum tegra_suspend_mode suspend_mode; 217 u32 cpu_good_time; 218 u32 cpu_off_time; 219 u32 core_osc_time; 220 u32 core_pmu_time; 221 u32 core_off_time; 222 bool corereq_high; 223 bool sysclkreq_high; 224 bool combined_req; 225 bool cpu_pwr_good_en; 226 u32 lp0_vec_phys; 227 u32 lp0_vec_size; 228 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 229 230 struct mutex powergates_lock; 231 232 struct pinctrl_dev *pctl_dev; 233 }; 234 235 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 236 .base = NULL, 237 .suspend_mode = TEGRA_SUSPEND_NONE, 238 }; 239 240 static inline struct tegra_powergate * 241 to_powergate(struct generic_pm_domain *domain) 242 { 243 return container_of(domain, struct tegra_powergate, genpd); 244 } 245 246 static u32 tegra_pmc_readl(unsigned long offset) 247 { 248 return readl(pmc->base + offset); 249 } 250 251 static void tegra_pmc_writel(u32 value, unsigned long offset) 252 { 253 writel(value, pmc->base + offset); 254 } 255 256 static inline bool tegra_powergate_state(int id) 257 { 258 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 259 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 260 else 261 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 262 } 263 264 static inline bool tegra_powergate_is_valid(int id) 265 { 266 return (pmc->soc && pmc->soc->powergates[id]); 267 } 268 269 static inline bool tegra_powergate_is_available(int id) 270 { 271 return test_bit(id, pmc->powergates_available); 272 } 273 274 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 275 { 276 unsigned int i; 277 278 if (!pmc || !pmc->soc || !name) 279 return -EINVAL; 280 281 for (i = 0; i < pmc->soc->num_powergates; i++) { 282 if (!tegra_powergate_is_valid(i)) 283 continue; 284 285 if (!strcmp(name, pmc->soc->powergates[i])) 286 return i; 287 } 288 289 return -ENODEV; 290 } 291 292 /** 293 * tegra_powergate_set() - set the state of a partition 294 * @id: partition ID 295 * @new_state: new state of the partition 296 */ 297 static int tegra_powergate_set(unsigned int id, bool new_state) 298 { 299 bool status; 300 int err; 301 302 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 303 return -EINVAL; 304 305 mutex_lock(&pmc->powergates_lock); 306 307 if (tegra_powergate_state(id) == new_state) { 308 mutex_unlock(&pmc->powergates_lock); 309 return 0; 310 } 311 312 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 313 314 err = readx_poll_timeout(tegra_powergate_state, id, status, 315 status == new_state, 10, 100000); 316 317 mutex_unlock(&pmc->powergates_lock); 318 319 return err; 320 } 321 322 static int __tegra_powergate_remove_clamping(unsigned int id) 323 { 324 u32 mask; 325 326 mutex_lock(&pmc->powergates_lock); 327 328 /* 329 * On Tegra124 and later, the clamps for the GPU are controlled by a 330 * separate register (with different semantics). 331 */ 332 if (id == TEGRA_POWERGATE_3D) { 333 if (pmc->soc->has_gpu_clamps) { 334 tegra_pmc_writel(0, GPU_RG_CNTRL); 335 goto out; 336 } 337 } 338 339 /* 340 * Tegra 2 has a bug where PCIE and VDE clamping masks are 341 * swapped relatively to the partition ids 342 */ 343 if (id == TEGRA_POWERGATE_VDEC) 344 mask = (1 << TEGRA_POWERGATE_PCIE); 345 else if (id == TEGRA_POWERGATE_PCIE) 346 mask = (1 << TEGRA_POWERGATE_VDEC); 347 else 348 mask = (1 << id); 349 350 tegra_pmc_writel(mask, REMOVE_CLAMPING); 351 352 out: 353 mutex_unlock(&pmc->powergates_lock); 354 355 return 0; 356 } 357 358 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 359 { 360 unsigned int i; 361 362 for (i = 0; i < pg->num_clks; i++) 363 clk_disable_unprepare(pg->clks[i]); 364 } 365 366 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 367 { 368 unsigned int i; 369 int err; 370 371 for (i = 0; i < pg->num_clks; i++) { 372 err = clk_prepare_enable(pg->clks[i]); 373 if (err) 374 goto out; 375 } 376 377 return 0; 378 379 out: 380 while (i--) 381 clk_disable_unprepare(pg->clks[i]); 382 383 return err; 384 } 385 386 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 387 { 388 return 0; 389 } 390 391 static int tegra_powergate_power_up(struct tegra_powergate *pg, 392 bool disable_clocks) 393 { 394 int err; 395 396 err = reset_control_assert(pg->reset); 397 if (err) 398 return err; 399 400 usleep_range(10, 20); 401 402 err = tegra_powergate_set(pg->id, true); 403 if (err < 0) 404 return err; 405 406 usleep_range(10, 20); 407 408 err = tegra_powergate_enable_clocks(pg); 409 if (err) 410 goto disable_clks; 411 412 usleep_range(10, 20); 413 414 err = __tegra_powergate_remove_clamping(pg->id); 415 if (err) 416 goto disable_clks; 417 418 usleep_range(10, 20); 419 420 err = reset_control_deassert(pg->reset); 421 if (err) 422 goto powergate_off; 423 424 usleep_range(10, 20); 425 426 if (pg->pmc->soc->needs_mbist_war) 427 err = tegra210_clk_handle_mbist_war(pg->id); 428 if (err) 429 goto disable_clks; 430 431 if (disable_clocks) 432 tegra_powergate_disable_clocks(pg); 433 434 return 0; 435 436 disable_clks: 437 tegra_powergate_disable_clocks(pg); 438 usleep_range(10, 20); 439 440 powergate_off: 441 tegra_powergate_set(pg->id, false); 442 443 return err; 444 } 445 446 static int tegra_powergate_power_down(struct tegra_powergate *pg) 447 { 448 int err; 449 450 err = tegra_powergate_enable_clocks(pg); 451 if (err) 452 return err; 453 454 usleep_range(10, 20); 455 456 err = reset_control_assert(pg->reset); 457 if (err) 458 goto disable_clks; 459 460 usleep_range(10, 20); 461 462 tegra_powergate_disable_clocks(pg); 463 464 usleep_range(10, 20); 465 466 err = tegra_powergate_set(pg->id, false); 467 if (err) 468 goto assert_resets; 469 470 return 0; 471 472 assert_resets: 473 tegra_powergate_enable_clocks(pg); 474 usleep_range(10, 20); 475 reset_control_deassert(pg->reset); 476 usleep_range(10, 20); 477 478 disable_clks: 479 tegra_powergate_disable_clocks(pg); 480 481 return err; 482 } 483 484 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 485 { 486 struct tegra_powergate *pg = to_powergate(domain); 487 int err; 488 489 err = tegra_powergate_power_up(pg, true); 490 if (err) 491 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, 492 err); 493 494 return err; 495 } 496 497 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 498 { 499 struct tegra_powergate *pg = to_powergate(domain); 500 int err; 501 502 err = tegra_powergate_power_down(pg); 503 if (err) 504 pr_err("failed to turn off PM domain %s: %d\n", 505 pg->genpd.name, err); 506 507 return err; 508 } 509 510 /** 511 * tegra_powergate_power_on() - power on partition 512 * @id: partition ID 513 */ 514 int tegra_powergate_power_on(unsigned int id) 515 { 516 if (!tegra_powergate_is_available(id)) 517 return -EINVAL; 518 519 return tegra_powergate_set(id, true); 520 } 521 522 /** 523 * tegra_powergate_power_off() - power off partition 524 * @id: partition ID 525 */ 526 int tegra_powergate_power_off(unsigned int id) 527 { 528 if (!tegra_powergate_is_available(id)) 529 return -EINVAL; 530 531 return tegra_powergate_set(id, false); 532 } 533 EXPORT_SYMBOL(tegra_powergate_power_off); 534 535 /** 536 * tegra_powergate_is_powered() - check if partition is powered 537 * @id: partition ID 538 */ 539 int tegra_powergate_is_powered(unsigned int id) 540 { 541 int status; 542 543 if (!tegra_powergate_is_valid(id)) 544 return -EINVAL; 545 546 mutex_lock(&pmc->powergates_lock); 547 status = tegra_powergate_state(id); 548 mutex_unlock(&pmc->powergates_lock); 549 550 return status; 551 } 552 553 /** 554 * tegra_powergate_remove_clamping() - remove power clamps for partition 555 * @id: partition ID 556 */ 557 int tegra_powergate_remove_clamping(unsigned int id) 558 { 559 if (!tegra_powergate_is_available(id)) 560 return -EINVAL; 561 562 return __tegra_powergate_remove_clamping(id); 563 } 564 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 565 566 /** 567 * tegra_powergate_sequence_power_up() - power up partition 568 * @id: partition ID 569 * @clk: clock for partition 570 * @rst: reset for partition 571 * 572 * Must be called with clk disabled, and returns with clk enabled. 573 */ 574 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 575 struct reset_control *rst) 576 { 577 struct tegra_powergate *pg; 578 int err; 579 580 if (!tegra_powergate_is_available(id)) 581 return -EINVAL; 582 583 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 584 if (!pg) 585 return -ENOMEM; 586 587 pg->id = id; 588 pg->clks = &clk; 589 pg->num_clks = 1; 590 pg->reset = rst; 591 pg->pmc = pmc; 592 593 err = tegra_powergate_power_up(pg, false); 594 if (err) 595 pr_err("failed to turn on partition %d: %d\n", id, err); 596 597 kfree(pg); 598 599 return err; 600 } 601 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 602 603 #ifdef CONFIG_SMP 604 /** 605 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 606 * @cpuid: CPU partition ID 607 * 608 * Returns the partition ID corresponding to the CPU partition ID or a 609 * negative error code on failure. 610 */ 611 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 612 { 613 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 614 return pmc->soc->cpu_powergates[cpuid]; 615 616 return -EINVAL; 617 } 618 619 /** 620 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 621 * @cpuid: CPU partition ID 622 */ 623 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 624 { 625 int id; 626 627 id = tegra_get_cpu_powergate_id(cpuid); 628 if (id < 0) 629 return false; 630 631 return tegra_powergate_is_powered(id); 632 } 633 634 /** 635 * tegra_pmc_cpu_power_on() - power on CPU partition 636 * @cpuid: CPU partition ID 637 */ 638 int tegra_pmc_cpu_power_on(unsigned int cpuid) 639 { 640 int id; 641 642 id = tegra_get_cpu_powergate_id(cpuid); 643 if (id < 0) 644 return id; 645 646 return tegra_powergate_set(id, true); 647 } 648 649 /** 650 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 651 * @cpuid: CPU partition ID 652 */ 653 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 654 { 655 int id; 656 657 id = tegra_get_cpu_powergate_id(cpuid); 658 if (id < 0) 659 return id; 660 661 return tegra_powergate_remove_clamping(id); 662 } 663 #endif /* CONFIG_SMP */ 664 665 static int tegra_pmc_restart_notify(struct notifier_block *this, 666 unsigned long action, void *data) 667 { 668 const char *cmd = data; 669 u32 value; 670 671 value = readl(pmc->scratch + pmc->soc->regs->scratch0); 672 value &= ~PMC_SCRATCH0_MODE_MASK; 673 674 if (cmd) { 675 if (strcmp(cmd, "recovery") == 0) 676 value |= PMC_SCRATCH0_MODE_RECOVERY; 677 678 if (strcmp(cmd, "bootloader") == 0) 679 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 680 681 if (strcmp(cmd, "forced-recovery") == 0) 682 value |= PMC_SCRATCH0_MODE_RCM; 683 } 684 685 writel(value, pmc->scratch + pmc->soc->regs->scratch0); 686 687 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 688 value = tegra_pmc_readl(PMC_CNTRL); 689 value |= PMC_CNTRL_MAIN_RST; 690 tegra_pmc_writel(value, PMC_CNTRL); 691 692 return NOTIFY_DONE; 693 } 694 695 static struct notifier_block tegra_pmc_restart_handler = { 696 .notifier_call = tegra_pmc_restart_notify, 697 .priority = 128, 698 }; 699 700 static int powergate_show(struct seq_file *s, void *data) 701 { 702 unsigned int i; 703 int status; 704 705 seq_printf(s, " powergate powered\n"); 706 seq_printf(s, "------------------\n"); 707 708 for (i = 0; i < pmc->soc->num_powergates; i++) { 709 status = tegra_powergate_is_powered(i); 710 if (status < 0) 711 continue; 712 713 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 714 status ? "yes" : "no"); 715 } 716 717 return 0; 718 } 719 720 static int powergate_open(struct inode *inode, struct file *file) 721 { 722 return single_open(file, powergate_show, inode->i_private); 723 } 724 725 static const struct file_operations powergate_fops = { 726 .open = powergate_open, 727 .read = seq_read, 728 .llseek = seq_lseek, 729 .release = single_release, 730 }; 731 732 static int tegra_powergate_debugfs_init(void) 733 { 734 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 735 &powergate_fops); 736 if (!pmc->debugfs) 737 return -ENOMEM; 738 739 return 0; 740 } 741 742 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 743 struct device_node *np) 744 { 745 struct clk *clk; 746 unsigned int i, count; 747 int err; 748 749 count = of_clk_get_parent_count(np); 750 if (count == 0) 751 return -ENODEV; 752 753 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 754 if (!pg->clks) 755 return -ENOMEM; 756 757 for (i = 0; i < count; i++) { 758 pg->clks[i] = of_clk_get(np, i); 759 if (IS_ERR(pg->clks[i])) { 760 err = PTR_ERR(pg->clks[i]); 761 goto err; 762 } 763 } 764 765 pg->num_clks = count; 766 767 return 0; 768 769 err: 770 while (i--) 771 clk_put(pg->clks[i]); 772 773 kfree(pg->clks); 774 775 return err; 776 } 777 778 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 779 struct device_node *np, bool off) 780 { 781 int err; 782 783 pg->reset = of_reset_control_array_get_exclusive(np); 784 if (IS_ERR(pg->reset)) { 785 err = PTR_ERR(pg->reset); 786 pr_err("failed to get device resets: %d\n", err); 787 return err; 788 } 789 790 if (off) 791 err = reset_control_assert(pg->reset); 792 else 793 err = reset_control_deassert(pg->reset); 794 795 if (err) 796 reset_control_put(pg->reset); 797 798 return err; 799 } 800 801 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 802 { 803 struct tegra_powergate *pg; 804 int id, err; 805 bool off; 806 807 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 808 if (!pg) 809 return; 810 811 id = tegra_powergate_lookup(pmc, np->name); 812 if (id < 0) { 813 pr_err("powergate lookup failed for %pOFn: %d\n", np, id); 814 goto free_mem; 815 } 816 817 /* 818 * Clear the bit for this powergate so it cannot be managed 819 * directly via the legacy APIs for controlling powergates. 820 */ 821 clear_bit(id, pmc->powergates_available); 822 823 pg->id = id; 824 pg->genpd.name = np->name; 825 pg->genpd.power_off = tegra_genpd_power_off; 826 pg->genpd.power_on = tegra_genpd_power_on; 827 pg->pmc = pmc; 828 829 off = !tegra_powergate_is_powered(pg->id); 830 831 err = tegra_powergate_of_get_clks(pg, np); 832 if (err < 0) { 833 pr_err("failed to get clocks for %pOFn: %d\n", np, err); 834 goto set_available; 835 } 836 837 err = tegra_powergate_of_get_resets(pg, np, off); 838 if (err < 0) { 839 pr_err("failed to get resets for %pOFn: %d\n", np, err); 840 goto remove_clks; 841 } 842 843 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 844 if (off) 845 WARN_ON(tegra_powergate_power_up(pg, true)); 846 847 goto remove_resets; 848 } 849 850 /* 851 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB 852 * host and super-speed partitions. Once the XHCI driver 853 * manages the partitions itself this code can be removed. Note 854 * that we don't register these partitions with the genpd core 855 * to avoid it from powering down the partitions as they appear 856 * to be unused. 857 */ 858 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && 859 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) { 860 if (off) 861 WARN_ON(tegra_powergate_power_up(pg, true)); 862 863 goto remove_resets; 864 } 865 866 err = pm_genpd_init(&pg->genpd, NULL, off); 867 if (err < 0) { 868 pr_err("failed to initialise PM domain %pOFn: %d\n", np, 869 err); 870 goto remove_resets; 871 } 872 873 err = of_genpd_add_provider_simple(np, &pg->genpd); 874 if (err < 0) { 875 pr_err("failed to add PM domain provider for %pOFn: %d\n", 876 np, err); 877 goto remove_genpd; 878 } 879 880 pr_debug("added PM domain %s\n", pg->genpd.name); 881 882 return; 883 884 remove_genpd: 885 pm_genpd_remove(&pg->genpd); 886 887 remove_resets: 888 reset_control_put(pg->reset); 889 890 remove_clks: 891 while (pg->num_clks--) 892 clk_put(pg->clks[pg->num_clks]); 893 894 kfree(pg->clks); 895 896 set_available: 897 set_bit(id, pmc->powergates_available); 898 899 free_mem: 900 kfree(pg); 901 } 902 903 static void tegra_powergate_init(struct tegra_pmc *pmc, 904 struct device_node *parent) 905 { 906 struct device_node *np, *child; 907 unsigned int i; 908 909 /* Create a bitmap of the available and valid partitions */ 910 for (i = 0; i < pmc->soc->num_powergates; i++) 911 if (pmc->soc->powergates[i]) 912 set_bit(i, pmc->powergates_available); 913 914 np = of_get_child_by_name(parent, "powergates"); 915 if (!np) 916 return; 917 918 for_each_child_of_node(np, child) 919 tegra_powergate_add(pmc, child); 920 921 of_node_put(np); 922 } 923 924 static const struct tegra_io_pad_soc * 925 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 926 { 927 unsigned int i; 928 929 for (i = 0; i < pmc->soc->num_io_pads; i++) 930 if (pmc->soc->io_pads[i].id == id) 931 return &pmc->soc->io_pads[i]; 932 933 return NULL; 934 } 935 936 static int tegra_io_pad_get_dpd_register_bit(enum tegra_io_pad id, 937 unsigned long *request, 938 unsigned long *status, 939 u32 *mask) 940 { 941 const struct tegra_io_pad_soc *pad; 942 943 pad = tegra_io_pad_find(pmc, id); 944 if (!pad) { 945 pr_err("invalid I/O pad ID %u\n", id); 946 return -ENOENT; 947 } 948 949 if (pad->dpd == UINT_MAX) 950 return -ENOTSUPP; 951 952 *mask = BIT(pad->dpd % 32); 953 954 if (pad->dpd < 32) { 955 *status = pmc->soc->regs->dpd_status; 956 *request = pmc->soc->regs->dpd_req; 957 } else { 958 *status = pmc->soc->regs->dpd2_status; 959 *request = pmc->soc->regs->dpd2_req; 960 } 961 962 return 0; 963 } 964 965 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 966 unsigned long *status, u32 *mask) 967 { 968 unsigned long rate, value; 969 int err; 970 971 err = tegra_io_pad_get_dpd_register_bit(id, request, status, mask); 972 if (err) 973 return err; 974 975 if (pmc->clk) { 976 rate = clk_get_rate(pmc->clk); 977 if (!rate) { 978 pr_err("failed to get clock rate\n"); 979 return -ENODEV; 980 } 981 982 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 983 984 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 985 value = DIV_ROUND_UP(1000000000, rate); 986 value = DIV_ROUND_UP(200, value); 987 tegra_pmc_writel(value, SEL_DPD_TIM); 988 } 989 990 return 0; 991 } 992 993 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 994 u32 val, unsigned long timeout) 995 { 996 u32 value; 997 998 timeout = jiffies + msecs_to_jiffies(timeout); 999 1000 while (time_after(timeout, jiffies)) { 1001 value = tegra_pmc_readl(offset); 1002 if ((value & mask) == val) 1003 return 0; 1004 1005 usleep_range(250, 1000); 1006 } 1007 1008 return -ETIMEDOUT; 1009 } 1010 1011 static void tegra_io_pad_unprepare(void) 1012 { 1013 if (pmc->clk) 1014 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1015 } 1016 1017 /** 1018 * tegra_io_pad_power_enable() - enable power to I/O pad 1019 * @id: Tegra I/O pad ID for which to enable power 1020 * 1021 * Returns: 0 on success or a negative error code on failure. 1022 */ 1023 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1024 { 1025 unsigned long request, status; 1026 u32 mask; 1027 int err; 1028 1029 mutex_lock(&pmc->powergates_lock); 1030 1031 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1032 if (err < 0) { 1033 pr_err("failed to prepare I/O pad: %d\n", err); 1034 goto unlock; 1035 } 1036 1037 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); 1038 1039 err = tegra_io_pad_poll(status, mask, 0, 250); 1040 if (err < 0) { 1041 pr_err("failed to enable I/O pad: %d\n", err); 1042 goto unlock; 1043 } 1044 1045 tegra_io_pad_unprepare(); 1046 1047 unlock: 1048 mutex_unlock(&pmc->powergates_lock); 1049 return err; 1050 } 1051 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1052 1053 /** 1054 * tegra_io_pad_power_disable() - disable power to I/O pad 1055 * @id: Tegra I/O pad ID for which to disable power 1056 * 1057 * Returns: 0 on success or a negative error code on failure. 1058 */ 1059 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1060 { 1061 unsigned long request, status; 1062 u32 mask; 1063 int err; 1064 1065 mutex_lock(&pmc->powergates_lock); 1066 1067 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1068 if (err < 0) { 1069 pr_err("failed to prepare I/O pad: %d\n", err); 1070 goto unlock; 1071 } 1072 1073 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); 1074 1075 err = tegra_io_pad_poll(status, mask, mask, 250); 1076 if (err < 0) { 1077 pr_err("failed to disable I/O pad: %d\n", err); 1078 goto unlock; 1079 } 1080 1081 tegra_io_pad_unprepare(); 1082 1083 unlock: 1084 mutex_unlock(&pmc->powergates_lock); 1085 return err; 1086 } 1087 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1088 1089 static int tegra_io_pad_is_powered(enum tegra_io_pad id) 1090 { 1091 unsigned long request, status; 1092 u32 mask, value; 1093 int err; 1094 1095 err = tegra_io_pad_get_dpd_register_bit(id, &request, &status, &mask); 1096 if (err) 1097 return err; 1098 1099 value = tegra_pmc_readl(status); 1100 1101 return !(value & mask); 1102 } 1103 1104 static int tegra_io_pad_set_voltage(enum tegra_io_pad id, int voltage) 1105 { 1106 const struct tegra_io_pad_soc *pad; 1107 u32 value; 1108 1109 pad = tegra_io_pad_find(pmc, id); 1110 if (!pad) 1111 return -ENOENT; 1112 1113 if (pad->voltage == UINT_MAX) 1114 return -ENOTSUPP; 1115 1116 mutex_lock(&pmc->powergates_lock); 1117 1118 if (pmc->soc->has_impl_33v_pwr) { 1119 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR); 1120 1121 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1122 value &= ~BIT(pad->voltage); 1123 else 1124 value |= BIT(pad->voltage); 1125 1126 tegra_pmc_writel(value, PMC_IMPL_E_33V_PWR); 1127 } else { 1128 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1129 value = tegra_pmc_readl(PMC_PWR_DET); 1130 value |= BIT(pad->voltage); 1131 tegra_pmc_writel(value, PMC_PWR_DET); 1132 1133 /* update I/O voltage */ 1134 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1135 1136 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1137 value &= ~BIT(pad->voltage); 1138 else 1139 value |= BIT(pad->voltage); 1140 1141 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1142 } 1143 1144 mutex_unlock(&pmc->powergates_lock); 1145 1146 usleep_range(100, 250); 1147 1148 return 0; 1149 } 1150 1151 static int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1152 { 1153 const struct tegra_io_pad_soc *pad; 1154 u32 value; 1155 1156 pad = tegra_io_pad_find(pmc, id); 1157 if (!pad) 1158 return -ENOENT; 1159 1160 if (pad->voltage == UINT_MAX) 1161 return -ENOTSUPP; 1162 1163 if (pmc->soc->has_impl_33v_pwr) 1164 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR); 1165 else 1166 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1167 1168 if ((value & BIT(pad->voltage)) == 0) 1169 return TEGRA_IO_PAD_VOLTAGE_1V8; 1170 1171 return TEGRA_IO_PAD_VOLTAGE_3V3; 1172 } 1173 1174 /** 1175 * tegra_io_rail_power_on() - enable power to I/O rail 1176 * @id: Tegra I/O pad ID for which to enable power 1177 * 1178 * See also: tegra_io_pad_power_enable() 1179 */ 1180 int tegra_io_rail_power_on(unsigned int id) 1181 { 1182 return tegra_io_pad_power_enable(id); 1183 } 1184 EXPORT_SYMBOL(tegra_io_rail_power_on); 1185 1186 /** 1187 * tegra_io_rail_power_off() - disable power to I/O rail 1188 * @id: Tegra I/O pad ID for which to disable power 1189 * 1190 * See also: tegra_io_pad_power_disable() 1191 */ 1192 int tegra_io_rail_power_off(unsigned int id) 1193 { 1194 return tegra_io_pad_power_disable(id); 1195 } 1196 EXPORT_SYMBOL(tegra_io_rail_power_off); 1197 1198 #ifdef CONFIG_PM_SLEEP 1199 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1200 { 1201 return pmc->suspend_mode; 1202 } 1203 1204 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1205 { 1206 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1207 return; 1208 1209 pmc->suspend_mode = mode; 1210 } 1211 1212 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1213 { 1214 unsigned long long rate = 0; 1215 u32 value; 1216 1217 switch (mode) { 1218 case TEGRA_SUSPEND_LP1: 1219 rate = 32768; 1220 break; 1221 1222 case TEGRA_SUSPEND_LP2: 1223 rate = clk_get_rate(pmc->clk); 1224 break; 1225 1226 default: 1227 break; 1228 } 1229 1230 if (WARN_ON_ONCE(rate == 0)) 1231 rate = 100000000; 1232 1233 if (rate != pmc->rate) { 1234 u64 ticks; 1235 1236 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1237 do_div(ticks, USEC_PER_SEC); 1238 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1239 1240 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1241 do_div(ticks, USEC_PER_SEC); 1242 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1243 1244 wmb(); 1245 1246 pmc->rate = rate; 1247 } 1248 1249 value = tegra_pmc_readl(PMC_CNTRL); 1250 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1251 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1252 tegra_pmc_writel(value, PMC_CNTRL); 1253 } 1254 #endif 1255 1256 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1257 { 1258 u32 value, values[2]; 1259 1260 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1261 } else { 1262 switch (value) { 1263 case 0: 1264 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1265 break; 1266 1267 case 1: 1268 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1269 break; 1270 1271 case 2: 1272 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1273 break; 1274 1275 default: 1276 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1277 break; 1278 } 1279 } 1280 1281 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1282 1283 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1284 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1285 1286 pmc->cpu_good_time = value; 1287 1288 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1289 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1290 1291 pmc->cpu_off_time = value; 1292 1293 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1294 values, ARRAY_SIZE(values))) 1295 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1296 1297 pmc->core_osc_time = values[0]; 1298 pmc->core_pmu_time = values[1]; 1299 1300 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1301 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1302 1303 pmc->core_off_time = value; 1304 1305 pmc->corereq_high = of_property_read_bool(np, 1306 "nvidia,core-power-req-active-high"); 1307 1308 pmc->sysclkreq_high = of_property_read_bool(np, 1309 "nvidia,sys-clock-req-active-high"); 1310 1311 pmc->combined_req = of_property_read_bool(np, 1312 "nvidia,combined-power-req"); 1313 1314 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1315 "nvidia,cpu-pwr-good-en"); 1316 1317 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1318 ARRAY_SIZE(values))) 1319 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1320 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1321 1322 pmc->lp0_vec_phys = values[0]; 1323 pmc->lp0_vec_size = values[1]; 1324 1325 return 0; 1326 } 1327 1328 static void tegra_pmc_init(struct tegra_pmc *pmc) 1329 { 1330 if (pmc->soc->init) 1331 pmc->soc->init(pmc); 1332 } 1333 1334 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1335 { 1336 static const char disabled[] = "emergency thermal reset disabled"; 1337 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1338 struct device *dev = pmc->dev; 1339 struct device_node *np; 1340 u32 value, checksum; 1341 1342 if (!pmc->soc->has_tsense_reset) 1343 return; 1344 1345 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1346 if (!np) { 1347 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1348 return; 1349 } 1350 1351 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1352 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1353 goto out; 1354 } 1355 1356 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1357 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1358 goto out; 1359 } 1360 1361 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1362 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1363 goto out; 1364 } 1365 1366 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1367 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1368 goto out; 1369 } 1370 1371 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1372 pinmux = 0; 1373 1374 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1375 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1376 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1377 1378 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1379 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1380 tegra_pmc_writel(value, PMC_SCRATCH54); 1381 1382 value = PMC_SCRATCH55_RESET_TEGRA; 1383 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1384 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1385 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1386 1387 /* 1388 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1389 * contain the checksum and are currently zero, so they are not added. 1390 */ 1391 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1392 + ((value >> 24) & 0xff); 1393 checksum &= 0xff; 1394 checksum = 0x100 - checksum; 1395 1396 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1397 1398 tegra_pmc_writel(value, PMC_SCRATCH55); 1399 1400 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1401 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1402 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1403 1404 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1405 1406 out: 1407 of_node_put(np); 1408 } 1409 1410 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1411 { 1412 return pmc->soc->num_io_pads; 1413 } 1414 1415 static const char *tegra_io_pad_pinctrl_get_group_name( 1416 struct pinctrl_dev *pctl, unsigned int group) 1417 { 1418 return pmc->soc->io_pads[group].name; 1419 } 1420 1421 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 1422 unsigned int group, 1423 const unsigned int **pins, 1424 unsigned int *num_pins) 1425 { 1426 *pins = &pmc->soc->io_pads[group].id; 1427 *num_pins = 1; 1428 return 0; 1429 } 1430 1431 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 1432 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 1433 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 1434 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 1435 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1436 .dt_free_map = pinconf_generic_dt_free_map, 1437 }; 1438 1439 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 1440 unsigned int pin, unsigned long *config) 1441 { 1442 const struct tegra_io_pad_soc *pad = tegra_io_pad_find(pmc, pin); 1443 enum pin_config_param param = pinconf_to_config_param(*config); 1444 int ret; 1445 u32 arg; 1446 1447 if (!pad) 1448 return -EINVAL; 1449 1450 switch (param) { 1451 case PIN_CONFIG_POWER_SOURCE: 1452 ret = tegra_io_pad_get_voltage(pad->id); 1453 if (ret < 0) 1454 return ret; 1455 arg = ret; 1456 break; 1457 case PIN_CONFIG_LOW_POWER_MODE: 1458 ret = tegra_io_pad_is_powered(pad->id); 1459 if (ret < 0) 1460 return ret; 1461 arg = !ret; 1462 break; 1463 default: 1464 return -EINVAL; 1465 } 1466 1467 *config = pinconf_to_config_packed(param, arg); 1468 1469 return 0; 1470 } 1471 1472 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 1473 unsigned int pin, unsigned long *configs, 1474 unsigned int num_configs) 1475 { 1476 const struct tegra_io_pad_soc *pad = tegra_io_pad_find(pmc, pin); 1477 enum pin_config_param param; 1478 unsigned int i; 1479 int err; 1480 u32 arg; 1481 1482 if (!pad) 1483 return -EINVAL; 1484 1485 for (i = 0; i < num_configs; ++i) { 1486 param = pinconf_to_config_param(configs[i]); 1487 arg = pinconf_to_config_argument(configs[i]); 1488 1489 switch (param) { 1490 case PIN_CONFIG_LOW_POWER_MODE: 1491 if (arg) 1492 err = tegra_io_pad_power_disable(pad->id); 1493 else 1494 err = tegra_io_pad_power_enable(pad->id); 1495 if (err) 1496 return err; 1497 break; 1498 case PIN_CONFIG_POWER_SOURCE: 1499 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 1500 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 1501 return -EINVAL; 1502 err = tegra_io_pad_set_voltage(pad->id, arg); 1503 if (err) 1504 return err; 1505 break; 1506 default: 1507 return -EINVAL; 1508 } 1509 } 1510 1511 return 0; 1512 } 1513 1514 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 1515 .pin_config_get = tegra_io_pad_pinconf_get, 1516 .pin_config_set = tegra_io_pad_pinconf_set, 1517 .is_generic = true, 1518 }; 1519 1520 static struct pinctrl_desc tegra_pmc_pctl_desc = { 1521 .pctlops = &tegra_io_pad_pinctrl_ops, 1522 .confops = &tegra_io_pad_pinconf_ops, 1523 }; 1524 1525 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 1526 { 1527 int err = 0; 1528 1529 if (!pmc->soc->num_pin_descs) 1530 return 0; 1531 1532 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 1533 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 1534 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 1535 1536 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 1537 pmc); 1538 if (IS_ERR(pmc->pctl_dev)) { 1539 err = PTR_ERR(pmc->pctl_dev); 1540 dev_err(pmc->dev, "unable to register pinctrl, %d\n", err); 1541 } 1542 1543 return err; 1544 } 1545 1546 static int tegra_pmc_probe(struct platform_device *pdev) 1547 { 1548 void __iomem *base; 1549 struct resource *res; 1550 int err; 1551 1552 /* 1553 * Early initialisation should have configured an initial 1554 * register mapping and setup the soc data pointer. If these 1555 * are not valid then something went badly wrong! 1556 */ 1557 if (WARN_ON(!pmc->base || !pmc->soc)) 1558 return -ENODEV; 1559 1560 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1561 if (err < 0) 1562 return err; 1563 1564 /* take over the memory region from the early initialization */ 1565 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1566 base = devm_ioremap_resource(&pdev->dev, res); 1567 if (IS_ERR(base)) 1568 return PTR_ERR(base); 1569 1570 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1571 if (res) { 1572 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1573 if (IS_ERR(pmc->wake)) 1574 return PTR_ERR(pmc->wake); 1575 } else { 1576 pmc->wake = base; 1577 } 1578 1579 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1580 if (res) { 1581 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1582 if (IS_ERR(pmc->aotag)) 1583 return PTR_ERR(pmc->aotag); 1584 } else { 1585 pmc->aotag = base; 1586 } 1587 1588 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1589 if (res) { 1590 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1591 if (IS_ERR(pmc->scratch)) 1592 return PTR_ERR(pmc->scratch); 1593 } else { 1594 pmc->scratch = base; 1595 } 1596 1597 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1598 if (IS_ERR(pmc->clk)) { 1599 err = PTR_ERR(pmc->clk); 1600 1601 if (err != -ENOENT) { 1602 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1603 return err; 1604 } 1605 1606 pmc->clk = NULL; 1607 } 1608 1609 pmc->dev = &pdev->dev; 1610 1611 tegra_pmc_init(pmc); 1612 1613 tegra_pmc_init_tsense_reset(pmc); 1614 1615 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1616 err = tegra_powergate_debugfs_init(); 1617 if (err < 0) 1618 return err; 1619 } 1620 1621 err = register_restart_handler(&tegra_pmc_restart_handler); 1622 if (err) { 1623 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1624 err); 1625 goto cleanup_debugfs; 1626 } 1627 1628 err = tegra_pmc_pinctrl_init(pmc); 1629 if (err) 1630 goto cleanup_restart_handler; 1631 1632 mutex_lock(&pmc->powergates_lock); 1633 iounmap(pmc->base); 1634 pmc->base = base; 1635 mutex_unlock(&pmc->powergates_lock); 1636 1637 return 0; 1638 1639 cleanup_restart_handler: 1640 unregister_restart_handler(&tegra_pmc_restart_handler); 1641 cleanup_debugfs: 1642 debugfs_remove(pmc->debugfs); 1643 return err; 1644 } 1645 1646 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1647 static int tegra_pmc_suspend(struct device *dev) 1648 { 1649 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1650 1651 return 0; 1652 } 1653 1654 static int tegra_pmc_resume(struct device *dev) 1655 { 1656 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1657 1658 return 0; 1659 } 1660 1661 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1662 1663 #endif 1664 1665 static const char * const tegra20_powergates[] = { 1666 [TEGRA_POWERGATE_CPU] = "cpu", 1667 [TEGRA_POWERGATE_3D] = "3d", 1668 [TEGRA_POWERGATE_VENC] = "venc", 1669 [TEGRA_POWERGATE_VDEC] = "vdec", 1670 [TEGRA_POWERGATE_PCIE] = "pcie", 1671 [TEGRA_POWERGATE_L2] = "l2", 1672 [TEGRA_POWERGATE_MPE] = "mpe", 1673 }; 1674 1675 static const struct tegra_pmc_regs tegra20_pmc_regs = { 1676 .scratch0 = 0x50, 1677 .dpd_req = 0x1b8, 1678 .dpd_status = 0x1bc, 1679 .dpd2_req = 0x1c0, 1680 .dpd2_status = 0x1c4, 1681 }; 1682 1683 static void tegra20_pmc_init(struct tegra_pmc *pmc) 1684 { 1685 u32 value; 1686 1687 /* Always enable CPU power request */ 1688 value = tegra_pmc_readl(PMC_CNTRL); 1689 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1690 tegra_pmc_writel(value, PMC_CNTRL); 1691 1692 value = tegra_pmc_readl(PMC_CNTRL); 1693 1694 if (pmc->sysclkreq_high) 1695 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1696 else 1697 value |= PMC_CNTRL_SYSCLK_POLARITY; 1698 1699 /* configure the output polarity while the request is tristated */ 1700 tegra_pmc_writel(value, PMC_CNTRL); 1701 1702 /* now enable the request */ 1703 value = tegra_pmc_readl(PMC_CNTRL); 1704 value |= PMC_CNTRL_SYSCLK_OE; 1705 tegra_pmc_writel(value, PMC_CNTRL); 1706 } 1707 1708 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1709 struct device_node *np, 1710 bool invert) 1711 { 1712 u32 value; 1713 1714 value = tegra_pmc_readl(PMC_CNTRL); 1715 1716 if (invert) 1717 value |= PMC_CNTRL_INTR_POLARITY; 1718 else 1719 value &= ~PMC_CNTRL_INTR_POLARITY; 1720 1721 tegra_pmc_writel(value, PMC_CNTRL); 1722 } 1723 1724 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1725 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1726 .powergates = tegra20_powergates, 1727 .num_cpu_powergates = 0, 1728 .cpu_powergates = NULL, 1729 .has_tsense_reset = false, 1730 .has_gpu_clamps = false, 1731 .num_io_pads = 0, 1732 .io_pads = NULL, 1733 .num_pin_descs = 0, 1734 .pin_descs = NULL, 1735 .regs = &tegra20_pmc_regs, 1736 .init = tegra20_pmc_init, 1737 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1738 }; 1739 1740 static const char * const tegra30_powergates[] = { 1741 [TEGRA_POWERGATE_CPU] = "cpu0", 1742 [TEGRA_POWERGATE_3D] = "3d0", 1743 [TEGRA_POWERGATE_VENC] = "venc", 1744 [TEGRA_POWERGATE_VDEC] = "vdec", 1745 [TEGRA_POWERGATE_PCIE] = "pcie", 1746 [TEGRA_POWERGATE_L2] = "l2", 1747 [TEGRA_POWERGATE_MPE] = "mpe", 1748 [TEGRA_POWERGATE_HEG] = "heg", 1749 [TEGRA_POWERGATE_SATA] = "sata", 1750 [TEGRA_POWERGATE_CPU1] = "cpu1", 1751 [TEGRA_POWERGATE_CPU2] = "cpu2", 1752 [TEGRA_POWERGATE_CPU3] = "cpu3", 1753 [TEGRA_POWERGATE_CELP] = "celp", 1754 [TEGRA_POWERGATE_3D1] = "3d1", 1755 }; 1756 1757 static const u8 tegra30_cpu_powergates[] = { 1758 TEGRA_POWERGATE_CPU, 1759 TEGRA_POWERGATE_CPU1, 1760 TEGRA_POWERGATE_CPU2, 1761 TEGRA_POWERGATE_CPU3, 1762 }; 1763 1764 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1765 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1766 .powergates = tegra30_powergates, 1767 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1768 .cpu_powergates = tegra30_cpu_powergates, 1769 .has_tsense_reset = true, 1770 .has_gpu_clamps = false, 1771 .has_impl_33v_pwr = false, 1772 .num_io_pads = 0, 1773 .io_pads = NULL, 1774 .num_pin_descs = 0, 1775 .pin_descs = NULL, 1776 .regs = &tegra20_pmc_regs, 1777 .init = tegra20_pmc_init, 1778 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1779 }; 1780 1781 static const char * const tegra114_powergates[] = { 1782 [TEGRA_POWERGATE_CPU] = "crail", 1783 [TEGRA_POWERGATE_3D] = "3d", 1784 [TEGRA_POWERGATE_VENC] = "venc", 1785 [TEGRA_POWERGATE_VDEC] = "vdec", 1786 [TEGRA_POWERGATE_MPE] = "mpe", 1787 [TEGRA_POWERGATE_HEG] = "heg", 1788 [TEGRA_POWERGATE_CPU1] = "cpu1", 1789 [TEGRA_POWERGATE_CPU2] = "cpu2", 1790 [TEGRA_POWERGATE_CPU3] = "cpu3", 1791 [TEGRA_POWERGATE_CELP] = "celp", 1792 [TEGRA_POWERGATE_CPU0] = "cpu0", 1793 [TEGRA_POWERGATE_C0NC] = "c0nc", 1794 [TEGRA_POWERGATE_C1NC] = "c1nc", 1795 [TEGRA_POWERGATE_DIS] = "dis", 1796 [TEGRA_POWERGATE_DISB] = "disb", 1797 [TEGRA_POWERGATE_XUSBA] = "xusba", 1798 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1799 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1800 }; 1801 1802 static const u8 tegra114_cpu_powergates[] = { 1803 TEGRA_POWERGATE_CPU0, 1804 TEGRA_POWERGATE_CPU1, 1805 TEGRA_POWERGATE_CPU2, 1806 TEGRA_POWERGATE_CPU3, 1807 }; 1808 1809 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1810 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1811 .powergates = tegra114_powergates, 1812 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1813 .cpu_powergates = tegra114_cpu_powergates, 1814 .has_tsense_reset = true, 1815 .has_gpu_clamps = false, 1816 .has_impl_33v_pwr = false, 1817 .num_io_pads = 0, 1818 .io_pads = NULL, 1819 .num_pin_descs = 0, 1820 .pin_descs = NULL, 1821 .regs = &tegra20_pmc_regs, 1822 .init = tegra20_pmc_init, 1823 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1824 }; 1825 1826 static const char * const tegra124_powergates[] = { 1827 [TEGRA_POWERGATE_CPU] = "crail", 1828 [TEGRA_POWERGATE_3D] = "3d", 1829 [TEGRA_POWERGATE_VENC] = "venc", 1830 [TEGRA_POWERGATE_PCIE] = "pcie", 1831 [TEGRA_POWERGATE_VDEC] = "vdec", 1832 [TEGRA_POWERGATE_MPE] = "mpe", 1833 [TEGRA_POWERGATE_HEG] = "heg", 1834 [TEGRA_POWERGATE_SATA] = "sata", 1835 [TEGRA_POWERGATE_CPU1] = "cpu1", 1836 [TEGRA_POWERGATE_CPU2] = "cpu2", 1837 [TEGRA_POWERGATE_CPU3] = "cpu3", 1838 [TEGRA_POWERGATE_CELP] = "celp", 1839 [TEGRA_POWERGATE_CPU0] = "cpu0", 1840 [TEGRA_POWERGATE_C0NC] = "c0nc", 1841 [TEGRA_POWERGATE_C1NC] = "c1nc", 1842 [TEGRA_POWERGATE_SOR] = "sor", 1843 [TEGRA_POWERGATE_DIS] = "dis", 1844 [TEGRA_POWERGATE_DISB] = "disb", 1845 [TEGRA_POWERGATE_XUSBA] = "xusba", 1846 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1847 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1848 [TEGRA_POWERGATE_VIC] = "vic", 1849 [TEGRA_POWERGATE_IRAM] = "iram", 1850 }; 1851 1852 static const u8 tegra124_cpu_powergates[] = { 1853 TEGRA_POWERGATE_CPU0, 1854 TEGRA_POWERGATE_CPU1, 1855 TEGRA_POWERGATE_CPU2, 1856 TEGRA_POWERGATE_CPU3, 1857 }; 1858 1859 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 1860 ((struct tegra_io_pad_soc) { \ 1861 .id = (_id), \ 1862 .dpd = (_dpd), \ 1863 .voltage = (_voltage), \ 1864 .name = (_name), \ 1865 }) 1866 1867 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 1868 ((struct pinctrl_pin_desc) { \ 1869 .number = (_id), \ 1870 .name = (_name) \ 1871 }) 1872 1873 #define TEGRA124_IO_PAD_TABLE(_pad) \ 1874 /* .id .dpd .voltage .name */ \ 1875 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 1876 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 1877 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 1878 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 1879 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 1880 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 1881 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 1882 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 1883 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 1884 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 1885 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 1886 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 1887 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 1888 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 1889 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 1890 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 1891 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 1892 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 1893 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 1894 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 1895 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 1896 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 1897 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 1898 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 1899 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 1900 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 1901 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 1902 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 1903 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 1904 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 1905 1906 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 1907 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 1908 }; 1909 1910 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 1911 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 1912 }; 1913 1914 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1915 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1916 .powergates = tegra124_powergates, 1917 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1918 .cpu_powergates = tegra124_cpu_powergates, 1919 .has_tsense_reset = true, 1920 .has_gpu_clamps = true, 1921 .has_impl_33v_pwr = false, 1922 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 1923 .io_pads = tegra124_io_pads, 1924 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 1925 .pin_descs = tegra124_pin_descs, 1926 .regs = &tegra20_pmc_regs, 1927 .init = tegra20_pmc_init, 1928 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1929 }; 1930 1931 static const char * const tegra210_powergates[] = { 1932 [TEGRA_POWERGATE_CPU] = "crail", 1933 [TEGRA_POWERGATE_3D] = "3d", 1934 [TEGRA_POWERGATE_VENC] = "venc", 1935 [TEGRA_POWERGATE_PCIE] = "pcie", 1936 [TEGRA_POWERGATE_MPE] = "mpe", 1937 [TEGRA_POWERGATE_SATA] = "sata", 1938 [TEGRA_POWERGATE_CPU1] = "cpu1", 1939 [TEGRA_POWERGATE_CPU2] = "cpu2", 1940 [TEGRA_POWERGATE_CPU3] = "cpu3", 1941 [TEGRA_POWERGATE_CPU0] = "cpu0", 1942 [TEGRA_POWERGATE_C0NC] = "c0nc", 1943 [TEGRA_POWERGATE_SOR] = "sor", 1944 [TEGRA_POWERGATE_DIS] = "dis", 1945 [TEGRA_POWERGATE_DISB] = "disb", 1946 [TEGRA_POWERGATE_XUSBA] = "xusba", 1947 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1948 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1949 [TEGRA_POWERGATE_VIC] = "vic", 1950 [TEGRA_POWERGATE_IRAM] = "iram", 1951 [TEGRA_POWERGATE_NVDEC] = "nvdec", 1952 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 1953 [TEGRA_POWERGATE_AUD] = "aud", 1954 [TEGRA_POWERGATE_DFD] = "dfd", 1955 [TEGRA_POWERGATE_VE2] = "ve2", 1956 }; 1957 1958 static const u8 tegra210_cpu_powergates[] = { 1959 TEGRA_POWERGATE_CPU0, 1960 TEGRA_POWERGATE_CPU1, 1961 TEGRA_POWERGATE_CPU2, 1962 TEGRA_POWERGATE_CPU3, 1963 }; 1964 1965 #define TEGRA210_IO_PAD_TABLE(_pad) \ 1966 /* .id .dpd .voltage .name */ \ 1967 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 1968 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 1969 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 1970 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 1971 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 1972 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 1973 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 1974 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 1975 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 1976 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 1977 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 1978 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 1979 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 1980 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 1981 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 1982 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 1983 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 1984 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 1985 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 1986 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 1987 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 1988 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 1989 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 1990 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 1991 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 1992 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 1993 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 1994 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 1995 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 1996 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 1997 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 1998 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 1999 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 2000 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2001 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2002 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2003 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 2004 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 2005 2006 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 2007 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 2008 }; 2009 2010 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 2011 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2012 }; 2013 2014 static const struct tegra_pmc_soc tegra210_pmc_soc = { 2015 .num_powergates = ARRAY_SIZE(tegra210_powergates), 2016 .powergates = tegra210_powergates, 2017 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 2018 .cpu_powergates = tegra210_cpu_powergates, 2019 .has_tsense_reset = true, 2020 .has_gpu_clamps = true, 2021 .has_impl_33v_pwr = false, 2022 .needs_mbist_war = true, 2023 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 2024 .io_pads = tegra210_io_pads, 2025 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 2026 .pin_descs = tegra210_pin_descs, 2027 .regs = &tegra20_pmc_regs, 2028 .init = tegra20_pmc_init, 2029 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2030 }; 2031 2032 #define TEGRA186_IO_PAD_TABLE(_pad) \ 2033 /* .id .dpd .voltage .name */ \ 2034 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2035 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2036 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2037 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2038 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 2039 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 2040 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2041 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 2042 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2043 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2044 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2045 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 2046 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2047 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2048 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2049 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 2050 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 2051 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 2052 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2053 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 2054 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 2055 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 2056 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 2057 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 2058 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 2059 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 2060 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 2061 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 2062 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 2063 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 2064 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 2065 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 2066 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 2067 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 2068 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 2069 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 2070 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 2071 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 2072 2073 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 2074 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 2075 }; 2076 2077 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 2078 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2079 }; 2080 2081 static const struct tegra_pmc_regs tegra186_pmc_regs = { 2082 .scratch0 = 0x2000, 2083 .dpd_req = 0x74, 2084 .dpd_status = 0x78, 2085 .dpd2_req = 0x7c, 2086 .dpd2_status = 0x80, 2087 }; 2088 2089 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2090 struct device_node *np, 2091 bool invert) 2092 { 2093 struct resource regs; 2094 void __iomem *wake; 2095 u32 value; 2096 int index; 2097 2098 index = of_property_match_string(np, "reg-names", "wake"); 2099 if (index < 0) { 2100 pr_err("failed to find PMC wake registers\n"); 2101 return; 2102 } 2103 2104 of_address_to_resource(np, index, ®s); 2105 2106 wake = ioremap_nocache(regs.start, resource_size(®s)); 2107 if (!wake) { 2108 pr_err("failed to map PMC wake registers\n"); 2109 return; 2110 } 2111 2112 value = readl(wake + WAKE_AOWAKE_CTRL); 2113 2114 if (invert) 2115 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 2116 else 2117 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 2118 2119 writel(value, wake + WAKE_AOWAKE_CTRL); 2120 2121 iounmap(wake); 2122 } 2123 2124 static const struct tegra_pmc_soc tegra186_pmc_soc = { 2125 .num_powergates = 0, 2126 .powergates = NULL, 2127 .num_cpu_powergates = 0, 2128 .cpu_powergates = NULL, 2129 .has_tsense_reset = false, 2130 .has_gpu_clamps = false, 2131 .has_impl_33v_pwr = true, 2132 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 2133 .io_pads = tegra186_io_pads, 2134 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 2135 .pin_descs = tegra186_pin_descs, 2136 .regs = &tegra186_pmc_regs, 2137 .init = NULL, 2138 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 2139 }; 2140 2141 static const struct of_device_id tegra_pmc_match[] = { 2142 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc }, 2143 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 2144 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 2145 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 2146 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 2147 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 2148 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 2149 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 2150 { } 2151 }; 2152 2153 static struct platform_driver tegra_pmc_driver = { 2154 .driver = { 2155 .name = "tegra-pmc", 2156 .suppress_bind_attrs = true, 2157 .of_match_table = tegra_pmc_match, 2158 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2159 .pm = &tegra_pmc_pm_ops, 2160 #endif 2161 }, 2162 .probe = tegra_pmc_probe, 2163 }; 2164 builtin_platform_driver(tegra_pmc_driver); 2165 2166 /* 2167 * Early initialization to allow access to registers in the very early boot 2168 * process. 2169 */ 2170 static int __init tegra_pmc_early_init(void) 2171 { 2172 const struct of_device_id *match; 2173 struct device_node *np; 2174 struct resource regs; 2175 bool invert; 2176 2177 mutex_init(&pmc->powergates_lock); 2178 2179 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 2180 if (!np) { 2181 /* 2182 * Fall back to legacy initialization for 32-bit ARM only. All 2183 * 64-bit ARM device tree files for Tegra are required to have 2184 * a PMC node. 2185 * 2186 * This is for backwards-compatibility with old device trees 2187 * that didn't contain a PMC node. Note that in this case the 2188 * SoC data can't be matched and therefore powergating is 2189 * disabled. 2190 */ 2191 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2192 pr_warn("DT node not found, powergating disabled\n"); 2193 2194 regs.start = 0x7000e400; 2195 regs.end = 0x7000e7ff; 2196 regs.flags = IORESOURCE_MEM; 2197 2198 pr_warn("Using memory region %pR\n", ®s); 2199 } else { 2200 /* 2201 * At this point we're not running on Tegra, so play 2202 * nice with multi-platform kernels. 2203 */ 2204 return 0; 2205 } 2206 } else { 2207 /* 2208 * Extract information from the device tree if we've found a 2209 * matching node. 2210 */ 2211 if (of_address_to_resource(np, 0, ®s) < 0) { 2212 pr_err("failed to get PMC registers\n"); 2213 of_node_put(np); 2214 return -ENXIO; 2215 } 2216 } 2217 2218 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 2219 if (!pmc->base) { 2220 pr_err("failed to map PMC registers\n"); 2221 of_node_put(np); 2222 return -ENXIO; 2223 } 2224 2225 if (np) { 2226 pmc->soc = match->data; 2227 2228 tegra_powergate_init(pmc, np); 2229 2230 /* 2231 * Invert the interrupt polarity if a PMC device tree node 2232 * exists and contains the nvidia,invert-interrupt property. 2233 */ 2234 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 2235 2236 pmc->soc->setup_irq_polarity(pmc, np, invert); 2237 2238 of_node_put(np); 2239 } 2240 2241 return 0; 2242 } 2243 early_initcall(tegra_pmc_early_init); 2244