1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. 6 * 7 * Author: 8 * Colin Cross <ccross@google.com> 9 * 10 * This software is licensed under the terms of the GNU General Public 11 * License version 2, as published by the Free Software Foundation, and 12 * may be copied, distributed, and modified under those terms. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 */ 20 21 #define pr_fmt(fmt) "tegra-pmc: " fmt 22 23 #include <linux/kernel.h> 24 #include <linux/clk.h> 25 #include <linux/clk/tegra.h> 26 #include <linux/debugfs.h> 27 #include <linux/delay.h> 28 #include <linux/err.h> 29 #include <linux/export.h> 30 #include <linux/init.h> 31 #include <linux/io.h> 32 #include <linux/iopoll.h> 33 #include <linux/irq.h> 34 #include <linux/irqdomain.h> 35 #include <linux/of.h> 36 #include <linux/of_address.h> 37 #include <linux/of_clk.h> 38 #include <linux/of_irq.h> 39 #include <linux/of_platform.h> 40 #include <linux/pinctrl/pinctrl.h> 41 #include <linux/pinctrl/pinconf.h> 42 #include <linux/pinctrl/pinconf-generic.h> 43 #include <linux/platform_device.h> 44 #include <linux/pm_domain.h> 45 #include <linux/reboot.h> 46 #include <linux/reset.h> 47 #include <linux/seq_file.h> 48 #include <linux/slab.h> 49 #include <linux/spinlock.h> 50 51 #include <soc/tegra/common.h> 52 #include <soc/tegra/fuse.h> 53 #include <soc/tegra/pmc.h> 54 55 #include <dt-bindings/interrupt-controller/arm-gic.h> 56 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 57 #include <dt-bindings/gpio/tegra186-gpio.h> 58 #include <dt-bindings/gpio/tegra194-gpio.h> 59 60 #define PMC_CNTRL 0x0 61 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 62 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 63 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 64 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 65 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 66 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 67 #define PMC_CNTRL_MAIN_RST BIT(4) 68 69 #define DPD_SAMPLE 0x020 70 #define DPD_SAMPLE_ENABLE BIT(0) 71 #define DPD_SAMPLE_DISABLE (0 << 0) 72 73 #define PWRGATE_TOGGLE 0x30 74 #define PWRGATE_TOGGLE_START BIT(8) 75 76 #define REMOVE_CLAMPING 0x34 77 78 #define PWRGATE_STATUS 0x38 79 80 #define PMC_IMPL_E_33V_PWR 0x40 81 82 #define PMC_PWR_DET 0x48 83 84 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 85 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 86 #define PMC_SCRATCH0_MODE_RCM BIT(1) 87 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 88 PMC_SCRATCH0_MODE_BOOTLOADER | \ 89 PMC_SCRATCH0_MODE_RCM) 90 91 #define PMC_CPUPWRGOOD_TIMER 0xc8 92 #define PMC_CPUPWROFF_TIMER 0xcc 93 94 #define PMC_PWR_DET_VALUE 0xe4 95 96 #define PMC_SCRATCH41 0x140 97 98 #define PMC_SENSOR_CTRL 0x1b0 99 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 100 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 101 102 #define PMC_RST_STATUS_POR 0 103 #define PMC_RST_STATUS_WATCHDOG 1 104 #define PMC_RST_STATUS_SENSOR 2 105 #define PMC_RST_STATUS_SW_MAIN 3 106 #define PMC_RST_STATUS_LP0 4 107 #define PMC_RST_STATUS_AOTAG 5 108 109 #define IO_DPD_REQ 0x1b8 110 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 111 #define IO_DPD_REQ_CODE_OFF (1U << 30) 112 #define IO_DPD_REQ_CODE_ON (2U << 30) 113 #define IO_DPD_REQ_CODE_MASK (3U << 30) 114 115 #define IO_DPD_STATUS 0x1bc 116 #define IO_DPD2_REQ 0x1c0 117 #define IO_DPD2_STATUS 0x1c4 118 #define SEL_DPD_TIM 0x1c8 119 120 #define PMC_SCRATCH54 0x258 121 #define PMC_SCRATCH54_DATA_SHIFT 8 122 #define PMC_SCRATCH54_ADDR_SHIFT 0 123 124 #define PMC_SCRATCH55 0x25c 125 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 126 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 127 #define PMC_SCRATCH55_PINMUX_SHIFT 24 128 #define PMC_SCRATCH55_16BITOP BIT(15) 129 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 130 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 131 132 #define GPU_RG_CNTRL 0x2d4 133 134 /* Tegra186 and later */ 135 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 136 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 137 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 138 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 139 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 140 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 141 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 142 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 143 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 144 145 #define WAKE_AOWAKE_CTRL 0x4f4 146 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 147 148 struct tegra_powergate { 149 struct generic_pm_domain genpd; 150 struct tegra_pmc *pmc; 151 unsigned int id; 152 struct clk **clks; 153 unsigned int num_clks; 154 struct reset_control *reset; 155 }; 156 157 struct tegra_io_pad_soc { 158 enum tegra_io_pad id; 159 unsigned int dpd; 160 unsigned int voltage; 161 const char *name; 162 }; 163 164 struct tegra_pmc_regs { 165 unsigned int scratch0; 166 unsigned int dpd_req; 167 unsigned int dpd_status; 168 unsigned int dpd2_req; 169 unsigned int dpd2_status; 170 unsigned int rst_status; 171 unsigned int rst_source_shift; 172 unsigned int rst_source_mask; 173 unsigned int rst_level_shift; 174 unsigned int rst_level_mask; 175 }; 176 177 struct tegra_wake_event { 178 const char *name; 179 unsigned int id; 180 unsigned int irq; 181 struct { 182 unsigned int instance; 183 unsigned int pin; 184 } gpio; 185 }; 186 187 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 188 { \ 189 .name = _name, \ 190 .id = _id, \ 191 .irq = _irq, \ 192 .gpio = { \ 193 .instance = UINT_MAX, \ 194 .pin = UINT_MAX, \ 195 }, \ 196 } 197 198 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 199 { \ 200 .name = _name, \ 201 .id = _id, \ 202 .irq = 0, \ 203 .gpio = { \ 204 .instance = _instance, \ 205 .pin = _pin, \ 206 }, \ 207 } 208 209 struct tegra_pmc_soc { 210 unsigned int num_powergates; 211 const char *const *powergates; 212 unsigned int num_cpu_powergates; 213 const u8 *cpu_powergates; 214 215 bool has_tsense_reset; 216 bool has_gpu_clamps; 217 bool needs_mbist_war; 218 bool has_impl_33v_pwr; 219 220 const struct tegra_io_pad_soc *io_pads; 221 unsigned int num_io_pads; 222 223 const struct pinctrl_pin_desc *pin_descs; 224 unsigned int num_pin_descs; 225 226 const struct tegra_pmc_regs *regs; 227 void (*init)(struct tegra_pmc *pmc); 228 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 229 struct device_node *np, 230 bool invert); 231 232 const char * const *reset_sources; 233 unsigned int num_reset_sources; 234 const char * const *reset_levels; 235 unsigned int num_reset_levels; 236 237 const struct tegra_wake_event *wake_events; 238 unsigned int num_wake_events; 239 }; 240 241 static const char * const tegra186_reset_sources[] = { 242 "SYS_RESET", 243 "AOWDT", 244 "MCCPLEXWDT", 245 "BPMPWDT", 246 "SCEWDT", 247 "SPEWDT", 248 "APEWDT", 249 "BCCPLEXWDT", 250 "SENSOR", 251 "AOTAG", 252 "VFSENSOR", 253 "SWREST", 254 "SC7", 255 "HSM", 256 "CORESIGHT" 257 }; 258 259 static const char * const tegra186_reset_levels[] = { 260 "L0", "L1", "L2", "WARM" 261 }; 262 263 static const char * const tegra30_reset_sources[] = { 264 "POWER_ON_RESET", 265 "WATCHDOG", 266 "SENSOR", 267 "SW_MAIN", 268 "LP0", 269 "AOTAG" 270 }; 271 272 /** 273 * struct tegra_pmc - NVIDIA Tegra PMC 274 * @dev: pointer to PMC device structure 275 * @base: pointer to I/O remapped register region 276 * @clk: pointer to pclk clock 277 * @soc: pointer to SoC data structure 278 * @debugfs: pointer to debugfs entry 279 * @rate: currently configured rate of pclk 280 * @suspend_mode: lowest suspend mode available 281 * @cpu_good_time: CPU power good time (in microseconds) 282 * @cpu_off_time: CPU power off time (in microsecends) 283 * @core_osc_time: core power good OSC time (in microseconds) 284 * @core_pmu_time: core power good PMU time (in microseconds) 285 * @core_off_time: core power off time (in microseconds) 286 * @corereq_high: core power request is active-high 287 * @sysclkreq_high: system clock request is active-high 288 * @combined_req: combined power request for CPU & core 289 * @cpu_pwr_good_en: CPU power good signal is enabled 290 * @lp0_vec_phys: physical base address of the LP0 warm boot code 291 * @lp0_vec_size: size of the LP0 warm boot code 292 * @powergates_available: Bitmap of available power gates 293 * @powergates_lock: mutex for power gate register access 294 */ 295 struct tegra_pmc { 296 struct device *dev; 297 void __iomem *base; 298 void __iomem *wake; 299 void __iomem *aotag; 300 void __iomem *scratch; 301 struct clk *clk; 302 struct dentry *debugfs; 303 304 const struct tegra_pmc_soc *soc; 305 306 unsigned long rate; 307 308 enum tegra_suspend_mode suspend_mode; 309 u32 cpu_good_time; 310 u32 cpu_off_time; 311 u32 core_osc_time; 312 u32 core_pmu_time; 313 u32 core_off_time; 314 bool corereq_high; 315 bool sysclkreq_high; 316 bool combined_req; 317 bool cpu_pwr_good_en; 318 u32 lp0_vec_phys; 319 u32 lp0_vec_size; 320 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 321 322 struct mutex powergates_lock; 323 324 struct pinctrl_dev *pctl_dev; 325 326 struct irq_domain *domain; 327 struct irq_chip irq; 328 }; 329 330 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 331 .base = NULL, 332 .suspend_mode = TEGRA_SUSPEND_NONE, 333 }; 334 335 static inline struct tegra_powergate * 336 to_powergate(struct generic_pm_domain *domain) 337 { 338 return container_of(domain, struct tegra_powergate, genpd); 339 } 340 341 static u32 tegra_pmc_readl(unsigned long offset) 342 { 343 return readl(pmc->base + offset); 344 } 345 346 static void tegra_pmc_writel(u32 value, unsigned long offset) 347 { 348 writel(value, pmc->base + offset); 349 } 350 351 static inline bool tegra_powergate_state(int id) 352 { 353 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 354 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 355 else 356 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 357 } 358 359 static inline bool tegra_powergate_is_valid(int id) 360 { 361 return (pmc->soc && pmc->soc->powergates[id]); 362 } 363 364 static inline bool tegra_powergate_is_available(int id) 365 { 366 return test_bit(id, pmc->powergates_available); 367 } 368 369 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 370 { 371 unsigned int i; 372 373 if (!pmc || !pmc->soc || !name) 374 return -EINVAL; 375 376 for (i = 0; i < pmc->soc->num_powergates; i++) { 377 if (!tegra_powergate_is_valid(i)) 378 continue; 379 380 if (!strcmp(name, pmc->soc->powergates[i])) 381 return i; 382 } 383 384 return -ENODEV; 385 } 386 387 /** 388 * tegra_powergate_set() - set the state of a partition 389 * @id: partition ID 390 * @new_state: new state of the partition 391 */ 392 static int tegra_powergate_set(unsigned int id, bool new_state) 393 { 394 bool status; 395 int err; 396 397 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 398 return -EINVAL; 399 400 mutex_lock(&pmc->powergates_lock); 401 402 if (tegra_powergate_state(id) == new_state) { 403 mutex_unlock(&pmc->powergates_lock); 404 return 0; 405 } 406 407 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 408 409 err = readx_poll_timeout(tegra_powergate_state, id, status, 410 status == new_state, 10, 100000); 411 412 mutex_unlock(&pmc->powergates_lock); 413 414 return err; 415 } 416 417 static int __tegra_powergate_remove_clamping(unsigned int id) 418 { 419 u32 mask; 420 421 mutex_lock(&pmc->powergates_lock); 422 423 /* 424 * On Tegra124 and later, the clamps for the GPU are controlled by a 425 * separate register (with different semantics). 426 */ 427 if (id == TEGRA_POWERGATE_3D) { 428 if (pmc->soc->has_gpu_clamps) { 429 tegra_pmc_writel(0, GPU_RG_CNTRL); 430 goto out; 431 } 432 } 433 434 /* 435 * Tegra 2 has a bug where PCIE and VDE clamping masks are 436 * swapped relatively to the partition ids 437 */ 438 if (id == TEGRA_POWERGATE_VDEC) 439 mask = (1 << TEGRA_POWERGATE_PCIE); 440 else if (id == TEGRA_POWERGATE_PCIE) 441 mask = (1 << TEGRA_POWERGATE_VDEC); 442 else 443 mask = (1 << id); 444 445 tegra_pmc_writel(mask, REMOVE_CLAMPING); 446 447 out: 448 mutex_unlock(&pmc->powergates_lock); 449 450 return 0; 451 } 452 453 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 454 { 455 unsigned int i; 456 457 for (i = 0; i < pg->num_clks; i++) 458 clk_disable_unprepare(pg->clks[i]); 459 } 460 461 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 462 { 463 unsigned int i; 464 int err; 465 466 for (i = 0; i < pg->num_clks; i++) { 467 err = clk_prepare_enable(pg->clks[i]); 468 if (err) 469 goto out; 470 } 471 472 return 0; 473 474 out: 475 while (i--) 476 clk_disable_unprepare(pg->clks[i]); 477 478 return err; 479 } 480 481 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 482 { 483 return 0; 484 } 485 486 static int tegra_powergate_power_up(struct tegra_powergate *pg, 487 bool disable_clocks) 488 { 489 int err; 490 491 err = reset_control_assert(pg->reset); 492 if (err) 493 return err; 494 495 usleep_range(10, 20); 496 497 err = tegra_powergate_set(pg->id, true); 498 if (err < 0) 499 return err; 500 501 usleep_range(10, 20); 502 503 err = tegra_powergate_enable_clocks(pg); 504 if (err) 505 goto disable_clks; 506 507 usleep_range(10, 20); 508 509 err = __tegra_powergate_remove_clamping(pg->id); 510 if (err) 511 goto disable_clks; 512 513 usleep_range(10, 20); 514 515 err = reset_control_deassert(pg->reset); 516 if (err) 517 goto powergate_off; 518 519 usleep_range(10, 20); 520 521 if (pg->pmc->soc->needs_mbist_war) 522 err = tegra210_clk_handle_mbist_war(pg->id); 523 if (err) 524 goto disable_clks; 525 526 if (disable_clocks) 527 tegra_powergate_disable_clocks(pg); 528 529 return 0; 530 531 disable_clks: 532 tegra_powergate_disable_clocks(pg); 533 usleep_range(10, 20); 534 535 powergate_off: 536 tegra_powergate_set(pg->id, false); 537 538 return err; 539 } 540 541 static int tegra_powergate_power_down(struct tegra_powergate *pg) 542 { 543 int err; 544 545 err = tegra_powergate_enable_clocks(pg); 546 if (err) 547 return err; 548 549 usleep_range(10, 20); 550 551 err = reset_control_assert(pg->reset); 552 if (err) 553 goto disable_clks; 554 555 usleep_range(10, 20); 556 557 tegra_powergate_disable_clocks(pg); 558 559 usleep_range(10, 20); 560 561 err = tegra_powergate_set(pg->id, false); 562 if (err) 563 goto assert_resets; 564 565 return 0; 566 567 assert_resets: 568 tegra_powergate_enable_clocks(pg); 569 usleep_range(10, 20); 570 reset_control_deassert(pg->reset); 571 usleep_range(10, 20); 572 573 disable_clks: 574 tegra_powergate_disable_clocks(pg); 575 576 return err; 577 } 578 579 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 580 { 581 struct tegra_powergate *pg = to_powergate(domain); 582 int err; 583 584 err = tegra_powergate_power_up(pg, true); 585 if (err) 586 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, 587 err); 588 589 return err; 590 } 591 592 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 593 { 594 struct tegra_powergate *pg = to_powergate(domain); 595 int err; 596 597 err = tegra_powergate_power_down(pg); 598 if (err) 599 pr_err("failed to turn off PM domain %s: %d\n", 600 pg->genpd.name, err); 601 602 return err; 603 } 604 605 /** 606 * tegra_powergate_power_on() - power on partition 607 * @id: partition ID 608 */ 609 int tegra_powergate_power_on(unsigned int id) 610 { 611 if (!tegra_powergate_is_available(id)) 612 return -EINVAL; 613 614 return tegra_powergate_set(id, true); 615 } 616 617 /** 618 * tegra_powergate_power_off() - power off partition 619 * @id: partition ID 620 */ 621 int tegra_powergate_power_off(unsigned int id) 622 { 623 if (!tegra_powergate_is_available(id)) 624 return -EINVAL; 625 626 return tegra_powergate_set(id, false); 627 } 628 EXPORT_SYMBOL(tegra_powergate_power_off); 629 630 /** 631 * tegra_powergate_is_powered() - check if partition is powered 632 * @id: partition ID 633 */ 634 int tegra_powergate_is_powered(unsigned int id) 635 { 636 if (!tegra_powergate_is_valid(id)) 637 return -EINVAL; 638 639 return tegra_powergate_state(id); 640 } 641 642 /** 643 * tegra_powergate_remove_clamping() - remove power clamps for partition 644 * @id: partition ID 645 */ 646 int tegra_powergate_remove_clamping(unsigned int id) 647 { 648 if (!tegra_powergate_is_available(id)) 649 return -EINVAL; 650 651 return __tegra_powergate_remove_clamping(id); 652 } 653 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 654 655 /** 656 * tegra_powergate_sequence_power_up() - power up partition 657 * @id: partition ID 658 * @clk: clock for partition 659 * @rst: reset for partition 660 * 661 * Must be called with clk disabled, and returns with clk enabled. 662 */ 663 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 664 struct reset_control *rst) 665 { 666 struct tegra_powergate *pg; 667 int err; 668 669 if (!tegra_powergate_is_available(id)) 670 return -EINVAL; 671 672 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 673 if (!pg) 674 return -ENOMEM; 675 676 pg->id = id; 677 pg->clks = &clk; 678 pg->num_clks = 1; 679 pg->reset = rst; 680 pg->pmc = pmc; 681 682 err = tegra_powergate_power_up(pg, false); 683 if (err) 684 pr_err("failed to turn on partition %d: %d\n", id, err); 685 686 kfree(pg); 687 688 return err; 689 } 690 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 691 692 /** 693 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 694 * @cpuid: CPU partition ID 695 * 696 * Returns the partition ID corresponding to the CPU partition ID or a 697 * negative error code on failure. 698 */ 699 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 700 { 701 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 702 return pmc->soc->cpu_powergates[cpuid]; 703 704 return -EINVAL; 705 } 706 707 /** 708 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 709 * @cpuid: CPU partition ID 710 */ 711 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 712 { 713 int id; 714 715 id = tegra_get_cpu_powergate_id(cpuid); 716 if (id < 0) 717 return false; 718 719 return tegra_powergate_is_powered(id); 720 } 721 722 /** 723 * tegra_pmc_cpu_power_on() - power on CPU partition 724 * @cpuid: CPU partition ID 725 */ 726 int tegra_pmc_cpu_power_on(unsigned int cpuid) 727 { 728 int id; 729 730 id = tegra_get_cpu_powergate_id(cpuid); 731 if (id < 0) 732 return id; 733 734 return tegra_powergate_set(id, true); 735 } 736 737 /** 738 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 739 * @cpuid: CPU partition ID 740 */ 741 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 742 { 743 int id; 744 745 id = tegra_get_cpu_powergate_id(cpuid); 746 if (id < 0) 747 return id; 748 749 return tegra_powergate_remove_clamping(id); 750 } 751 752 static int tegra_pmc_restart_notify(struct notifier_block *this, 753 unsigned long action, void *data) 754 { 755 const char *cmd = data; 756 u32 value; 757 758 value = readl(pmc->scratch + pmc->soc->regs->scratch0); 759 value &= ~PMC_SCRATCH0_MODE_MASK; 760 761 if (cmd) { 762 if (strcmp(cmd, "recovery") == 0) 763 value |= PMC_SCRATCH0_MODE_RECOVERY; 764 765 if (strcmp(cmd, "bootloader") == 0) 766 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 767 768 if (strcmp(cmd, "forced-recovery") == 0) 769 value |= PMC_SCRATCH0_MODE_RCM; 770 } 771 772 writel(value, pmc->scratch + pmc->soc->regs->scratch0); 773 774 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 775 value = tegra_pmc_readl(PMC_CNTRL); 776 value |= PMC_CNTRL_MAIN_RST; 777 tegra_pmc_writel(value, PMC_CNTRL); 778 779 return NOTIFY_DONE; 780 } 781 782 static struct notifier_block tegra_pmc_restart_handler = { 783 .notifier_call = tegra_pmc_restart_notify, 784 .priority = 128, 785 }; 786 787 static int powergate_show(struct seq_file *s, void *data) 788 { 789 unsigned int i; 790 int status; 791 792 seq_printf(s, " powergate powered\n"); 793 seq_printf(s, "------------------\n"); 794 795 for (i = 0; i < pmc->soc->num_powergates; i++) { 796 status = tegra_powergate_is_powered(i); 797 if (status < 0) 798 continue; 799 800 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 801 status ? "yes" : "no"); 802 } 803 804 return 0; 805 } 806 807 DEFINE_SHOW_ATTRIBUTE(powergate); 808 809 static int tegra_powergate_debugfs_init(void) 810 { 811 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 812 &powergate_fops); 813 if (!pmc->debugfs) 814 return -ENOMEM; 815 816 return 0; 817 } 818 819 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 820 struct device_node *np) 821 { 822 struct clk *clk; 823 unsigned int i, count; 824 int err; 825 826 count = of_clk_get_parent_count(np); 827 if (count == 0) 828 return -ENODEV; 829 830 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 831 if (!pg->clks) 832 return -ENOMEM; 833 834 for (i = 0; i < count; i++) { 835 pg->clks[i] = of_clk_get(np, i); 836 if (IS_ERR(pg->clks[i])) { 837 err = PTR_ERR(pg->clks[i]); 838 goto err; 839 } 840 } 841 842 pg->num_clks = count; 843 844 return 0; 845 846 err: 847 while (i--) 848 clk_put(pg->clks[i]); 849 850 kfree(pg->clks); 851 852 return err; 853 } 854 855 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 856 struct device_node *np, bool off) 857 { 858 int err; 859 860 pg->reset = of_reset_control_array_get_exclusive(np); 861 if (IS_ERR(pg->reset)) { 862 err = PTR_ERR(pg->reset); 863 pr_err("failed to get device resets: %d\n", err); 864 return err; 865 } 866 867 if (off) 868 err = reset_control_assert(pg->reset); 869 else 870 err = reset_control_deassert(pg->reset); 871 872 if (err) 873 reset_control_put(pg->reset); 874 875 return err; 876 } 877 878 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 879 { 880 struct tegra_powergate *pg; 881 int id, err; 882 bool off; 883 884 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 885 if (!pg) 886 return; 887 888 id = tegra_powergate_lookup(pmc, np->name); 889 if (id < 0) { 890 pr_err("powergate lookup failed for %pOFn: %d\n", np, id); 891 goto free_mem; 892 } 893 894 /* 895 * Clear the bit for this powergate so it cannot be managed 896 * directly via the legacy APIs for controlling powergates. 897 */ 898 clear_bit(id, pmc->powergates_available); 899 900 pg->id = id; 901 pg->genpd.name = np->name; 902 pg->genpd.power_off = tegra_genpd_power_off; 903 pg->genpd.power_on = tegra_genpd_power_on; 904 pg->pmc = pmc; 905 906 off = !tegra_powergate_is_powered(pg->id); 907 908 err = tegra_powergate_of_get_clks(pg, np); 909 if (err < 0) { 910 pr_err("failed to get clocks for %pOFn: %d\n", np, err); 911 goto set_available; 912 } 913 914 err = tegra_powergate_of_get_resets(pg, np, off); 915 if (err < 0) { 916 pr_err("failed to get resets for %pOFn: %d\n", np, err); 917 goto remove_clks; 918 } 919 920 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 921 if (off) 922 WARN_ON(tegra_powergate_power_up(pg, true)); 923 924 goto remove_resets; 925 } 926 927 err = pm_genpd_init(&pg->genpd, NULL, off); 928 if (err < 0) { 929 pr_err("failed to initialise PM domain %pOFn: %d\n", np, 930 err); 931 goto remove_resets; 932 } 933 934 err = of_genpd_add_provider_simple(np, &pg->genpd); 935 if (err < 0) { 936 pr_err("failed to add PM domain provider for %pOFn: %d\n", 937 np, err); 938 goto remove_genpd; 939 } 940 941 pr_debug("added PM domain %s\n", pg->genpd.name); 942 943 return; 944 945 remove_genpd: 946 pm_genpd_remove(&pg->genpd); 947 948 remove_resets: 949 reset_control_put(pg->reset); 950 951 remove_clks: 952 while (pg->num_clks--) 953 clk_put(pg->clks[pg->num_clks]); 954 955 kfree(pg->clks); 956 957 set_available: 958 set_bit(id, pmc->powergates_available); 959 960 free_mem: 961 kfree(pg); 962 } 963 964 static void tegra_powergate_init(struct tegra_pmc *pmc, 965 struct device_node *parent) 966 { 967 struct device_node *np, *child; 968 unsigned int i; 969 970 /* Create a bitmap of the available and valid partitions */ 971 for (i = 0; i < pmc->soc->num_powergates; i++) 972 if (pmc->soc->powergates[i]) 973 set_bit(i, pmc->powergates_available); 974 975 np = of_get_child_by_name(parent, "powergates"); 976 if (!np) 977 return; 978 979 for_each_child_of_node(np, child) 980 tegra_powergate_add(pmc, child); 981 982 of_node_put(np); 983 } 984 985 static const struct tegra_io_pad_soc * 986 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 987 { 988 unsigned int i; 989 990 for (i = 0; i < pmc->soc->num_io_pads; i++) 991 if (pmc->soc->io_pads[i].id == id) 992 return &pmc->soc->io_pads[i]; 993 994 return NULL; 995 } 996 997 static int tegra_io_pad_get_dpd_register_bit(enum tegra_io_pad id, 998 unsigned long *request, 999 unsigned long *status, 1000 u32 *mask) 1001 { 1002 const struct tegra_io_pad_soc *pad; 1003 1004 pad = tegra_io_pad_find(pmc, id); 1005 if (!pad) { 1006 pr_err("invalid I/O pad ID %u\n", id); 1007 return -ENOENT; 1008 } 1009 1010 if (pad->dpd == UINT_MAX) 1011 return -ENOTSUPP; 1012 1013 *mask = BIT(pad->dpd % 32); 1014 1015 if (pad->dpd < 32) { 1016 *status = pmc->soc->regs->dpd_status; 1017 *request = pmc->soc->regs->dpd_req; 1018 } else { 1019 *status = pmc->soc->regs->dpd2_status; 1020 *request = pmc->soc->regs->dpd2_req; 1021 } 1022 1023 return 0; 1024 } 1025 1026 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 1027 unsigned long *status, u32 *mask) 1028 { 1029 unsigned long rate, value; 1030 int err; 1031 1032 err = tegra_io_pad_get_dpd_register_bit(id, request, status, mask); 1033 if (err) 1034 return err; 1035 1036 if (pmc->clk) { 1037 rate = clk_get_rate(pmc->clk); 1038 if (!rate) { 1039 pr_err("failed to get clock rate\n"); 1040 return -ENODEV; 1041 } 1042 1043 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1044 1045 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1046 value = DIV_ROUND_UP(1000000000, rate); 1047 value = DIV_ROUND_UP(200, value); 1048 tegra_pmc_writel(value, SEL_DPD_TIM); 1049 } 1050 1051 return 0; 1052 } 1053 1054 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 1055 u32 val, unsigned long timeout) 1056 { 1057 u32 value; 1058 1059 timeout = jiffies + msecs_to_jiffies(timeout); 1060 1061 while (time_after(timeout, jiffies)) { 1062 value = tegra_pmc_readl(offset); 1063 if ((value & mask) == val) 1064 return 0; 1065 1066 usleep_range(250, 1000); 1067 } 1068 1069 return -ETIMEDOUT; 1070 } 1071 1072 static void tegra_io_pad_unprepare(void) 1073 { 1074 if (pmc->clk) 1075 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1076 } 1077 1078 /** 1079 * tegra_io_pad_power_enable() - enable power to I/O pad 1080 * @id: Tegra I/O pad ID for which to enable power 1081 * 1082 * Returns: 0 on success or a negative error code on failure. 1083 */ 1084 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1085 { 1086 unsigned long request, status; 1087 u32 mask; 1088 int err; 1089 1090 mutex_lock(&pmc->powergates_lock); 1091 1092 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1093 if (err < 0) { 1094 pr_err("failed to prepare I/O pad: %d\n", err); 1095 goto unlock; 1096 } 1097 1098 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); 1099 1100 err = tegra_io_pad_poll(status, mask, 0, 250); 1101 if (err < 0) { 1102 pr_err("failed to enable I/O pad: %d\n", err); 1103 goto unlock; 1104 } 1105 1106 tegra_io_pad_unprepare(); 1107 1108 unlock: 1109 mutex_unlock(&pmc->powergates_lock); 1110 return err; 1111 } 1112 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1113 1114 /** 1115 * tegra_io_pad_power_disable() - disable power to I/O pad 1116 * @id: Tegra I/O pad ID for which to disable power 1117 * 1118 * Returns: 0 on success or a negative error code on failure. 1119 */ 1120 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1121 { 1122 unsigned long request, status; 1123 u32 mask; 1124 int err; 1125 1126 mutex_lock(&pmc->powergates_lock); 1127 1128 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1129 if (err < 0) { 1130 pr_err("failed to prepare I/O pad: %d\n", err); 1131 goto unlock; 1132 } 1133 1134 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); 1135 1136 err = tegra_io_pad_poll(status, mask, mask, 250); 1137 if (err < 0) { 1138 pr_err("failed to disable I/O pad: %d\n", err); 1139 goto unlock; 1140 } 1141 1142 tegra_io_pad_unprepare(); 1143 1144 unlock: 1145 mutex_unlock(&pmc->powergates_lock); 1146 return err; 1147 } 1148 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1149 1150 static int tegra_io_pad_is_powered(enum tegra_io_pad id) 1151 { 1152 unsigned long request, status; 1153 u32 mask, value; 1154 int err; 1155 1156 err = tegra_io_pad_get_dpd_register_bit(id, &request, &status, &mask); 1157 if (err) 1158 return err; 1159 1160 value = tegra_pmc_readl(status); 1161 1162 return !(value & mask); 1163 } 1164 1165 static int tegra_io_pad_set_voltage(enum tegra_io_pad id, int voltage) 1166 { 1167 const struct tegra_io_pad_soc *pad; 1168 u32 value; 1169 1170 pad = tegra_io_pad_find(pmc, id); 1171 if (!pad) 1172 return -ENOENT; 1173 1174 if (pad->voltage == UINT_MAX) 1175 return -ENOTSUPP; 1176 1177 mutex_lock(&pmc->powergates_lock); 1178 1179 if (pmc->soc->has_impl_33v_pwr) { 1180 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR); 1181 1182 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1183 value &= ~BIT(pad->voltage); 1184 else 1185 value |= BIT(pad->voltage); 1186 1187 tegra_pmc_writel(value, PMC_IMPL_E_33V_PWR); 1188 } else { 1189 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1190 value = tegra_pmc_readl(PMC_PWR_DET); 1191 value |= BIT(pad->voltage); 1192 tegra_pmc_writel(value, PMC_PWR_DET); 1193 1194 /* update I/O voltage */ 1195 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1196 1197 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1198 value &= ~BIT(pad->voltage); 1199 else 1200 value |= BIT(pad->voltage); 1201 1202 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1203 } 1204 1205 mutex_unlock(&pmc->powergates_lock); 1206 1207 usleep_range(100, 250); 1208 1209 return 0; 1210 } 1211 1212 static int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1213 { 1214 const struct tegra_io_pad_soc *pad; 1215 u32 value; 1216 1217 pad = tegra_io_pad_find(pmc, id); 1218 if (!pad) 1219 return -ENOENT; 1220 1221 if (pad->voltage == UINT_MAX) 1222 return -ENOTSUPP; 1223 1224 if (pmc->soc->has_impl_33v_pwr) 1225 value = tegra_pmc_readl(PMC_IMPL_E_33V_PWR); 1226 else 1227 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1228 1229 if ((value & BIT(pad->voltage)) == 0) 1230 return TEGRA_IO_PAD_VOLTAGE_1V8; 1231 1232 return TEGRA_IO_PAD_VOLTAGE_3V3; 1233 } 1234 1235 /** 1236 * tegra_io_rail_power_on() - enable power to I/O rail 1237 * @id: Tegra I/O pad ID for which to enable power 1238 * 1239 * See also: tegra_io_pad_power_enable() 1240 */ 1241 int tegra_io_rail_power_on(unsigned int id) 1242 { 1243 return tegra_io_pad_power_enable(id); 1244 } 1245 EXPORT_SYMBOL(tegra_io_rail_power_on); 1246 1247 /** 1248 * tegra_io_rail_power_off() - disable power to I/O rail 1249 * @id: Tegra I/O pad ID for which to disable power 1250 * 1251 * See also: tegra_io_pad_power_disable() 1252 */ 1253 int tegra_io_rail_power_off(unsigned int id) 1254 { 1255 return tegra_io_pad_power_disable(id); 1256 } 1257 EXPORT_SYMBOL(tegra_io_rail_power_off); 1258 1259 #ifdef CONFIG_PM_SLEEP 1260 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1261 { 1262 return pmc->suspend_mode; 1263 } 1264 1265 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1266 { 1267 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1268 return; 1269 1270 pmc->suspend_mode = mode; 1271 } 1272 1273 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1274 { 1275 unsigned long long rate = 0; 1276 u32 value; 1277 1278 switch (mode) { 1279 case TEGRA_SUSPEND_LP1: 1280 rate = 32768; 1281 break; 1282 1283 case TEGRA_SUSPEND_LP2: 1284 rate = clk_get_rate(pmc->clk); 1285 break; 1286 1287 default: 1288 break; 1289 } 1290 1291 if (WARN_ON_ONCE(rate == 0)) 1292 rate = 100000000; 1293 1294 if (rate != pmc->rate) { 1295 u64 ticks; 1296 1297 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1298 do_div(ticks, USEC_PER_SEC); 1299 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1300 1301 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1302 do_div(ticks, USEC_PER_SEC); 1303 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1304 1305 wmb(); 1306 1307 pmc->rate = rate; 1308 } 1309 1310 value = tegra_pmc_readl(PMC_CNTRL); 1311 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1312 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1313 tegra_pmc_writel(value, PMC_CNTRL); 1314 } 1315 #endif 1316 1317 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1318 { 1319 u32 value, values[2]; 1320 1321 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1322 } else { 1323 switch (value) { 1324 case 0: 1325 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1326 break; 1327 1328 case 1: 1329 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1330 break; 1331 1332 case 2: 1333 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1334 break; 1335 1336 default: 1337 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1338 break; 1339 } 1340 } 1341 1342 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1343 1344 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1345 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1346 1347 pmc->cpu_good_time = value; 1348 1349 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1350 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1351 1352 pmc->cpu_off_time = value; 1353 1354 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1355 values, ARRAY_SIZE(values))) 1356 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1357 1358 pmc->core_osc_time = values[0]; 1359 pmc->core_pmu_time = values[1]; 1360 1361 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1362 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1363 1364 pmc->core_off_time = value; 1365 1366 pmc->corereq_high = of_property_read_bool(np, 1367 "nvidia,core-power-req-active-high"); 1368 1369 pmc->sysclkreq_high = of_property_read_bool(np, 1370 "nvidia,sys-clock-req-active-high"); 1371 1372 pmc->combined_req = of_property_read_bool(np, 1373 "nvidia,combined-power-req"); 1374 1375 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1376 "nvidia,cpu-pwr-good-en"); 1377 1378 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1379 ARRAY_SIZE(values))) 1380 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1381 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1382 1383 pmc->lp0_vec_phys = values[0]; 1384 pmc->lp0_vec_size = values[1]; 1385 1386 return 0; 1387 } 1388 1389 static void tegra_pmc_init(struct tegra_pmc *pmc) 1390 { 1391 if (pmc->soc->init) 1392 pmc->soc->init(pmc); 1393 } 1394 1395 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1396 { 1397 static const char disabled[] = "emergency thermal reset disabled"; 1398 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1399 struct device *dev = pmc->dev; 1400 struct device_node *np; 1401 u32 value, checksum; 1402 1403 if (!pmc->soc->has_tsense_reset) 1404 return; 1405 1406 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1407 if (!np) { 1408 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1409 return; 1410 } 1411 1412 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1413 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1414 goto out; 1415 } 1416 1417 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1418 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1419 goto out; 1420 } 1421 1422 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1423 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1424 goto out; 1425 } 1426 1427 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1428 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1429 goto out; 1430 } 1431 1432 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1433 pinmux = 0; 1434 1435 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1436 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1437 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1438 1439 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1440 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1441 tegra_pmc_writel(value, PMC_SCRATCH54); 1442 1443 value = PMC_SCRATCH55_RESET_TEGRA; 1444 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1445 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1446 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1447 1448 /* 1449 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1450 * contain the checksum and are currently zero, so they are not added. 1451 */ 1452 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1453 + ((value >> 24) & 0xff); 1454 checksum &= 0xff; 1455 checksum = 0x100 - checksum; 1456 1457 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1458 1459 tegra_pmc_writel(value, PMC_SCRATCH55); 1460 1461 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1462 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1463 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1464 1465 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1466 1467 out: 1468 of_node_put(np); 1469 } 1470 1471 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1472 { 1473 return pmc->soc->num_io_pads; 1474 } 1475 1476 static const char *tegra_io_pad_pinctrl_get_group_name( 1477 struct pinctrl_dev *pctl, unsigned int group) 1478 { 1479 return pmc->soc->io_pads[group].name; 1480 } 1481 1482 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 1483 unsigned int group, 1484 const unsigned int **pins, 1485 unsigned int *num_pins) 1486 { 1487 *pins = &pmc->soc->io_pads[group].id; 1488 *num_pins = 1; 1489 return 0; 1490 } 1491 1492 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 1493 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 1494 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 1495 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 1496 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1497 .dt_free_map = pinconf_generic_dt_free_map, 1498 }; 1499 1500 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 1501 unsigned int pin, unsigned long *config) 1502 { 1503 const struct tegra_io_pad_soc *pad = tegra_io_pad_find(pmc, pin); 1504 enum pin_config_param param = pinconf_to_config_param(*config); 1505 int ret; 1506 u32 arg; 1507 1508 if (!pad) 1509 return -EINVAL; 1510 1511 switch (param) { 1512 case PIN_CONFIG_POWER_SOURCE: 1513 ret = tegra_io_pad_get_voltage(pad->id); 1514 if (ret < 0) 1515 return ret; 1516 arg = ret; 1517 break; 1518 case PIN_CONFIG_LOW_POWER_MODE: 1519 ret = tegra_io_pad_is_powered(pad->id); 1520 if (ret < 0) 1521 return ret; 1522 arg = !ret; 1523 break; 1524 default: 1525 return -EINVAL; 1526 } 1527 1528 *config = pinconf_to_config_packed(param, arg); 1529 1530 return 0; 1531 } 1532 1533 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 1534 unsigned int pin, unsigned long *configs, 1535 unsigned int num_configs) 1536 { 1537 const struct tegra_io_pad_soc *pad = tegra_io_pad_find(pmc, pin); 1538 enum pin_config_param param; 1539 unsigned int i; 1540 int err; 1541 u32 arg; 1542 1543 if (!pad) 1544 return -EINVAL; 1545 1546 for (i = 0; i < num_configs; ++i) { 1547 param = pinconf_to_config_param(configs[i]); 1548 arg = pinconf_to_config_argument(configs[i]); 1549 1550 switch (param) { 1551 case PIN_CONFIG_LOW_POWER_MODE: 1552 if (arg) 1553 err = tegra_io_pad_power_disable(pad->id); 1554 else 1555 err = tegra_io_pad_power_enable(pad->id); 1556 if (err) 1557 return err; 1558 break; 1559 case PIN_CONFIG_POWER_SOURCE: 1560 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 1561 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 1562 return -EINVAL; 1563 err = tegra_io_pad_set_voltage(pad->id, arg); 1564 if (err) 1565 return err; 1566 break; 1567 default: 1568 return -EINVAL; 1569 } 1570 } 1571 1572 return 0; 1573 } 1574 1575 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 1576 .pin_config_get = tegra_io_pad_pinconf_get, 1577 .pin_config_set = tegra_io_pad_pinconf_set, 1578 .is_generic = true, 1579 }; 1580 1581 static struct pinctrl_desc tegra_pmc_pctl_desc = { 1582 .pctlops = &tegra_io_pad_pinctrl_ops, 1583 .confops = &tegra_io_pad_pinconf_ops, 1584 }; 1585 1586 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 1587 { 1588 int err = 0; 1589 1590 if (!pmc->soc->num_pin_descs) 1591 return 0; 1592 1593 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 1594 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 1595 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 1596 1597 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 1598 pmc); 1599 if (IS_ERR(pmc->pctl_dev)) { 1600 err = PTR_ERR(pmc->pctl_dev); 1601 dev_err(pmc->dev, "unable to register pinctrl, %d\n", err); 1602 } 1603 1604 return err; 1605 } 1606 1607 static ssize_t reset_reason_show(struct device *dev, 1608 struct device_attribute *attr, char *buf) 1609 { 1610 u32 value, rst_src; 1611 1612 value = tegra_pmc_readl(pmc->soc->regs->rst_status); 1613 rst_src = (value & pmc->soc->regs->rst_source_mask) >> 1614 pmc->soc->regs->rst_source_shift; 1615 1616 return sprintf(buf, "%s\n", pmc->soc->reset_sources[rst_src]); 1617 } 1618 1619 static DEVICE_ATTR_RO(reset_reason); 1620 1621 static ssize_t reset_level_show(struct device *dev, 1622 struct device_attribute *attr, char *buf) 1623 { 1624 u32 value, rst_lvl; 1625 1626 value = tegra_pmc_readl(pmc->soc->regs->rst_status); 1627 rst_lvl = (value & pmc->soc->regs->rst_level_mask) >> 1628 pmc->soc->regs->rst_level_shift; 1629 1630 return sprintf(buf, "%s\n", pmc->soc->reset_levels[rst_lvl]); 1631 } 1632 1633 static DEVICE_ATTR_RO(reset_level); 1634 1635 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 1636 { 1637 struct device *dev = pmc->dev; 1638 int err = 0; 1639 1640 if (pmc->soc->reset_sources) { 1641 err = device_create_file(dev, &dev_attr_reset_reason); 1642 if (err < 0) 1643 dev_warn(dev, 1644 "failed to create attr \"reset_reason\": %d\n", 1645 err); 1646 } 1647 1648 if (pmc->soc->reset_levels) { 1649 err = device_create_file(dev, &dev_attr_reset_level); 1650 if (err < 0) 1651 dev_warn(dev, 1652 "failed to create attr \"reset_level\": %d\n", 1653 err); 1654 } 1655 } 1656 1657 static int tegra_pmc_irq_translate(struct irq_domain *domain, 1658 struct irq_fwspec *fwspec, 1659 unsigned long *hwirq, 1660 unsigned int *type) 1661 { 1662 if (WARN_ON(fwspec->param_count < 2)) 1663 return -EINVAL; 1664 1665 *hwirq = fwspec->param[0]; 1666 *type = fwspec->param[1]; 1667 1668 return 0; 1669 } 1670 1671 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 1672 unsigned int num_irqs, void *data) 1673 { 1674 struct tegra_pmc *pmc = domain->host_data; 1675 const struct tegra_pmc_soc *soc = pmc->soc; 1676 struct irq_fwspec *fwspec = data; 1677 unsigned int i; 1678 int err = 0; 1679 1680 for (i = 0; i < soc->num_wake_events; i++) { 1681 const struct tegra_wake_event *event = &soc->wake_events[i]; 1682 1683 if (fwspec->param_count == 2) { 1684 struct irq_fwspec spec; 1685 1686 if (event->id != fwspec->param[0]) 1687 continue; 1688 1689 err = irq_domain_set_hwirq_and_chip(domain, virq, 1690 event->id, 1691 &pmc->irq, pmc); 1692 if (err < 0) 1693 break; 1694 1695 spec.fwnode = &pmc->dev->of_node->fwnode; 1696 spec.param_count = 3; 1697 spec.param[0] = GIC_SPI; 1698 spec.param[1] = event->irq; 1699 spec.param[2] = fwspec->param[1]; 1700 1701 err = irq_domain_alloc_irqs_parent(domain, virq, 1702 num_irqs, &spec); 1703 1704 break; 1705 } 1706 1707 if (fwspec->param_count == 3) { 1708 if (event->gpio.instance != fwspec->param[0] || 1709 event->gpio.pin != fwspec->param[1]) 1710 continue; 1711 1712 err = irq_domain_set_hwirq_and_chip(domain, virq, 1713 event->id, 1714 &pmc->irq, pmc); 1715 1716 break; 1717 } 1718 } 1719 1720 if (i == soc->num_wake_events) 1721 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX, 1722 &pmc->irq, pmc); 1723 1724 return err; 1725 } 1726 1727 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 1728 .translate = tegra_pmc_irq_translate, 1729 .alloc = tegra_pmc_irq_alloc, 1730 }; 1731 1732 static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 1733 { 1734 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 1735 unsigned int offset, bit; 1736 u32 value; 1737 1738 offset = data->hwirq / 32; 1739 bit = data->hwirq % 32; 1740 1741 /* clear wake status */ 1742 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 1743 1744 /* route wake to tier 2 */ 1745 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 1746 1747 if (!on) 1748 value &= ~(1 << bit); 1749 else 1750 value |= 1 << bit; 1751 1752 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 1753 1754 /* enable wakeup event */ 1755 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 1756 1757 return 0; 1758 } 1759 1760 static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type) 1761 { 1762 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 1763 u32 value; 1764 1765 if (data->hwirq == ULONG_MAX) 1766 return 0; 1767 1768 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 1769 1770 switch (type) { 1771 case IRQ_TYPE_EDGE_RISING: 1772 case IRQ_TYPE_LEVEL_HIGH: 1773 value |= WAKE_AOWAKE_CNTRL_LEVEL; 1774 break; 1775 1776 case IRQ_TYPE_EDGE_FALLING: 1777 case IRQ_TYPE_LEVEL_LOW: 1778 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 1779 break; 1780 1781 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 1782 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 1783 break; 1784 1785 default: 1786 return -EINVAL; 1787 } 1788 1789 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 1790 1791 return 0; 1792 } 1793 1794 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 1795 { 1796 struct irq_domain *parent = NULL; 1797 struct device_node *np; 1798 1799 np = of_irq_find_parent(pmc->dev->of_node); 1800 if (np) { 1801 parent = irq_find_host(np); 1802 of_node_put(np); 1803 } 1804 1805 if (!parent) 1806 return 0; 1807 1808 pmc->irq.name = dev_name(pmc->dev); 1809 pmc->irq.irq_mask = irq_chip_mask_parent; 1810 pmc->irq.irq_unmask = irq_chip_unmask_parent; 1811 pmc->irq.irq_eoi = irq_chip_eoi_parent; 1812 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent; 1813 pmc->irq.irq_set_type = tegra_pmc_irq_set_type; 1814 pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake; 1815 1816 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, 1817 &tegra_pmc_irq_domain_ops, pmc); 1818 if (!pmc->domain) { 1819 dev_err(pmc->dev, "failed to allocate domain\n"); 1820 return -ENOMEM; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int tegra_pmc_probe(struct platform_device *pdev) 1827 { 1828 void __iomem *base; 1829 struct resource *res; 1830 int err; 1831 1832 /* 1833 * Early initialisation should have configured an initial 1834 * register mapping and setup the soc data pointer. If these 1835 * are not valid then something went badly wrong! 1836 */ 1837 if (WARN_ON(!pmc->base || !pmc->soc)) 1838 return -ENODEV; 1839 1840 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1841 if (err < 0) 1842 return err; 1843 1844 /* take over the memory region from the early initialization */ 1845 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1846 base = devm_ioremap_resource(&pdev->dev, res); 1847 if (IS_ERR(base)) 1848 return PTR_ERR(base); 1849 1850 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1851 if (res) { 1852 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1853 if (IS_ERR(pmc->wake)) 1854 return PTR_ERR(pmc->wake); 1855 } else { 1856 pmc->wake = base; 1857 } 1858 1859 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1860 if (res) { 1861 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1862 if (IS_ERR(pmc->aotag)) 1863 return PTR_ERR(pmc->aotag); 1864 } else { 1865 pmc->aotag = base; 1866 } 1867 1868 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1869 if (res) { 1870 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1871 if (IS_ERR(pmc->scratch)) 1872 return PTR_ERR(pmc->scratch); 1873 } else { 1874 pmc->scratch = base; 1875 } 1876 1877 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1878 if (IS_ERR(pmc->clk)) { 1879 err = PTR_ERR(pmc->clk); 1880 1881 if (err != -ENOENT) { 1882 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1883 return err; 1884 } 1885 1886 pmc->clk = NULL; 1887 } 1888 1889 pmc->dev = &pdev->dev; 1890 1891 tegra_pmc_init(pmc); 1892 1893 tegra_pmc_init_tsense_reset(pmc); 1894 1895 tegra_pmc_reset_sysfs_init(pmc); 1896 1897 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1898 err = tegra_powergate_debugfs_init(); 1899 if (err < 0) 1900 return err; 1901 } 1902 1903 err = register_restart_handler(&tegra_pmc_restart_handler); 1904 if (err) { 1905 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1906 err); 1907 goto cleanup_debugfs; 1908 } 1909 1910 err = tegra_pmc_pinctrl_init(pmc); 1911 if (err) 1912 goto cleanup_restart_handler; 1913 1914 err = tegra_pmc_irq_init(pmc); 1915 if (err < 0) 1916 goto cleanup_restart_handler; 1917 1918 mutex_lock(&pmc->powergates_lock); 1919 iounmap(pmc->base); 1920 pmc->base = base; 1921 mutex_unlock(&pmc->powergates_lock); 1922 1923 return 0; 1924 1925 cleanup_restart_handler: 1926 unregister_restart_handler(&tegra_pmc_restart_handler); 1927 cleanup_debugfs: 1928 debugfs_remove(pmc->debugfs); 1929 return err; 1930 } 1931 1932 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1933 static int tegra_pmc_suspend(struct device *dev) 1934 { 1935 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1936 1937 return 0; 1938 } 1939 1940 static int tegra_pmc_resume(struct device *dev) 1941 { 1942 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1943 1944 return 0; 1945 } 1946 1947 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1948 1949 #endif 1950 1951 static const char * const tegra20_powergates[] = { 1952 [TEGRA_POWERGATE_CPU] = "cpu", 1953 [TEGRA_POWERGATE_3D] = "3d", 1954 [TEGRA_POWERGATE_VENC] = "venc", 1955 [TEGRA_POWERGATE_VDEC] = "vdec", 1956 [TEGRA_POWERGATE_PCIE] = "pcie", 1957 [TEGRA_POWERGATE_L2] = "l2", 1958 [TEGRA_POWERGATE_MPE] = "mpe", 1959 }; 1960 1961 static const struct tegra_pmc_regs tegra20_pmc_regs = { 1962 .scratch0 = 0x50, 1963 .dpd_req = 0x1b8, 1964 .dpd_status = 0x1bc, 1965 .dpd2_req = 0x1c0, 1966 .dpd2_status = 0x1c4, 1967 .rst_status = 0x1b4, 1968 .rst_source_shift = 0x0, 1969 .rst_source_mask = 0x7, 1970 .rst_level_shift = 0x0, 1971 .rst_level_mask = 0x0, 1972 }; 1973 1974 static void tegra20_pmc_init(struct tegra_pmc *pmc) 1975 { 1976 u32 value; 1977 1978 /* Always enable CPU power request */ 1979 value = tegra_pmc_readl(PMC_CNTRL); 1980 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1981 tegra_pmc_writel(value, PMC_CNTRL); 1982 1983 value = tegra_pmc_readl(PMC_CNTRL); 1984 1985 if (pmc->sysclkreq_high) 1986 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1987 else 1988 value |= PMC_CNTRL_SYSCLK_POLARITY; 1989 1990 /* configure the output polarity while the request is tristated */ 1991 tegra_pmc_writel(value, PMC_CNTRL); 1992 1993 /* now enable the request */ 1994 value = tegra_pmc_readl(PMC_CNTRL); 1995 value |= PMC_CNTRL_SYSCLK_OE; 1996 tegra_pmc_writel(value, PMC_CNTRL); 1997 } 1998 1999 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2000 struct device_node *np, 2001 bool invert) 2002 { 2003 u32 value; 2004 2005 value = tegra_pmc_readl(PMC_CNTRL); 2006 2007 if (invert) 2008 value |= PMC_CNTRL_INTR_POLARITY; 2009 else 2010 value &= ~PMC_CNTRL_INTR_POLARITY; 2011 2012 tegra_pmc_writel(value, PMC_CNTRL); 2013 } 2014 2015 static const struct tegra_pmc_soc tegra20_pmc_soc = { 2016 .num_powergates = ARRAY_SIZE(tegra20_powergates), 2017 .powergates = tegra20_powergates, 2018 .num_cpu_powergates = 0, 2019 .cpu_powergates = NULL, 2020 .has_tsense_reset = false, 2021 .has_gpu_clamps = false, 2022 .num_io_pads = 0, 2023 .io_pads = NULL, 2024 .num_pin_descs = 0, 2025 .pin_descs = NULL, 2026 .regs = &tegra20_pmc_regs, 2027 .init = tegra20_pmc_init, 2028 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2029 .reset_sources = NULL, 2030 .num_reset_sources = 0, 2031 .reset_levels = NULL, 2032 .num_reset_levels = 0, 2033 }; 2034 2035 static const char * const tegra30_powergates[] = { 2036 [TEGRA_POWERGATE_CPU] = "cpu0", 2037 [TEGRA_POWERGATE_3D] = "3d0", 2038 [TEGRA_POWERGATE_VENC] = "venc", 2039 [TEGRA_POWERGATE_VDEC] = "vdec", 2040 [TEGRA_POWERGATE_PCIE] = "pcie", 2041 [TEGRA_POWERGATE_L2] = "l2", 2042 [TEGRA_POWERGATE_MPE] = "mpe", 2043 [TEGRA_POWERGATE_HEG] = "heg", 2044 [TEGRA_POWERGATE_SATA] = "sata", 2045 [TEGRA_POWERGATE_CPU1] = "cpu1", 2046 [TEGRA_POWERGATE_CPU2] = "cpu2", 2047 [TEGRA_POWERGATE_CPU3] = "cpu3", 2048 [TEGRA_POWERGATE_CELP] = "celp", 2049 [TEGRA_POWERGATE_3D1] = "3d1", 2050 }; 2051 2052 static const u8 tegra30_cpu_powergates[] = { 2053 TEGRA_POWERGATE_CPU, 2054 TEGRA_POWERGATE_CPU1, 2055 TEGRA_POWERGATE_CPU2, 2056 TEGRA_POWERGATE_CPU3, 2057 }; 2058 2059 static const struct tegra_pmc_soc tegra30_pmc_soc = { 2060 .num_powergates = ARRAY_SIZE(tegra30_powergates), 2061 .powergates = tegra30_powergates, 2062 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 2063 .cpu_powergates = tegra30_cpu_powergates, 2064 .has_tsense_reset = true, 2065 .has_gpu_clamps = false, 2066 .has_impl_33v_pwr = false, 2067 .num_io_pads = 0, 2068 .io_pads = NULL, 2069 .num_pin_descs = 0, 2070 .pin_descs = NULL, 2071 .regs = &tegra20_pmc_regs, 2072 .init = tegra20_pmc_init, 2073 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2074 .reset_sources = tegra30_reset_sources, 2075 .num_reset_sources = 5, 2076 .reset_levels = NULL, 2077 .num_reset_levels = 0, 2078 }; 2079 2080 static const char * const tegra114_powergates[] = { 2081 [TEGRA_POWERGATE_CPU] = "crail", 2082 [TEGRA_POWERGATE_3D] = "3d", 2083 [TEGRA_POWERGATE_VENC] = "venc", 2084 [TEGRA_POWERGATE_VDEC] = "vdec", 2085 [TEGRA_POWERGATE_MPE] = "mpe", 2086 [TEGRA_POWERGATE_HEG] = "heg", 2087 [TEGRA_POWERGATE_CPU1] = "cpu1", 2088 [TEGRA_POWERGATE_CPU2] = "cpu2", 2089 [TEGRA_POWERGATE_CPU3] = "cpu3", 2090 [TEGRA_POWERGATE_CELP] = "celp", 2091 [TEGRA_POWERGATE_CPU0] = "cpu0", 2092 [TEGRA_POWERGATE_C0NC] = "c0nc", 2093 [TEGRA_POWERGATE_C1NC] = "c1nc", 2094 [TEGRA_POWERGATE_DIS] = "dis", 2095 [TEGRA_POWERGATE_DISB] = "disb", 2096 [TEGRA_POWERGATE_XUSBA] = "xusba", 2097 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2098 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2099 }; 2100 2101 static const u8 tegra114_cpu_powergates[] = { 2102 TEGRA_POWERGATE_CPU0, 2103 TEGRA_POWERGATE_CPU1, 2104 TEGRA_POWERGATE_CPU2, 2105 TEGRA_POWERGATE_CPU3, 2106 }; 2107 2108 static const struct tegra_pmc_soc tegra114_pmc_soc = { 2109 .num_powergates = ARRAY_SIZE(tegra114_powergates), 2110 .powergates = tegra114_powergates, 2111 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 2112 .cpu_powergates = tegra114_cpu_powergates, 2113 .has_tsense_reset = true, 2114 .has_gpu_clamps = false, 2115 .has_impl_33v_pwr = false, 2116 .num_io_pads = 0, 2117 .io_pads = NULL, 2118 .num_pin_descs = 0, 2119 .pin_descs = NULL, 2120 .regs = &tegra20_pmc_regs, 2121 .init = tegra20_pmc_init, 2122 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2123 .reset_sources = tegra30_reset_sources, 2124 .num_reset_sources = 5, 2125 .reset_levels = NULL, 2126 .num_reset_levels = 0, 2127 }; 2128 2129 static const char * const tegra124_powergates[] = { 2130 [TEGRA_POWERGATE_CPU] = "crail", 2131 [TEGRA_POWERGATE_3D] = "3d", 2132 [TEGRA_POWERGATE_VENC] = "venc", 2133 [TEGRA_POWERGATE_PCIE] = "pcie", 2134 [TEGRA_POWERGATE_VDEC] = "vdec", 2135 [TEGRA_POWERGATE_MPE] = "mpe", 2136 [TEGRA_POWERGATE_HEG] = "heg", 2137 [TEGRA_POWERGATE_SATA] = "sata", 2138 [TEGRA_POWERGATE_CPU1] = "cpu1", 2139 [TEGRA_POWERGATE_CPU2] = "cpu2", 2140 [TEGRA_POWERGATE_CPU3] = "cpu3", 2141 [TEGRA_POWERGATE_CELP] = "celp", 2142 [TEGRA_POWERGATE_CPU0] = "cpu0", 2143 [TEGRA_POWERGATE_C0NC] = "c0nc", 2144 [TEGRA_POWERGATE_C1NC] = "c1nc", 2145 [TEGRA_POWERGATE_SOR] = "sor", 2146 [TEGRA_POWERGATE_DIS] = "dis", 2147 [TEGRA_POWERGATE_DISB] = "disb", 2148 [TEGRA_POWERGATE_XUSBA] = "xusba", 2149 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2150 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2151 [TEGRA_POWERGATE_VIC] = "vic", 2152 [TEGRA_POWERGATE_IRAM] = "iram", 2153 }; 2154 2155 static const u8 tegra124_cpu_powergates[] = { 2156 TEGRA_POWERGATE_CPU0, 2157 TEGRA_POWERGATE_CPU1, 2158 TEGRA_POWERGATE_CPU2, 2159 TEGRA_POWERGATE_CPU3, 2160 }; 2161 2162 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 2163 ((struct tegra_io_pad_soc) { \ 2164 .id = (_id), \ 2165 .dpd = (_dpd), \ 2166 .voltage = (_voltage), \ 2167 .name = (_name), \ 2168 }) 2169 2170 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 2171 ((struct pinctrl_pin_desc) { \ 2172 .number = (_id), \ 2173 .name = (_name) \ 2174 }) 2175 2176 #define TEGRA124_IO_PAD_TABLE(_pad) \ 2177 /* .id .dpd .voltage .name */ \ 2178 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2179 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 2180 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 2181 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 2182 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2183 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 2184 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 2185 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2186 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 2187 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 2188 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 2189 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 2190 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2191 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 2192 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 2193 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2194 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 2195 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 2196 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 2197 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2198 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2199 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 2200 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 2201 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 2202 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 2203 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2204 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2205 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2206 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2207 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 2208 2209 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 2210 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 2211 }; 2212 2213 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 2214 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2215 }; 2216 2217 static const struct tegra_pmc_soc tegra124_pmc_soc = { 2218 .num_powergates = ARRAY_SIZE(tegra124_powergates), 2219 .powergates = tegra124_powergates, 2220 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 2221 .cpu_powergates = tegra124_cpu_powergates, 2222 .has_tsense_reset = true, 2223 .has_gpu_clamps = true, 2224 .has_impl_33v_pwr = false, 2225 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 2226 .io_pads = tegra124_io_pads, 2227 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 2228 .pin_descs = tegra124_pin_descs, 2229 .regs = &tegra20_pmc_regs, 2230 .init = tegra20_pmc_init, 2231 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2232 .reset_sources = tegra30_reset_sources, 2233 .num_reset_sources = 5, 2234 .reset_levels = NULL, 2235 .num_reset_levels = 0, 2236 }; 2237 2238 static const char * const tegra210_powergates[] = { 2239 [TEGRA_POWERGATE_CPU] = "crail", 2240 [TEGRA_POWERGATE_3D] = "3d", 2241 [TEGRA_POWERGATE_VENC] = "venc", 2242 [TEGRA_POWERGATE_PCIE] = "pcie", 2243 [TEGRA_POWERGATE_MPE] = "mpe", 2244 [TEGRA_POWERGATE_SATA] = "sata", 2245 [TEGRA_POWERGATE_CPU1] = "cpu1", 2246 [TEGRA_POWERGATE_CPU2] = "cpu2", 2247 [TEGRA_POWERGATE_CPU3] = "cpu3", 2248 [TEGRA_POWERGATE_CPU0] = "cpu0", 2249 [TEGRA_POWERGATE_C0NC] = "c0nc", 2250 [TEGRA_POWERGATE_SOR] = "sor", 2251 [TEGRA_POWERGATE_DIS] = "dis", 2252 [TEGRA_POWERGATE_DISB] = "disb", 2253 [TEGRA_POWERGATE_XUSBA] = "xusba", 2254 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2255 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2256 [TEGRA_POWERGATE_VIC] = "vic", 2257 [TEGRA_POWERGATE_IRAM] = "iram", 2258 [TEGRA_POWERGATE_NVDEC] = "nvdec", 2259 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 2260 [TEGRA_POWERGATE_AUD] = "aud", 2261 [TEGRA_POWERGATE_DFD] = "dfd", 2262 [TEGRA_POWERGATE_VE2] = "ve2", 2263 }; 2264 2265 static const u8 tegra210_cpu_powergates[] = { 2266 TEGRA_POWERGATE_CPU0, 2267 TEGRA_POWERGATE_CPU1, 2268 TEGRA_POWERGATE_CPU2, 2269 TEGRA_POWERGATE_CPU3, 2270 }; 2271 2272 #define TEGRA210_IO_PAD_TABLE(_pad) \ 2273 /* .id .dpd .voltage .name */ \ 2274 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 2275 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 2276 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 2277 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2278 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2279 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 2280 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 2281 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 2282 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 2283 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 2284 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 2285 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 2286 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 2287 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2288 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 2289 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 2290 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 2291 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 2292 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 2293 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 2294 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 2295 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2296 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 2297 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2298 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 2299 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 2300 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2301 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 2302 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 2303 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 2304 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 2305 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 2306 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 2307 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2308 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2309 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2310 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 2311 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 2312 2313 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 2314 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 2315 }; 2316 2317 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 2318 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2319 }; 2320 2321 static const struct tegra_pmc_soc tegra210_pmc_soc = { 2322 .num_powergates = ARRAY_SIZE(tegra210_powergates), 2323 .powergates = tegra210_powergates, 2324 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 2325 .cpu_powergates = tegra210_cpu_powergates, 2326 .has_tsense_reset = true, 2327 .has_gpu_clamps = true, 2328 .has_impl_33v_pwr = false, 2329 .needs_mbist_war = true, 2330 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 2331 .io_pads = tegra210_io_pads, 2332 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 2333 .pin_descs = tegra210_pin_descs, 2334 .regs = &tegra20_pmc_regs, 2335 .init = tegra20_pmc_init, 2336 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2337 .reset_sources = tegra30_reset_sources, 2338 .num_reset_sources = 5, 2339 .reset_levels = NULL, 2340 .num_reset_levels = 0, 2341 }; 2342 2343 #define TEGRA186_IO_PAD_TABLE(_pad) \ 2344 /* .id .dpd .voltage .name */ \ 2345 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2346 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2347 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2348 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2349 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 2350 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 2351 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2352 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 2353 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2354 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2355 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2356 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 2357 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2358 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2359 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2360 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 2361 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 2362 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 2363 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2364 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 2365 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 2366 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 2367 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 2368 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 2369 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 2370 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 2371 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 2372 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 2373 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 2374 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 2375 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 2376 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 2377 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 2378 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 2379 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 2380 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 2381 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 2382 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 2383 2384 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 2385 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 2386 }; 2387 2388 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 2389 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2390 }; 2391 2392 static const struct tegra_pmc_regs tegra186_pmc_regs = { 2393 .scratch0 = 0x2000, 2394 .dpd_req = 0x74, 2395 .dpd_status = 0x78, 2396 .dpd2_req = 0x7c, 2397 .dpd2_status = 0x80, 2398 .rst_status = 0x70, 2399 .rst_source_shift = 0x2, 2400 .rst_source_mask = 0x3C, 2401 .rst_level_shift = 0x0, 2402 .rst_level_mask = 0x3, 2403 }; 2404 2405 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2406 struct device_node *np, 2407 bool invert) 2408 { 2409 struct resource regs; 2410 void __iomem *wake; 2411 u32 value; 2412 int index; 2413 2414 index = of_property_match_string(np, "reg-names", "wake"); 2415 if (index < 0) { 2416 pr_err("failed to find PMC wake registers\n"); 2417 return; 2418 } 2419 2420 of_address_to_resource(np, index, ®s); 2421 2422 wake = ioremap_nocache(regs.start, resource_size(®s)); 2423 if (!wake) { 2424 pr_err("failed to map PMC wake registers\n"); 2425 return; 2426 } 2427 2428 value = readl(wake + WAKE_AOWAKE_CTRL); 2429 2430 if (invert) 2431 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 2432 else 2433 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 2434 2435 writel(value, wake + WAKE_AOWAKE_CTRL); 2436 2437 iounmap(wake); 2438 } 2439 2440 static const struct tegra_wake_event tegra186_wake_events[] = { 2441 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA_AON_GPIO(FF, 0)), 2442 TEGRA_WAKE_IRQ("rtc", 73, 10), 2443 }; 2444 2445 static const struct tegra_pmc_soc tegra186_pmc_soc = { 2446 .num_powergates = 0, 2447 .powergates = NULL, 2448 .num_cpu_powergates = 0, 2449 .cpu_powergates = NULL, 2450 .has_tsense_reset = false, 2451 .has_gpu_clamps = false, 2452 .has_impl_33v_pwr = true, 2453 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 2454 .io_pads = tegra186_io_pads, 2455 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 2456 .pin_descs = tegra186_pin_descs, 2457 .regs = &tegra186_pmc_regs, 2458 .init = NULL, 2459 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 2460 .reset_sources = tegra186_reset_sources, 2461 .num_reset_sources = 14, 2462 .reset_levels = tegra186_reset_levels, 2463 .num_reset_levels = 3, 2464 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 2465 .wake_events = tegra186_wake_events, 2466 }; 2467 2468 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 2469 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 2470 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 2471 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 2472 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, 2473 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, 2474 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 2475 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, 2476 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX }, 2477 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX }, 2478 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX }, 2479 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX }, 2480 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX }, 2481 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 2482 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX }, 2483 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX }, 2484 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 2485 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX }, 2486 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX }, 2487 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX }, 2488 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX }, 2489 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX }, 2490 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX }, 2491 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX }, 2492 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, 2493 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX }, 2494 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX }, 2495 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, 2496 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, 2497 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 2498 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX }, 2499 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX }, 2500 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX }, 2501 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, 2502 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX }, 2503 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, 2504 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, 2505 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, 2506 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, 2507 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, 2508 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, 2509 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX }, 2510 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX }, 2511 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, 2512 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, 2513 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, 2514 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, 2515 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, 2516 }; 2517 2518 static const struct tegra_wake_event tegra194_wake_events[] = { 2519 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 2520 TEGRA_WAKE_IRQ("rtc", 73, 10), 2521 }; 2522 2523 static const struct tegra_pmc_soc tegra194_pmc_soc = { 2524 .num_powergates = 0, 2525 .powergates = NULL, 2526 .num_cpu_powergates = 0, 2527 .cpu_powergates = NULL, 2528 .has_tsense_reset = false, 2529 .has_gpu_clamps = false, 2530 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 2531 .io_pads = tegra194_io_pads, 2532 .regs = &tegra186_pmc_regs, 2533 .init = NULL, 2534 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 2535 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 2536 .wake_events = tegra194_wake_events, 2537 }; 2538 2539 static const struct of_device_id tegra_pmc_match[] = { 2540 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 2541 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 2542 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 2543 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 2544 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 2545 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 2546 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 2547 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 2548 { } 2549 }; 2550 2551 static struct platform_driver tegra_pmc_driver = { 2552 .driver = { 2553 .name = "tegra-pmc", 2554 .suppress_bind_attrs = true, 2555 .of_match_table = tegra_pmc_match, 2556 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2557 .pm = &tegra_pmc_pm_ops, 2558 #endif 2559 }, 2560 .probe = tegra_pmc_probe, 2561 }; 2562 builtin_platform_driver(tegra_pmc_driver); 2563 2564 /* 2565 * Early initialization to allow access to registers in the very early boot 2566 * process. 2567 */ 2568 static int __init tegra_pmc_early_init(void) 2569 { 2570 const struct of_device_id *match; 2571 struct device_node *np; 2572 struct resource regs; 2573 bool invert; 2574 2575 mutex_init(&pmc->powergates_lock); 2576 2577 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 2578 if (!np) { 2579 /* 2580 * Fall back to legacy initialization for 32-bit ARM only. All 2581 * 64-bit ARM device tree files for Tegra are required to have 2582 * a PMC node. 2583 * 2584 * This is for backwards-compatibility with old device trees 2585 * that didn't contain a PMC node. Note that in this case the 2586 * SoC data can't be matched and therefore powergating is 2587 * disabled. 2588 */ 2589 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 2590 pr_warn("DT node not found, powergating disabled\n"); 2591 2592 regs.start = 0x7000e400; 2593 regs.end = 0x7000e7ff; 2594 regs.flags = IORESOURCE_MEM; 2595 2596 pr_warn("Using memory region %pR\n", ®s); 2597 } else { 2598 /* 2599 * At this point we're not running on Tegra, so play 2600 * nice with multi-platform kernels. 2601 */ 2602 return 0; 2603 } 2604 } else { 2605 /* 2606 * Extract information from the device tree if we've found a 2607 * matching node. 2608 */ 2609 if (of_address_to_resource(np, 0, ®s) < 0) { 2610 pr_err("failed to get PMC registers\n"); 2611 of_node_put(np); 2612 return -ENXIO; 2613 } 2614 } 2615 2616 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 2617 if (!pmc->base) { 2618 pr_err("failed to map PMC registers\n"); 2619 of_node_put(np); 2620 return -ENXIO; 2621 } 2622 2623 if (np) { 2624 pmc->soc = match->data; 2625 2626 tegra_powergate_init(pmc, np); 2627 2628 /* 2629 * Invert the interrupt polarity if a PMC device tree node 2630 * exists and contains the nvidia,invert-interrupt property. 2631 */ 2632 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 2633 2634 pmc->soc->setup_irq_polarity(pmc, np, invert); 2635 2636 of_node_put(np); 2637 } 2638 2639 return 0; 2640 } 2641 early_initcall(tegra_pmc_early_init); 2642