1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #define pr_fmt(fmt) "tegra-pmc: " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/clk/tegra.h> 25 #include <linux/debugfs.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/export.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_platform.h> 35 #include <linux/platform_device.h> 36 #include <linux/pm_domain.h> 37 #include <linux/reboot.h> 38 #include <linux/reset.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 43 #include <soc/tegra/common.h> 44 #include <soc/tegra/fuse.h> 45 #include <soc/tegra/pmc.h> 46 47 #define PMC_CNTRL 0x0 48 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 49 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 50 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 51 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 52 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 53 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 54 #define PMC_CNTRL_MAIN_RST BIT(4) 55 56 #define DPD_SAMPLE 0x020 57 #define DPD_SAMPLE_ENABLE BIT(0) 58 #define DPD_SAMPLE_DISABLE (0 << 0) 59 60 #define PWRGATE_TOGGLE 0x30 61 #define PWRGATE_TOGGLE_START BIT(8) 62 63 #define REMOVE_CLAMPING 0x34 64 65 #define PWRGATE_STATUS 0x38 66 67 #define PMC_PWR_DET 0x48 68 69 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 70 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 71 #define PMC_SCRATCH0_MODE_RCM BIT(1) 72 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 73 PMC_SCRATCH0_MODE_BOOTLOADER | \ 74 PMC_SCRATCH0_MODE_RCM) 75 76 #define PMC_CPUPWRGOOD_TIMER 0xc8 77 #define PMC_CPUPWROFF_TIMER 0xcc 78 79 #define PMC_PWR_DET_VALUE 0xe4 80 81 #define PMC_SCRATCH41 0x140 82 83 #define PMC_SENSOR_CTRL 0x1b0 84 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 85 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 86 87 #define PMC_RST_STATUS 0x1b4 88 #define PMC_RST_STATUS_POR 0 89 #define PMC_RST_STATUS_WATCHDOG 1 90 #define PMC_RST_STATUS_SENSOR 2 91 #define PMC_RST_STATUS_SW_MAIN 3 92 #define PMC_RST_STATUS_LP0 4 93 #define PMC_RST_STATUS_AOTAG 5 94 95 #define IO_DPD_REQ 0x1b8 96 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 97 #define IO_DPD_REQ_CODE_OFF (1U << 30) 98 #define IO_DPD_REQ_CODE_ON (2U << 30) 99 #define IO_DPD_REQ_CODE_MASK (3U << 30) 100 101 #define IO_DPD_STATUS 0x1bc 102 #define IO_DPD2_REQ 0x1c0 103 #define IO_DPD2_STATUS 0x1c4 104 #define SEL_DPD_TIM 0x1c8 105 106 #define PMC_SCRATCH54 0x258 107 #define PMC_SCRATCH54_DATA_SHIFT 8 108 #define PMC_SCRATCH54_ADDR_SHIFT 0 109 110 #define PMC_SCRATCH55 0x25c 111 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 112 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 113 #define PMC_SCRATCH55_PINMUX_SHIFT 24 114 #define PMC_SCRATCH55_16BITOP BIT(15) 115 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 116 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 117 118 #define GPU_RG_CNTRL 0x2d4 119 120 /* Tegra186 and later */ 121 #define WAKE_AOWAKE_CTRL 0x4f4 122 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 123 124 struct tegra_powergate { 125 struct generic_pm_domain genpd; 126 struct tegra_pmc *pmc; 127 unsigned int id; 128 struct clk **clks; 129 unsigned int num_clks; 130 struct reset_control **resets; 131 unsigned int num_resets; 132 }; 133 134 struct tegra_io_pad_soc { 135 enum tegra_io_pad id; 136 unsigned int dpd; 137 unsigned int voltage; 138 }; 139 140 struct tegra_pmc_regs { 141 unsigned int scratch0; 142 unsigned int dpd_req; 143 unsigned int dpd_status; 144 unsigned int dpd2_req; 145 unsigned int dpd2_status; 146 }; 147 148 struct tegra_pmc_soc { 149 unsigned int num_powergates; 150 const char *const *powergates; 151 unsigned int num_cpu_powergates; 152 const u8 *cpu_powergates; 153 154 bool has_tsense_reset; 155 bool has_gpu_clamps; 156 157 const struct tegra_io_pad_soc *io_pads; 158 unsigned int num_io_pads; 159 160 const struct tegra_pmc_regs *regs; 161 void (*init)(struct tegra_pmc *pmc); 162 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 163 struct device_node *np, 164 bool invert); 165 }; 166 167 /** 168 * struct tegra_pmc - NVIDIA Tegra PMC 169 * @dev: pointer to PMC device structure 170 * @base: pointer to I/O remapped register region 171 * @clk: pointer to pclk clock 172 * @soc: pointer to SoC data structure 173 * @debugfs: pointer to debugfs entry 174 * @rate: currently configured rate of pclk 175 * @suspend_mode: lowest suspend mode available 176 * @cpu_good_time: CPU power good time (in microseconds) 177 * @cpu_off_time: CPU power off time (in microsecends) 178 * @core_osc_time: core power good OSC time (in microseconds) 179 * @core_pmu_time: core power good PMU time (in microseconds) 180 * @core_off_time: core power off time (in microseconds) 181 * @corereq_high: core power request is active-high 182 * @sysclkreq_high: system clock request is active-high 183 * @combined_req: combined power request for CPU & core 184 * @cpu_pwr_good_en: CPU power good signal is enabled 185 * @lp0_vec_phys: physical base address of the LP0 warm boot code 186 * @lp0_vec_size: size of the LP0 warm boot code 187 * @powergates_available: Bitmap of available power gates 188 * @powergates_lock: mutex for power gate register access 189 */ 190 struct tegra_pmc { 191 struct device *dev; 192 void __iomem *base; 193 void __iomem *wake; 194 void __iomem *aotag; 195 void __iomem *scratch; 196 struct clk *clk; 197 struct dentry *debugfs; 198 199 const struct tegra_pmc_soc *soc; 200 201 unsigned long rate; 202 203 enum tegra_suspend_mode suspend_mode; 204 u32 cpu_good_time; 205 u32 cpu_off_time; 206 u32 core_osc_time; 207 u32 core_pmu_time; 208 u32 core_off_time; 209 bool corereq_high; 210 bool sysclkreq_high; 211 bool combined_req; 212 bool cpu_pwr_good_en; 213 u32 lp0_vec_phys; 214 u32 lp0_vec_size; 215 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 216 217 struct mutex powergates_lock; 218 }; 219 220 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 221 .base = NULL, 222 .suspend_mode = TEGRA_SUSPEND_NONE, 223 }; 224 225 static inline struct tegra_powergate * 226 to_powergate(struct generic_pm_domain *domain) 227 { 228 return container_of(domain, struct tegra_powergate, genpd); 229 } 230 231 static u32 tegra_pmc_readl(unsigned long offset) 232 { 233 return readl(pmc->base + offset); 234 } 235 236 static void tegra_pmc_writel(u32 value, unsigned long offset) 237 { 238 writel(value, pmc->base + offset); 239 } 240 241 static inline bool tegra_powergate_state(int id) 242 { 243 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 244 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 245 else 246 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 247 } 248 249 static inline bool tegra_powergate_is_valid(int id) 250 { 251 return (pmc->soc && pmc->soc->powergates[id]); 252 } 253 254 static inline bool tegra_powergate_is_available(int id) 255 { 256 return test_bit(id, pmc->powergates_available); 257 } 258 259 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 260 { 261 unsigned int i; 262 263 if (!pmc || !pmc->soc || !name) 264 return -EINVAL; 265 266 for (i = 0; i < pmc->soc->num_powergates; i++) { 267 if (!tegra_powergate_is_valid(i)) 268 continue; 269 270 if (!strcmp(name, pmc->soc->powergates[i])) 271 return i; 272 } 273 274 return -ENODEV; 275 } 276 277 /** 278 * tegra_powergate_set() - set the state of a partition 279 * @id: partition ID 280 * @new_state: new state of the partition 281 */ 282 static int tegra_powergate_set(unsigned int id, bool new_state) 283 { 284 bool status; 285 int err; 286 287 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 288 return -EINVAL; 289 290 mutex_lock(&pmc->powergates_lock); 291 292 if (tegra_powergate_state(id) == new_state) { 293 mutex_unlock(&pmc->powergates_lock); 294 return 0; 295 } 296 297 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 298 299 err = readx_poll_timeout(tegra_powergate_state, id, status, 300 status == new_state, 10, 100000); 301 302 mutex_unlock(&pmc->powergates_lock); 303 304 return err; 305 } 306 307 static int __tegra_powergate_remove_clamping(unsigned int id) 308 { 309 u32 mask; 310 311 mutex_lock(&pmc->powergates_lock); 312 313 /* 314 * On Tegra124 and later, the clamps for the GPU are controlled by a 315 * separate register (with different semantics). 316 */ 317 if (id == TEGRA_POWERGATE_3D) { 318 if (pmc->soc->has_gpu_clamps) { 319 tegra_pmc_writel(0, GPU_RG_CNTRL); 320 goto out; 321 } 322 } 323 324 /* 325 * Tegra 2 has a bug where PCIE and VDE clamping masks are 326 * swapped relatively to the partition ids 327 */ 328 if (id == TEGRA_POWERGATE_VDEC) 329 mask = (1 << TEGRA_POWERGATE_PCIE); 330 else if (id == TEGRA_POWERGATE_PCIE) 331 mask = (1 << TEGRA_POWERGATE_VDEC); 332 else 333 mask = (1 << id); 334 335 tegra_pmc_writel(mask, REMOVE_CLAMPING); 336 337 out: 338 mutex_unlock(&pmc->powergates_lock); 339 340 return 0; 341 } 342 343 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 344 { 345 unsigned int i; 346 347 for (i = 0; i < pg->num_clks; i++) 348 clk_disable_unprepare(pg->clks[i]); 349 } 350 351 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 352 { 353 unsigned int i; 354 int err; 355 356 for (i = 0; i < pg->num_clks; i++) { 357 err = clk_prepare_enable(pg->clks[i]); 358 if (err) 359 goto out; 360 } 361 362 return 0; 363 364 out: 365 while (i--) 366 clk_disable_unprepare(pg->clks[i]); 367 368 return err; 369 } 370 371 static int tegra_powergate_reset_assert(struct tegra_powergate *pg) 372 { 373 unsigned int i; 374 int err; 375 376 for (i = 0; i < pg->num_resets; i++) { 377 err = reset_control_assert(pg->resets[i]); 378 if (err) 379 return err; 380 } 381 382 return 0; 383 } 384 385 static int tegra_powergate_reset_deassert(struct tegra_powergate *pg) 386 { 387 unsigned int i; 388 int err; 389 390 for (i = 0; i < pg->num_resets; i++) { 391 err = reset_control_deassert(pg->resets[i]); 392 if (err) 393 return err; 394 } 395 396 return 0; 397 } 398 399 static int tegra_powergate_power_up(struct tegra_powergate *pg, 400 bool disable_clocks) 401 { 402 int err; 403 404 err = tegra_powergate_reset_assert(pg); 405 if (err) 406 return err; 407 408 usleep_range(10, 20); 409 410 err = tegra_powergate_set(pg->id, true); 411 if (err < 0) 412 return err; 413 414 usleep_range(10, 20); 415 416 err = tegra_powergate_enable_clocks(pg); 417 if (err) 418 goto disable_clks; 419 420 usleep_range(10, 20); 421 422 err = __tegra_powergate_remove_clamping(pg->id); 423 if (err) 424 goto disable_clks; 425 426 usleep_range(10, 20); 427 428 err = tegra_powergate_reset_deassert(pg); 429 if (err) 430 goto powergate_off; 431 432 usleep_range(10, 20); 433 434 if (disable_clocks) 435 tegra_powergate_disable_clocks(pg); 436 437 return 0; 438 439 disable_clks: 440 tegra_powergate_disable_clocks(pg); 441 usleep_range(10, 20); 442 443 powergate_off: 444 tegra_powergate_set(pg->id, false); 445 446 return err; 447 } 448 449 static int tegra_powergate_power_down(struct tegra_powergate *pg) 450 { 451 int err; 452 453 err = tegra_powergate_enable_clocks(pg); 454 if (err) 455 return err; 456 457 usleep_range(10, 20); 458 459 err = tegra_powergate_reset_assert(pg); 460 if (err) 461 goto disable_clks; 462 463 usleep_range(10, 20); 464 465 tegra_powergate_disable_clocks(pg); 466 467 usleep_range(10, 20); 468 469 err = tegra_powergate_set(pg->id, false); 470 if (err) 471 goto assert_resets; 472 473 return 0; 474 475 assert_resets: 476 tegra_powergate_enable_clocks(pg); 477 usleep_range(10, 20); 478 tegra_powergate_reset_deassert(pg); 479 usleep_range(10, 20); 480 481 disable_clks: 482 tegra_powergate_disable_clocks(pg); 483 484 return err; 485 } 486 487 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 488 { 489 struct tegra_powergate *pg = to_powergate(domain); 490 int err; 491 492 err = tegra_powergate_power_up(pg, true); 493 if (err) 494 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, 495 err); 496 497 return err; 498 } 499 500 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 501 { 502 struct tegra_powergate *pg = to_powergate(domain); 503 int err; 504 505 err = tegra_powergate_power_down(pg); 506 if (err) 507 pr_err("failed to turn off PM domain %s: %d\n", 508 pg->genpd.name, err); 509 510 return err; 511 } 512 513 /** 514 * tegra_powergate_power_on() - power on partition 515 * @id: partition ID 516 */ 517 int tegra_powergate_power_on(unsigned int id) 518 { 519 if (!tegra_powergate_is_available(id)) 520 return -EINVAL; 521 522 return tegra_powergate_set(id, true); 523 } 524 525 /** 526 * tegra_powergate_power_off() - power off partition 527 * @id: partition ID 528 */ 529 int tegra_powergate_power_off(unsigned int id) 530 { 531 if (!tegra_powergate_is_available(id)) 532 return -EINVAL; 533 534 return tegra_powergate_set(id, false); 535 } 536 EXPORT_SYMBOL(tegra_powergate_power_off); 537 538 /** 539 * tegra_powergate_is_powered() - check if partition is powered 540 * @id: partition ID 541 */ 542 int tegra_powergate_is_powered(unsigned int id) 543 { 544 int status; 545 546 if (!tegra_powergate_is_valid(id)) 547 return -EINVAL; 548 549 mutex_lock(&pmc->powergates_lock); 550 status = tegra_powergate_state(id); 551 mutex_unlock(&pmc->powergates_lock); 552 553 return status; 554 } 555 556 /** 557 * tegra_powergate_remove_clamping() - remove power clamps for partition 558 * @id: partition ID 559 */ 560 int tegra_powergate_remove_clamping(unsigned int id) 561 { 562 if (!tegra_powergate_is_available(id)) 563 return -EINVAL; 564 565 return __tegra_powergate_remove_clamping(id); 566 } 567 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 568 569 /** 570 * tegra_powergate_sequence_power_up() - power up partition 571 * @id: partition ID 572 * @clk: clock for partition 573 * @rst: reset for partition 574 * 575 * Must be called with clk disabled, and returns with clk enabled. 576 */ 577 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 578 struct reset_control *rst) 579 { 580 struct tegra_powergate pg; 581 int err; 582 583 if (!tegra_powergate_is_available(id)) 584 return -EINVAL; 585 586 pg.id = id; 587 pg.clks = &clk; 588 pg.num_clks = 1; 589 pg.resets = &rst; 590 pg.num_resets = 1; 591 592 err = tegra_powergate_power_up(&pg, false); 593 if (err) 594 pr_err("failed to turn on partition %d: %d\n", id, err); 595 596 return err; 597 } 598 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 599 600 #ifdef CONFIG_SMP 601 /** 602 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 603 * @cpuid: CPU partition ID 604 * 605 * Returns the partition ID corresponding to the CPU partition ID or a 606 * negative error code on failure. 607 */ 608 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 609 { 610 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 611 return pmc->soc->cpu_powergates[cpuid]; 612 613 return -EINVAL; 614 } 615 616 /** 617 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 618 * @cpuid: CPU partition ID 619 */ 620 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 621 { 622 int id; 623 624 id = tegra_get_cpu_powergate_id(cpuid); 625 if (id < 0) 626 return false; 627 628 return tegra_powergate_is_powered(id); 629 } 630 631 /** 632 * tegra_pmc_cpu_power_on() - power on CPU partition 633 * @cpuid: CPU partition ID 634 */ 635 int tegra_pmc_cpu_power_on(unsigned int cpuid) 636 { 637 int id; 638 639 id = tegra_get_cpu_powergate_id(cpuid); 640 if (id < 0) 641 return id; 642 643 return tegra_powergate_set(id, true); 644 } 645 646 /** 647 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 648 * @cpuid: CPU partition ID 649 */ 650 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 651 { 652 int id; 653 654 id = tegra_get_cpu_powergate_id(cpuid); 655 if (id < 0) 656 return id; 657 658 return tegra_powergate_remove_clamping(id); 659 } 660 #endif /* CONFIG_SMP */ 661 662 static int tegra_pmc_restart_notify(struct notifier_block *this, 663 unsigned long action, void *data) 664 { 665 const char *cmd = data; 666 u32 value; 667 668 value = readl(pmc->scratch + pmc->soc->regs->scratch0); 669 value &= ~PMC_SCRATCH0_MODE_MASK; 670 671 if (cmd) { 672 if (strcmp(cmd, "recovery") == 0) 673 value |= PMC_SCRATCH0_MODE_RECOVERY; 674 675 if (strcmp(cmd, "bootloader") == 0) 676 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 677 678 if (strcmp(cmd, "forced-recovery") == 0) 679 value |= PMC_SCRATCH0_MODE_RCM; 680 } 681 682 writel(value, pmc->scratch + pmc->soc->regs->scratch0); 683 684 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 685 value = tegra_pmc_readl(PMC_CNTRL); 686 value |= PMC_CNTRL_MAIN_RST; 687 tegra_pmc_writel(value, PMC_CNTRL); 688 689 return NOTIFY_DONE; 690 } 691 692 static struct notifier_block tegra_pmc_restart_handler = { 693 .notifier_call = tegra_pmc_restart_notify, 694 .priority = 128, 695 }; 696 697 static int powergate_show(struct seq_file *s, void *data) 698 { 699 unsigned int i; 700 int status; 701 702 seq_printf(s, " powergate powered\n"); 703 seq_printf(s, "------------------\n"); 704 705 for (i = 0; i < pmc->soc->num_powergates; i++) { 706 status = tegra_powergate_is_powered(i); 707 if (status < 0) 708 continue; 709 710 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 711 status ? "yes" : "no"); 712 } 713 714 return 0; 715 } 716 717 static int powergate_open(struct inode *inode, struct file *file) 718 { 719 return single_open(file, powergate_show, inode->i_private); 720 } 721 722 static const struct file_operations powergate_fops = { 723 .open = powergate_open, 724 .read = seq_read, 725 .llseek = seq_lseek, 726 .release = single_release, 727 }; 728 729 static int tegra_powergate_debugfs_init(void) 730 { 731 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 732 &powergate_fops); 733 if (!pmc->debugfs) 734 return -ENOMEM; 735 736 return 0; 737 } 738 739 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 740 struct device_node *np) 741 { 742 struct clk *clk; 743 unsigned int i, count; 744 int err; 745 746 count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); 747 if (count == 0) 748 return -ENODEV; 749 750 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 751 if (!pg->clks) 752 return -ENOMEM; 753 754 for (i = 0; i < count; i++) { 755 pg->clks[i] = of_clk_get(np, i); 756 if (IS_ERR(pg->clks[i])) { 757 err = PTR_ERR(pg->clks[i]); 758 goto err; 759 } 760 } 761 762 pg->num_clks = count; 763 764 return 0; 765 766 err: 767 while (i--) 768 clk_put(pg->clks[i]); 769 770 kfree(pg->clks); 771 772 return err; 773 } 774 775 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 776 struct device_node *np, bool off) 777 { 778 struct reset_control *rst; 779 unsigned int i, count; 780 int err; 781 782 count = of_count_phandle_with_args(np, "resets", "#reset-cells"); 783 if (count == 0) 784 return -ENODEV; 785 786 pg->resets = kcalloc(count, sizeof(rst), GFP_KERNEL); 787 if (!pg->resets) 788 return -ENOMEM; 789 790 for (i = 0; i < count; i++) { 791 pg->resets[i] = of_reset_control_get_by_index(np, i); 792 if (IS_ERR(pg->resets[i])) { 793 err = PTR_ERR(pg->resets[i]); 794 goto error; 795 } 796 797 if (off) 798 err = reset_control_assert(pg->resets[i]); 799 else 800 err = reset_control_deassert(pg->resets[i]); 801 802 if (err) { 803 reset_control_put(pg->resets[i]); 804 goto error; 805 } 806 } 807 808 pg->num_resets = count; 809 810 return 0; 811 812 error: 813 while (i--) 814 reset_control_put(pg->resets[i]); 815 816 kfree(pg->resets); 817 818 return err; 819 } 820 821 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 822 { 823 struct tegra_powergate *pg; 824 int id, err; 825 bool off; 826 827 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 828 if (!pg) 829 return; 830 831 id = tegra_powergate_lookup(pmc, np->name); 832 if (id < 0) { 833 pr_err("powergate lookup failed for %s: %d\n", np->name, id); 834 goto free_mem; 835 } 836 837 /* 838 * Clear the bit for this powergate so it cannot be managed 839 * directly via the legacy APIs for controlling powergates. 840 */ 841 clear_bit(id, pmc->powergates_available); 842 843 pg->id = id; 844 pg->genpd.name = np->name; 845 pg->genpd.power_off = tegra_genpd_power_off; 846 pg->genpd.power_on = tegra_genpd_power_on; 847 pg->pmc = pmc; 848 849 off = !tegra_powergate_is_powered(pg->id); 850 851 err = tegra_powergate_of_get_clks(pg, np); 852 if (err < 0) { 853 pr_err("failed to get clocks for %s: %d\n", np->name, err); 854 goto set_available; 855 } 856 857 err = tegra_powergate_of_get_resets(pg, np, off); 858 if (err < 0) { 859 pr_err("failed to get resets for %s: %d\n", np->name, err); 860 goto remove_clks; 861 } 862 863 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 864 if (off) 865 WARN_ON(tegra_powergate_power_up(pg, true)); 866 867 goto remove_resets; 868 } 869 870 /* 871 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB 872 * host and super-speed partitions. Once the XHCI driver 873 * manages the partitions itself this code can be removed. Note 874 * that we don't register these partitions with the genpd core 875 * to avoid it from powering down the partitions as they appear 876 * to be unused. 877 */ 878 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && 879 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) { 880 if (off) 881 WARN_ON(tegra_powergate_power_up(pg, true)); 882 883 goto remove_resets; 884 } 885 886 err = pm_genpd_init(&pg->genpd, NULL, off); 887 if (err < 0) { 888 pr_err("failed to initialise PM domain %s: %d\n", np->name, 889 err); 890 goto remove_resets; 891 } 892 893 err = of_genpd_add_provider_simple(np, &pg->genpd); 894 if (err < 0) { 895 pr_err("failed to add PM domain provider for %s: %d\n", 896 np->name, err); 897 goto remove_genpd; 898 } 899 900 pr_debug("added PM domain %s\n", pg->genpd.name); 901 902 return; 903 904 remove_genpd: 905 pm_genpd_remove(&pg->genpd); 906 907 remove_resets: 908 while (pg->num_resets--) 909 reset_control_put(pg->resets[pg->num_resets]); 910 911 kfree(pg->resets); 912 913 remove_clks: 914 while (pg->num_clks--) 915 clk_put(pg->clks[pg->num_clks]); 916 917 kfree(pg->clks); 918 919 set_available: 920 set_bit(id, pmc->powergates_available); 921 922 free_mem: 923 kfree(pg); 924 } 925 926 static void tegra_powergate_init(struct tegra_pmc *pmc, 927 struct device_node *parent) 928 { 929 struct device_node *np, *child; 930 unsigned int i; 931 932 /* Create a bitmap of the available and valid partitions */ 933 for (i = 0; i < pmc->soc->num_powergates; i++) 934 if (pmc->soc->powergates[i]) 935 set_bit(i, pmc->powergates_available); 936 937 np = of_get_child_by_name(parent, "powergates"); 938 if (!np) 939 return; 940 941 for_each_child_of_node(np, child) 942 tegra_powergate_add(pmc, child); 943 944 of_node_put(np); 945 } 946 947 static const struct tegra_io_pad_soc * 948 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 949 { 950 unsigned int i; 951 952 for (i = 0; i < pmc->soc->num_io_pads; i++) 953 if (pmc->soc->io_pads[i].id == id) 954 return &pmc->soc->io_pads[i]; 955 956 return NULL; 957 } 958 959 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 960 unsigned long *status, u32 *mask) 961 { 962 const struct tegra_io_pad_soc *pad; 963 unsigned long rate, value; 964 965 pad = tegra_io_pad_find(pmc, id); 966 if (!pad) { 967 pr_err("invalid I/O pad ID %u\n", id); 968 return -ENOENT; 969 } 970 971 if (pad->dpd == UINT_MAX) 972 return -ENOTSUPP; 973 974 *mask = BIT(pad->dpd % 32); 975 976 if (pad->dpd < 32) { 977 *status = pmc->soc->regs->dpd_status; 978 *request = pmc->soc->regs->dpd_req; 979 } else { 980 *status = pmc->soc->regs->dpd2_status; 981 *request = pmc->soc->regs->dpd2_req; 982 } 983 984 if (pmc->clk) { 985 rate = clk_get_rate(pmc->clk); 986 if (!rate) { 987 pr_err("failed to get clock rate\n"); 988 return -ENODEV; 989 } 990 991 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 992 993 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 994 value = DIV_ROUND_UP(1000000000, rate); 995 value = DIV_ROUND_UP(200, value); 996 tegra_pmc_writel(value, SEL_DPD_TIM); 997 } 998 999 return 0; 1000 } 1001 1002 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 1003 u32 val, unsigned long timeout) 1004 { 1005 u32 value; 1006 1007 timeout = jiffies + msecs_to_jiffies(timeout); 1008 1009 while (time_after(timeout, jiffies)) { 1010 value = tegra_pmc_readl(offset); 1011 if ((value & mask) == val) 1012 return 0; 1013 1014 usleep_range(250, 1000); 1015 } 1016 1017 return -ETIMEDOUT; 1018 } 1019 1020 static void tegra_io_pad_unprepare(void) 1021 { 1022 if (pmc->clk) 1023 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1024 } 1025 1026 /** 1027 * tegra_io_pad_power_enable() - enable power to I/O pad 1028 * @id: Tegra I/O pad ID for which to enable power 1029 * 1030 * Returns: 0 on success or a negative error code on failure. 1031 */ 1032 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1033 { 1034 unsigned long request, status; 1035 u32 mask; 1036 int err; 1037 1038 mutex_lock(&pmc->powergates_lock); 1039 1040 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1041 if (err < 0) { 1042 pr_err("failed to prepare I/O pad: %d\n", err); 1043 goto unlock; 1044 } 1045 1046 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); 1047 1048 err = tegra_io_pad_poll(status, mask, 0, 250); 1049 if (err < 0) { 1050 pr_err("failed to enable I/O pad: %d\n", err); 1051 goto unlock; 1052 } 1053 1054 tegra_io_pad_unprepare(); 1055 1056 unlock: 1057 mutex_unlock(&pmc->powergates_lock); 1058 return err; 1059 } 1060 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1061 1062 /** 1063 * tegra_io_pad_power_disable() - disable power to I/O pad 1064 * @id: Tegra I/O pad ID for which to disable power 1065 * 1066 * Returns: 0 on success or a negative error code on failure. 1067 */ 1068 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1069 { 1070 unsigned long request, status; 1071 u32 mask; 1072 int err; 1073 1074 mutex_lock(&pmc->powergates_lock); 1075 1076 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1077 if (err < 0) { 1078 pr_err("failed to prepare I/O pad: %d\n", err); 1079 goto unlock; 1080 } 1081 1082 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); 1083 1084 err = tegra_io_pad_poll(status, mask, mask, 250); 1085 if (err < 0) { 1086 pr_err("failed to disable I/O pad: %d\n", err); 1087 goto unlock; 1088 } 1089 1090 tegra_io_pad_unprepare(); 1091 1092 unlock: 1093 mutex_unlock(&pmc->powergates_lock); 1094 return err; 1095 } 1096 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1097 1098 int tegra_io_pad_set_voltage(enum tegra_io_pad id, 1099 enum tegra_io_pad_voltage voltage) 1100 { 1101 const struct tegra_io_pad_soc *pad; 1102 u32 value; 1103 1104 pad = tegra_io_pad_find(pmc, id); 1105 if (!pad) 1106 return -ENOENT; 1107 1108 if (pad->voltage == UINT_MAX) 1109 return -ENOTSUPP; 1110 1111 mutex_lock(&pmc->powergates_lock); 1112 1113 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1114 value = tegra_pmc_readl(PMC_PWR_DET); 1115 value |= BIT(pad->voltage); 1116 tegra_pmc_writel(value, PMC_PWR_DET); 1117 1118 /* update I/O voltage */ 1119 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1120 1121 if (voltage == TEGRA_IO_PAD_1800000UV) 1122 value &= ~BIT(pad->voltage); 1123 else 1124 value |= BIT(pad->voltage); 1125 1126 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1127 1128 mutex_unlock(&pmc->powergates_lock); 1129 1130 usleep_range(100, 250); 1131 1132 return 0; 1133 } 1134 EXPORT_SYMBOL(tegra_io_pad_set_voltage); 1135 1136 int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1137 { 1138 const struct tegra_io_pad_soc *pad; 1139 u32 value; 1140 1141 pad = tegra_io_pad_find(pmc, id); 1142 if (!pad) 1143 return -ENOENT; 1144 1145 if (pad->voltage == UINT_MAX) 1146 return -ENOTSUPP; 1147 1148 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1149 1150 if ((value & BIT(pad->voltage)) == 0) 1151 return TEGRA_IO_PAD_1800000UV; 1152 1153 return TEGRA_IO_PAD_3300000UV; 1154 } 1155 EXPORT_SYMBOL(tegra_io_pad_get_voltage); 1156 1157 /** 1158 * tegra_io_rail_power_on() - enable power to I/O rail 1159 * @id: Tegra I/O pad ID for which to enable power 1160 * 1161 * See also: tegra_io_pad_power_enable() 1162 */ 1163 int tegra_io_rail_power_on(unsigned int id) 1164 { 1165 return tegra_io_pad_power_enable(id); 1166 } 1167 EXPORT_SYMBOL(tegra_io_rail_power_on); 1168 1169 /** 1170 * tegra_io_rail_power_off() - disable power to I/O rail 1171 * @id: Tegra I/O pad ID for which to disable power 1172 * 1173 * See also: tegra_io_pad_power_disable() 1174 */ 1175 int tegra_io_rail_power_off(unsigned int id) 1176 { 1177 return tegra_io_pad_power_disable(id); 1178 } 1179 EXPORT_SYMBOL(tegra_io_rail_power_off); 1180 1181 #ifdef CONFIG_PM_SLEEP 1182 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1183 { 1184 return pmc->suspend_mode; 1185 } 1186 1187 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1188 { 1189 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1190 return; 1191 1192 pmc->suspend_mode = mode; 1193 } 1194 1195 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1196 { 1197 unsigned long long rate = 0; 1198 u32 value; 1199 1200 switch (mode) { 1201 case TEGRA_SUSPEND_LP1: 1202 rate = 32768; 1203 break; 1204 1205 case TEGRA_SUSPEND_LP2: 1206 rate = clk_get_rate(pmc->clk); 1207 break; 1208 1209 default: 1210 break; 1211 } 1212 1213 if (WARN_ON_ONCE(rate == 0)) 1214 rate = 100000000; 1215 1216 if (rate != pmc->rate) { 1217 u64 ticks; 1218 1219 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1220 do_div(ticks, USEC_PER_SEC); 1221 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1222 1223 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1224 do_div(ticks, USEC_PER_SEC); 1225 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1226 1227 wmb(); 1228 1229 pmc->rate = rate; 1230 } 1231 1232 value = tegra_pmc_readl(PMC_CNTRL); 1233 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1234 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1235 tegra_pmc_writel(value, PMC_CNTRL); 1236 } 1237 #endif 1238 1239 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1240 { 1241 u32 value, values[2]; 1242 1243 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1244 } else { 1245 switch (value) { 1246 case 0: 1247 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1248 break; 1249 1250 case 1: 1251 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1252 break; 1253 1254 case 2: 1255 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1256 break; 1257 1258 default: 1259 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1260 break; 1261 } 1262 } 1263 1264 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1265 1266 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1267 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1268 1269 pmc->cpu_good_time = value; 1270 1271 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1272 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1273 1274 pmc->cpu_off_time = value; 1275 1276 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1277 values, ARRAY_SIZE(values))) 1278 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1279 1280 pmc->core_osc_time = values[0]; 1281 pmc->core_pmu_time = values[1]; 1282 1283 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1284 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1285 1286 pmc->core_off_time = value; 1287 1288 pmc->corereq_high = of_property_read_bool(np, 1289 "nvidia,core-power-req-active-high"); 1290 1291 pmc->sysclkreq_high = of_property_read_bool(np, 1292 "nvidia,sys-clock-req-active-high"); 1293 1294 pmc->combined_req = of_property_read_bool(np, 1295 "nvidia,combined-power-req"); 1296 1297 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1298 "nvidia,cpu-pwr-good-en"); 1299 1300 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1301 ARRAY_SIZE(values))) 1302 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1303 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1304 1305 pmc->lp0_vec_phys = values[0]; 1306 pmc->lp0_vec_size = values[1]; 1307 1308 return 0; 1309 } 1310 1311 static void tegra_pmc_init(struct tegra_pmc *pmc) 1312 { 1313 if (pmc->soc->init) 1314 pmc->soc->init(pmc); 1315 } 1316 1317 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1318 { 1319 static const char disabled[] = "emergency thermal reset disabled"; 1320 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1321 struct device *dev = pmc->dev; 1322 struct device_node *np; 1323 u32 value, checksum; 1324 1325 if (!pmc->soc->has_tsense_reset) 1326 return; 1327 1328 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1329 if (!np) { 1330 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1331 return; 1332 } 1333 1334 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1335 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1336 goto out; 1337 } 1338 1339 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1340 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1341 goto out; 1342 } 1343 1344 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1345 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1346 goto out; 1347 } 1348 1349 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1350 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1351 goto out; 1352 } 1353 1354 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1355 pinmux = 0; 1356 1357 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1358 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1359 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1360 1361 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1362 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1363 tegra_pmc_writel(value, PMC_SCRATCH54); 1364 1365 value = PMC_SCRATCH55_RESET_TEGRA; 1366 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1367 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1368 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1369 1370 /* 1371 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1372 * contain the checksum and are currently zero, so they are not added. 1373 */ 1374 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1375 + ((value >> 24) & 0xff); 1376 checksum &= 0xff; 1377 checksum = 0x100 - checksum; 1378 1379 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1380 1381 tegra_pmc_writel(value, PMC_SCRATCH55); 1382 1383 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1384 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1385 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1386 1387 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1388 1389 out: 1390 of_node_put(np); 1391 } 1392 1393 static int tegra_pmc_probe(struct platform_device *pdev) 1394 { 1395 void __iomem *base; 1396 struct resource *res; 1397 int err; 1398 1399 /* 1400 * Early initialisation should have configured an initial 1401 * register mapping and setup the soc data pointer. If these 1402 * are not valid then something went badly wrong! 1403 */ 1404 if (WARN_ON(!pmc->base || !pmc->soc)) 1405 return -ENODEV; 1406 1407 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1408 if (err < 0) 1409 return err; 1410 1411 /* take over the memory region from the early initialization */ 1412 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1413 base = devm_ioremap_resource(&pdev->dev, res); 1414 if (IS_ERR(base)) 1415 return PTR_ERR(base); 1416 1417 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1418 if (res) { 1419 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1420 if (IS_ERR(pmc->wake)) 1421 return PTR_ERR(pmc->wake); 1422 } else { 1423 pmc->wake = base; 1424 } 1425 1426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1427 if (res) { 1428 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1429 if (IS_ERR(pmc->aotag)) 1430 return PTR_ERR(pmc->aotag); 1431 } else { 1432 pmc->aotag = base; 1433 } 1434 1435 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1436 if (res) { 1437 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1438 if (IS_ERR(pmc->scratch)) 1439 return PTR_ERR(pmc->scratch); 1440 } else { 1441 pmc->scratch = base; 1442 } 1443 1444 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1445 if (IS_ERR(pmc->clk)) { 1446 err = PTR_ERR(pmc->clk); 1447 1448 if (err != -ENOENT) { 1449 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1450 return err; 1451 } 1452 1453 pmc->clk = NULL; 1454 } 1455 1456 pmc->dev = &pdev->dev; 1457 1458 tegra_pmc_init(pmc); 1459 1460 tegra_pmc_init_tsense_reset(pmc); 1461 1462 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1463 err = tegra_powergate_debugfs_init(); 1464 if (err < 0) 1465 return err; 1466 } 1467 1468 err = register_restart_handler(&tegra_pmc_restart_handler); 1469 if (err) { 1470 debugfs_remove(pmc->debugfs); 1471 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1472 err); 1473 return err; 1474 } 1475 1476 mutex_lock(&pmc->powergates_lock); 1477 iounmap(pmc->base); 1478 pmc->base = base; 1479 mutex_unlock(&pmc->powergates_lock); 1480 1481 return 0; 1482 } 1483 1484 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1485 static int tegra_pmc_suspend(struct device *dev) 1486 { 1487 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1488 1489 return 0; 1490 } 1491 1492 static int tegra_pmc_resume(struct device *dev) 1493 { 1494 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1495 1496 return 0; 1497 } 1498 1499 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1500 1501 #endif 1502 1503 static const char * const tegra20_powergates[] = { 1504 [TEGRA_POWERGATE_CPU] = "cpu", 1505 [TEGRA_POWERGATE_3D] = "3d", 1506 [TEGRA_POWERGATE_VENC] = "venc", 1507 [TEGRA_POWERGATE_VDEC] = "vdec", 1508 [TEGRA_POWERGATE_PCIE] = "pcie", 1509 [TEGRA_POWERGATE_L2] = "l2", 1510 [TEGRA_POWERGATE_MPE] = "mpe", 1511 }; 1512 1513 static const struct tegra_pmc_regs tegra20_pmc_regs = { 1514 .scratch0 = 0x50, 1515 .dpd_req = 0x1b8, 1516 .dpd_status = 0x1bc, 1517 .dpd2_req = 0x1c0, 1518 .dpd2_status = 0x1c4, 1519 }; 1520 1521 static void tegra20_pmc_init(struct tegra_pmc *pmc) 1522 { 1523 u32 value; 1524 1525 /* Always enable CPU power request */ 1526 value = tegra_pmc_readl(PMC_CNTRL); 1527 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1528 tegra_pmc_writel(value, PMC_CNTRL); 1529 1530 value = tegra_pmc_readl(PMC_CNTRL); 1531 1532 if (pmc->sysclkreq_high) 1533 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1534 else 1535 value |= PMC_CNTRL_SYSCLK_POLARITY; 1536 1537 /* configure the output polarity while the request is tristated */ 1538 tegra_pmc_writel(value, PMC_CNTRL); 1539 1540 /* now enable the request */ 1541 value = tegra_pmc_readl(PMC_CNTRL); 1542 value |= PMC_CNTRL_SYSCLK_OE; 1543 tegra_pmc_writel(value, PMC_CNTRL); 1544 } 1545 1546 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1547 struct device_node *np, 1548 bool invert) 1549 { 1550 u32 value; 1551 1552 value = tegra_pmc_readl(PMC_CNTRL); 1553 1554 if (invert) 1555 value |= PMC_CNTRL_INTR_POLARITY; 1556 else 1557 value &= ~PMC_CNTRL_INTR_POLARITY; 1558 1559 tegra_pmc_writel(value, PMC_CNTRL); 1560 } 1561 1562 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1563 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1564 .powergates = tegra20_powergates, 1565 .num_cpu_powergates = 0, 1566 .cpu_powergates = NULL, 1567 .has_tsense_reset = false, 1568 .has_gpu_clamps = false, 1569 .num_io_pads = 0, 1570 .io_pads = NULL, 1571 .regs = &tegra20_pmc_regs, 1572 .init = tegra20_pmc_init, 1573 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1574 }; 1575 1576 static const char * const tegra30_powergates[] = { 1577 [TEGRA_POWERGATE_CPU] = "cpu0", 1578 [TEGRA_POWERGATE_3D] = "3d0", 1579 [TEGRA_POWERGATE_VENC] = "venc", 1580 [TEGRA_POWERGATE_VDEC] = "vdec", 1581 [TEGRA_POWERGATE_PCIE] = "pcie", 1582 [TEGRA_POWERGATE_L2] = "l2", 1583 [TEGRA_POWERGATE_MPE] = "mpe", 1584 [TEGRA_POWERGATE_HEG] = "heg", 1585 [TEGRA_POWERGATE_SATA] = "sata", 1586 [TEGRA_POWERGATE_CPU1] = "cpu1", 1587 [TEGRA_POWERGATE_CPU2] = "cpu2", 1588 [TEGRA_POWERGATE_CPU3] = "cpu3", 1589 [TEGRA_POWERGATE_CELP] = "celp", 1590 [TEGRA_POWERGATE_3D1] = "3d1", 1591 }; 1592 1593 static const u8 tegra30_cpu_powergates[] = { 1594 TEGRA_POWERGATE_CPU, 1595 TEGRA_POWERGATE_CPU1, 1596 TEGRA_POWERGATE_CPU2, 1597 TEGRA_POWERGATE_CPU3, 1598 }; 1599 1600 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1601 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1602 .powergates = tegra30_powergates, 1603 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1604 .cpu_powergates = tegra30_cpu_powergates, 1605 .has_tsense_reset = true, 1606 .has_gpu_clamps = false, 1607 .num_io_pads = 0, 1608 .io_pads = NULL, 1609 .regs = &tegra20_pmc_regs, 1610 .init = tegra20_pmc_init, 1611 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1612 }; 1613 1614 static const char * const tegra114_powergates[] = { 1615 [TEGRA_POWERGATE_CPU] = "crail", 1616 [TEGRA_POWERGATE_3D] = "3d", 1617 [TEGRA_POWERGATE_VENC] = "venc", 1618 [TEGRA_POWERGATE_VDEC] = "vdec", 1619 [TEGRA_POWERGATE_MPE] = "mpe", 1620 [TEGRA_POWERGATE_HEG] = "heg", 1621 [TEGRA_POWERGATE_CPU1] = "cpu1", 1622 [TEGRA_POWERGATE_CPU2] = "cpu2", 1623 [TEGRA_POWERGATE_CPU3] = "cpu3", 1624 [TEGRA_POWERGATE_CELP] = "celp", 1625 [TEGRA_POWERGATE_CPU0] = "cpu0", 1626 [TEGRA_POWERGATE_C0NC] = "c0nc", 1627 [TEGRA_POWERGATE_C1NC] = "c1nc", 1628 [TEGRA_POWERGATE_DIS] = "dis", 1629 [TEGRA_POWERGATE_DISB] = "disb", 1630 [TEGRA_POWERGATE_XUSBA] = "xusba", 1631 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1632 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1633 }; 1634 1635 static const u8 tegra114_cpu_powergates[] = { 1636 TEGRA_POWERGATE_CPU0, 1637 TEGRA_POWERGATE_CPU1, 1638 TEGRA_POWERGATE_CPU2, 1639 TEGRA_POWERGATE_CPU3, 1640 }; 1641 1642 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1643 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1644 .powergates = tegra114_powergates, 1645 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1646 .cpu_powergates = tegra114_cpu_powergates, 1647 .has_tsense_reset = true, 1648 .has_gpu_clamps = false, 1649 .num_io_pads = 0, 1650 .io_pads = NULL, 1651 .regs = &tegra20_pmc_regs, 1652 .init = tegra20_pmc_init, 1653 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1654 }; 1655 1656 static const char * const tegra124_powergates[] = { 1657 [TEGRA_POWERGATE_CPU] = "crail", 1658 [TEGRA_POWERGATE_3D] = "3d", 1659 [TEGRA_POWERGATE_VENC] = "venc", 1660 [TEGRA_POWERGATE_PCIE] = "pcie", 1661 [TEGRA_POWERGATE_VDEC] = "vdec", 1662 [TEGRA_POWERGATE_MPE] = "mpe", 1663 [TEGRA_POWERGATE_HEG] = "heg", 1664 [TEGRA_POWERGATE_SATA] = "sata", 1665 [TEGRA_POWERGATE_CPU1] = "cpu1", 1666 [TEGRA_POWERGATE_CPU2] = "cpu2", 1667 [TEGRA_POWERGATE_CPU3] = "cpu3", 1668 [TEGRA_POWERGATE_CELP] = "celp", 1669 [TEGRA_POWERGATE_CPU0] = "cpu0", 1670 [TEGRA_POWERGATE_C0NC] = "c0nc", 1671 [TEGRA_POWERGATE_C1NC] = "c1nc", 1672 [TEGRA_POWERGATE_SOR] = "sor", 1673 [TEGRA_POWERGATE_DIS] = "dis", 1674 [TEGRA_POWERGATE_DISB] = "disb", 1675 [TEGRA_POWERGATE_XUSBA] = "xusba", 1676 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1677 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1678 [TEGRA_POWERGATE_VIC] = "vic", 1679 [TEGRA_POWERGATE_IRAM] = "iram", 1680 }; 1681 1682 static const u8 tegra124_cpu_powergates[] = { 1683 TEGRA_POWERGATE_CPU0, 1684 TEGRA_POWERGATE_CPU1, 1685 TEGRA_POWERGATE_CPU2, 1686 TEGRA_POWERGATE_CPU3, 1687 }; 1688 1689 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 1690 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1691 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX }, 1692 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX }, 1693 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX }, 1694 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1695 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1696 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1697 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1698 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1699 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1700 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1701 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1702 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1703 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX }, 1704 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1705 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1706 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX }, 1707 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1708 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1709 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1710 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1711 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX }, 1712 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX }, 1713 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX }, 1714 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX }, 1715 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1716 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1717 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1718 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1719 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1720 }; 1721 1722 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1723 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1724 .powergates = tegra124_powergates, 1725 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1726 .cpu_powergates = tegra124_cpu_powergates, 1727 .has_tsense_reset = true, 1728 .has_gpu_clamps = true, 1729 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 1730 .io_pads = tegra124_io_pads, 1731 .regs = &tegra20_pmc_regs, 1732 .init = tegra20_pmc_init, 1733 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1734 }; 1735 1736 static const char * const tegra210_powergates[] = { 1737 [TEGRA_POWERGATE_CPU] = "crail", 1738 [TEGRA_POWERGATE_3D] = "3d", 1739 [TEGRA_POWERGATE_VENC] = "venc", 1740 [TEGRA_POWERGATE_PCIE] = "pcie", 1741 [TEGRA_POWERGATE_MPE] = "mpe", 1742 [TEGRA_POWERGATE_SATA] = "sata", 1743 [TEGRA_POWERGATE_CPU1] = "cpu1", 1744 [TEGRA_POWERGATE_CPU2] = "cpu2", 1745 [TEGRA_POWERGATE_CPU3] = "cpu3", 1746 [TEGRA_POWERGATE_CPU0] = "cpu0", 1747 [TEGRA_POWERGATE_C0NC] = "c0nc", 1748 [TEGRA_POWERGATE_SOR] = "sor", 1749 [TEGRA_POWERGATE_DIS] = "dis", 1750 [TEGRA_POWERGATE_DISB] = "disb", 1751 [TEGRA_POWERGATE_XUSBA] = "xusba", 1752 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1753 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1754 [TEGRA_POWERGATE_VIC] = "vic", 1755 [TEGRA_POWERGATE_IRAM] = "iram", 1756 [TEGRA_POWERGATE_NVDEC] = "nvdec", 1757 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 1758 [TEGRA_POWERGATE_AUD] = "aud", 1759 [TEGRA_POWERGATE_DFD] = "dfd", 1760 [TEGRA_POWERGATE_VE2] = "ve2", 1761 }; 1762 1763 static const u8 tegra210_cpu_powergates[] = { 1764 TEGRA_POWERGATE_CPU0, 1765 TEGRA_POWERGATE_CPU1, 1766 TEGRA_POWERGATE_CPU2, 1767 TEGRA_POWERGATE_CPU3, 1768 }; 1769 1770 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 1771 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 }, 1772 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 }, 1773 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 }, 1774 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1775 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1776 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX }, 1777 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX }, 1778 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1779 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX }, 1780 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 }, 1781 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX }, 1782 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 }, 1783 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX }, 1784 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1785 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1786 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1787 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1788 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX }, 1789 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX }, 1790 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 }, 1791 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1792 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1793 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1794 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1795 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1796 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1797 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1798 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 }, 1799 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 }, 1800 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 }, 1801 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 }, 1802 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 }, 1803 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 }, 1804 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1805 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1806 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1807 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX }, 1808 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1809 }; 1810 1811 static const struct tegra_pmc_soc tegra210_pmc_soc = { 1812 .num_powergates = ARRAY_SIZE(tegra210_powergates), 1813 .powergates = tegra210_powergates, 1814 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 1815 .cpu_powergates = tegra210_cpu_powergates, 1816 .has_tsense_reset = true, 1817 .has_gpu_clamps = true, 1818 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 1819 .io_pads = tegra210_io_pads, 1820 .regs = &tegra20_pmc_regs, 1821 .init = tegra20_pmc_init, 1822 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1823 }; 1824 1825 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 1826 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1827 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1828 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1829 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1830 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1831 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, 1832 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1833 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, 1834 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1835 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1836 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1837 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1838 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1839 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1840 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1841 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, 1842 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, 1843 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, 1844 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1845 { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = UINT_MAX }, 1846 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, 1847 { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX }, 1848 { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX }, 1849 { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX }, 1850 { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX }, 1851 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, 1852 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, 1853 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, 1854 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, 1855 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, 1856 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, 1857 { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = UINT_MAX }, 1858 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, 1859 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, 1860 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, 1861 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, 1862 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, 1863 }; 1864 1865 static const struct tegra_pmc_regs tegra186_pmc_regs = { 1866 .scratch0 = 0x2000, 1867 .dpd_req = 0x74, 1868 .dpd_status = 0x78, 1869 .dpd2_req = 0x7c, 1870 .dpd2_status = 0x80, 1871 }; 1872 1873 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1874 struct device_node *np, 1875 bool invert) 1876 { 1877 struct resource regs; 1878 void __iomem *wake; 1879 u32 value; 1880 int index; 1881 1882 index = of_property_match_string(np, "reg-names", "wake"); 1883 if (index < 0) { 1884 pr_err("failed to find PMC wake registers\n"); 1885 return; 1886 } 1887 1888 of_address_to_resource(np, index, ®s); 1889 1890 wake = ioremap_nocache(regs.start, resource_size(®s)); 1891 if (!wake) { 1892 pr_err("failed to map PMC wake registers\n"); 1893 return; 1894 } 1895 1896 value = readl(wake + WAKE_AOWAKE_CTRL); 1897 1898 if (invert) 1899 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 1900 else 1901 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 1902 1903 writel(value, wake + WAKE_AOWAKE_CTRL); 1904 1905 iounmap(wake); 1906 } 1907 1908 static const struct tegra_pmc_soc tegra186_pmc_soc = { 1909 .num_powergates = 0, 1910 .powergates = NULL, 1911 .num_cpu_powergates = 0, 1912 .cpu_powergates = NULL, 1913 .has_tsense_reset = false, 1914 .has_gpu_clamps = false, 1915 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 1916 .io_pads = tegra186_io_pads, 1917 .regs = &tegra186_pmc_regs, 1918 .init = NULL, 1919 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 1920 }; 1921 1922 static const struct of_device_id tegra_pmc_match[] = { 1923 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 1924 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 1925 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 1926 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 1927 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 1928 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 1929 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 1930 { } 1931 }; 1932 1933 static struct platform_driver tegra_pmc_driver = { 1934 .driver = { 1935 .name = "tegra-pmc", 1936 .suppress_bind_attrs = true, 1937 .of_match_table = tegra_pmc_match, 1938 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1939 .pm = &tegra_pmc_pm_ops, 1940 #endif 1941 }, 1942 .probe = tegra_pmc_probe, 1943 }; 1944 builtin_platform_driver(tegra_pmc_driver); 1945 1946 /* 1947 * Early initialization to allow access to registers in the very early boot 1948 * process. 1949 */ 1950 static int __init tegra_pmc_early_init(void) 1951 { 1952 const struct of_device_id *match; 1953 struct device_node *np; 1954 struct resource regs; 1955 bool invert; 1956 1957 mutex_init(&pmc->powergates_lock); 1958 1959 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 1960 if (!np) { 1961 /* 1962 * Fall back to legacy initialization for 32-bit ARM only. All 1963 * 64-bit ARM device tree files for Tegra are required to have 1964 * a PMC node. 1965 * 1966 * This is for backwards-compatibility with old device trees 1967 * that didn't contain a PMC node. Note that in this case the 1968 * SoC data can't be matched and therefore powergating is 1969 * disabled. 1970 */ 1971 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 1972 pr_warn("DT node not found, powergating disabled\n"); 1973 1974 regs.start = 0x7000e400; 1975 regs.end = 0x7000e7ff; 1976 regs.flags = IORESOURCE_MEM; 1977 1978 pr_warn("Using memory region %pR\n", ®s); 1979 } else { 1980 /* 1981 * At this point we're not running on Tegra, so play 1982 * nice with multi-platform kernels. 1983 */ 1984 return 0; 1985 } 1986 } else { 1987 /* 1988 * Extract information from the device tree if we've found a 1989 * matching node. 1990 */ 1991 if (of_address_to_resource(np, 0, ®s) < 0) { 1992 pr_err("failed to get PMC registers\n"); 1993 of_node_put(np); 1994 return -ENXIO; 1995 } 1996 } 1997 1998 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 1999 if (!pmc->base) { 2000 pr_err("failed to map PMC registers\n"); 2001 of_node_put(np); 2002 return -ENXIO; 2003 } 2004 2005 if (np) { 2006 pmc->soc = match->data; 2007 2008 tegra_powergate_init(pmc, np); 2009 2010 /* 2011 * Invert the interrupt polarity if a PMC device tree node 2012 * exists and contains the nvidia,invert-interrupt property. 2013 */ 2014 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 2015 2016 pmc->soc->setup_irq_polarity(pmc, np, invert); 2017 2018 of_node_put(np); 2019 } 2020 2021 return 0; 2022 } 2023 early_initcall(tegra_pmc_early_init); 2024