1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * drivers/soc/tegra/pmc.c 4 * 5 * Copyright (c) 2010 Google, Inc 6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Author: 9 * Colin Cross <ccross@google.com> 10 */ 11 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 13 14 #include <linux/arm-smccc.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 20 #include <linux/debugfs.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <linux/err.h> 24 #include <linux/export.h> 25 #include <linux/init.h> 26 #include <linux/io.h> 27 #include <linux/iopoll.h> 28 #include <linux/irqdomain.h> 29 #include <linux/irq.h> 30 #include <linux/kernel.h> 31 #include <linux/of_address.h> 32 #include <linux/of_clk.h> 33 #include <linux/of.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_platform.h> 36 #include <linux/pinctrl/pinconf-generic.h> 37 #include <linux/pinctrl/pinconf.h> 38 #include <linux/pinctrl/pinctrl.h> 39 #include <linux/platform_device.h> 40 #include <linux/pm_domain.h> 41 #include <linux/reboot.h> 42 #include <linux/reset.h> 43 #include <linux/seq_file.h> 44 #include <linux/slab.h> 45 #include <linux/spinlock.h> 46 47 #include <soc/tegra/common.h> 48 #include <soc/tegra/fuse.h> 49 #include <soc/tegra/pmc.h> 50 51 #include <dt-bindings/interrupt-controller/arm-gic.h> 52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 53 #include <dt-bindings/gpio/tegra186-gpio.h> 54 #include <dt-bindings/gpio/tegra194-gpio.h> 55 #include <dt-bindings/soc/tegra-pmc.h> 56 57 #define PMC_CNTRL 0x0 58 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 59 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 60 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 61 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 62 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 63 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 64 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8) 65 #define PMC_CNTRL_BLINK_EN 7 66 #define PMC_CNTRL_MAIN_RST BIT(4) 67 68 #define PMC_WAKE_MASK 0x0c 69 #define PMC_WAKE_LEVEL 0x10 70 #define PMC_WAKE_STATUS 0x14 71 #define PMC_SW_WAKE_STATUS 0x18 72 #define PMC_DPD_PADS_ORIDE 0x1c 73 #define PMC_DPD_PADS_ORIDE_BLINK 20 74 75 #define DPD_SAMPLE 0x020 76 #define DPD_SAMPLE_ENABLE BIT(0) 77 #define DPD_SAMPLE_DISABLE (0 << 0) 78 79 #define PWRGATE_TOGGLE 0x30 80 #define PWRGATE_TOGGLE_START BIT(8) 81 82 #define REMOVE_CLAMPING 0x34 83 84 #define PWRGATE_STATUS 0x38 85 86 #define PMC_BLINK_TIMER 0x40 87 #define PMC_IMPL_E_33V_PWR 0x40 88 89 #define PMC_PWR_DET 0x48 90 91 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 92 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 93 #define PMC_SCRATCH0_MODE_RCM BIT(1) 94 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 95 PMC_SCRATCH0_MODE_BOOTLOADER | \ 96 PMC_SCRATCH0_MODE_RCM) 97 98 #define PMC_CPUPWRGOOD_TIMER 0xc8 99 #define PMC_CPUPWROFF_TIMER 0xcc 100 #define PMC_COREPWRGOOD_TIMER 0x3c 101 #define PMC_COREPWROFF_TIMER 0xe0 102 103 #define PMC_PWR_DET_VALUE 0xe4 104 105 #define PMC_SCRATCH41 0x140 106 107 #define PMC_WAKE2_MASK 0x160 108 #define PMC_WAKE2_LEVEL 0x164 109 #define PMC_WAKE2_STATUS 0x168 110 #define PMC_SW_WAKE2_STATUS 0x16c 111 112 #define PMC_CLK_OUT_CNTRL 0x1a8 113 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0) 114 #define PMC_SENSOR_CTRL 0x1b0 115 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 116 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 117 118 #define PMC_RST_STATUS_POR 0 119 #define PMC_RST_STATUS_WATCHDOG 1 120 #define PMC_RST_STATUS_SENSOR 2 121 #define PMC_RST_STATUS_SW_MAIN 3 122 #define PMC_RST_STATUS_LP0 4 123 #define PMC_RST_STATUS_AOTAG 5 124 125 #define IO_DPD_REQ 0x1b8 126 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 127 #define IO_DPD_REQ_CODE_OFF (1U << 30) 128 #define IO_DPD_REQ_CODE_ON (2U << 30) 129 #define IO_DPD_REQ_CODE_MASK (3U << 30) 130 131 #define IO_DPD_STATUS 0x1bc 132 #define IO_DPD2_REQ 0x1c0 133 #define IO_DPD2_STATUS 0x1c4 134 #define SEL_DPD_TIM 0x1c8 135 136 #define PMC_SCRATCH54 0x258 137 #define PMC_SCRATCH54_DATA_SHIFT 8 138 #define PMC_SCRATCH54_ADDR_SHIFT 0 139 140 #define PMC_SCRATCH55 0x25c 141 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 142 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 143 #define PMC_SCRATCH55_PINMUX_SHIFT 24 144 #define PMC_SCRATCH55_16BITOP BIT(15) 145 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 146 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 147 148 #define GPU_RG_CNTRL 0x2d4 149 150 /* Tegra186 and later */ 151 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) 152 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) 153 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) 154 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) 155 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) 156 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2)) 157 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2)) 158 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2)) 159 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2)) 160 161 #define WAKE_AOWAKE_CTRL 0x4f4 162 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 163 164 /* for secure PMC */ 165 #define TEGRA_SMC_PMC 0xc2fffe00 166 #define TEGRA_SMC_PMC_READ 0xaa 167 #define TEGRA_SMC_PMC_WRITE 0xbb 168 169 struct pmc_clk { 170 struct clk_hw hw; 171 unsigned long offs; 172 u32 mux_shift; 173 u32 force_en_shift; 174 }; 175 176 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw) 177 178 struct pmc_clk_gate { 179 struct clk_hw hw; 180 unsigned long offs; 181 u32 shift; 182 }; 183 184 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw) 185 186 struct pmc_clk_init_data { 187 char *name; 188 const char *const *parents; 189 int num_parents; 190 int clk_id; 191 u8 mux_shift; 192 u8 force_en_shift; 193 }; 194 195 static const char * const clk_out1_parents[] = { "osc", "osc_div2", 196 "osc_div4", "extern1", 197 }; 198 199 static const char * const clk_out2_parents[] = { "osc", "osc_div2", 200 "osc_div4", "extern2", 201 }; 202 203 static const char * const clk_out3_parents[] = { "osc", "osc_div2", 204 "osc_div4", "extern3", 205 }; 206 207 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = { 208 { 209 .name = "pmc_clk_out_1", 210 .parents = clk_out1_parents, 211 .num_parents = ARRAY_SIZE(clk_out1_parents), 212 .clk_id = TEGRA_PMC_CLK_OUT_1, 213 .mux_shift = 6, 214 .force_en_shift = 2, 215 }, 216 { 217 .name = "pmc_clk_out_2", 218 .parents = clk_out2_parents, 219 .num_parents = ARRAY_SIZE(clk_out2_parents), 220 .clk_id = TEGRA_PMC_CLK_OUT_2, 221 .mux_shift = 14, 222 .force_en_shift = 10, 223 }, 224 { 225 .name = "pmc_clk_out_3", 226 .parents = clk_out3_parents, 227 .num_parents = ARRAY_SIZE(clk_out3_parents), 228 .clk_id = TEGRA_PMC_CLK_OUT_3, 229 .mux_shift = 22, 230 .force_en_shift = 18, 231 }, 232 }; 233 234 struct tegra_powergate { 235 struct generic_pm_domain genpd; 236 struct tegra_pmc *pmc; 237 unsigned int id; 238 struct clk **clks; 239 unsigned int num_clks; 240 struct reset_control *reset; 241 }; 242 243 struct tegra_io_pad_soc { 244 enum tegra_io_pad id; 245 unsigned int dpd; 246 unsigned int voltage; 247 const char *name; 248 }; 249 250 struct tegra_pmc_regs { 251 unsigned int scratch0; 252 unsigned int dpd_req; 253 unsigned int dpd_status; 254 unsigned int dpd2_req; 255 unsigned int dpd2_status; 256 unsigned int rst_status; 257 unsigned int rst_source_shift; 258 unsigned int rst_source_mask; 259 unsigned int rst_level_shift; 260 unsigned int rst_level_mask; 261 }; 262 263 struct tegra_wake_event { 264 const char *name; 265 unsigned int id; 266 unsigned int irq; 267 struct { 268 unsigned int instance; 269 unsigned int pin; 270 } gpio; 271 }; 272 273 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \ 274 { \ 275 .name = _name, \ 276 .id = _id, \ 277 .irq = _irq, \ 278 .gpio = { \ 279 .instance = UINT_MAX, \ 280 .pin = UINT_MAX, \ 281 }, \ 282 } 283 284 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \ 285 { \ 286 .name = _name, \ 287 .id = _id, \ 288 .irq = 0, \ 289 .gpio = { \ 290 .instance = _instance, \ 291 .pin = _pin, \ 292 }, \ 293 } 294 295 struct tegra_pmc_soc { 296 unsigned int num_powergates; 297 const char *const *powergates; 298 unsigned int num_cpu_powergates; 299 const u8 *cpu_powergates; 300 301 bool has_tsense_reset; 302 bool has_gpu_clamps; 303 bool needs_mbist_war; 304 bool has_impl_33v_pwr; 305 bool maybe_tz_only; 306 307 const struct tegra_io_pad_soc *io_pads; 308 unsigned int num_io_pads; 309 310 const struct pinctrl_pin_desc *pin_descs; 311 unsigned int num_pin_descs; 312 313 const struct tegra_pmc_regs *regs; 314 void (*init)(struct tegra_pmc *pmc); 315 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 316 struct device_node *np, 317 bool invert); 318 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 319 int (*irq_set_type)(struct irq_data *data, unsigned int type); 320 321 const char * const *reset_sources; 322 unsigned int num_reset_sources; 323 const char * const *reset_levels; 324 unsigned int num_reset_levels; 325 326 /* 327 * These describe events that can wake the system from sleep (i.e. 328 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2) 329 * are dealt with in the LIC. 330 */ 331 const struct tegra_wake_event *wake_events; 332 unsigned int num_wake_events; 333 334 const struct pmc_clk_init_data *pmc_clks_data; 335 unsigned int num_pmc_clks; 336 bool has_blink_output; 337 }; 338 339 /** 340 * struct tegra_pmc - NVIDIA Tegra PMC 341 * @dev: pointer to PMC device structure 342 * @base: pointer to I/O remapped register region 343 * @wake: pointer to I/O remapped region for WAKE registers 344 * @aotag: pointer to I/O remapped region for AOTAG registers 345 * @scratch: pointer to I/O remapped region for scratch registers 346 * @clk: pointer to pclk clock 347 * @soc: pointer to SoC data structure 348 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone 349 * @debugfs: pointer to debugfs entry 350 * @rate: currently configured rate of pclk 351 * @suspend_mode: lowest suspend mode available 352 * @cpu_good_time: CPU power good time (in microseconds) 353 * @cpu_off_time: CPU power off time (in microsecends) 354 * @core_osc_time: core power good OSC time (in microseconds) 355 * @core_pmu_time: core power good PMU time (in microseconds) 356 * @core_off_time: core power off time (in microseconds) 357 * @corereq_high: core power request is active-high 358 * @sysclkreq_high: system clock request is active-high 359 * @combined_req: combined power request for CPU & core 360 * @cpu_pwr_good_en: CPU power good signal is enabled 361 * @lp0_vec_phys: physical base address of the LP0 warm boot code 362 * @lp0_vec_size: size of the LP0 warm boot code 363 * @powergates_available: Bitmap of available power gates 364 * @powergates_lock: mutex for power gate register access 365 * @pctl_dev: pin controller exposed by the PMC 366 * @domain: IRQ domain provided by the PMC 367 * @irq: chip implementation for the IRQ domain 368 * @clk_nb: pclk clock changes handler 369 */ 370 struct tegra_pmc { 371 struct device *dev; 372 void __iomem *base; 373 void __iomem *wake; 374 void __iomem *aotag; 375 void __iomem *scratch; 376 struct clk *clk; 377 struct dentry *debugfs; 378 379 const struct tegra_pmc_soc *soc; 380 bool tz_only; 381 382 unsigned long rate; 383 384 enum tegra_suspend_mode suspend_mode; 385 u32 cpu_good_time; 386 u32 cpu_off_time; 387 u32 core_osc_time; 388 u32 core_pmu_time; 389 u32 core_off_time; 390 bool corereq_high; 391 bool sysclkreq_high; 392 bool combined_req; 393 bool cpu_pwr_good_en; 394 u32 lp0_vec_phys; 395 u32 lp0_vec_size; 396 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 397 398 struct mutex powergates_lock; 399 400 struct pinctrl_dev *pctl_dev; 401 402 struct irq_domain *domain; 403 struct irq_chip irq; 404 405 struct notifier_block clk_nb; 406 }; 407 408 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 409 .base = NULL, 410 .suspend_mode = TEGRA_SUSPEND_NONE, 411 }; 412 413 static inline struct tegra_powergate * 414 to_powergate(struct generic_pm_domain *domain) 415 { 416 return container_of(domain, struct tegra_powergate, genpd); 417 } 418 419 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) 420 { 421 struct arm_smccc_res res; 422 423 if (pmc->tz_only) { 424 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, 425 0, 0, 0, &res); 426 if (res.a0) { 427 if (pmc->dev) 428 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 429 __func__, res.a0); 430 else 431 pr_warn("%s(): SMC failed: %lu\n", __func__, 432 res.a0); 433 } 434 435 return res.a1; 436 } 437 438 return readl(pmc->base + offset); 439 } 440 441 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, 442 unsigned long offset) 443 { 444 struct arm_smccc_res res; 445 446 if (pmc->tz_only) { 447 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset, 448 value, 0, 0, 0, 0, &res); 449 if (res.a0) { 450 if (pmc->dev) 451 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", 452 __func__, res.a0); 453 else 454 pr_warn("%s(): SMC failed: %lu\n", __func__, 455 res.a0); 456 } 457 } else { 458 writel(value, pmc->base + offset); 459 } 460 } 461 462 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) 463 { 464 if (pmc->tz_only) 465 return tegra_pmc_readl(pmc, offset); 466 467 return readl(pmc->scratch + offset); 468 } 469 470 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, 471 unsigned long offset) 472 { 473 if (pmc->tz_only) 474 tegra_pmc_writel(pmc, value, offset); 475 else 476 writel(value, pmc->scratch + offset); 477 } 478 479 /* 480 * TODO Figure out a way to call this with the struct tegra_pmc * passed in. 481 * This currently doesn't work because readx_poll_timeout() can only operate 482 * on functions that take a single argument. 483 */ 484 static inline bool tegra_powergate_state(int id) 485 { 486 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 487 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; 488 else 489 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; 490 } 491 492 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) 493 { 494 return (pmc->soc && pmc->soc->powergates[id]); 495 } 496 497 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) 498 { 499 return test_bit(id, pmc->powergates_available); 500 } 501 502 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 503 { 504 unsigned int i; 505 506 if (!pmc || !pmc->soc || !name) 507 return -EINVAL; 508 509 for (i = 0; i < pmc->soc->num_powergates; i++) { 510 if (!tegra_powergate_is_valid(pmc, i)) 511 continue; 512 513 if (!strcmp(name, pmc->soc->powergates[i])) 514 return i; 515 } 516 517 return -ENODEV; 518 } 519 520 /** 521 * tegra_powergate_set() - set the state of a partition 522 * @pmc: power management controller 523 * @id: partition ID 524 * @new_state: new state of the partition 525 */ 526 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, 527 bool new_state) 528 { 529 bool status; 530 int err; 531 532 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 533 return -EINVAL; 534 535 mutex_lock(&pmc->powergates_lock); 536 537 if (tegra_powergate_state(id) == new_state) { 538 mutex_unlock(&pmc->powergates_lock); 539 return 0; 540 } 541 542 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 543 544 err = readx_poll_timeout(tegra_powergate_state, id, status, 545 status == new_state, 10, 100000); 546 547 mutex_unlock(&pmc->powergates_lock); 548 549 return err; 550 } 551 552 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, 553 unsigned int id) 554 { 555 u32 mask; 556 557 mutex_lock(&pmc->powergates_lock); 558 559 /* 560 * On Tegra124 and later, the clamps for the GPU are controlled by a 561 * separate register (with different semantics). 562 */ 563 if (id == TEGRA_POWERGATE_3D) { 564 if (pmc->soc->has_gpu_clamps) { 565 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); 566 goto out; 567 } 568 } 569 570 /* 571 * Tegra 2 has a bug where PCIE and VDE clamping masks are 572 * swapped relatively to the partition ids 573 */ 574 if (id == TEGRA_POWERGATE_VDEC) 575 mask = (1 << TEGRA_POWERGATE_PCIE); 576 else if (id == TEGRA_POWERGATE_PCIE) 577 mask = (1 << TEGRA_POWERGATE_VDEC); 578 else 579 mask = (1 << id); 580 581 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); 582 583 out: 584 mutex_unlock(&pmc->powergates_lock); 585 586 return 0; 587 } 588 589 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 590 { 591 unsigned int i; 592 593 for (i = 0; i < pg->num_clks; i++) 594 clk_disable_unprepare(pg->clks[i]); 595 } 596 597 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 598 { 599 unsigned int i; 600 int err; 601 602 for (i = 0; i < pg->num_clks; i++) { 603 err = clk_prepare_enable(pg->clks[i]); 604 if (err) 605 goto out; 606 } 607 608 return 0; 609 610 out: 611 while (i--) 612 clk_disable_unprepare(pg->clks[i]); 613 614 return err; 615 } 616 617 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 618 { 619 return 0; 620 } 621 622 static int tegra_powergate_power_up(struct tegra_powergate *pg, 623 bool disable_clocks) 624 { 625 int err; 626 627 err = reset_control_assert(pg->reset); 628 if (err) 629 return err; 630 631 usleep_range(10, 20); 632 633 err = tegra_powergate_set(pg->pmc, pg->id, true); 634 if (err < 0) 635 return err; 636 637 usleep_range(10, 20); 638 639 err = tegra_powergate_enable_clocks(pg); 640 if (err) 641 goto disable_clks; 642 643 usleep_range(10, 20); 644 645 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); 646 if (err) 647 goto disable_clks; 648 649 usleep_range(10, 20); 650 651 err = reset_control_deassert(pg->reset); 652 if (err) 653 goto powergate_off; 654 655 usleep_range(10, 20); 656 657 if (pg->pmc->soc->needs_mbist_war) 658 err = tegra210_clk_handle_mbist_war(pg->id); 659 if (err) 660 goto disable_clks; 661 662 if (disable_clocks) 663 tegra_powergate_disable_clocks(pg); 664 665 return 0; 666 667 disable_clks: 668 tegra_powergate_disable_clocks(pg); 669 usleep_range(10, 20); 670 671 powergate_off: 672 tegra_powergate_set(pg->pmc, pg->id, false); 673 674 return err; 675 } 676 677 static int tegra_powergate_power_down(struct tegra_powergate *pg) 678 { 679 int err; 680 681 err = tegra_powergate_enable_clocks(pg); 682 if (err) 683 return err; 684 685 usleep_range(10, 20); 686 687 err = reset_control_assert(pg->reset); 688 if (err) 689 goto disable_clks; 690 691 usleep_range(10, 20); 692 693 tegra_powergate_disable_clocks(pg); 694 695 usleep_range(10, 20); 696 697 err = tegra_powergate_set(pg->pmc, pg->id, false); 698 if (err) 699 goto assert_resets; 700 701 return 0; 702 703 assert_resets: 704 tegra_powergate_enable_clocks(pg); 705 usleep_range(10, 20); 706 reset_control_deassert(pg->reset); 707 usleep_range(10, 20); 708 709 disable_clks: 710 tegra_powergate_disable_clocks(pg); 711 712 return err; 713 } 714 715 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 716 { 717 struct tegra_powergate *pg = to_powergate(domain); 718 struct device *dev = pg->pmc->dev; 719 int err; 720 721 err = tegra_powergate_power_up(pg, true); 722 if (err) { 723 dev_err(dev, "failed to turn on PM domain %s: %d\n", 724 pg->genpd.name, err); 725 goto out; 726 } 727 728 reset_control_release(pg->reset); 729 730 out: 731 return err; 732 } 733 734 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 735 { 736 struct tegra_powergate *pg = to_powergate(domain); 737 struct device *dev = pg->pmc->dev; 738 int err; 739 740 err = reset_control_acquire(pg->reset); 741 if (err < 0) { 742 pr_err("failed to acquire resets: %d\n", err); 743 return err; 744 } 745 746 err = tegra_powergate_power_down(pg); 747 if (err) { 748 dev_err(dev, "failed to turn off PM domain %s: %d\n", 749 pg->genpd.name, err); 750 reset_control_release(pg->reset); 751 } 752 753 return err; 754 } 755 756 /** 757 * tegra_powergate_power_on() - power on partition 758 * @id: partition ID 759 */ 760 int tegra_powergate_power_on(unsigned int id) 761 { 762 if (!tegra_powergate_is_available(pmc, id)) 763 return -EINVAL; 764 765 return tegra_powergate_set(pmc, id, true); 766 } 767 EXPORT_SYMBOL(tegra_powergate_power_on); 768 769 /** 770 * tegra_powergate_power_off() - power off partition 771 * @id: partition ID 772 */ 773 int tegra_powergate_power_off(unsigned int id) 774 { 775 if (!tegra_powergate_is_available(pmc, id)) 776 return -EINVAL; 777 778 return tegra_powergate_set(pmc, id, false); 779 } 780 EXPORT_SYMBOL(tegra_powergate_power_off); 781 782 /** 783 * tegra_powergate_is_powered() - check if partition is powered 784 * @pmc: power management controller 785 * @id: partition ID 786 */ 787 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) 788 { 789 if (!tegra_powergate_is_valid(pmc, id)) 790 return -EINVAL; 791 792 return tegra_powergate_state(id); 793 } 794 795 /** 796 * tegra_powergate_remove_clamping() - remove power clamps for partition 797 * @id: partition ID 798 */ 799 int tegra_powergate_remove_clamping(unsigned int id) 800 { 801 if (!tegra_powergate_is_available(pmc, id)) 802 return -EINVAL; 803 804 return __tegra_powergate_remove_clamping(pmc, id); 805 } 806 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 807 808 /** 809 * tegra_powergate_sequence_power_up() - power up partition 810 * @id: partition ID 811 * @clk: clock for partition 812 * @rst: reset for partition 813 * 814 * Must be called with clk disabled, and returns with clk enabled. 815 */ 816 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 817 struct reset_control *rst) 818 { 819 struct tegra_powergate *pg; 820 int err; 821 822 if (!tegra_powergate_is_available(pmc, id)) 823 return -EINVAL; 824 825 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 826 if (!pg) 827 return -ENOMEM; 828 829 pg->id = id; 830 pg->clks = &clk; 831 pg->num_clks = 1; 832 pg->reset = rst; 833 pg->pmc = pmc; 834 835 err = tegra_powergate_power_up(pg, false); 836 if (err) 837 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, 838 err); 839 840 kfree(pg); 841 842 return err; 843 } 844 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 845 846 /** 847 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 848 * @pmc: power management controller 849 * @cpuid: CPU partition ID 850 * 851 * Returns the partition ID corresponding to the CPU partition ID or a 852 * negative error code on failure. 853 */ 854 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, 855 unsigned int cpuid) 856 { 857 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 858 return pmc->soc->cpu_powergates[cpuid]; 859 860 return -EINVAL; 861 } 862 863 /** 864 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 865 * @cpuid: CPU partition ID 866 */ 867 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 868 { 869 int id; 870 871 id = tegra_get_cpu_powergate_id(pmc, cpuid); 872 if (id < 0) 873 return false; 874 875 return tegra_powergate_is_powered(pmc, id); 876 } 877 878 /** 879 * tegra_pmc_cpu_power_on() - power on CPU partition 880 * @cpuid: CPU partition ID 881 */ 882 int tegra_pmc_cpu_power_on(unsigned int cpuid) 883 { 884 int id; 885 886 id = tegra_get_cpu_powergate_id(pmc, cpuid); 887 if (id < 0) 888 return id; 889 890 return tegra_powergate_set(pmc, id, true); 891 } 892 893 /** 894 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 895 * @cpuid: CPU partition ID 896 */ 897 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 898 { 899 int id; 900 901 id = tegra_get_cpu_powergate_id(pmc, cpuid); 902 if (id < 0) 903 return id; 904 905 return tegra_powergate_remove_clamping(id); 906 } 907 908 static int tegra_pmc_restart_notify(struct notifier_block *this, 909 unsigned long action, void *data) 910 { 911 const char *cmd = data; 912 u32 value; 913 914 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); 915 value &= ~PMC_SCRATCH0_MODE_MASK; 916 917 if (cmd) { 918 if (strcmp(cmd, "recovery") == 0) 919 value |= PMC_SCRATCH0_MODE_RECOVERY; 920 921 if (strcmp(cmd, "bootloader") == 0) 922 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 923 924 if (strcmp(cmd, "forced-recovery") == 0) 925 value |= PMC_SCRATCH0_MODE_RCM; 926 } 927 928 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); 929 930 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 931 value = tegra_pmc_readl(pmc, PMC_CNTRL); 932 value |= PMC_CNTRL_MAIN_RST; 933 tegra_pmc_writel(pmc, value, PMC_CNTRL); 934 935 return NOTIFY_DONE; 936 } 937 938 static struct notifier_block tegra_pmc_restart_handler = { 939 .notifier_call = tegra_pmc_restart_notify, 940 .priority = 128, 941 }; 942 943 static int powergate_show(struct seq_file *s, void *data) 944 { 945 unsigned int i; 946 int status; 947 948 seq_printf(s, " powergate powered\n"); 949 seq_printf(s, "------------------\n"); 950 951 for (i = 0; i < pmc->soc->num_powergates; i++) { 952 status = tegra_powergate_is_powered(pmc, i); 953 if (status < 0) 954 continue; 955 956 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 957 status ? "yes" : "no"); 958 } 959 960 return 0; 961 } 962 963 DEFINE_SHOW_ATTRIBUTE(powergate); 964 965 static int tegra_powergate_debugfs_init(void) 966 { 967 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 968 &powergate_fops); 969 if (!pmc->debugfs) 970 return -ENOMEM; 971 972 return 0; 973 } 974 975 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 976 struct device_node *np) 977 { 978 struct clk *clk; 979 unsigned int i, count; 980 int err; 981 982 count = of_clk_get_parent_count(np); 983 if (count == 0) 984 return -ENODEV; 985 986 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 987 if (!pg->clks) 988 return -ENOMEM; 989 990 for (i = 0; i < count; i++) { 991 pg->clks[i] = of_clk_get(np, i); 992 if (IS_ERR(pg->clks[i])) { 993 err = PTR_ERR(pg->clks[i]); 994 goto err; 995 } 996 } 997 998 pg->num_clks = count; 999 1000 return 0; 1001 1002 err: 1003 while (i--) 1004 clk_put(pg->clks[i]); 1005 1006 kfree(pg->clks); 1007 1008 return err; 1009 } 1010 1011 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 1012 struct device_node *np, bool off) 1013 { 1014 struct device *dev = pg->pmc->dev; 1015 int err; 1016 1017 pg->reset = of_reset_control_array_get_exclusive_released(np); 1018 if (IS_ERR(pg->reset)) { 1019 err = PTR_ERR(pg->reset); 1020 dev_err(dev, "failed to get device resets: %d\n", err); 1021 return err; 1022 } 1023 1024 err = reset_control_acquire(pg->reset); 1025 if (err < 0) { 1026 pr_err("failed to acquire resets: %d\n", err); 1027 goto out; 1028 } 1029 1030 if (off) { 1031 err = reset_control_assert(pg->reset); 1032 } else { 1033 err = reset_control_deassert(pg->reset); 1034 if (err < 0) 1035 goto out; 1036 1037 reset_control_release(pg->reset); 1038 } 1039 1040 out: 1041 if (err) { 1042 reset_control_release(pg->reset); 1043 reset_control_put(pg->reset); 1044 } 1045 1046 return err; 1047 } 1048 1049 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 1050 { 1051 struct device *dev = pmc->dev; 1052 struct tegra_powergate *pg; 1053 int id, err = 0; 1054 bool off; 1055 1056 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 1057 if (!pg) 1058 return -ENOMEM; 1059 1060 id = tegra_powergate_lookup(pmc, np->name); 1061 if (id < 0) { 1062 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id); 1063 err = -ENODEV; 1064 goto free_mem; 1065 } 1066 1067 /* 1068 * Clear the bit for this powergate so it cannot be managed 1069 * directly via the legacy APIs for controlling powergates. 1070 */ 1071 clear_bit(id, pmc->powergates_available); 1072 1073 pg->id = id; 1074 pg->genpd.name = np->name; 1075 pg->genpd.power_off = tegra_genpd_power_off; 1076 pg->genpd.power_on = tegra_genpd_power_on; 1077 pg->pmc = pmc; 1078 1079 off = !tegra_powergate_is_powered(pmc, pg->id); 1080 1081 err = tegra_powergate_of_get_clks(pg, np); 1082 if (err < 0) { 1083 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err); 1084 goto set_available; 1085 } 1086 1087 err = tegra_powergate_of_get_resets(pg, np, off); 1088 if (err < 0) { 1089 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err); 1090 goto remove_clks; 1091 } 1092 1093 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 1094 if (off) 1095 WARN_ON(tegra_powergate_power_up(pg, true)); 1096 1097 goto remove_resets; 1098 } 1099 1100 err = pm_genpd_init(&pg->genpd, NULL, off); 1101 if (err < 0) { 1102 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np, 1103 err); 1104 goto remove_resets; 1105 } 1106 1107 err = of_genpd_add_provider_simple(np, &pg->genpd); 1108 if (err < 0) { 1109 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n", 1110 np, err); 1111 goto remove_genpd; 1112 } 1113 1114 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); 1115 1116 return 0; 1117 1118 remove_genpd: 1119 pm_genpd_remove(&pg->genpd); 1120 1121 remove_resets: 1122 reset_control_put(pg->reset); 1123 1124 remove_clks: 1125 while (pg->num_clks--) 1126 clk_put(pg->clks[pg->num_clks]); 1127 1128 kfree(pg->clks); 1129 1130 set_available: 1131 set_bit(id, pmc->powergates_available); 1132 1133 free_mem: 1134 kfree(pg); 1135 1136 return err; 1137 } 1138 1139 static int tegra_powergate_init(struct tegra_pmc *pmc, 1140 struct device_node *parent) 1141 { 1142 struct device_node *np, *child; 1143 int err = 0; 1144 1145 np = of_get_child_by_name(parent, "powergates"); 1146 if (!np) 1147 return 0; 1148 1149 for_each_child_of_node(np, child) { 1150 err = tegra_powergate_add(pmc, child); 1151 if (err < 0) { 1152 of_node_put(child); 1153 break; 1154 } 1155 } 1156 1157 of_node_put(np); 1158 1159 return err; 1160 } 1161 1162 static void tegra_powergate_remove(struct generic_pm_domain *genpd) 1163 { 1164 struct tegra_powergate *pg = to_powergate(genpd); 1165 1166 reset_control_put(pg->reset); 1167 1168 while (pg->num_clks--) 1169 clk_put(pg->clks[pg->num_clks]); 1170 1171 kfree(pg->clks); 1172 1173 set_bit(pg->id, pmc->powergates_available); 1174 1175 kfree(pg); 1176 } 1177 1178 static void tegra_powergate_remove_all(struct device_node *parent) 1179 { 1180 struct generic_pm_domain *genpd; 1181 struct device_node *np, *child; 1182 1183 np = of_get_child_by_name(parent, "powergates"); 1184 if (!np) 1185 return; 1186 1187 for_each_child_of_node(np, child) { 1188 of_genpd_del_provider(child); 1189 1190 genpd = of_genpd_remove_last(child); 1191 if (IS_ERR(genpd)) 1192 continue; 1193 1194 tegra_powergate_remove(genpd); 1195 } 1196 1197 of_node_put(np); 1198 } 1199 1200 static const struct tegra_io_pad_soc * 1201 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 1202 { 1203 unsigned int i; 1204 1205 for (i = 0; i < pmc->soc->num_io_pads; i++) 1206 if (pmc->soc->io_pads[i].id == id) 1207 return &pmc->soc->io_pads[i]; 1208 1209 return NULL; 1210 } 1211 1212 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, 1213 enum tegra_io_pad id, 1214 unsigned long *request, 1215 unsigned long *status, 1216 u32 *mask) 1217 { 1218 const struct tegra_io_pad_soc *pad; 1219 1220 pad = tegra_io_pad_find(pmc, id); 1221 if (!pad) { 1222 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); 1223 return -ENOENT; 1224 } 1225 1226 if (pad->dpd == UINT_MAX) 1227 return -ENOTSUPP; 1228 1229 *mask = BIT(pad->dpd % 32); 1230 1231 if (pad->dpd < 32) { 1232 *status = pmc->soc->regs->dpd_status; 1233 *request = pmc->soc->regs->dpd_req; 1234 } else { 1235 *status = pmc->soc->regs->dpd2_status; 1236 *request = pmc->soc->regs->dpd2_req; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, 1243 unsigned long *request, unsigned long *status, 1244 u32 *mask) 1245 { 1246 unsigned long rate, value; 1247 int err; 1248 1249 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); 1250 if (err) 1251 return err; 1252 1253 if (pmc->clk) { 1254 rate = pmc->rate; 1255 if (!rate) { 1256 dev_err(pmc->dev, "failed to get clock rate\n"); 1257 return -ENODEV; 1258 } 1259 1260 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); 1261 1262 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 1263 value = DIV_ROUND_UP(1000000000, rate); 1264 value = DIV_ROUND_UP(200, value); 1265 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); 1266 } 1267 1268 return 0; 1269 } 1270 1271 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, 1272 u32 mask, u32 val, unsigned long timeout) 1273 { 1274 u32 value; 1275 1276 timeout = jiffies + msecs_to_jiffies(timeout); 1277 1278 while (time_after(timeout, jiffies)) { 1279 value = tegra_pmc_readl(pmc, offset); 1280 if ((value & mask) == val) 1281 return 0; 1282 1283 usleep_range(250, 1000); 1284 } 1285 1286 return -ETIMEDOUT; 1287 } 1288 1289 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) 1290 { 1291 if (pmc->clk) 1292 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); 1293 } 1294 1295 /** 1296 * tegra_io_pad_power_enable() - enable power to I/O pad 1297 * @id: Tegra I/O pad ID for which to enable power 1298 * 1299 * Returns: 0 on success or a negative error code on failure. 1300 */ 1301 int tegra_io_pad_power_enable(enum tegra_io_pad id) 1302 { 1303 unsigned long request, status; 1304 u32 mask; 1305 int err; 1306 1307 mutex_lock(&pmc->powergates_lock); 1308 1309 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1310 if (err < 0) { 1311 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1312 goto unlock; 1313 } 1314 1315 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); 1316 1317 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); 1318 if (err < 0) { 1319 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); 1320 goto unlock; 1321 } 1322 1323 tegra_io_pad_unprepare(pmc); 1324 1325 unlock: 1326 mutex_unlock(&pmc->powergates_lock); 1327 return err; 1328 } 1329 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1330 1331 /** 1332 * tegra_io_pad_power_disable() - disable power to I/O pad 1333 * @id: Tegra I/O pad ID for which to disable power 1334 * 1335 * Returns: 0 on success or a negative error code on failure. 1336 */ 1337 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1338 { 1339 unsigned long request, status; 1340 u32 mask; 1341 int err; 1342 1343 mutex_lock(&pmc->powergates_lock); 1344 1345 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); 1346 if (err < 0) { 1347 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); 1348 goto unlock; 1349 } 1350 1351 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); 1352 1353 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); 1354 if (err < 0) { 1355 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); 1356 goto unlock; 1357 } 1358 1359 tegra_io_pad_unprepare(pmc); 1360 1361 unlock: 1362 mutex_unlock(&pmc->powergates_lock); 1363 return err; 1364 } 1365 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1366 1367 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) 1368 { 1369 unsigned long request, status; 1370 u32 mask, value; 1371 int err; 1372 1373 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, 1374 &mask); 1375 if (err) 1376 return err; 1377 1378 value = tegra_pmc_readl(pmc, status); 1379 1380 return !(value & mask); 1381 } 1382 1383 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, 1384 int voltage) 1385 { 1386 const struct tegra_io_pad_soc *pad; 1387 u32 value; 1388 1389 pad = tegra_io_pad_find(pmc, id); 1390 if (!pad) 1391 return -ENOENT; 1392 1393 if (pad->voltage == UINT_MAX) 1394 return -ENOTSUPP; 1395 1396 mutex_lock(&pmc->powergates_lock); 1397 1398 if (pmc->soc->has_impl_33v_pwr) { 1399 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1400 1401 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1402 value &= ~BIT(pad->voltage); 1403 else 1404 value |= BIT(pad->voltage); 1405 1406 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); 1407 } else { 1408 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1409 value = tegra_pmc_readl(pmc, PMC_PWR_DET); 1410 value |= BIT(pad->voltage); 1411 tegra_pmc_writel(pmc, value, PMC_PWR_DET); 1412 1413 /* update I/O voltage */ 1414 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1415 1416 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) 1417 value &= ~BIT(pad->voltage); 1418 else 1419 value |= BIT(pad->voltage); 1420 1421 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); 1422 } 1423 1424 mutex_unlock(&pmc->powergates_lock); 1425 1426 usleep_range(100, 250); 1427 1428 return 0; 1429 } 1430 1431 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) 1432 { 1433 const struct tegra_io_pad_soc *pad; 1434 u32 value; 1435 1436 pad = tegra_io_pad_find(pmc, id); 1437 if (!pad) 1438 return -ENOENT; 1439 1440 if (pad->voltage == UINT_MAX) 1441 return -ENOTSUPP; 1442 1443 if (pmc->soc->has_impl_33v_pwr) 1444 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); 1445 else 1446 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); 1447 1448 if ((value & BIT(pad->voltage)) == 0) 1449 return TEGRA_IO_PAD_VOLTAGE_1V8; 1450 1451 return TEGRA_IO_PAD_VOLTAGE_3V3; 1452 } 1453 1454 /** 1455 * tegra_io_rail_power_on() - enable power to I/O rail 1456 * @id: Tegra I/O pad ID for which to enable power 1457 * 1458 * See also: tegra_io_pad_power_enable() 1459 */ 1460 int tegra_io_rail_power_on(unsigned int id) 1461 { 1462 return tegra_io_pad_power_enable(id); 1463 } 1464 EXPORT_SYMBOL(tegra_io_rail_power_on); 1465 1466 /** 1467 * tegra_io_rail_power_off() - disable power to I/O rail 1468 * @id: Tegra I/O pad ID for which to disable power 1469 * 1470 * See also: tegra_io_pad_power_disable() 1471 */ 1472 int tegra_io_rail_power_off(unsigned int id) 1473 { 1474 return tegra_io_pad_power_disable(id); 1475 } 1476 EXPORT_SYMBOL(tegra_io_rail_power_off); 1477 1478 #ifdef CONFIG_PM_SLEEP 1479 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1480 { 1481 return pmc->suspend_mode; 1482 } 1483 1484 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1485 { 1486 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1487 return; 1488 1489 pmc->suspend_mode = mode; 1490 } 1491 1492 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1493 { 1494 unsigned long long rate = 0; 1495 u64 ticks; 1496 u32 value; 1497 1498 switch (mode) { 1499 case TEGRA_SUSPEND_LP1: 1500 rate = 32768; 1501 break; 1502 1503 case TEGRA_SUSPEND_LP2: 1504 rate = pmc->rate; 1505 break; 1506 1507 default: 1508 break; 1509 } 1510 1511 if (WARN_ON_ONCE(rate == 0)) 1512 rate = 100000000; 1513 1514 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1515 do_div(ticks, USEC_PER_SEC); 1516 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); 1517 1518 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1519 do_div(ticks, USEC_PER_SEC); 1520 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); 1521 1522 value = tegra_pmc_readl(pmc, PMC_CNTRL); 1523 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1524 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1525 tegra_pmc_writel(pmc, value, PMC_CNTRL); 1526 } 1527 #endif 1528 1529 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1530 { 1531 u32 value, values[2]; 1532 1533 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1534 } else { 1535 switch (value) { 1536 case 0: 1537 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1538 break; 1539 1540 case 1: 1541 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1542 break; 1543 1544 case 2: 1545 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1546 break; 1547 1548 default: 1549 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1550 break; 1551 } 1552 } 1553 1554 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1555 1556 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1557 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1558 1559 pmc->cpu_good_time = value; 1560 1561 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1562 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1563 1564 pmc->cpu_off_time = value; 1565 1566 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1567 values, ARRAY_SIZE(values))) 1568 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1569 1570 pmc->core_osc_time = values[0]; 1571 pmc->core_pmu_time = values[1]; 1572 1573 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1574 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1575 1576 pmc->core_off_time = value; 1577 1578 pmc->corereq_high = of_property_read_bool(np, 1579 "nvidia,core-power-req-active-high"); 1580 1581 pmc->sysclkreq_high = of_property_read_bool(np, 1582 "nvidia,sys-clock-req-active-high"); 1583 1584 pmc->combined_req = of_property_read_bool(np, 1585 "nvidia,combined-power-req"); 1586 1587 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1588 "nvidia,cpu-pwr-good-en"); 1589 1590 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1591 ARRAY_SIZE(values))) 1592 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1593 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1594 1595 pmc->lp0_vec_phys = values[0]; 1596 pmc->lp0_vec_size = values[1]; 1597 1598 return 0; 1599 } 1600 1601 static void tegra_pmc_init(struct tegra_pmc *pmc) 1602 { 1603 if (pmc->soc->init) 1604 pmc->soc->init(pmc); 1605 } 1606 1607 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1608 { 1609 static const char disabled[] = "emergency thermal reset disabled"; 1610 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1611 struct device *dev = pmc->dev; 1612 struct device_node *np; 1613 u32 value, checksum; 1614 1615 if (!pmc->soc->has_tsense_reset) 1616 return; 1617 1618 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1619 if (!np) { 1620 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1621 return; 1622 } 1623 1624 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1625 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1626 goto out; 1627 } 1628 1629 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1630 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1631 goto out; 1632 } 1633 1634 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1635 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1636 goto out; 1637 } 1638 1639 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1640 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1641 goto out; 1642 } 1643 1644 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1645 pinmux = 0; 1646 1647 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1648 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1649 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1650 1651 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1652 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1653 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); 1654 1655 value = PMC_SCRATCH55_RESET_TEGRA; 1656 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1657 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1658 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1659 1660 /* 1661 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1662 * contain the checksum and are currently zero, so they are not added. 1663 */ 1664 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1665 + ((value >> 24) & 0xff); 1666 checksum &= 0xff; 1667 checksum = 0x100 - checksum; 1668 1669 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1670 1671 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); 1672 1673 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); 1674 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1675 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); 1676 1677 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1678 1679 out: 1680 of_node_put(np); 1681 } 1682 1683 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev) 1684 { 1685 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1686 1687 return pmc->soc->num_io_pads; 1688 } 1689 1690 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl, 1691 unsigned int group) 1692 { 1693 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); 1694 1695 return pmc->soc->io_pads[group].name; 1696 } 1697 1698 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev, 1699 unsigned int group, 1700 const unsigned int **pins, 1701 unsigned int *num_pins) 1702 { 1703 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1704 1705 *pins = &pmc->soc->io_pads[group].id; 1706 *num_pins = 1; 1707 1708 return 0; 1709 } 1710 1711 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = { 1712 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count, 1713 .get_group_name = tegra_io_pad_pinctrl_get_group_name, 1714 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins, 1715 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 1716 .dt_free_map = pinconf_generic_dt_free_map, 1717 }; 1718 1719 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev, 1720 unsigned int pin, unsigned long *config) 1721 { 1722 enum pin_config_param param = pinconf_to_config_param(*config); 1723 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1724 const struct tegra_io_pad_soc *pad; 1725 int ret; 1726 u32 arg; 1727 1728 pad = tegra_io_pad_find(pmc, pin); 1729 if (!pad) 1730 return -EINVAL; 1731 1732 switch (param) { 1733 case PIN_CONFIG_POWER_SOURCE: 1734 ret = tegra_io_pad_get_voltage(pmc, pad->id); 1735 if (ret < 0) 1736 return ret; 1737 1738 arg = ret; 1739 break; 1740 1741 case PIN_CONFIG_LOW_POWER_MODE: 1742 ret = tegra_io_pad_is_powered(pmc, pad->id); 1743 if (ret < 0) 1744 return ret; 1745 1746 arg = !ret; 1747 break; 1748 1749 default: 1750 return -EINVAL; 1751 } 1752 1753 *config = pinconf_to_config_packed(param, arg); 1754 1755 return 0; 1756 } 1757 1758 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev, 1759 unsigned int pin, unsigned long *configs, 1760 unsigned int num_configs) 1761 { 1762 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); 1763 const struct tegra_io_pad_soc *pad; 1764 enum pin_config_param param; 1765 unsigned int i; 1766 int err; 1767 u32 arg; 1768 1769 pad = tegra_io_pad_find(pmc, pin); 1770 if (!pad) 1771 return -EINVAL; 1772 1773 for (i = 0; i < num_configs; ++i) { 1774 param = pinconf_to_config_param(configs[i]); 1775 arg = pinconf_to_config_argument(configs[i]); 1776 1777 switch (param) { 1778 case PIN_CONFIG_LOW_POWER_MODE: 1779 if (arg) 1780 err = tegra_io_pad_power_disable(pad->id); 1781 else 1782 err = tegra_io_pad_power_enable(pad->id); 1783 if (err) 1784 return err; 1785 break; 1786 case PIN_CONFIG_POWER_SOURCE: 1787 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 && 1788 arg != TEGRA_IO_PAD_VOLTAGE_3V3) 1789 return -EINVAL; 1790 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); 1791 if (err) 1792 return err; 1793 break; 1794 default: 1795 return -EINVAL; 1796 } 1797 } 1798 1799 return 0; 1800 } 1801 1802 static const struct pinconf_ops tegra_io_pad_pinconf_ops = { 1803 .pin_config_get = tegra_io_pad_pinconf_get, 1804 .pin_config_set = tegra_io_pad_pinconf_set, 1805 .is_generic = true, 1806 }; 1807 1808 static struct pinctrl_desc tegra_pmc_pctl_desc = { 1809 .pctlops = &tegra_io_pad_pinctrl_ops, 1810 .confops = &tegra_io_pad_pinconf_ops, 1811 }; 1812 1813 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) 1814 { 1815 int err; 1816 1817 if (!pmc->soc->num_pin_descs) 1818 return 0; 1819 1820 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); 1821 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; 1822 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; 1823 1824 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, 1825 pmc); 1826 if (IS_ERR(pmc->pctl_dev)) { 1827 err = PTR_ERR(pmc->pctl_dev); 1828 dev_err(pmc->dev, "failed to register pin controller: %d\n", 1829 err); 1830 return err; 1831 } 1832 1833 return 0; 1834 } 1835 1836 static ssize_t reset_reason_show(struct device *dev, 1837 struct device_attribute *attr, char *buf) 1838 { 1839 u32 value; 1840 1841 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 1842 value &= pmc->soc->regs->rst_source_mask; 1843 value >>= pmc->soc->regs->rst_source_shift; 1844 1845 if (WARN_ON(value >= pmc->soc->num_reset_sources)) 1846 return sprintf(buf, "%s\n", "UNKNOWN"); 1847 1848 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); 1849 } 1850 1851 static DEVICE_ATTR_RO(reset_reason); 1852 1853 static ssize_t reset_level_show(struct device *dev, 1854 struct device_attribute *attr, char *buf) 1855 { 1856 u32 value; 1857 1858 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); 1859 value &= pmc->soc->regs->rst_level_mask; 1860 value >>= pmc->soc->regs->rst_level_shift; 1861 1862 if (WARN_ON(value >= pmc->soc->num_reset_levels)) 1863 return sprintf(buf, "%s\n", "UNKNOWN"); 1864 1865 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); 1866 } 1867 1868 static DEVICE_ATTR_RO(reset_level); 1869 1870 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) 1871 { 1872 struct device *dev = pmc->dev; 1873 int err = 0; 1874 1875 if (pmc->soc->reset_sources) { 1876 err = device_create_file(dev, &dev_attr_reset_reason); 1877 if (err < 0) 1878 dev_warn(dev, 1879 "failed to create attr \"reset_reason\": %d\n", 1880 err); 1881 } 1882 1883 if (pmc->soc->reset_levels) { 1884 err = device_create_file(dev, &dev_attr_reset_level); 1885 if (err < 0) 1886 dev_warn(dev, 1887 "failed to create attr \"reset_level\": %d\n", 1888 err); 1889 } 1890 } 1891 1892 static int tegra_pmc_irq_translate(struct irq_domain *domain, 1893 struct irq_fwspec *fwspec, 1894 unsigned long *hwirq, 1895 unsigned int *type) 1896 { 1897 if (WARN_ON(fwspec->param_count < 2)) 1898 return -EINVAL; 1899 1900 *hwirq = fwspec->param[0]; 1901 *type = fwspec->param[1]; 1902 1903 return 0; 1904 } 1905 1906 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq, 1907 unsigned int num_irqs, void *data) 1908 { 1909 struct tegra_pmc *pmc = domain->host_data; 1910 const struct tegra_pmc_soc *soc = pmc->soc; 1911 struct irq_fwspec *fwspec = data; 1912 unsigned int i; 1913 int err = 0; 1914 1915 if (WARN_ON(num_irqs > 1)) 1916 return -EINVAL; 1917 1918 for (i = 0; i < soc->num_wake_events; i++) { 1919 const struct tegra_wake_event *event = &soc->wake_events[i]; 1920 1921 if (fwspec->param_count == 2) { 1922 struct irq_fwspec spec; 1923 1924 if (event->id != fwspec->param[0]) 1925 continue; 1926 1927 err = irq_domain_set_hwirq_and_chip(domain, virq, 1928 event->id, 1929 &pmc->irq, pmc); 1930 if (err < 0) 1931 break; 1932 1933 spec.fwnode = &pmc->dev->of_node->fwnode; 1934 spec.param_count = 3; 1935 spec.param[0] = GIC_SPI; 1936 spec.param[1] = event->irq; 1937 spec.param[2] = fwspec->param[1]; 1938 1939 err = irq_domain_alloc_irqs_parent(domain, virq, 1940 num_irqs, &spec); 1941 1942 break; 1943 } 1944 1945 if (fwspec->param_count == 3) { 1946 if (event->gpio.instance != fwspec->param[0] || 1947 event->gpio.pin != fwspec->param[1]) 1948 continue; 1949 1950 err = irq_domain_set_hwirq_and_chip(domain, virq, 1951 event->id, 1952 &pmc->irq, pmc); 1953 1954 /* GPIO hierarchies stop at the PMC level */ 1955 if (!err && domain->parent) 1956 err = irq_domain_disconnect_hierarchy(domain->parent, 1957 virq); 1958 break; 1959 } 1960 } 1961 1962 /* If there is no wake-up event, there is no PMC mapping */ 1963 if (i == soc->num_wake_events) 1964 err = irq_domain_disconnect_hierarchy(domain, virq); 1965 1966 return err; 1967 } 1968 1969 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = { 1970 .translate = tegra_pmc_irq_translate, 1971 .alloc = tegra_pmc_irq_alloc, 1972 }; 1973 1974 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 1975 { 1976 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 1977 unsigned int offset, bit; 1978 u32 value; 1979 1980 offset = data->hwirq / 32; 1981 bit = data->hwirq % 32; 1982 1983 /* clear wake status */ 1984 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); 1985 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); 1986 1987 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); 1988 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); 1989 1990 /* enable PMC wake */ 1991 if (data->hwirq >= 32) 1992 offset = PMC_WAKE2_MASK; 1993 else 1994 offset = PMC_WAKE_MASK; 1995 1996 value = tegra_pmc_readl(pmc, offset); 1997 1998 if (on) 1999 value |= BIT(bit); 2000 else 2001 value &= ~BIT(bit); 2002 2003 tegra_pmc_writel(pmc, value, offset); 2004 2005 return 0; 2006 } 2007 2008 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2009 { 2010 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2011 unsigned int offset, bit; 2012 u32 value; 2013 2014 offset = data->hwirq / 32; 2015 bit = data->hwirq % 32; 2016 2017 if (data->hwirq >= 32) 2018 offset = PMC_WAKE2_LEVEL; 2019 else 2020 offset = PMC_WAKE_LEVEL; 2021 2022 value = tegra_pmc_readl(pmc, offset); 2023 2024 switch (type) { 2025 case IRQ_TYPE_EDGE_RISING: 2026 case IRQ_TYPE_LEVEL_HIGH: 2027 value |= BIT(bit); 2028 break; 2029 2030 case IRQ_TYPE_EDGE_FALLING: 2031 case IRQ_TYPE_LEVEL_LOW: 2032 value &= ~BIT(bit); 2033 break; 2034 2035 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2036 value ^= BIT(bit); 2037 break; 2038 2039 default: 2040 return -EINVAL; 2041 } 2042 2043 tegra_pmc_writel(pmc, value, offset); 2044 2045 return 0; 2046 } 2047 2048 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) 2049 { 2050 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2051 unsigned int offset, bit; 2052 u32 value; 2053 2054 offset = data->hwirq / 32; 2055 bit = data->hwirq % 32; 2056 2057 /* clear wake status */ 2058 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); 2059 2060 /* route wake to tier 2 */ 2061 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2062 2063 if (!on) 2064 value &= ~(1 << bit); 2065 else 2066 value |= 1 << bit; 2067 2068 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); 2069 2070 /* enable wakeup event */ 2071 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); 2072 2073 return 0; 2074 } 2075 2076 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type) 2077 { 2078 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); 2079 u32 value; 2080 2081 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2082 2083 switch (type) { 2084 case IRQ_TYPE_EDGE_RISING: 2085 case IRQ_TYPE_LEVEL_HIGH: 2086 value |= WAKE_AOWAKE_CNTRL_LEVEL; 2087 break; 2088 2089 case IRQ_TYPE_EDGE_FALLING: 2090 case IRQ_TYPE_LEVEL_LOW: 2091 value &= ~WAKE_AOWAKE_CNTRL_LEVEL; 2092 break; 2093 2094 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING: 2095 value ^= WAKE_AOWAKE_CNTRL_LEVEL; 2096 break; 2097 2098 default: 2099 return -EINVAL; 2100 } 2101 2102 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); 2103 2104 return 0; 2105 } 2106 2107 static void tegra_irq_mask_parent(struct irq_data *data) 2108 { 2109 if (data->parent_data) 2110 irq_chip_mask_parent(data); 2111 } 2112 2113 static void tegra_irq_unmask_parent(struct irq_data *data) 2114 { 2115 if (data->parent_data) 2116 irq_chip_unmask_parent(data); 2117 } 2118 2119 static void tegra_irq_eoi_parent(struct irq_data *data) 2120 { 2121 if (data->parent_data) 2122 irq_chip_eoi_parent(data); 2123 } 2124 2125 static int tegra_irq_set_affinity_parent(struct irq_data *data, 2126 const struct cpumask *dest, 2127 bool force) 2128 { 2129 if (data->parent_data) 2130 return irq_chip_set_affinity_parent(data, dest, force); 2131 2132 return -EINVAL; 2133 } 2134 2135 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) 2136 { 2137 struct irq_domain *parent = NULL; 2138 struct device_node *np; 2139 2140 np = of_irq_find_parent(pmc->dev->of_node); 2141 if (np) { 2142 parent = irq_find_host(np); 2143 of_node_put(np); 2144 } 2145 2146 if (!parent) 2147 return 0; 2148 2149 pmc->irq.name = dev_name(pmc->dev); 2150 pmc->irq.irq_mask = tegra_irq_mask_parent; 2151 pmc->irq.irq_unmask = tegra_irq_unmask_parent; 2152 pmc->irq.irq_eoi = tegra_irq_eoi_parent; 2153 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; 2154 pmc->irq.irq_set_type = pmc->soc->irq_set_type; 2155 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; 2156 2157 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, 2158 &tegra_pmc_irq_domain_ops, pmc); 2159 if (!pmc->domain) { 2160 dev_err(pmc->dev, "failed to allocate domain\n"); 2161 return -ENOMEM; 2162 } 2163 2164 return 0; 2165 } 2166 2167 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb, 2168 unsigned long action, void *ptr) 2169 { 2170 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); 2171 struct clk_notifier_data *data = ptr; 2172 2173 switch (action) { 2174 case PRE_RATE_CHANGE: 2175 mutex_lock(&pmc->powergates_lock); 2176 break; 2177 2178 case POST_RATE_CHANGE: 2179 pmc->rate = data->new_rate; 2180 fallthrough; 2181 2182 case ABORT_RATE_CHANGE: 2183 mutex_unlock(&pmc->powergates_lock); 2184 break; 2185 2186 default: 2187 WARN_ON_ONCE(1); 2188 return notifier_from_errno(-EINVAL); 2189 } 2190 2191 return NOTIFY_OK; 2192 } 2193 2194 static void pmc_clk_fence_udelay(u32 offset) 2195 { 2196 tegra_pmc_readl(pmc, offset); 2197 /* pmc clk propagation delay 2 us */ 2198 udelay(2); 2199 } 2200 2201 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw) 2202 { 2203 struct pmc_clk *clk = to_pmc_clk(hw); 2204 u32 val; 2205 2206 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; 2207 val &= PMC_CLK_OUT_MUX_MASK; 2208 2209 return val; 2210 } 2211 2212 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index) 2213 { 2214 struct pmc_clk *clk = to_pmc_clk(hw); 2215 u32 val; 2216 2217 val = tegra_pmc_readl(pmc, clk->offs); 2218 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); 2219 val |= index << clk->mux_shift; 2220 tegra_pmc_writel(pmc, val, clk->offs); 2221 pmc_clk_fence_udelay(clk->offs); 2222 2223 return 0; 2224 } 2225 2226 static int pmc_clk_is_enabled(struct clk_hw *hw) 2227 { 2228 struct pmc_clk *clk = to_pmc_clk(hw); 2229 u32 val; 2230 2231 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); 2232 2233 return val ? 1 : 0; 2234 } 2235 2236 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state) 2237 { 2238 u32 val; 2239 2240 val = tegra_pmc_readl(pmc, offs); 2241 val = state ? (val | BIT(shift)) : (val & ~BIT(shift)); 2242 tegra_pmc_writel(pmc, val, offs); 2243 pmc_clk_fence_udelay(offs); 2244 } 2245 2246 static int pmc_clk_enable(struct clk_hw *hw) 2247 { 2248 struct pmc_clk *clk = to_pmc_clk(hw); 2249 2250 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); 2251 2252 return 0; 2253 } 2254 2255 static void pmc_clk_disable(struct clk_hw *hw) 2256 { 2257 struct pmc_clk *clk = to_pmc_clk(hw); 2258 2259 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); 2260 } 2261 2262 static const struct clk_ops pmc_clk_ops = { 2263 .get_parent = pmc_clk_mux_get_parent, 2264 .set_parent = pmc_clk_mux_set_parent, 2265 .determine_rate = __clk_mux_determine_rate, 2266 .is_enabled = pmc_clk_is_enabled, 2267 .enable = pmc_clk_enable, 2268 .disable = pmc_clk_disable, 2269 }; 2270 2271 static struct clk * 2272 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, 2273 const struct pmc_clk_init_data *data, 2274 unsigned long offset) 2275 { 2276 struct clk_init_data init; 2277 struct pmc_clk *pmc_clk; 2278 2279 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); 2280 if (!pmc_clk) 2281 return ERR_PTR(-ENOMEM); 2282 2283 init.name = data->name; 2284 init.ops = &pmc_clk_ops; 2285 init.parent_names = data->parents; 2286 init.num_parents = data->num_parents; 2287 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | 2288 CLK_SET_PARENT_GATE; 2289 2290 pmc_clk->hw.init = &init; 2291 pmc_clk->offs = offset; 2292 pmc_clk->mux_shift = data->mux_shift; 2293 pmc_clk->force_en_shift = data->force_en_shift; 2294 2295 return clk_register(NULL, &pmc_clk->hw); 2296 } 2297 2298 static int pmc_clk_gate_is_enabled(struct clk_hw *hw) 2299 { 2300 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2301 2302 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; 2303 } 2304 2305 static int pmc_clk_gate_enable(struct clk_hw *hw) 2306 { 2307 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2308 2309 pmc_clk_set_state(gate->offs, gate->shift, 1); 2310 2311 return 0; 2312 } 2313 2314 static void pmc_clk_gate_disable(struct clk_hw *hw) 2315 { 2316 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw); 2317 2318 pmc_clk_set_state(gate->offs, gate->shift, 0); 2319 } 2320 2321 static const struct clk_ops pmc_clk_gate_ops = { 2322 .is_enabled = pmc_clk_gate_is_enabled, 2323 .enable = pmc_clk_gate_enable, 2324 .disable = pmc_clk_gate_disable, 2325 }; 2326 2327 static struct clk * 2328 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, 2329 const char *parent_name, unsigned long offset, 2330 u32 shift) 2331 { 2332 struct clk_init_data init; 2333 struct pmc_clk_gate *gate; 2334 2335 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); 2336 if (!gate) 2337 return ERR_PTR(-ENOMEM); 2338 2339 init.name = name; 2340 init.ops = &pmc_clk_gate_ops; 2341 init.parent_names = &parent_name; 2342 init.num_parents = 1; 2343 init.flags = 0; 2344 2345 gate->hw.init = &init; 2346 gate->offs = offset; 2347 gate->shift = shift; 2348 2349 return clk_register(NULL, &gate->hw); 2350 } 2351 2352 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, 2353 struct device_node *np) 2354 { 2355 struct clk *clk; 2356 struct clk_onecell_data *clk_data; 2357 unsigned int num_clks; 2358 int i, err; 2359 2360 num_clks = pmc->soc->num_pmc_clks; 2361 if (pmc->soc->has_blink_output) 2362 num_clks += 1; 2363 2364 if (!num_clks) 2365 return; 2366 2367 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); 2368 if (!clk_data) 2369 return; 2370 2371 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, 2372 sizeof(*clk_data->clks), GFP_KERNEL); 2373 if (!clk_data->clks) 2374 return; 2375 2376 clk_data->clk_num = TEGRA_PMC_CLK_MAX; 2377 2378 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) 2379 clk_data->clks[i] = ERR_PTR(-ENOENT); 2380 2381 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { 2382 const struct pmc_clk_init_data *data; 2383 2384 data = pmc->soc->pmc_clks_data + i; 2385 2386 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); 2387 if (IS_ERR(clk)) { 2388 dev_warn(pmc->dev, "unable to register clock %s: %d\n", 2389 data->name, PTR_ERR_OR_ZERO(clk)); 2390 return; 2391 } 2392 2393 err = clk_register_clkdev(clk, data->name, NULL); 2394 if (err) { 2395 dev_warn(pmc->dev, 2396 "unable to register %s clock lookup: %d\n", 2397 data->name, err); 2398 return; 2399 } 2400 2401 clk_data->clks[data->clk_id] = clk; 2402 } 2403 2404 if (pmc->soc->has_blink_output) { 2405 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); 2406 clk = tegra_pmc_clk_gate_register(pmc, 2407 "pmc_blink_override", 2408 "clk_32k", 2409 PMC_DPD_PADS_ORIDE, 2410 PMC_DPD_PADS_ORIDE_BLINK); 2411 if (IS_ERR(clk)) { 2412 dev_warn(pmc->dev, 2413 "unable to register pmc_blink_override: %d\n", 2414 PTR_ERR_OR_ZERO(clk)); 2415 return; 2416 } 2417 2418 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", 2419 "pmc_blink_override", 2420 PMC_CNTRL, 2421 PMC_CNTRL_BLINK_EN); 2422 if (IS_ERR(clk)) { 2423 dev_warn(pmc->dev, 2424 "unable to register pmc_blink: %d\n", 2425 PTR_ERR_OR_ZERO(clk)); 2426 return; 2427 } 2428 2429 err = clk_register_clkdev(clk, "pmc_blink", NULL); 2430 if (err) { 2431 dev_warn(pmc->dev, 2432 "unable to register pmc_blink lookup: %d\n", 2433 err); 2434 return; 2435 } 2436 2437 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; 2438 } 2439 2440 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 2441 if (err) 2442 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", 2443 err); 2444 } 2445 2446 static int tegra_pmc_probe(struct platform_device *pdev) 2447 { 2448 void __iomem *base; 2449 struct resource *res; 2450 int err; 2451 2452 /* 2453 * Early initialisation should have configured an initial 2454 * register mapping and setup the soc data pointer. If these 2455 * are not valid then something went badly wrong! 2456 */ 2457 if (WARN_ON(!pmc->base || !pmc->soc)) 2458 return -ENODEV; 2459 2460 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 2461 if (err < 0) 2462 return err; 2463 2464 /* take over the memory region from the early initialization */ 2465 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2466 base = devm_ioremap_resource(&pdev->dev, res); 2467 if (IS_ERR(base)) 2468 return PTR_ERR(base); 2469 2470 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 2471 if (res) { 2472 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 2473 if (IS_ERR(pmc->wake)) 2474 return PTR_ERR(pmc->wake); 2475 } else { 2476 pmc->wake = base; 2477 } 2478 2479 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 2480 if (res) { 2481 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 2482 if (IS_ERR(pmc->aotag)) 2483 return PTR_ERR(pmc->aotag); 2484 } else { 2485 pmc->aotag = base; 2486 } 2487 2488 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 2489 if (res) { 2490 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 2491 if (IS_ERR(pmc->scratch)) 2492 return PTR_ERR(pmc->scratch); 2493 } else { 2494 pmc->scratch = base; 2495 } 2496 2497 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 2498 if (IS_ERR(pmc->clk)) { 2499 err = PTR_ERR(pmc->clk); 2500 2501 if (err != -ENOENT) { 2502 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 2503 return err; 2504 } 2505 2506 pmc->clk = NULL; 2507 } 2508 2509 /* 2510 * PCLK clock rate can't be retrieved using CLK API because it 2511 * causes lockup if CPU enters LP2 idle state from some other 2512 * CLK notifier, hence we're caching the rate's value locally. 2513 */ 2514 if (pmc->clk) { 2515 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; 2516 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); 2517 if (err) { 2518 dev_err(&pdev->dev, 2519 "failed to register clk notifier\n"); 2520 return err; 2521 } 2522 2523 pmc->rate = clk_get_rate(pmc->clk); 2524 } 2525 2526 pmc->dev = &pdev->dev; 2527 2528 tegra_pmc_init(pmc); 2529 2530 tegra_pmc_init_tsense_reset(pmc); 2531 2532 tegra_pmc_reset_sysfs_init(pmc); 2533 2534 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 2535 err = tegra_powergate_debugfs_init(); 2536 if (err < 0) 2537 goto cleanup_sysfs; 2538 } 2539 2540 err = register_restart_handler(&tegra_pmc_restart_handler); 2541 if (err) { 2542 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 2543 err); 2544 goto cleanup_debugfs; 2545 } 2546 2547 err = tegra_pmc_pinctrl_init(pmc); 2548 if (err) 2549 goto cleanup_restart_handler; 2550 2551 err = tegra_powergate_init(pmc, pdev->dev.of_node); 2552 if (err < 0) 2553 goto cleanup_powergates; 2554 2555 err = tegra_pmc_irq_init(pmc); 2556 if (err < 0) 2557 goto cleanup_powergates; 2558 2559 mutex_lock(&pmc->powergates_lock); 2560 iounmap(pmc->base); 2561 pmc->base = base; 2562 mutex_unlock(&pmc->powergates_lock); 2563 2564 tegra_pmc_clock_register(pmc, pdev->dev.of_node); 2565 platform_set_drvdata(pdev, pmc); 2566 2567 return 0; 2568 2569 cleanup_powergates: 2570 tegra_powergate_remove_all(pdev->dev.of_node); 2571 cleanup_restart_handler: 2572 unregister_restart_handler(&tegra_pmc_restart_handler); 2573 cleanup_debugfs: 2574 debugfs_remove(pmc->debugfs); 2575 cleanup_sysfs: 2576 device_remove_file(&pdev->dev, &dev_attr_reset_reason); 2577 device_remove_file(&pdev->dev, &dev_attr_reset_level); 2578 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); 2579 2580 return err; 2581 } 2582 2583 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 2584 static int tegra_pmc_suspend(struct device *dev) 2585 { 2586 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2587 2588 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); 2589 2590 return 0; 2591 } 2592 2593 static int tegra_pmc_resume(struct device *dev) 2594 { 2595 struct tegra_pmc *pmc = dev_get_drvdata(dev); 2596 2597 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); 2598 2599 return 0; 2600 } 2601 2602 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 2603 2604 #endif 2605 2606 static const char * const tegra20_powergates[] = { 2607 [TEGRA_POWERGATE_CPU] = "cpu", 2608 [TEGRA_POWERGATE_3D] = "3d", 2609 [TEGRA_POWERGATE_VENC] = "venc", 2610 [TEGRA_POWERGATE_VDEC] = "vdec", 2611 [TEGRA_POWERGATE_PCIE] = "pcie", 2612 [TEGRA_POWERGATE_L2] = "l2", 2613 [TEGRA_POWERGATE_MPE] = "mpe", 2614 }; 2615 2616 static const struct tegra_pmc_regs tegra20_pmc_regs = { 2617 .scratch0 = 0x50, 2618 .dpd_req = 0x1b8, 2619 .dpd_status = 0x1bc, 2620 .dpd2_req = 0x1c0, 2621 .dpd2_status = 0x1c4, 2622 .rst_status = 0x1b4, 2623 .rst_source_shift = 0x0, 2624 .rst_source_mask = 0x7, 2625 .rst_level_shift = 0x0, 2626 .rst_level_mask = 0x0, 2627 }; 2628 2629 static void tegra20_pmc_init(struct tegra_pmc *pmc) 2630 { 2631 u32 value, osc, pmu, off; 2632 2633 /* Always enable CPU power request */ 2634 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2635 value |= PMC_CNTRL_CPU_PWRREQ_OE; 2636 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2637 2638 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2639 2640 if (pmc->sysclkreq_high) 2641 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 2642 else 2643 value |= PMC_CNTRL_SYSCLK_POLARITY; 2644 2645 if (pmc->corereq_high) 2646 value &= ~PMC_CNTRL_PWRREQ_POLARITY; 2647 else 2648 value |= PMC_CNTRL_PWRREQ_POLARITY; 2649 2650 /* configure the output polarity while the request is tristated */ 2651 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2652 2653 /* now enable the request */ 2654 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2655 value |= PMC_CNTRL_SYSCLK_OE; 2656 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2657 2658 /* program core timings which are applicable only for suspend state */ 2659 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { 2660 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); 2661 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); 2662 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); 2663 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), 2664 PMC_COREPWRGOOD_TIMER); 2665 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); 2666 } 2667 } 2668 2669 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 2670 struct device_node *np, 2671 bool invert) 2672 { 2673 u32 value; 2674 2675 value = tegra_pmc_readl(pmc, PMC_CNTRL); 2676 2677 if (invert) 2678 value |= PMC_CNTRL_INTR_POLARITY; 2679 else 2680 value &= ~PMC_CNTRL_INTR_POLARITY; 2681 2682 tegra_pmc_writel(pmc, value, PMC_CNTRL); 2683 } 2684 2685 static const struct tegra_pmc_soc tegra20_pmc_soc = { 2686 .num_powergates = ARRAY_SIZE(tegra20_powergates), 2687 .powergates = tegra20_powergates, 2688 .num_cpu_powergates = 0, 2689 .cpu_powergates = NULL, 2690 .has_tsense_reset = false, 2691 .has_gpu_clamps = false, 2692 .needs_mbist_war = false, 2693 .has_impl_33v_pwr = false, 2694 .maybe_tz_only = false, 2695 .num_io_pads = 0, 2696 .io_pads = NULL, 2697 .num_pin_descs = 0, 2698 .pin_descs = NULL, 2699 .regs = &tegra20_pmc_regs, 2700 .init = tegra20_pmc_init, 2701 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2702 .reset_sources = NULL, 2703 .num_reset_sources = 0, 2704 .reset_levels = NULL, 2705 .num_reset_levels = 0, 2706 .pmc_clks_data = NULL, 2707 .num_pmc_clks = 0, 2708 .has_blink_output = true, 2709 }; 2710 2711 static const char * const tegra30_powergates[] = { 2712 [TEGRA_POWERGATE_CPU] = "cpu0", 2713 [TEGRA_POWERGATE_3D] = "3d0", 2714 [TEGRA_POWERGATE_VENC] = "venc", 2715 [TEGRA_POWERGATE_VDEC] = "vdec", 2716 [TEGRA_POWERGATE_PCIE] = "pcie", 2717 [TEGRA_POWERGATE_L2] = "l2", 2718 [TEGRA_POWERGATE_MPE] = "mpe", 2719 [TEGRA_POWERGATE_HEG] = "heg", 2720 [TEGRA_POWERGATE_SATA] = "sata", 2721 [TEGRA_POWERGATE_CPU1] = "cpu1", 2722 [TEGRA_POWERGATE_CPU2] = "cpu2", 2723 [TEGRA_POWERGATE_CPU3] = "cpu3", 2724 [TEGRA_POWERGATE_CELP] = "celp", 2725 [TEGRA_POWERGATE_3D1] = "3d1", 2726 }; 2727 2728 static const u8 tegra30_cpu_powergates[] = { 2729 TEGRA_POWERGATE_CPU, 2730 TEGRA_POWERGATE_CPU1, 2731 TEGRA_POWERGATE_CPU2, 2732 TEGRA_POWERGATE_CPU3, 2733 }; 2734 2735 static const char * const tegra30_reset_sources[] = { 2736 "POWER_ON_RESET", 2737 "WATCHDOG", 2738 "SENSOR", 2739 "SW_MAIN", 2740 "LP0" 2741 }; 2742 2743 static const struct tegra_pmc_soc tegra30_pmc_soc = { 2744 .num_powergates = ARRAY_SIZE(tegra30_powergates), 2745 .powergates = tegra30_powergates, 2746 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 2747 .cpu_powergates = tegra30_cpu_powergates, 2748 .has_tsense_reset = true, 2749 .has_gpu_clamps = false, 2750 .needs_mbist_war = false, 2751 .has_impl_33v_pwr = false, 2752 .maybe_tz_only = false, 2753 .num_io_pads = 0, 2754 .io_pads = NULL, 2755 .num_pin_descs = 0, 2756 .pin_descs = NULL, 2757 .regs = &tegra20_pmc_regs, 2758 .init = tegra20_pmc_init, 2759 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2760 .reset_sources = tegra30_reset_sources, 2761 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 2762 .reset_levels = NULL, 2763 .num_reset_levels = 0, 2764 .pmc_clks_data = tegra_pmc_clks_data, 2765 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 2766 .has_blink_output = true, 2767 }; 2768 2769 static const char * const tegra114_powergates[] = { 2770 [TEGRA_POWERGATE_CPU] = "crail", 2771 [TEGRA_POWERGATE_3D] = "3d", 2772 [TEGRA_POWERGATE_VENC] = "venc", 2773 [TEGRA_POWERGATE_VDEC] = "vdec", 2774 [TEGRA_POWERGATE_MPE] = "mpe", 2775 [TEGRA_POWERGATE_HEG] = "heg", 2776 [TEGRA_POWERGATE_CPU1] = "cpu1", 2777 [TEGRA_POWERGATE_CPU2] = "cpu2", 2778 [TEGRA_POWERGATE_CPU3] = "cpu3", 2779 [TEGRA_POWERGATE_CELP] = "celp", 2780 [TEGRA_POWERGATE_CPU0] = "cpu0", 2781 [TEGRA_POWERGATE_C0NC] = "c0nc", 2782 [TEGRA_POWERGATE_C1NC] = "c1nc", 2783 [TEGRA_POWERGATE_DIS] = "dis", 2784 [TEGRA_POWERGATE_DISB] = "disb", 2785 [TEGRA_POWERGATE_XUSBA] = "xusba", 2786 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2787 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2788 }; 2789 2790 static const u8 tegra114_cpu_powergates[] = { 2791 TEGRA_POWERGATE_CPU0, 2792 TEGRA_POWERGATE_CPU1, 2793 TEGRA_POWERGATE_CPU2, 2794 TEGRA_POWERGATE_CPU3, 2795 }; 2796 2797 static const struct tegra_pmc_soc tegra114_pmc_soc = { 2798 .num_powergates = ARRAY_SIZE(tegra114_powergates), 2799 .powergates = tegra114_powergates, 2800 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 2801 .cpu_powergates = tegra114_cpu_powergates, 2802 .has_tsense_reset = true, 2803 .has_gpu_clamps = false, 2804 .needs_mbist_war = false, 2805 .has_impl_33v_pwr = false, 2806 .maybe_tz_only = false, 2807 .num_io_pads = 0, 2808 .io_pads = NULL, 2809 .num_pin_descs = 0, 2810 .pin_descs = NULL, 2811 .regs = &tegra20_pmc_regs, 2812 .init = tegra20_pmc_init, 2813 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2814 .reset_sources = tegra30_reset_sources, 2815 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 2816 .reset_levels = NULL, 2817 .num_reset_levels = 0, 2818 .pmc_clks_data = tegra_pmc_clks_data, 2819 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 2820 .has_blink_output = true, 2821 }; 2822 2823 static const char * const tegra124_powergates[] = { 2824 [TEGRA_POWERGATE_CPU] = "crail", 2825 [TEGRA_POWERGATE_3D] = "3d", 2826 [TEGRA_POWERGATE_VENC] = "venc", 2827 [TEGRA_POWERGATE_PCIE] = "pcie", 2828 [TEGRA_POWERGATE_VDEC] = "vdec", 2829 [TEGRA_POWERGATE_MPE] = "mpe", 2830 [TEGRA_POWERGATE_HEG] = "heg", 2831 [TEGRA_POWERGATE_SATA] = "sata", 2832 [TEGRA_POWERGATE_CPU1] = "cpu1", 2833 [TEGRA_POWERGATE_CPU2] = "cpu2", 2834 [TEGRA_POWERGATE_CPU3] = "cpu3", 2835 [TEGRA_POWERGATE_CELP] = "celp", 2836 [TEGRA_POWERGATE_CPU0] = "cpu0", 2837 [TEGRA_POWERGATE_C0NC] = "c0nc", 2838 [TEGRA_POWERGATE_C1NC] = "c1nc", 2839 [TEGRA_POWERGATE_SOR] = "sor", 2840 [TEGRA_POWERGATE_DIS] = "dis", 2841 [TEGRA_POWERGATE_DISB] = "disb", 2842 [TEGRA_POWERGATE_XUSBA] = "xusba", 2843 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2844 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2845 [TEGRA_POWERGATE_VIC] = "vic", 2846 [TEGRA_POWERGATE_IRAM] = "iram", 2847 }; 2848 2849 static const u8 tegra124_cpu_powergates[] = { 2850 TEGRA_POWERGATE_CPU0, 2851 TEGRA_POWERGATE_CPU1, 2852 TEGRA_POWERGATE_CPU2, 2853 TEGRA_POWERGATE_CPU3, 2854 }; 2855 2856 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \ 2857 ((struct tegra_io_pad_soc) { \ 2858 .id = (_id), \ 2859 .dpd = (_dpd), \ 2860 .voltage = (_voltage), \ 2861 .name = (_name), \ 2862 }) 2863 2864 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \ 2865 ((struct pinctrl_pin_desc) { \ 2866 .number = (_id), \ 2867 .name = (_name) \ 2868 }) 2869 2870 #define TEGRA124_IO_PAD_TABLE(_pad) \ 2871 /* .id .dpd .voltage .name */ \ 2872 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 2873 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \ 2874 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \ 2875 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \ 2876 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2877 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \ 2878 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \ 2879 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2880 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 2881 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 2882 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 2883 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 2884 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2885 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \ 2886 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 2887 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2888 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \ 2889 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 2890 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 2891 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 2892 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 2893 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \ 2894 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \ 2895 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \ 2896 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \ 2897 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 2898 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 2899 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 2900 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 2901 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias") 2902 2903 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 2904 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD) 2905 }; 2906 2907 static const struct pinctrl_pin_desc tegra124_pin_descs[] = { 2908 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 2909 }; 2910 2911 static const struct tegra_pmc_soc tegra124_pmc_soc = { 2912 .num_powergates = ARRAY_SIZE(tegra124_powergates), 2913 .powergates = tegra124_powergates, 2914 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 2915 .cpu_powergates = tegra124_cpu_powergates, 2916 .has_tsense_reset = true, 2917 .has_gpu_clamps = true, 2918 .needs_mbist_war = false, 2919 .has_impl_33v_pwr = false, 2920 .maybe_tz_only = false, 2921 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 2922 .io_pads = tegra124_io_pads, 2923 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs), 2924 .pin_descs = tegra124_pin_descs, 2925 .regs = &tegra20_pmc_regs, 2926 .init = tegra20_pmc_init, 2927 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 2928 .reset_sources = tegra30_reset_sources, 2929 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources), 2930 .reset_levels = NULL, 2931 .num_reset_levels = 0, 2932 .pmc_clks_data = tegra_pmc_clks_data, 2933 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 2934 .has_blink_output = true, 2935 }; 2936 2937 static const char * const tegra210_powergates[] = { 2938 [TEGRA_POWERGATE_CPU] = "crail", 2939 [TEGRA_POWERGATE_3D] = "3d", 2940 [TEGRA_POWERGATE_VENC] = "venc", 2941 [TEGRA_POWERGATE_PCIE] = "pcie", 2942 [TEGRA_POWERGATE_MPE] = "mpe", 2943 [TEGRA_POWERGATE_SATA] = "sata", 2944 [TEGRA_POWERGATE_CPU1] = "cpu1", 2945 [TEGRA_POWERGATE_CPU2] = "cpu2", 2946 [TEGRA_POWERGATE_CPU3] = "cpu3", 2947 [TEGRA_POWERGATE_CPU0] = "cpu0", 2948 [TEGRA_POWERGATE_C0NC] = "c0nc", 2949 [TEGRA_POWERGATE_SOR] = "sor", 2950 [TEGRA_POWERGATE_DIS] = "dis", 2951 [TEGRA_POWERGATE_DISB] = "disb", 2952 [TEGRA_POWERGATE_XUSBA] = "xusba", 2953 [TEGRA_POWERGATE_XUSBB] = "xusbb", 2954 [TEGRA_POWERGATE_XUSBC] = "xusbc", 2955 [TEGRA_POWERGATE_VIC] = "vic", 2956 [TEGRA_POWERGATE_IRAM] = "iram", 2957 [TEGRA_POWERGATE_NVDEC] = "nvdec", 2958 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 2959 [TEGRA_POWERGATE_AUD] = "aud", 2960 [TEGRA_POWERGATE_DFD] = "dfd", 2961 [TEGRA_POWERGATE_VE2] = "ve2", 2962 }; 2963 2964 static const u8 tegra210_cpu_powergates[] = { 2965 TEGRA_POWERGATE_CPU0, 2966 TEGRA_POWERGATE_CPU1, 2967 TEGRA_POWERGATE_CPU2, 2968 TEGRA_POWERGATE_CPU3, 2969 }; 2970 2971 #define TEGRA210_IO_PAD_TABLE(_pad) \ 2972 /* .id .dpd .voltage .name */ \ 2973 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \ 2974 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \ 2975 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \ 2976 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 2977 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 2978 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \ 2979 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \ 2980 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \ 2981 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \ 2982 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \ 2983 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \ 2984 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \ 2985 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \ 2986 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 2987 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \ 2988 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \ 2989 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \ 2990 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \ 2991 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \ 2992 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \ 2993 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \ 2994 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 2995 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \ 2996 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 2997 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \ 2998 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \ 2999 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3000 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \ 3001 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \ 3002 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \ 3003 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \ 3004 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \ 3005 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \ 3006 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3007 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3008 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3009 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \ 3010 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias") 3011 3012 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 3013 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD) 3014 }; 3015 3016 static const struct pinctrl_pin_desc tegra210_pin_descs[] = { 3017 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3018 }; 3019 3020 static const char * const tegra210_reset_sources[] = { 3021 "POWER_ON_RESET", 3022 "WATCHDOG", 3023 "SENSOR", 3024 "SW_MAIN", 3025 "LP0", 3026 "AOTAG" 3027 }; 3028 3029 static const struct tegra_wake_event tegra210_wake_events[] = { 3030 TEGRA_WAKE_IRQ("rtc", 16, 2), 3031 TEGRA_WAKE_IRQ("pmu", 51, 86), 3032 }; 3033 3034 static const struct tegra_pmc_soc tegra210_pmc_soc = { 3035 .num_powergates = ARRAY_SIZE(tegra210_powergates), 3036 .powergates = tegra210_powergates, 3037 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 3038 .cpu_powergates = tegra210_cpu_powergates, 3039 .has_tsense_reset = true, 3040 .has_gpu_clamps = true, 3041 .needs_mbist_war = true, 3042 .has_impl_33v_pwr = false, 3043 .maybe_tz_only = true, 3044 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 3045 .io_pads = tegra210_io_pads, 3046 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs), 3047 .pin_descs = tegra210_pin_descs, 3048 .regs = &tegra20_pmc_regs, 3049 .init = tegra20_pmc_init, 3050 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 3051 .irq_set_wake = tegra210_pmc_irq_set_wake, 3052 .irq_set_type = tegra210_pmc_irq_set_type, 3053 .reset_sources = tegra210_reset_sources, 3054 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources), 3055 .reset_levels = NULL, 3056 .num_reset_levels = 0, 3057 .num_wake_events = ARRAY_SIZE(tegra210_wake_events), 3058 .wake_events = tegra210_wake_events, 3059 .pmc_clks_data = tegra_pmc_clks_data, 3060 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), 3061 .has_blink_output = true, 3062 }; 3063 3064 #define TEGRA186_IO_PAD_TABLE(_pad) \ 3065 /* .id .dpd .voltage .name */ \ 3066 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3067 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3068 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \ 3069 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3070 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3071 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3072 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3073 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3074 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \ 3075 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \ 3076 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \ 3077 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \ 3078 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3079 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3080 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \ 3081 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3082 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3083 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3084 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3085 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \ 3086 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3087 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3088 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \ 3089 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \ 3090 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \ 3091 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3092 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3093 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3094 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3095 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3096 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3097 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \ 3098 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3099 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3100 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3101 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3102 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3103 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3104 3105 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 3106 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD) 3107 }; 3108 3109 static const struct pinctrl_pin_desc tegra186_pin_descs[] = { 3110 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3111 }; 3112 3113 static const struct tegra_pmc_regs tegra186_pmc_regs = { 3114 .scratch0 = 0x2000, 3115 .dpd_req = 0x74, 3116 .dpd_status = 0x78, 3117 .dpd2_req = 0x7c, 3118 .dpd2_status = 0x80, 3119 .rst_status = 0x70, 3120 .rst_source_shift = 0x2, 3121 .rst_source_mask = 0x3c, 3122 .rst_level_shift = 0x0, 3123 .rst_level_mask = 0x3, 3124 }; 3125 3126 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 3127 struct device_node *np, 3128 bool invert) 3129 { 3130 struct resource regs; 3131 void __iomem *wake; 3132 u32 value; 3133 int index; 3134 3135 index = of_property_match_string(np, "reg-names", "wake"); 3136 if (index < 0) { 3137 dev_err(pmc->dev, "failed to find PMC wake registers\n"); 3138 return; 3139 } 3140 3141 of_address_to_resource(np, index, ®s); 3142 3143 wake = ioremap(regs.start, resource_size(®s)); 3144 if (!wake) { 3145 dev_err(pmc->dev, "failed to map PMC wake registers\n"); 3146 return; 3147 } 3148 3149 value = readl(wake + WAKE_AOWAKE_CTRL); 3150 3151 if (invert) 3152 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 3153 else 3154 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 3155 3156 writel(value, wake + WAKE_AOWAKE_CTRL); 3157 3158 iounmap(wake); 3159 } 3160 3161 static const char * const tegra186_reset_sources[] = { 3162 "SYS_RESET", 3163 "AOWDT", 3164 "MCCPLEXWDT", 3165 "BPMPWDT", 3166 "SCEWDT", 3167 "SPEWDT", 3168 "APEWDT", 3169 "BCCPLEXWDT", 3170 "SENSOR", 3171 "AOTAG", 3172 "VFSENSOR", 3173 "SWREST", 3174 "SC7", 3175 "HSM", 3176 "CORESIGHT" 3177 }; 3178 3179 static const char * const tegra186_reset_levels[] = { 3180 "L0", "L1", "L2", "WARM" 3181 }; 3182 3183 static const struct tegra_wake_event tegra186_wake_events[] = { 3184 TEGRA_WAKE_IRQ("pmu", 24, 209), 3185 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)), 3186 TEGRA_WAKE_IRQ("rtc", 73, 10), 3187 }; 3188 3189 static const struct tegra_pmc_soc tegra186_pmc_soc = { 3190 .num_powergates = 0, 3191 .powergates = NULL, 3192 .num_cpu_powergates = 0, 3193 .cpu_powergates = NULL, 3194 .has_tsense_reset = false, 3195 .has_gpu_clamps = false, 3196 .needs_mbist_war = false, 3197 .has_impl_33v_pwr = true, 3198 .maybe_tz_only = false, 3199 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 3200 .io_pads = tegra186_io_pads, 3201 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs), 3202 .pin_descs = tegra186_pin_descs, 3203 .regs = &tegra186_pmc_regs, 3204 .init = NULL, 3205 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3206 .irq_set_wake = tegra186_pmc_irq_set_wake, 3207 .irq_set_type = tegra186_pmc_irq_set_type, 3208 .reset_sources = tegra186_reset_sources, 3209 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources), 3210 .reset_levels = tegra186_reset_levels, 3211 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3212 .num_wake_events = ARRAY_SIZE(tegra186_wake_events), 3213 .wake_events = tegra186_wake_events, 3214 .pmc_clks_data = NULL, 3215 .num_pmc_clks = 0, 3216 .has_blink_output = false, 3217 }; 3218 3219 #define TEGRA194_IO_PAD_TABLE(_pad) \ 3220 /* .id .dpd .voltage .name */ \ 3221 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \ 3222 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \ 3223 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \ 3224 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \ 3225 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \ 3226 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \ 3227 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \ 3228 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \ 3229 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \ 3230 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \ 3231 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \ 3232 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \ 3233 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \ 3234 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \ 3235 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \ 3236 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \ 3237 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \ 3238 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \ 3239 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \ 3240 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \ 3241 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \ 3242 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \ 3243 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \ 3244 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \ 3245 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \ 3246 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \ 3247 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \ 3248 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \ 3249 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \ 3250 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \ 3251 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \ 3252 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \ 3253 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \ 3254 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \ 3255 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \ 3256 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \ 3257 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \ 3258 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \ 3259 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \ 3260 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \ 3261 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \ 3262 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \ 3263 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \ 3264 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \ 3265 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \ 3266 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \ 3267 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \ 3268 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \ 3269 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv") 3270 3271 static const struct tegra_io_pad_soc tegra194_io_pads[] = { 3272 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD) 3273 }; 3274 3275 static const struct pinctrl_pin_desc tegra194_pin_descs[] = { 3276 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC) 3277 }; 3278 3279 static const struct tegra_pmc_regs tegra194_pmc_regs = { 3280 .scratch0 = 0x2000, 3281 .dpd_req = 0x74, 3282 .dpd_status = 0x78, 3283 .dpd2_req = 0x7c, 3284 .dpd2_status = 0x80, 3285 .rst_status = 0x70, 3286 .rst_source_shift = 0x2, 3287 .rst_source_mask = 0x7c, 3288 .rst_level_shift = 0x0, 3289 .rst_level_mask = 0x3, 3290 }; 3291 3292 static const char * const tegra194_reset_sources[] = { 3293 "SYS_RESET_N", 3294 "AOWDT", 3295 "BCCPLEXWDT", 3296 "BPMPWDT", 3297 "SCEWDT", 3298 "SPEWDT", 3299 "APEWDT", 3300 "LCCPLEXWDT", 3301 "SENSOR", 3302 "AOTAG", 3303 "VFSENSOR", 3304 "MAINSWRST", 3305 "SC7", 3306 "HSM", 3307 "CSITE", 3308 "RCEWDT", 3309 "PVA0WDT", 3310 "PVA1WDT", 3311 "L1A_ASYNC", 3312 "BPMPBOOT", 3313 "FUSECRC", 3314 }; 3315 3316 static const struct tegra_wake_event tegra194_wake_events[] = { 3317 TEGRA_WAKE_IRQ("pmu", 24, 209), 3318 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), 3319 TEGRA_WAKE_IRQ("rtc", 73, 10), 3320 }; 3321 3322 static const struct tegra_pmc_soc tegra194_pmc_soc = { 3323 .num_powergates = 0, 3324 .powergates = NULL, 3325 .num_cpu_powergates = 0, 3326 .cpu_powergates = NULL, 3327 .has_tsense_reset = false, 3328 .has_gpu_clamps = false, 3329 .needs_mbist_war = false, 3330 .has_impl_33v_pwr = true, 3331 .maybe_tz_only = false, 3332 .num_io_pads = ARRAY_SIZE(tegra194_io_pads), 3333 .io_pads = tegra194_io_pads, 3334 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs), 3335 .pin_descs = tegra194_pin_descs, 3336 .regs = &tegra194_pmc_regs, 3337 .init = NULL, 3338 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3339 .irq_set_wake = tegra186_pmc_irq_set_wake, 3340 .irq_set_type = tegra186_pmc_irq_set_type, 3341 .reset_sources = tegra194_reset_sources, 3342 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources), 3343 .reset_levels = tegra186_reset_levels, 3344 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3345 .num_wake_events = ARRAY_SIZE(tegra194_wake_events), 3346 .wake_events = tegra194_wake_events, 3347 .pmc_clks_data = NULL, 3348 .num_pmc_clks = 0, 3349 .has_blink_output = false, 3350 }; 3351 3352 static const struct tegra_pmc_regs tegra234_pmc_regs = { 3353 .scratch0 = 0x2000, 3354 .dpd_req = 0, 3355 .dpd_status = 0, 3356 .dpd2_req = 0, 3357 .dpd2_status = 0, 3358 .rst_status = 0x70, 3359 .rst_source_shift = 0x2, 3360 .rst_source_mask = 0xfc, 3361 .rst_level_shift = 0x0, 3362 .rst_level_mask = 0x3, 3363 }; 3364 3365 static const char * const tegra234_reset_sources[] = { 3366 "SYS_RESET_N", 3367 "AOWDT", 3368 "BCCPLEXWDT", 3369 "BPMPWDT", 3370 "SCEWDT", 3371 "SPEWDT", 3372 "APEWDT", 3373 "LCCPLEXWDT", 3374 "SENSOR", 3375 "AOTAG", 3376 "VFSENSOR", 3377 "MAINSWRST", 3378 "SC7", 3379 "HSM", 3380 "CSITE", 3381 "RCEWDT", 3382 "PVA0WDT", 3383 "PVA1WDT", 3384 "L1A_ASYNC", 3385 "BPMPBOOT", 3386 "FUSECRC", 3387 }; 3388 3389 static const struct tegra_pmc_soc tegra234_pmc_soc = { 3390 .num_powergates = 0, 3391 .powergates = NULL, 3392 .num_cpu_powergates = 0, 3393 .cpu_powergates = NULL, 3394 .has_tsense_reset = false, 3395 .has_gpu_clamps = false, 3396 .needs_mbist_war = false, 3397 .has_impl_33v_pwr = true, 3398 .maybe_tz_only = false, 3399 .num_io_pads = 0, 3400 .io_pads = NULL, 3401 .num_pin_descs = 0, 3402 .pin_descs = NULL, 3403 .regs = &tegra234_pmc_regs, 3404 .init = NULL, 3405 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 3406 .irq_set_wake = tegra186_pmc_irq_set_wake, 3407 .irq_set_type = tegra186_pmc_irq_set_type, 3408 .reset_sources = tegra234_reset_sources, 3409 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), 3410 .reset_levels = tegra186_reset_levels, 3411 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), 3412 .num_wake_events = 0, 3413 .wake_events = NULL, 3414 .pmc_clks_data = NULL, 3415 .num_pmc_clks = 0, 3416 .has_blink_output = false, 3417 }; 3418 3419 static const struct of_device_id tegra_pmc_match[] = { 3420 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc }, 3421 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc }, 3422 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 3423 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 3424 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 3425 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 3426 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 3427 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 3428 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 3429 { } 3430 }; 3431 3432 static struct platform_driver tegra_pmc_driver = { 3433 .driver = { 3434 .name = "tegra-pmc", 3435 .suppress_bind_attrs = true, 3436 .of_match_table = tegra_pmc_match, 3437 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 3438 .pm = &tegra_pmc_pm_ops, 3439 #endif 3440 }, 3441 .probe = tegra_pmc_probe, 3442 }; 3443 builtin_platform_driver(tegra_pmc_driver); 3444 3445 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) 3446 { 3447 u32 value, saved; 3448 3449 saved = readl(pmc->base + pmc->soc->regs->scratch0); 3450 value = saved ^ 0xffffffff; 3451 3452 if (value == 0xffffffff) 3453 value = 0xdeadbeef; 3454 3455 /* write pattern and read it back */ 3456 writel(value, pmc->base + pmc->soc->regs->scratch0); 3457 value = readl(pmc->base + pmc->soc->regs->scratch0); 3458 3459 /* if we read all-zeroes, access is restricted to TZ only */ 3460 if (value == 0) { 3461 pr_info("access to PMC is restricted to TZ\n"); 3462 return true; 3463 } 3464 3465 /* restore original value */ 3466 writel(saved, pmc->base + pmc->soc->regs->scratch0); 3467 3468 return false; 3469 } 3470 3471 /* 3472 * Early initialization to allow access to registers in the very early boot 3473 * process. 3474 */ 3475 static int __init tegra_pmc_early_init(void) 3476 { 3477 const struct of_device_id *match; 3478 struct device_node *np; 3479 struct resource regs; 3480 unsigned int i; 3481 bool invert; 3482 3483 mutex_init(&pmc->powergates_lock); 3484 3485 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 3486 if (!np) { 3487 /* 3488 * Fall back to legacy initialization for 32-bit ARM only. All 3489 * 64-bit ARM device tree files for Tegra are required to have 3490 * a PMC node. 3491 * 3492 * This is for backwards-compatibility with old device trees 3493 * that didn't contain a PMC node. Note that in this case the 3494 * SoC data can't be matched and therefore powergating is 3495 * disabled. 3496 */ 3497 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 3498 pr_warn("DT node not found, powergating disabled\n"); 3499 3500 regs.start = 0x7000e400; 3501 regs.end = 0x7000e7ff; 3502 regs.flags = IORESOURCE_MEM; 3503 3504 pr_warn("Using memory region %pR\n", ®s); 3505 } else { 3506 /* 3507 * At this point we're not running on Tegra, so play 3508 * nice with multi-platform kernels. 3509 */ 3510 return 0; 3511 } 3512 } else { 3513 /* 3514 * Extract information from the device tree if we've found a 3515 * matching node. 3516 */ 3517 if (of_address_to_resource(np, 0, ®s) < 0) { 3518 pr_err("failed to get PMC registers\n"); 3519 of_node_put(np); 3520 return -ENXIO; 3521 } 3522 } 3523 3524 pmc->base = ioremap(regs.start, resource_size(®s)); 3525 if (!pmc->base) { 3526 pr_err("failed to map PMC registers\n"); 3527 of_node_put(np); 3528 return -ENXIO; 3529 } 3530 3531 if (np) { 3532 pmc->soc = match->data; 3533 3534 if (pmc->soc->maybe_tz_only) 3535 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); 3536 3537 /* Create a bitmap of the available and valid partitions */ 3538 for (i = 0; i < pmc->soc->num_powergates; i++) 3539 if (pmc->soc->powergates[i]) 3540 set_bit(i, pmc->powergates_available); 3541 3542 /* 3543 * Invert the interrupt polarity if a PMC device tree node 3544 * exists and contains the nvidia,invert-interrupt property. 3545 */ 3546 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 3547 3548 pmc->soc->setup_irq_polarity(pmc, np, invert); 3549 3550 of_node_put(np); 3551 } 3552 3553 return 0; 3554 } 3555 early_initcall(tegra_pmc_early_init); 3556