1 /*
2  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  *
16  */
17 
18 #include <linux/clk.h>
19 #include <linux/device.h>
20 #include <linux/kobject.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/sys_soc.h>
28 
29 #include <soc/tegra/common.h>
30 #include <soc/tegra/fuse.h>
31 
32 #include "fuse.h"
33 
34 struct tegra_sku_info tegra_sku_info;
35 EXPORT_SYMBOL(tegra_sku_info);
36 
37 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
38 	[TEGRA_REVISION_UNKNOWN] = "unknown",
39 	[TEGRA_REVISION_A01]     = "A01",
40 	[TEGRA_REVISION_A02]     = "A02",
41 	[TEGRA_REVISION_A03]     = "A03",
42 	[TEGRA_REVISION_A03p]    = "A03 prime",
43 	[TEGRA_REVISION_A04]     = "A04",
44 };
45 
46 static u8 fuse_readb(struct tegra_fuse *fuse, unsigned int offset)
47 {
48 	u32 val;
49 
50 	val = fuse->read(fuse, round_down(offset, 4));
51 	val >>= (offset % 4) * 8;
52 	val &= 0xff;
53 
54 	return val;
55 }
56 
57 static ssize_t fuse_read(struct file *fd, struct kobject *kobj,
58 			 struct bin_attribute *attr, char *buf,
59 			 loff_t pos, size_t size)
60 {
61 	struct device *dev = kobj_to_dev(kobj);
62 	struct tegra_fuse *fuse = dev_get_drvdata(dev);
63 	int i;
64 
65 	if (pos < 0 || pos >= attr->size)
66 		return 0;
67 
68 	if (size > attr->size - pos)
69 		size = attr->size - pos;
70 
71 	for (i = 0; i < size; i++)
72 		buf[i] = fuse_readb(fuse, pos + i);
73 
74 	return i;
75 }
76 
77 static struct bin_attribute fuse_bin_attr = {
78 	.attr = { .name = "fuse", .mode = S_IRUGO, },
79 	.read = fuse_read,
80 };
81 
82 static int tegra_fuse_create_sysfs(struct device *dev, unsigned int size,
83 				   const struct tegra_fuse_info *info)
84 {
85 	fuse_bin_attr.size = size;
86 
87 	return device_create_bin_file(dev, &fuse_bin_attr);
88 }
89 
90 static const struct of_device_id car_match[] __initconst = {
91 	{ .compatible = "nvidia,tegra20-car", },
92 	{ .compatible = "nvidia,tegra30-car", },
93 	{ .compatible = "nvidia,tegra114-car", },
94 	{ .compatible = "nvidia,tegra124-car", },
95 	{ .compatible = "nvidia,tegra132-car", },
96 	{ .compatible = "nvidia,tegra210-car", },
97 	{},
98 };
99 
100 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
101 	.base = NULL,
102 	.soc = NULL,
103 };
104 
105 static const struct of_device_id tegra_fuse_match[] = {
106 #ifdef CONFIG_ARCH_TEGRA_186_SOC
107 	{ .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
108 #endif
109 #ifdef CONFIG_ARCH_TEGRA_210_SOC
110 	{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
111 #endif
112 #ifdef CONFIG_ARCH_TEGRA_132_SOC
113 	{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
114 #endif
115 #ifdef CONFIG_ARCH_TEGRA_124_SOC
116 	{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
117 #endif
118 #ifdef CONFIG_ARCH_TEGRA_114_SOC
119 	{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
120 #endif
121 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
122 	{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
123 #endif
124 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
125 	{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
126 #endif
127 	{ /* sentinel */ }
128 };
129 
130 static int tegra_fuse_probe(struct platform_device *pdev)
131 {
132 	void __iomem *base = fuse->base;
133 	struct resource *res;
134 	int err;
135 
136 	/* take over the memory region from the early initialization */
137 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
138 	fuse->phys = res->start;
139 	fuse->base = devm_ioremap_resource(&pdev->dev, res);
140 	if (IS_ERR(fuse->base)) {
141 		err = PTR_ERR(fuse->base);
142 		fuse->base = base;
143 		return err;
144 	}
145 
146 	fuse->clk = devm_clk_get(&pdev->dev, "fuse");
147 	if (IS_ERR(fuse->clk)) {
148 		dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
149 			PTR_ERR(fuse->clk));
150 		fuse->base = base;
151 		return PTR_ERR(fuse->clk);
152 	}
153 
154 	platform_set_drvdata(pdev, fuse);
155 	fuse->dev = &pdev->dev;
156 
157 	if (fuse->soc->probe) {
158 		err = fuse->soc->probe(fuse);
159 		if (err < 0) {
160 			fuse->base = base;
161 			return err;
162 		}
163 	}
164 
165 	if (tegra_fuse_create_sysfs(&pdev->dev, fuse->soc->info->size,
166 				    fuse->soc->info))
167 		return -ENODEV;
168 
169 	/* release the early I/O memory mapping */
170 	iounmap(base);
171 
172 	return 0;
173 }
174 
175 static struct platform_driver tegra_fuse_driver = {
176 	.driver = {
177 		.name = "tegra-fuse",
178 		.of_match_table = tegra_fuse_match,
179 		.suppress_bind_attrs = true,
180 	},
181 	.probe = tegra_fuse_probe,
182 };
183 builtin_platform_driver(tegra_fuse_driver);
184 
185 bool __init tegra_fuse_read_spare(unsigned int spare)
186 {
187 	unsigned int offset = fuse->soc->info->spare + spare * 4;
188 
189 	return fuse->read_early(fuse, offset) & 1;
190 }
191 
192 u32 __init tegra_fuse_read_early(unsigned int offset)
193 {
194 	return fuse->read_early(fuse, offset);
195 }
196 
197 int tegra_fuse_readl(unsigned long offset, u32 *value)
198 {
199 	if (!fuse->read)
200 		return -EPROBE_DEFER;
201 
202 	*value = fuse->read(fuse, offset);
203 
204 	return 0;
205 }
206 EXPORT_SYMBOL(tegra_fuse_readl);
207 
208 static void tegra_enable_fuse_clk(void __iomem *base)
209 {
210 	u32 reg;
211 
212 	reg = readl_relaxed(base + 0x48);
213 	reg |= 1 << 28;
214 	writel(reg, base + 0x48);
215 
216 	/*
217 	 * Enable FUSE clock. This needs to be hardcoded because the clock
218 	 * subsystem is not active during early boot.
219 	 */
220 	reg = readl(base + 0x14);
221 	reg |= 1 << 7;
222 	writel(reg, base + 0x14);
223 }
224 
225 struct device * __init tegra_soc_device_register(void)
226 {
227 	struct soc_device_attribute *attr;
228 	struct soc_device *dev;
229 
230 	attr = kzalloc(sizeof(*attr), GFP_KERNEL);
231 	if (!attr)
232 		return NULL;
233 
234 	attr->family = kasprintf(GFP_KERNEL, "Tegra");
235 	attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision);
236 	attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
237 
238 	dev = soc_device_register(attr);
239 	if (IS_ERR(dev)) {
240 		kfree(attr->soc_id);
241 		kfree(attr->revision);
242 		kfree(attr->family);
243 		kfree(attr);
244 		return ERR_CAST(dev);
245 	}
246 
247 	return soc_device_to_device(dev);
248 }
249 
250 static int __init tegra_init_fuse(void)
251 {
252 	const struct of_device_id *match;
253 	struct device_node *np;
254 	struct resource regs;
255 
256 	tegra_init_apbmisc();
257 
258 	np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
259 	if (!np) {
260 		/*
261 		 * Fall back to legacy initialization for 32-bit ARM only. All
262 		 * 64-bit ARM device tree files for Tegra are required to have
263 		 * a FUSE node.
264 		 *
265 		 * This is for backwards-compatibility with old device trees
266 		 * that didn't contain a FUSE node.
267 		 */
268 		if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
269 			u8 chip = tegra_get_chip_id();
270 
271 			regs.start = 0x7000f800;
272 			regs.end = 0x7000fbff;
273 			regs.flags = IORESOURCE_MEM;
274 
275 			switch (chip) {
276 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
277 			case TEGRA20:
278 				fuse->soc = &tegra20_fuse_soc;
279 				break;
280 #endif
281 
282 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
283 			case TEGRA30:
284 				fuse->soc = &tegra30_fuse_soc;
285 				break;
286 #endif
287 
288 #ifdef CONFIG_ARCH_TEGRA_114_SOC
289 			case TEGRA114:
290 				fuse->soc = &tegra114_fuse_soc;
291 				break;
292 #endif
293 
294 #ifdef CONFIG_ARCH_TEGRA_124_SOC
295 			case TEGRA124:
296 				fuse->soc = &tegra124_fuse_soc;
297 				break;
298 #endif
299 
300 			default:
301 				pr_warn("Unsupported SoC: %02x\n", chip);
302 				break;
303 			}
304 		} else {
305 			/*
306 			 * At this point we're not running on Tegra, so play
307 			 * nice with multi-platform kernels.
308 			 */
309 			return 0;
310 		}
311 	} else {
312 		/*
313 		 * Extract information from the device tree if we've found a
314 		 * matching node.
315 		 */
316 		if (of_address_to_resource(np, 0, &regs) < 0) {
317 			pr_err("failed to get FUSE register\n");
318 			return -ENXIO;
319 		}
320 
321 		fuse->soc = match->data;
322 	}
323 
324 	np = of_find_matching_node(NULL, car_match);
325 	if (np) {
326 		void __iomem *base = of_iomap(np, 0);
327 		if (base) {
328 			tegra_enable_fuse_clk(base);
329 			iounmap(base);
330 		} else {
331 			pr_err("failed to map clock registers\n");
332 			return -ENXIO;
333 		}
334 	}
335 
336 	fuse->base = ioremap_nocache(regs.start, resource_size(&regs));
337 	if (!fuse->base) {
338 		pr_err("failed to map FUSE registers\n");
339 		return -ENXIO;
340 	}
341 
342 	fuse->soc->init(fuse);
343 
344 	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
345 		tegra_revision_name[tegra_sku_info.revision],
346 		tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
347 		tegra_sku_info.soc_process_id);
348 	pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
349 		 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
350 
351 
352 	return 0;
353 }
354 early_initcall(tegra_init_fuse);
355 
356 #ifdef CONFIG_ARM64
357 static int __init tegra_init_soc(void)
358 {
359 	struct device_node *np;
360 	struct device *soc;
361 
362 	/* make sure we're running on Tegra */
363 	np = of_find_matching_node(NULL, tegra_fuse_match);
364 	if (!np)
365 		return 0;
366 
367 	of_node_put(np);
368 
369 	soc = tegra_soc_device_register();
370 	if (IS_ERR(soc)) {
371 		pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
372 		return PTR_ERR(soc);
373 	}
374 
375 	return 0;
376 }
377 device_initcall(tegra_init_soc);
378 #endif
379