1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/device.h>
8 #include <linux/kobject.h>
9 #include <linux/init.h>
10 #include <linux/io.h>
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/sys_soc.h>
18 
19 #include <soc/tegra/common.h>
20 #include <soc/tegra/fuse.h>
21 
22 #include "fuse.h"
23 
24 struct tegra_sku_info tegra_sku_info;
25 EXPORT_SYMBOL(tegra_sku_info);
26 
27 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
28 	[TEGRA_REVISION_UNKNOWN] = "unknown",
29 	[TEGRA_REVISION_A01]     = "A01",
30 	[TEGRA_REVISION_A02]     = "A02",
31 	[TEGRA_REVISION_A03]     = "A03",
32 	[TEGRA_REVISION_A03p]    = "A03 prime",
33 	[TEGRA_REVISION_A04]     = "A04",
34 };
35 
36 static const struct of_device_id car_match[] __initconst = {
37 	{ .compatible = "nvidia,tegra20-car", },
38 	{ .compatible = "nvidia,tegra30-car", },
39 	{ .compatible = "nvidia,tegra114-car", },
40 	{ .compatible = "nvidia,tegra124-car", },
41 	{ .compatible = "nvidia,tegra132-car", },
42 	{ .compatible = "nvidia,tegra210-car", },
43 	{},
44 };
45 
46 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
47 	.base = NULL,
48 	.soc = NULL,
49 };
50 
51 static const struct of_device_id tegra_fuse_match[] = {
52 #ifdef CONFIG_ARCH_TEGRA_194_SOC
53 	{ .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
54 #endif
55 #ifdef CONFIG_ARCH_TEGRA_186_SOC
56 	{ .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
57 #endif
58 #ifdef CONFIG_ARCH_TEGRA_210_SOC
59 	{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
60 #endif
61 #ifdef CONFIG_ARCH_TEGRA_132_SOC
62 	{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
63 #endif
64 #ifdef CONFIG_ARCH_TEGRA_124_SOC
65 	{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
66 #endif
67 #ifdef CONFIG_ARCH_TEGRA_114_SOC
68 	{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
69 #endif
70 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
71 	{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
72 #endif
73 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
74 	{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
75 #endif
76 	{ /* sentinel */ }
77 };
78 
79 static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
80 			   size_t bytes)
81 {
82 	unsigned int count = bytes / 4, i;
83 	struct tegra_fuse *fuse = priv;
84 	u32 *buffer = value;
85 
86 	for (i = 0; i < count; i++)
87 		buffer[i] = fuse->read(fuse, offset + i * 4);
88 
89 	return 0;
90 }
91 
92 static const struct nvmem_cell_info tegra_fuse_cells[] = {
93 	{
94 		.name = "tsensor-cpu1",
95 		.offset = 0x084,
96 		.bytes = 4,
97 		.bit_offset = 0,
98 		.nbits = 32,
99 	}, {
100 		.name = "tsensor-cpu2",
101 		.offset = 0x088,
102 		.bytes = 4,
103 		.bit_offset = 0,
104 		.nbits = 32,
105 	}, {
106 		.name = "tsensor-cpu0",
107 		.offset = 0x098,
108 		.bytes = 4,
109 		.bit_offset = 0,
110 		.nbits = 32,
111 	}, {
112 		.name = "xusb-pad-calibration",
113 		.offset = 0x0f0,
114 		.bytes = 4,
115 		.bit_offset = 0,
116 		.nbits = 32,
117 	}, {
118 		.name = "tsensor-cpu3",
119 		.offset = 0x12c,
120 		.bytes = 4,
121 		.bit_offset = 0,
122 		.nbits = 32,
123 	}, {
124 		.name = "sata-calibration",
125 		.offset = 0x124,
126 		.bytes = 1,
127 		.bit_offset = 0,
128 		.nbits = 2,
129 	}, {
130 		.name = "tsensor-gpu",
131 		.offset = 0x154,
132 		.bytes = 4,
133 		.bit_offset = 0,
134 		.nbits = 32,
135 	}, {
136 		.name = "tsensor-mem0",
137 		.offset = 0x158,
138 		.bytes = 4,
139 		.bit_offset = 0,
140 		.nbits = 32,
141 	}, {
142 		.name = "tsensor-mem1",
143 		.offset = 0x15c,
144 		.bytes = 4,
145 		.bit_offset = 0,
146 		.nbits = 32,
147 	}, {
148 		.name = "tsensor-pllx",
149 		.offset = 0x160,
150 		.bytes = 4,
151 		.bit_offset = 0,
152 		.nbits = 32,
153 	}, {
154 		.name = "tsensor-common",
155 		.offset = 0x180,
156 		.bytes = 4,
157 		.bit_offset = 0,
158 		.nbits = 32,
159 	}, {
160 		.name = "tsensor-realignment",
161 		.offset = 0x1fc,
162 		.bytes = 4,
163 		.bit_offset = 0,
164 		.nbits = 32,
165 	}, {
166 		.name = "gpu-calibration",
167 		.offset = 0x204,
168 		.bytes = 4,
169 		.bit_offset = 0,
170 		.nbits = 32,
171 	}, {
172 		.name = "xusb-pad-calibration-ext",
173 		.offset = 0x250,
174 		.bytes = 4,
175 		.bit_offset = 0,
176 		.nbits = 32,
177 	},
178 };
179 
180 static int tegra_fuse_probe(struct platform_device *pdev)
181 {
182 	void __iomem *base = fuse->base;
183 	struct nvmem_config nvmem;
184 	struct resource *res;
185 	int err;
186 
187 	/* take over the memory region from the early initialization */
188 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
189 	fuse->phys = res->start;
190 	fuse->base = devm_ioremap_resource(&pdev->dev, res);
191 	if (IS_ERR(fuse->base)) {
192 		err = PTR_ERR(fuse->base);
193 		fuse->base = base;
194 		return err;
195 	}
196 
197 	fuse->clk = devm_clk_get(&pdev->dev, "fuse");
198 	if (IS_ERR(fuse->clk)) {
199 		if (PTR_ERR(fuse->clk) != -EPROBE_DEFER)
200 			dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
201 				PTR_ERR(fuse->clk));
202 
203 		fuse->base = base;
204 		return PTR_ERR(fuse->clk);
205 	}
206 
207 	platform_set_drvdata(pdev, fuse);
208 	fuse->dev = &pdev->dev;
209 
210 	if (fuse->soc->probe) {
211 		err = fuse->soc->probe(fuse);
212 		if (err < 0)
213 			goto restore;
214 	}
215 
216 	memset(&nvmem, 0, sizeof(nvmem));
217 	nvmem.dev = &pdev->dev;
218 	nvmem.name = "fuse";
219 	nvmem.id = -1;
220 	nvmem.owner = THIS_MODULE;
221 	nvmem.cells = tegra_fuse_cells;
222 	nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
223 	nvmem.type = NVMEM_TYPE_OTP;
224 	nvmem.read_only = true;
225 	nvmem.root_only = true;
226 	nvmem.reg_read = tegra_fuse_read;
227 	nvmem.size = fuse->soc->info->size;
228 	nvmem.word_size = 4;
229 	nvmem.stride = 4;
230 	nvmem.priv = fuse;
231 
232 	fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
233 	if (IS_ERR(fuse->nvmem)) {
234 		err = PTR_ERR(fuse->nvmem);
235 		dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
236 			err);
237 		goto restore;
238 	}
239 
240 	/* release the early I/O memory mapping */
241 	iounmap(base);
242 
243 	return 0;
244 
245 restore:
246 	fuse->base = base;
247 	return err;
248 }
249 
250 static struct platform_driver tegra_fuse_driver = {
251 	.driver = {
252 		.name = "tegra-fuse",
253 		.of_match_table = tegra_fuse_match,
254 		.suppress_bind_attrs = true,
255 	},
256 	.probe = tegra_fuse_probe,
257 };
258 builtin_platform_driver(tegra_fuse_driver);
259 
260 bool __init tegra_fuse_read_spare(unsigned int spare)
261 {
262 	unsigned int offset = fuse->soc->info->spare + spare * 4;
263 
264 	return fuse->read_early(fuse, offset) & 1;
265 }
266 
267 u32 __init tegra_fuse_read_early(unsigned int offset)
268 {
269 	return fuse->read_early(fuse, offset);
270 }
271 
272 int tegra_fuse_readl(unsigned long offset, u32 *value)
273 {
274 	if (!fuse->read || !fuse->clk)
275 		return -EPROBE_DEFER;
276 
277 	if (IS_ERR(fuse->clk))
278 		return PTR_ERR(fuse->clk);
279 
280 	*value = fuse->read(fuse, offset);
281 
282 	return 0;
283 }
284 EXPORT_SYMBOL(tegra_fuse_readl);
285 
286 static void tegra_enable_fuse_clk(void __iomem *base)
287 {
288 	u32 reg;
289 
290 	reg = readl_relaxed(base + 0x48);
291 	reg |= 1 << 28;
292 	writel(reg, base + 0x48);
293 
294 	/*
295 	 * Enable FUSE clock. This needs to be hardcoded because the clock
296 	 * subsystem is not active during early boot.
297 	 */
298 	reg = readl(base + 0x14);
299 	reg |= 1 << 7;
300 	writel(reg, base + 0x14);
301 }
302 
303 struct device * __init tegra_soc_device_register(void)
304 {
305 	struct soc_device_attribute *attr;
306 	struct soc_device *dev;
307 
308 	attr = kzalloc(sizeof(*attr), GFP_KERNEL);
309 	if (!attr)
310 		return NULL;
311 
312 	attr->family = kasprintf(GFP_KERNEL, "Tegra");
313 	attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_sku_info.revision);
314 	attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
315 
316 	dev = soc_device_register(attr);
317 	if (IS_ERR(dev)) {
318 		kfree(attr->soc_id);
319 		kfree(attr->revision);
320 		kfree(attr->family);
321 		kfree(attr);
322 		return ERR_CAST(dev);
323 	}
324 
325 	return soc_device_to_device(dev);
326 }
327 
328 static int __init tegra_init_fuse(void)
329 {
330 	const struct of_device_id *match;
331 	struct device_node *np;
332 	struct resource regs;
333 
334 	tegra_init_apbmisc();
335 
336 	np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
337 	if (!np) {
338 		/*
339 		 * Fall back to legacy initialization for 32-bit ARM only. All
340 		 * 64-bit ARM device tree files for Tegra are required to have
341 		 * a FUSE node.
342 		 *
343 		 * This is for backwards-compatibility with old device trees
344 		 * that didn't contain a FUSE node.
345 		 */
346 		if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
347 			u8 chip = tegra_get_chip_id();
348 
349 			regs.start = 0x7000f800;
350 			regs.end = 0x7000fbff;
351 			regs.flags = IORESOURCE_MEM;
352 
353 			switch (chip) {
354 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
355 			case TEGRA20:
356 				fuse->soc = &tegra20_fuse_soc;
357 				break;
358 #endif
359 
360 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
361 			case TEGRA30:
362 				fuse->soc = &tegra30_fuse_soc;
363 				break;
364 #endif
365 
366 #ifdef CONFIG_ARCH_TEGRA_114_SOC
367 			case TEGRA114:
368 				fuse->soc = &tegra114_fuse_soc;
369 				break;
370 #endif
371 
372 #ifdef CONFIG_ARCH_TEGRA_124_SOC
373 			case TEGRA124:
374 				fuse->soc = &tegra124_fuse_soc;
375 				break;
376 #endif
377 
378 			default:
379 				pr_warn("Unsupported SoC: %02x\n", chip);
380 				break;
381 			}
382 		} else {
383 			/*
384 			 * At this point we're not running on Tegra, so play
385 			 * nice with multi-platform kernels.
386 			 */
387 			return 0;
388 		}
389 	} else {
390 		/*
391 		 * Extract information from the device tree if we've found a
392 		 * matching node.
393 		 */
394 		if (of_address_to_resource(np, 0, &regs) < 0) {
395 			pr_err("failed to get FUSE register\n");
396 			return -ENXIO;
397 		}
398 
399 		fuse->soc = match->data;
400 	}
401 
402 	np = of_find_matching_node(NULL, car_match);
403 	if (np) {
404 		void __iomem *base = of_iomap(np, 0);
405 		if (base) {
406 			tegra_enable_fuse_clk(base);
407 			iounmap(base);
408 		} else {
409 			pr_err("failed to map clock registers\n");
410 			return -ENXIO;
411 		}
412 	}
413 
414 	fuse->base = ioremap(regs.start, resource_size(&regs));
415 	if (!fuse->base) {
416 		pr_err("failed to map FUSE registers\n");
417 		return -ENXIO;
418 	}
419 
420 	fuse->soc->init(fuse);
421 
422 	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
423 		tegra_revision_name[tegra_sku_info.revision],
424 		tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
425 		tegra_sku_info.soc_process_id);
426 	pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
427 		 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
428 
429 	if (fuse->soc->lookups) {
430 		size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups;
431 
432 		fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL);
433 		if (!fuse->lookups)
434 			return -ENOMEM;
435 
436 		nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
437 	}
438 
439 	return 0;
440 }
441 early_initcall(tegra_init_fuse);
442 
443 #ifdef CONFIG_ARM64
444 static int __init tegra_init_soc(void)
445 {
446 	struct device_node *np;
447 	struct device *soc;
448 
449 	/* make sure we're running on Tegra */
450 	np = of_find_matching_node(NULL, tegra_fuse_match);
451 	if (!np)
452 		return 0;
453 
454 	of_node_put(np);
455 
456 	soc = tegra_soc_device_register();
457 	if (IS_ERR(soc)) {
458 		pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
459 		return PTR_ERR(soc);
460 	}
461 
462 	return 0;
463 }
464 device_initcall(tegra_init_soc);
465 #endif
466