1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2013-2023, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/device.h>
8 #include <linux/kobject.h>
9 #include <linux/init.h>
10 #include <linux/io.h>
11 #include <linux/nvmem-consumer.h>
12 #include <linux/nvmem-provider.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/slab.h>
19 #include <linux/sys_soc.h>
20 
21 #include <soc/tegra/common.h>
22 #include <soc/tegra/fuse.h>
23 
24 #include "fuse.h"
25 
26 struct tegra_sku_info tegra_sku_info;
27 EXPORT_SYMBOL(tegra_sku_info);
28 
29 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
30 	[TEGRA_REVISION_UNKNOWN] = "unknown",
31 	[TEGRA_REVISION_A01]     = "A01",
32 	[TEGRA_REVISION_A02]     = "A02",
33 	[TEGRA_REVISION_A03]     = "A03",
34 	[TEGRA_REVISION_A03p]    = "A03 prime",
35 	[TEGRA_REVISION_A04]     = "A04",
36 };
37 
38 static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
39 	[TEGRA_PLATFORM_SILICON]			= "Silicon",
40 	[TEGRA_PLATFORM_QT]				= "QT",
41 	[TEGRA_PLATFORM_SYSTEM_FPGA]			= "System FPGA",
42 	[TEGRA_PLATFORM_UNIT_FPGA]			= "Unit FPGA",
43 	[TEGRA_PLATFORM_ASIM_QT]			= "Asim QT",
44 	[TEGRA_PLATFORM_ASIM_LINSIM]			= "Asim Linsim",
45 	[TEGRA_PLATFORM_DSIM_ASIM_LINSIM]		= "Dsim Asim Linsim",
46 	[TEGRA_PLATFORM_VERIFICATION_SIMULATION]	= "Verification Simulation",
47 	[TEGRA_PLATFORM_VDK]				= "VDK",
48 	[TEGRA_PLATFORM_VSP]				= "VSP",
49 };
50 
51 static const struct of_device_id car_match[] __initconst = {
52 	{ .compatible = "nvidia,tegra20-car", },
53 	{ .compatible = "nvidia,tegra30-car", },
54 	{ .compatible = "nvidia,tegra114-car", },
55 	{ .compatible = "nvidia,tegra124-car", },
56 	{ .compatible = "nvidia,tegra132-car", },
57 	{ .compatible = "nvidia,tegra210-car", },
58 	{},
59 };
60 
61 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
62 	.base = NULL,
63 	.soc = NULL,
64 };
65 
66 static const struct of_device_id tegra_fuse_match[] = {
67 #ifdef CONFIG_ARCH_TEGRA_234_SOC
68 	{ .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
69 #endif
70 #ifdef CONFIG_ARCH_TEGRA_194_SOC
71 	{ .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
72 #endif
73 #ifdef CONFIG_ARCH_TEGRA_186_SOC
74 	{ .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
75 #endif
76 #ifdef CONFIG_ARCH_TEGRA_210_SOC
77 	{ .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
78 #endif
79 #ifdef CONFIG_ARCH_TEGRA_132_SOC
80 	{ .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
81 #endif
82 #ifdef CONFIG_ARCH_TEGRA_124_SOC
83 	{ .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
84 #endif
85 #ifdef CONFIG_ARCH_TEGRA_114_SOC
86 	{ .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
87 #endif
88 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
89 	{ .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
90 #endif
91 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
92 	{ .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
93 #endif
94 	{ /* sentinel */ }
95 };
96 
97 static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
98 			   size_t bytes)
99 {
100 	unsigned int count = bytes / 4, i;
101 	struct tegra_fuse *fuse = priv;
102 	u32 *buffer = value;
103 
104 	for (i = 0; i < count; i++)
105 		buffer[i] = fuse->read(fuse, offset + i * 4);
106 
107 	return 0;
108 }
109 
110 static void tegra_fuse_restore(void *base)
111 {
112 	fuse->base = (void __iomem *)base;
113 	fuse->clk = NULL;
114 }
115 
116 static int tegra_fuse_probe(struct platform_device *pdev)
117 {
118 	void __iomem *base = fuse->base;
119 	struct nvmem_config nvmem;
120 	struct resource *res;
121 	int err;
122 
123 	err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base);
124 	if (err)
125 		return err;
126 
127 	/* take over the memory region from the early initialization */
128 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
129 	fuse->phys = res->start;
130 	fuse->base = devm_ioremap_resource(&pdev->dev, res);
131 	if (IS_ERR(fuse->base)) {
132 		err = PTR_ERR(fuse->base);
133 		return err;
134 	}
135 
136 	fuse->clk = devm_clk_get(&pdev->dev, "fuse");
137 	if (IS_ERR(fuse->clk)) {
138 		if (PTR_ERR(fuse->clk) != -EPROBE_DEFER)
139 			dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
140 				PTR_ERR(fuse->clk));
141 
142 		return PTR_ERR(fuse->clk);
143 	}
144 
145 	platform_set_drvdata(pdev, fuse);
146 	fuse->dev = &pdev->dev;
147 
148 	err = devm_pm_runtime_enable(&pdev->dev);
149 	if (err)
150 		return err;
151 
152 	if (fuse->soc->probe) {
153 		err = fuse->soc->probe(fuse);
154 		if (err < 0)
155 			return err;
156 	}
157 
158 	memset(&nvmem, 0, sizeof(nvmem));
159 	nvmem.dev = &pdev->dev;
160 	nvmem.name = "fuse";
161 	nvmem.id = -1;
162 	nvmem.owner = THIS_MODULE;
163 	nvmem.cells = fuse->soc->cells;
164 	nvmem.ncells = fuse->soc->num_cells;
165 	nvmem.keepout = fuse->soc->keepouts;
166 	nvmem.nkeepout = fuse->soc->num_keepouts;
167 	nvmem.type = NVMEM_TYPE_OTP;
168 	nvmem.read_only = true;
169 	nvmem.root_only = false;
170 	nvmem.reg_read = tegra_fuse_read;
171 	nvmem.size = fuse->soc->info->size;
172 	nvmem.word_size = 4;
173 	nvmem.stride = 4;
174 	nvmem.priv = fuse;
175 
176 	fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
177 	if (IS_ERR(fuse->nvmem)) {
178 		err = PTR_ERR(fuse->nvmem);
179 		dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
180 			err);
181 		return err;
182 	}
183 
184 	fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");
185 	if (IS_ERR(fuse->rst)) {
186 		err = PTR_ERR(fuse->rst);
187 		dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n",
188 			fuse->rst);
189 		return err;
190 	}
191 
192 	/*
193 	 * FUSE clock is enabled at a boot time, hence this resume/suspend
194 	 * disables the clock besides the h/w resetting.
195 	 */
196 	err = pm_runtime_resume_and_get(&pdev->dev);
197 	if (err)
198 		return err;
199 
200 	err = reset_control_reset(fuse->rst);
201 	pm_runtime_put(&pdev->dev);
202 
203 	if (err < 0) {
204 		dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err);
205 		return err;
206 	}
207 
208 	/* release the early I/O memory mapping */
209 	iounmap(base);
210 
211 	return 0;
212 }
213 
214 static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev)
215 {
216 	int err;
217 
218 	err = clk_prepare_enable(fuse->clk);
219 	if (err < 0) {
220 		dev_err(dev, "failed to enable FUSE clock: %d\n", err);
221 		return err;
222 	}
223 
224 	return 0;
225 }
226 
227 static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev)
228 {
229 	clk_disable_unprepare(fuse->clk);
230 
231 	return 0;
232 }
233 
234 static int __maybe_unused tegra_fuse_suspend(struct device *dev)
235 {
236 	int ret;
237 
238 	/*
239 	 * Critical for RAM re-repair operation, which must occur on resume
240 	 * from LP1 system suspend and as part of CCPLEX cluster switching.
241 	 */
242 	if (fuse->soc->clk_suspend_on)
243 		ret = pm_runtime_resume_and_get(dev);
244 	else
245 		ret = pm_runtime_force_suspend(dev);
246 
247 	return ret;
248 }
249 
250 static int __maybe_unused tegra_fuse_resume(struct device *dev)
251 {
252 	int ret = 0;
253 
254 	if (fuse->soc->clk_suspend_on)
255 		pm_runtime_put(dev);
256 	else
257 		ret = pm_runtime_force_resume(dev);
258 
259 	return ret;
260 }
261 
262 static const struct dev_pm_ops tegra_fuse_pm = {
263 	SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume,
264 			   NULL)
265 	SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume)
266 };
267 
268 static struct platform_driver tegra_fuse_driver = {
269 	.driver = {
270 		.name = "tegra-fuse",
271 		.of_match_table = tegra_fuse_match,
272 		.pm = &tegra_fuse_pm,
273 		.suppress_bind_attrs = true,
274 	},
275 	.probe = tegra_fuse_probe,
276 };
277 builtin_platform_driver(tegra_fuse_driver);
278 
279 u32 __init tegra_fuse_read_spare(unsigned int spare)
280 {
281 	unsigned int offset = fuse->soc->info->spare + spare * 4;
282 
283 	return fuse->read_early(fuse, offset) & 1;
284 }
285 
286 u32 __init tegra_fuse_read_early(unsigned int offset)
287 {
288 	return fuse->read_early(fuse, offset);
289 }
290 
291 int tegra_fuse_readl(unsigned long offset, u32 *value)
292 {
293 	if (!fuse->read || !fuse->clk)
294 		return -EPROBE_DEFER;
295 
296 	if (IS_ERR(fuse->clk))
297 		return PTR_ERR(fuse->clk);
298 
299 	*value = fuse->read(fuse, offset);
300 
301 	return 0;
302 }
303 EXPORT_SYMBOL(tegra_fuse_readl);
304 
305 static void tegra_enable_fuse_clk(void __iomem *base)
306 {
307 	u32 reg;
308 
309 	reg = readl_relaxed(base + 0x48);
310 	reg |= 1 << 28;
311 	writel(reg, base + 0x48);
312 
313 	/*
314 	 * Enable FUSE clock. This needs to be hardcoded because the clock
315 	 * subsystem is not active during early boot.
316 	 */
317 	reg = readl(base + 0x14);
318 	reg |= 1 << 7;
319 	writel(reg, base + 0x14);
320 }
321 
322 static ssize_t major_show(struct device *dev, struct device_attribute *attr,
323 			     char *buf)
324 {
325 	return sprintf(buf, "%d\n", tegra_get_major_rev());
326 }
327 
328 static DEVICE_ATTR_RO(major);
329 
330 static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
331 			     char *buf)
332 {
333 	return sprintf(buf, "%d\n", tegra_get_minor_rev());
334 }
335 
336 static DEVICE_ATTR_RO(minor);
337 
338 static struct attribute *tegra_soc_attr[] = {
339 	&dev_attr_major.attr,
340 	&dev_attr_minor.attr,
341 	NULL,
342 };
343 
344 const struct attribute_group tegra_soc_attr_group = {
345 	.attrs = tegra_soc_attr,
346 };
347 
348 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
349     IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
350 static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
351 			     char *buf)
352 {
353 	/*
354 	 * Displays the value in the 'pre_si_platform' field of the HIDREV
355 	 * register for Tegra194 devices. A value of 0 indicates that the
356 	 * platform type is silicon and all other non-zero values indicate
357 	 * the type of simulation platform is being used.
358 	 */
359 	return sprintf(buf, "%d\n", tegra_get_platform());
360 }
361 
362 static DEVICE_ATTR_RO(platform);
363 
364 static struct attribute *tegra194_soc_attr[] = {
365 	&dev_attr_major.attr,
366 	&dev_attr_minor.attr,
367 	&dev_attr_platform.attr,
368 	NULL,
369 };
370 
371 const struct attribute_group tegra194_soc_attr_group = {
372 	.attrs = tegra194_soc_attr,
373 };
374 #endif
375 
376 struct device * __init tegra_soc_device_register(void)
377 {
378 	struct soc_device_attribute *attr;
379 	struct soc_device *dev;
380 
381 	attr = kzalloc(sizeof(*attr), GFP_KERNEL);
382 	if (!attr)
383 		return NULL;
384 
385 	attr->family = kasprintf(GFP_KERNEL, "Tegra");
386 	if (tegra_is_silicon())
387 		attr->revision = kasprintf(GFP_KERNEL, "%s %s",
388 					   tegra_platform_name[tegra_sku_info.platform],
389 					   tegra_revision_name[tegra_sku_info.revision]);
390 	else
391 		attr->revision = kasprintf(GFP_KERNEL, "%s",
392 					   tegra_platform_name[tegra_sku_info.platform]);
393 	attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
394 	attr->custom_attr_group = fuse->soc->soc_attr_group;
395 
396 	dev = soc_device_register(attr);
397 	if (IS_ERR(dev)) {
398 		kfree(attr->soc_id);
399 		kfree(attr->revision);
400 		kfree(attr->family);
401 		kfree(attr);
402 		return ERR_CAST(dev);
403 	}
404 
405 	return soc_device_to_device(dev);
406 }
407 
408 static int __init tegra_init_fuse(void)
409 {
410 	const struct of_device_id *match;
411 	struct device_node *np;
412 	struct resource regs;
413 
414 	tegra_init_apbmisc();
415 
416 	np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
417 	if (!np) {
418 		/*
419 		 * Fall back to legacy initialization for 32-bit ARM only. All
420 		 * 64-bit ARM device tree files for Tegra are required to have
421 		 * a FUSE node.
422 		 *
423 		 * This is for backwards-compatibility with old device trees
424 		 * that didn't contain a FUSE node.
425 		 */
426 		if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
427 			u8 chip = tegra_get_chip_id();
428 
429 			regs.start = 0x7000f800;
430 			regs.end = 0x7000fbff;
431 			regs.flags = IORESOURCE_MEM;
432 
433 			switch (chip) {
434 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
435 			case TEGRA20:
436 				fuse->soc = &tegra20_fuse_soc;
437 				break;
438 #endif
439 
440 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
441 			case TEGRA30:
442 				fuse->soc = &tegra30_fuse_soc;
443 				break;
444 #endif
445 
446 #ifdef CONFIG_ARCH_TEGRA_114_SOC
447 			case TEGRA114:
448 				fuse->soc = &tegra114_fuse_soc;
449 				break;
450 #endif
451 
452 #ifdef CONFIG_ARCH_TEGRA_124_SOC
453 			case TEGRA124:
454 				fuse->soc = &tegra124_fuse_soc;
455 				break;
456 #endif
457 
458 			default:
459 				pr_warn("Unsupported SoC: %02x\n", chip);
460 				break;
461 			}
462 		} else {
463 			/*
464 			 * At this point we're not running on Tegra, so play
465 			 * nice with multi-platform kernels.
466 			 */
467 			return 0;
468 		}
469 	} else {
470 		/*
471 		 * Extract information from the device tree if we've found a
472 		 * matching node.
473 		 */
474 		if (of_address_to_resource(np, 0, &regs) < 0) {
475 			pr_err("failed to get FUSE register\n");
476 			return -ENXIO;
477 		}
478 
479 		fuse->soc = match->data;
480 	}
481 
482 	np = of_find_matching_node(NULL, car_match);
483 	if (np) {
484 		void __iomem *base = of_iomap(np, 0);
485 		of_node_put(np);
486 		if (base) {
487 			tegra_enable_fuse_clk(base);
488 			iounmap(base);
489 		} else {
490 			pr_err("failed to map clock registers\n");
491 			return -ENXIO;
492 		}
493 	}
494 
495 	fuse->base = ioremap(regs.start, resource_size(&regs));
496 	if (!fuse->base) {
497 		pr_err("failed to map FUSE registers\n");
498 		return -ENXIO;
499 	}
500 
501 	fuse->soc->init(fuse);
502 
503 	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
504 		tegra_revision_name[tegra_sku_info.revision],
505 		tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
506 		tegra_sku_info.soc_process_id);
507 	pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
508 		 tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
509 
510 	if (fuse->soc->lookups) {
511 		size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups;
512 
513 		fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL);
514 		if (fuse->lookups)
515 			nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
516 	}
517 
518 	return 0;
519 }
520 early_initcall(tegra_init_fuse);
521 
522 #ifdef CONFIG_ARM64
523 static int __init tegra_init_soc(void)
524 {
525 	struct device_node *np;
526 	struct device *soc;
527 
528 	/* make sure we're running on Tegra */
529 	np = of_find_matching_node(NULL, tegra_fuse_match);
530 	if (!np)
531 		return 0;
532 
533 	of_node_put(np);
534 
535 	soc = tegra_soc_device_register();
536 	if (IS_ERR(soc)) {
537 		pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
538 		return PTR_ERR(soc);
539 	}
540 
541 	return 0;
542 }
543 device_initcall(tegra_init_soc);
544 #endif
545