1 /* 2 * Allwinner SoCs SRAM Controller Driver 3 * 4 * Copyright (C) 2015 Maxime Ripard 5 * 6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/debugfs.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_device.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 22 #include <linux/soc/sunxi/sunxi_sram.h> 23 24 struct sunxi_sram_func { 25 char *func; 26 u8 val; 27 u32 reg_val; 28 }; 29 30 struct sunxi_sram_data { 31 char *name; 32 u8 reg; 33 u8 offset; 34 u8 width; 35 struct sunxi_sram_func *func; 36 struct list_head list; 37 }; 38 39 struct sunxi_sram_desc { 40 struct sunxi_sram_data data; 41 bool claimed; 42 }; 43 44 #define SUNXI_SRAM_MAP(_reg_val, _val, _func) \ 45 { \ 46 .func = _func, \ 47 .val = _val, \ 48 .reg_val = _reg_val, \ 49 } 50 51 #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \ 52 { \ 53 .name = _name, \ 54 .reg = _reg, \ 55 .offset = _off, \ 56 .width = _width, \ 57 .func = (struct sunxi_sram_func[]){ \ 58 __VA_ARGS__, { } }, \ 59 } 60 61 static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = { 62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2, 63 SUNXI_SRAM_MAP(0, 0, "cpu"), 64 SUNXI_SRAM_MAP(1, 1, "emac")), 65 }; 66 67 static struct sunxi_sram_desc sun4i_a10_sram_c1 = { 68 .data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31, 69 SUNXI_SRAM_MAP(0, 0, "cpu"), 70 SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")), 71 }; 72 73 static struct sunxi_sram_desc sun4i_a10_sram_d = { 74 .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1, 75 SUNXI_SRAM_MAP(0, 0, "cpu"), 76 SUNXI_SRAM_MAP(1, 1, "usb-otg")), 77 }; 78 79 static struct sunxi_sram_desc sun50i_a64_sram_c = { 80 .data = SUNXI_SRAM_DATA("C", 0x4, 24, 1, 81 SUNXI_SRAM_MAP(0, 1, "cpu"), 82 SUNXI_SRAM_MAP(1, 0, "de2")), 83 }; 84 85 static const struct of_device_id sunxi_sram_dt_ids[] = { 86 { 87 .compatible = "allwinner,sun4i-a10-sram-a3-a4", 88 .data = &sun4i_a10_sram_a3_a4.data, 89 }, 90 { 91 .compatible = "allwinner,sun4i-a10-sram-c1", 92 .data = &sun4i_a10_sram_c1.data, 93 }, 94 { 95 .compatible = "allwinner,sun4i-a10-sram-d", 96 .data = &sun4i_a10_sram_d.data, 97 }, 98 { 99 .compatible = "allwinner,sun50i-a64-sram-c", 100 .data = &sun50i_a64_sram_c.data, 101 }, 102 {} 103 }; 104 105 static struct device *sram_dev; 106 static LIST_HEAD(claimed_sram); 107 static DEFINE_SPINLOCK(sram_lock); 108 static void __iomem *base; 109 110 static int sunxi_sram_show(struct seq_file *s, void *data) 111 { 112 struct device_node *sram_node, *section_node; 113 const struct sunxi_sram_data *sram_data; 114 const struct of_device_id *match; 115 struct sunxi_sram_func *func; 116 const __be32 *sram_addr_p, *section_addr_p; 117 u32 val; 118 119 seq_puts(s, "Allwinner sunXi SRAM\n"); 120 seq_puts(s, "--------------------\n\n"); 121 122 for_each_child_of_node(sram_dev->of_node, sram_node) { 123 sram_addr_p = of_get_address(sram_node, 0, NULL, NULL); 124 125 seq_printf(s, "sram@%08x\n", 126 be32_to_cpu(*sram_addr_p)); 127 128 for_each_child_of_node(sram_node, section_node) { 129 match = of_match_node(sunxi_sram_dt_ids, section_node); 130 if (!match) 131 continue; 132 sram_data = match->data; 133 134 section_addr_p = of_get_address(section_node, 0, 135 NULL, NULL); 136 137 seq_printf(s, "\tsection@%04x\t(%s)\n", 138 be32_to_cpu(*section_addr_p), 139 sram_data->name); 140 141 val = readl(base + sram_data->reg); 142 val >>= sram_data->offset; 143 val &= GENMASK(sram_data->width - 1, 0); 144 145 for (func = sram_data->func; func->func; func++) { 146 seq_printf(s, "\t\t%s%c\n", func->func, 147 func->reg_val == val ? 148 '*' : ' '); 149 } 150 } 151 152 seq_puts(s, "\n"); 153 } 154 155 return 0; 156 } 157 158 static int sunxi_sram_open(struct inode *inode, struct file *file) 159 { 160 return single_open(file, sunxi_sram_show, inode->i_private); 161 } 162 163 static const struct file_operations sunxi_sram_fops = { 164 .open = sunxi_sram_open, 165 .read = seq_read, 166 .llseek = seq_lseek, 167 .release = single_release, 168 }; 169 170 static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data) 171 { 172 return container_of(data, struct sunxi_sram_desc, data); 173 } 174 175 static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node, 176 unsigned int *reg_value) 177 { 178 const struct of_device_id *match; 179 const struct sunxi_sram_data *data; 180 struct sunxi_sram_func *func; 181 struct of_phandle_args args; 182 u8 val; 183 int ret; 184 185 ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0, 186 &args); 187 if (ret) 188 return ERR_PTR(ret); 189 190 if (!of_device_is_available(args.np)) { 191 ret = -EBUSY; 192 goto err; 193 } 194 195 val = args.args[0]; 196 197 match = of_match_node(sunxi_sram_dt_ids, args.np); 198 if (!match) { 199 ret = -EINVAL; 200 goto err; 201 } 202 203 data = match->data; 204 if (!data) { 205 ret = -EINVAL; 206 goto err; 207 }; 208 209 for (func = data->func; func->func; func++) { 210 if (val == func->val) { 211 if (reg_value) 212 *reg_value = func->reg_val; 213 214 break; 215 } 216 } 217 218 if (!func->func) { 219 ret = -EINVAL; 220 goto err; 221 } 222 223 of_node_put(args.np); 224 return match->data; 225 226 err: 227 of_node_put(args.np); 228 return ERR_PTR(ret); 229 } 230 231 int sunxi_sram_claim(struct device *dev) 232 { 233 const struct sunxi_sram_data *sram_data; 234 struct sunxi_sram_desc *sram_desc; 235 unsigned int device; 236 u32 val, mask; 237 238 if (IS_ERR(base)) 239 return PTR_ERR(base); 240 241 if (!base) 242 return -EPROBE_DEFER; 243 244 if (!dev || !dev->of_node) 245 return -EINVAL; 246 247 sram_data = sunxi_sram_of_parse(dev->of_node, &device); 248 if (IS_ERR(sram_data)) 249 return PTR_ERR(sram_data); 250 251 sram_desc = to_sram_desc(sram_data); 252 253 spin_lock(&sram_lock); 254 255 if (sram_desc->claimed) { 256 spin_unlock(&sram_lock); 257 return -EBUSY; 258 } 259 260 mask = GENMASK(sram_data->offset + sram_data->width - 1, 261 sram_data->offset); 262 val = readl(base + sram_data->reg); 263 val &= ~mask; 264 writel(val | ((device << sram_data->offset) & mask), 265 base + sram_data->reg); 266 267 spin_unlock(&sram_lock); 268 269 return 0; 270 } 271 EXPORT_SYMBOL(sunxi_sram_claim); 272 273 int sunxi_sram_release(struct device *dev) 274 { 275 const struct sunxi_sram_data *sram_data; 276 struct sunxi_sram_desc *sram_desc; 277 278 if (!dev || !dev->of_node) 279 return -EINVAL; 280 281 sram_data = sunxi_sram_of_parse(dev->of_node, NULL); 282 if (IS_ERR(sram_data)) 283 return -EINVAL; 284 285 sram_desc = to_sram_desc(sram_data); 286 287 spin_lock(&sram_lock); 288 sram_desc->claimed = false; 289 spin_unlock(&sram_lock); 290 291 return 0; 292 } 293 EXPORT_SYMBOL(sunxi_sram_release); 294 295 struct sunxi_sramc_variant { 296 bool has_emac_clock; 297 }; 298 299 static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { 300 /* Nothing special */ 301 }; 302 303 static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = { 304 .has_emac_clock = true, 305 }; 306 307 #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 308 static bool sunxi_sram_regmap_accessible_reg(struct device *dev, 309 unsigned int reg) 310 { 311 if (reg == SUNXI_SRAM_EMAC_CLOCK_REG) 312 return true; 313 return false; 314 } 315 316 static struct regmap_config sunxi_sram_emac_clock_regmap = { 317 .reg_bits = 32, 318 .val_bits = 32, 319 .reg_stride = 4, 320 /* last defined register */ 321 .max_register = SUNXI_SRAM_EMAC_CLOCK_REG, 322 /* other devices have no business accessing other registers */ 323 .readable_reg = sunxi_sram_regmap_accessible_reg, 324 .writeable_reg = sunxi_sram_regmap_accessible_reg, 325 }; 326 327 static int sunxi_sram_probe(struct platform_device *pdev) 328 { 329 struct resource *res; 330 struct dentry *d; 331 struct regmap *emac_clock; 332 const struct sunxi_sramc_variant *variant; 333 334 sram_dev = &pdev->dev; 335 336 variant = of_device_get_match_data(&pdev->dev); 337 if (!variant) 338 return -EINVAL; 339 340 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 341 base = devm_ioremap_resource(&pdev->dev, res); 342 if (IS_ERR(base)) 343 return PTR_ERR(base); 344 345 of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 346 347 d = debugfs_create_file("sram", S_IRUGO, NULL, NULL, 348 &sunxi_sram_fops); 349 if (!d) 350 return -ENOMEM; 351 352 if (variant->has_emac_clock) { 353 emac_clock = devm_regmap_init_mmio(&pdev->dev, base, 354 &sunxi_sram_emac_clock_regmap); 355 356 if (IS_ERR(emac_clock)) 357 return PTR_ERR(emac_clock); 358 } 359 360 return 0; 361 } 362 363 static const struct of_device_id sunxi_sram_dt_match[] = { 364 { 365 .compatible = "allwinner,sun4i-a10-sram-controller", 366 .data = &sun4i_a10_sramc_variant, 367 }, 368 { 369 .compatible = "allwinner,sun4i-a10-system-control", 370 .data = &sun4i_a10_sramc_variant, 371 }, 372 { 373 .compatible = "allwinner,sun5i-a13-system-control", 374 .data = &sun4i_a10_sramc_variant, 375 }, 376 { 377 .compatible = "allwinner,sun8i-a23-system-control", 378 .data = &sun4i_a10_sramc_variant, 379 }, 380 { 381 .compatible = "allwinner,sun8i-h3-system-control", 382 .data = &sun4i_a10_sramc_variant, 383 }, 384 { 385 .compatible = "allwinner,sun50i-a64-sram-controller", 386 .data = &sun50i_a64_sramc_variant, 387 }, 388 { 389 .compatible = "allwinner,sun50i-a64-system-control", 390 .data = &sun50i_a64_sramc_variant, 391 }, 392 { }, 393 }; 394 MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); 395 396 static struct platform_driver sunxi_sram_driver = { 397 .driver = { 398 .name = "sunxi-sram", 399 .of_match_table = sunxi_sram_dt_match, 400 }, 401 .probe = sunxi_sram_probe, 402 }; 403 module_platform_driver(sunxi_sram_driver); 404 405 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 406 MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver"); 407 MODULE_LICENSE("GPL"); 408