1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SiFive composable cache controller Driver 4 * 5 * Copyright (C) 2018-2022 SiFive, Inc. 6 * 7 */ 8 #include <linux/debugfs.h> 9 #include <linux/interrupt.h> 10 #include <linux/of_irq.h> 11 #include <linux/of_address.h> 12 #include <linux/device.h> 13 #include <asm/cacheinfo.h> 14 #include <soc/sifive/sifive_ccache.h> 15 16 #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 17 #define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104 18 #define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108 19 20 #define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120 21 #define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124 22 #define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128 23 24 #define SIFIVE_CCACHE_DATECCFIX_LOW 0x140 25 #define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144 26 #define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148 27 28 #define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160 29 #define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164 30 #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 31 32 #define SIFIVE_CCACHE_CONFIG 0x00 33 #define SIFIVE_CCACHE_WAYENABLE 0x08 34 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 35 36 #define SIFIVE_CCACHE_MAX_ECCINTR 4 37 38 static void __iomem *ccache_base; 39 static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; 40 static struct riscv_cacheinfo_ops ccache_cache_ops; 41 42 enum { 43 DIR_CORR = 0, 44 DATA_CORR, 45 DATA_UNCORR, 46 DIR_UNCORR, 47 }; 48 49 #ifdef CONFIG_DEBUG_FS 50 static struct dentry *sifive_test; 51 52 static ssize_t ccache_write(struct file *file, const char __user *data, 53 size_t count, loff_t *ppos) 54 { 55 unsigned int val; 56 57 if (kstrtouint_from_user(data, count, 0, &val)) 58 return -EINVAL; 59 if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF)) 60 writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR); 61 else 62 return -EINVAL; 63 return count; 64 } 65 66 static const struct file_operations ccache_fops = { 67 .owner = THIS_MODULE, 68 .open = simple_open, 69 .write = ccache_write 70 }; 71 72 static void setup_sifive_debug(void) 73 { 74 sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL); 75 76 debugfs_create_file("sifive_debug_inject_error", 0200, 77 sifive_test, NULL, &ccache_fops); 78 } 79 #endif 80 81 static void ccache_config_read(void) 82 { 83 u32 regval, val; 84 85 regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG); 86 val = regval & 0xFF; 87 pr_info("CCACHE: No. of Banks in the cache: %d\n", val); 88 val = (regval & 0xFF00) >> 8; 89 pr_info("CCACHE: No. of ways per bank: %d\n", val); 90 val = (regval & 0xFF0000) >> 16; 91 pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val); 92 val = (regval & 0xFF000000) >> 24; 93 pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val); 94 95 regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); 96 pr_info("CCACHE: Index of the largest way enabled: %d\n", regval); 97 } 98 99 static const struct of_device_id sifive_ccache_ids[] = { 100 { .compatible = "sifive,fu540-c000-ccache" }, 101 { .compatible = "sifive,fu740-c000-ccache" }, 102 { .compatible = "sifive,ccache0" }, 103 { /* end of table */ } 104 }; 105 106 static ATOMIC_NOTIFIER_HEAD(ccache_err_chain); 107 108 int register_sifive_ccache_error_notifier(struct notifier_block *nb) 109 { 110 return atomic_notifier_chain_register(&ccache_err_chain, nb); 111 } 112 EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier); 113 114 int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) 115 { 116 return atomic_notifier_chain_unregister(&ccache_err_chain, nb); 117 } 118 EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); 119 120 static int ccache_largest_wayenabled(void) 121 { 122 return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; 123 } 124 125 static ssize_t number_of_ways_enabled_show(struct device *dev, 126 struct device_attribute *attr, 127 char *buf) 128 { 129 return sprintf(buf, "%u\n", ccache_largest_wayenabled()); 130 } 131 132 static DEVICE_ATTR_RO(number_of_ways_enabled); 133 134 static struct attribute *priv_attrs[] = { 135 &dev_attr_number_of_ways_enabled.attr, 136 NULL, 137 }; 138 139 static const struct attribute_group priv_attr_group = { 140 .attrs = priv_attrs, 141 }; 142 143 static const struct attribute_group *ccache_get_priv_group(struct cacheinfo 144 *this_leaf) 145 { 146 /* We want to use private group for composable cache only */ 147 if (this_leaf->level == 2) 148 return &priv_attr_group; 149 else 150 return NULL; 151 } 152 153 static irqreturn_t ccache_int_handler(int irq, void *device) 154 { 155 unsigned int add_h, add_l; 156 157 if (irq == g_irq[DIR_CORR]) { 158 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); 159 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); 160 pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l); 161 /* Reading this register clears the DirError interrupt sig */ 162 readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); 163 atomic_notifier_call_chain(&ccache_err_chain, 164 SIFIVE_CCACHE_ERR_TYPE_CE, 165 "DirECCFix"); 166 } 167 if (irq == g_irq[DIR_UNCORR]) { 168 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); 169 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); 170 /* Reading this register clears the DirFail interrupt sig */ 171 readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); 172 atomic_notifier_call_chain(&ccache_err_chain, 173 SIFIVE_CCACHE_ERR_TYPE_UE, 174 "DirECCFail"); 175 panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l); 176 } 177 if (irq == g_irq[DATA_CORR]) { 178 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH); 179 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW); 180 pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l); 181 /* Reading this register clears the DataError interrupt sig */ 182 readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT); 183 atomic_notifier_call_chain(&ccache_err_chain, 184 SIFIVE_CCACHE_ERR_TYPE_CE, 185 "DatECCFix"); 186 } 187 if (irq == g_irq[DATA_UNCORR]) { 188 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH); 189 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW); 190 pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l); 191 /* Reading this register clears the DataFail interrupt sig */ 192 readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT); 193 atomic_notifier_call_chain(&ccache_err_chain, 194 SIFIVE_CCACHE_ERR_TYPE_UE, 195 "DatECCFail"); 196 } 197 198 return IRQ_HANDLED; 199 } 200 201 static int __init sifive_ccache_init(void) 202 { 203 struct device_node *np; 204 struct resource res; 205 int i, rc, intr_num; 206 207 np = of_find_matching_node(NULL, sifive_ccache_ids); 208 if (!np) 209 return -ENODEV; 210 211 if (of_address_to_resource(np, 0, &res)) 212 return -ENODEV; 213 214 ccache_base = ioremap(res.start, resource_size(&res)); 215 if (!ccache_base) 216 return -ENOMEM; 217 218 intr_num = of_property_count_u32_elems(np, "interrupts"); 219 if (!intr_num) { 220 pr_err("CCACHE: no interrupts property\n"); 221 return -ENODEV; 222 } 223 224 for (i = 0; i < intr_num; i++) { 225 g_irq[i] = irq_of_parse_and_map(np, i); 226 rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", 227 NULL); 228 if (rc) { 229 pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]); 230 return rc; 231 } 232 } 233 234 ccache_config_read(); 235 236 ccache_cache_ops.get_priv_group = ccache_get_priv_group; 237 riscv_set_cacheinfo_ops(&ccache_cache_ops); 238 239 #ifdef CONFIG_DEBUG_FS 240 setup_sifive_debug(); 241 #endif 242 return 0; 243 } 244 245 device_initcall(sifive_ccache_init); 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